1/* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32#ifndef CXGB4_ABI_USER_H 33#define CXGB4_ABI_USER_H 34 35#include <linux/types.h> 36 37#define C4IW_UVERBS_ABI_VERSION 3 38 39/* 40 * Make sure that all structs defined in this file remain laid out so 41 * that they pack the same way on 32-bit and 64-bit architectures (to 42 * avoid incompatibility between 32-bit userspace and 64-bit kernels). 43 * In particular do not use pointer types -- pass pointers in __aligned_u64 44 * instead. 45 */ 46 47enum { 48 C4IW_64B_CQE = (1 << 0) 49}; 50 51struct c4iw_create_cq { 52 __u32 flags; 53 __u32 reserved; 54}; 55 56struct c4iw_create_cq_resp { 57 __aligned_u64 key; 58 __aligned_u64 gts_key; 59 __aligned_u64 memsize; 60 __u32 cqid; 61 __u32 size; 62 __u32 qid_mask; 63 __u32 flags; 64}; 65 66enum { 67 C4IW_QPF_ONCHIP = (1 << 0), 68 C4IW_QPF_WRITE_W_IMM = (1 << 1) 69}; 70 71struct c4iw_create_qp_resp { 72 __aligned_u64 ma_sync_key; 73 __aligned_u64 sq_key; 74 __aligned_u64 rq_key; 75 __aligned_u64 sq_db_gts_key; 76 __aligned_u64 rq_db_gts_key; 77 __aligned_u64 sq_memsize; 78 __aligned_u64 rq_memsize; 79 __u32 sqid; 80 __u32 rqid; 81 __u32 sq_size; 82 __u32 rq_size; 83 __u32 qid_mask; 84 __u32 flags; 85}; 86 87struct c4iw_create_srq_resp { 88 __aligned_u64 srq_key; 89 __aligned_u64 srq_db_gts_key; 90 __aligned_u64 srq_memsize; 91 __u32 srqid; 92 __u32 srq_size; 93 __u32 rqt_abs_idx; 94 __u32 qid_mask; 95 __u32 flags; 96 __u32 reserved; /* explicit padding */ 97}; 98 99enum { 100 /* HW supports SRQ_LIMIT_REACHED event */ 101 T4_SRQ_LIMIT_SUPPORT = 1 << 0, 102}; 103 104struct c4iw_alloc_ucontext_resp { 105 __aligned_u64 status_page_key; 106 __u32 status_page_size; 107 __u32 reserved; /* explicit padding (optional for i386) */ 108}; 109 110struct c4iw_alloc_pd_resp { 111 __u32 pdid; 112}; 113 114#endif /* CXGB4_ABI_USER_H */ 115