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20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/mutex.h>
23#include <linux/pci.h>
24#include <linux/slab.h>
25#include <linux/module.h>
26#include <sound/ac97_codec.h>
27#include <sound/asoundef.h>
28#include <sound/core.h>
29#include <sound/info.h>
30#include <sound/mpu401.h>
31#include <sound/pcm.h>
32#include "oxygen.h"
33#include "cm9780.h"
34
35MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
36MODULE_DESCRIPTION("C-Media CMI8788 helper library");
37MODULE_LICENSE("GPL v2");
38
39#define DRIVER "oxygen"
40
41static inline int oxygen_uart_input_ready(struct oxygen *chip)
42{
43 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
44}
45
46static void oxygen_read_uart(struct oxygen *chip)
47{
48 if (unlikely(!oxygen_uart_input_ready(chip))) {
49
50 oxygen_read8(chip, OXYGEN_MPU401);
51 return;
52 }
53 do {
54 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
55 if (data == MPU401_ACK)
56 continue;
57 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
58 chip->uart_input_count = 0;
59 chip->uart_input[chip->uart_input_count++] = data;
60 } while (oxygen_uart_input_ready(chip));
61 if (chip->model.uart_input)
62 chip->model.uart_input(chip);
63}
64
65static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
66{
67 struct oxygen *chip = dev_id;
68 unsigned int status, clear, elapsed_streams, i;
69
70 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
71 if (!status)
72 return IRQ_NONE;
73
74 spin_lock(&chip->reg_lock);
75
76 clear = status & (OXYGEN_CHANNEL_A |
77 OXYGEN_CHANNEL_B |
78 OXYGEN_CHANNEL_C |
79 OXYGEN_CHANNEL_SPDIF |
80 OXYGEN_CHANNEL_MULTICH |
81 OXYGEN_CHANNEL_AC97 |
82 OXYGEN_INT_SPDIF_IN_DETECT |
83 OXYGEN_INT_GPIO |
84 OXYGEN_INT_AC97);
85 if (clear) {
86 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
87 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
88 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
89 chip->interrupt_mask & ~clear);
90 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
91 chip->interrupt_mask);
92 }
93
94 elapsed_streams = status & chip->pcm_running;
95
96 spin_unlock(&chip->reg_lock);
97
98 for (i = 0; i < PCM_COUNT; ++i)
99 if ((elapsed_streams & (1 << i)) && chip->streams[i])
100 snd_pcm_period_elapsed(chip->streams[i]);
101
102 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
103 spin_lock(&chip->reg_lock);
104 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
105 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
106 OXYGEN_SPDIF_RATE_INT)) {
107
108 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
109 schedule_work(&chip->spdif_input_bits_work);
110 }
111 spin_unlock(&chip->reg_lock);
112 }
113
114 if (status & OXYGEN_INT_GPIO)
115 schedule_work(&chip->gpio_work);
116
117 if (status & OXYGEN_INT_MIDI) {
118 if (chip->midi)
119 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
120 else
121 oxygen_read_uart(chip);
122 }
123
124 if (status & OXYGEN_INT_AC97)
125 wake_up(&chip->ac97_waitqueue);
126
127 return IRQ_HANDLED;
128}
129
130static void oxygen_spdif_input_bits_changed(struct work_struct *work)
131{
132 struct oxygen *chip = container_of(work, struct oxygen,
133 spdif_input_bits_work);
134 u32 reg;
135
136
137
138
139
140
141 msleep(1);
142 spin_lock_irq(&chip->reg_lock);
143 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
144 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
145 OXYGEN_SPDIF_LOCK_STATUS))
146 == OXYGEN_SPDIF_SENSE_STATUS) {
147
148
149
150
151 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
152 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
153 spin_unlock_irq(&chip->reg_lock);
154 msleep(1);
155 spin_lock_irq(&chip->reg_lock);
156 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
157 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
158 OXYGEN_SPDIF_LOCK_STATUS))
159 == OXYGEN_SPDIF_SENSE_STATUS) {
160
161 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
162 == OXYGEN_SPDIF_IN_CLOCK_192) {
163
164
165
166
167 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
168 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
169 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
170 }
171 }
172 }
173 spin_unlock_irq(&chip->reg_lock);
174
175 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
176 spin_lock_irq(&chip->reg_lock);
177 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
178 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
179 chip->interrupt_mask);
180 spin_unlock_irq(&chip->reg_lock);
181
182
183
184
185
186 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
187 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
188 }
189}
190
191static void oxygen_gpio_changed(struct work_struct *work)
192{
193 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
194
195 if (chip->model.gpio_changed)
196 chip->model.gpio_changed(chip);
197}
198
199static void oxygen_proc_read(struct snd_info_entry *entry,
200 struct snd_info_buffer *buffer)
201{
202 struct oxygen *chip = entry->private_data;
203 int i, j;
204
205 switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) {
206 case OXYGEN_PACKAGE_ID_8786: i = '6'; break;
207 case OXYGEN_PACKAGE_ID_8787: i = '7'; break;
208 case OXYGEN_PACKAGE_ID_8788: i = '8'; break;
209 default: i = '?'; break;
210 }
211 snd_iprintf(buffer, "CMI878%c:\n", i);
212 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
213 snd_iprintf(buffer, "%02x:", i);
214 for (j = 0; j < 0x10; ++j)
215 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
216 snd_iprintf(buffer, "\n");
217 }
218 if (mutex_lock_interruptible(&chip->mutex) < 0)
219 return;
220 if (chip->has_ac97_0) {
221 snd_iprintf(buffer, "\nAC97:\n");
222 for (i = 0; i < 0x80; i += 0x10) {
223 snd_iprintf(buffer, "%02x:", i);
224 for (j = 0; j < 0x10; j += 2)
225 snd_iprintf(buffer, " %04x",
226 oxygen_read_ac97(chip, 0, i + j));
227 snd_iprintf(buffer, "\n");
228 }
229 }
230 if (chip->has_ac97_1) {
231 snd_iprintf(buffer, "\nAC97 2:\n");
232 for (i = 0; i < 0x80; i += 0x10) {
233 snd_iprintf(buffer, "%02x:", i);
234 for (j = 0; j < 0x10; j += 2)
235 snd_iprintf(buffer, " %04x",
236 oxygen_read_ac97(chip, 1, i + j));
237 snd_iprintf(buffer, "\n");
238 }
239 }
240 mutex_unlock(&chip->mutex);
241 if (chip->model.dump_registers)
242 chip->model.dump_registers(chip, buffer);
243}
244
245static void oxygen_proc_init(struct oxygen *chip)
246{
247 snd_card_ro_proc_new(chip->card, "oxygen", chip, oxygen_proc_read);
248}
249
250static const struct pci_device_id *
251oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
252{
253 u16 subdevice;
254
255
256
257
258
259 oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
260 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
261
262
263
264
265 subdevice = oxygen_read_eeprom(chip, 2);
266
267 if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff)
268 subdevice = 0x8788;
269
270
271
272
273
274 for (; ids->vendor; ++ids)
275 if (ids->subdevice == subdevice &&
276 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
277 return ids;
278 return NULL;
279}
280
281static void oxygen_restore_eeprom(struct oxygen *chip,
282 const struct pci_device_id *id)
283{
284 u16 eeprom_id;
285
286 eeprom_id = oxygen_read_eeprom(chip, 0);
287 if (eeprom_id != OXYGEN_EEPROM_ID &&
288 (eeprom_id != 0xffff || id->subdevice != 0x8788)) {
289
290
291
292
293
294
295
296
297 oxygen_write_eeprom(chip, 1, id->subvendor);
298 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
299
300 oxygen_set_bits8(chip, OXYGEN_MISC,
301 OXYGEN_MISC_WRITE_PCI_SUBID);
302 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
303 id->subvendor);
304 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
305 id->subdevice);
306 oxygen_clear_bits8(chip, OXYGEN_MISC,
307 OXYGEN_MISC_WRITE_PCI_SUBID);
308
309 dev_info(chip->card->dev, "EEPROM ID restored\n");
310 }
311}
312
313static void configure_pcie_bridge(struct pci_dev *pci)
314{
315 enum { PEX811X, PI7C9X110, XIO2001 };
316 static const struct pci_device_id bridge_ids[] = {
317 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X },
318 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X },
319 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 },
320 { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 },
321 { }
322 };
323 struct pci_dev *bridge;
324 const struct pci_device_id *id;
325 u32 tmp;
326
327 if (!pci->bus || !pci->bus->self)
328 return;
329 bridge = pci->bus->self;
330
331 id = pci_match_id(bridge_ids, bridge);
332 if (!id)
333 return;
334
335 switch (id->driver_data) {
336 case PEX811X:
337 pci_read_config_dword(bridge, 0x48, &tmp);
338 tmp |= 1;
339 tmp |= 1 << 11;
340 pci_write_config_dword(bridge, 0x48, tmp);
341
342 pci_write_config_dword(bridge, 0x84, 0x0c);
343 pci_read_config_dword(bridge, 0x88, &tmp);
344 tmp &= ~(7 << 27);
345 tmp |= 2 << 27;
346 pci_write_config_dword(bridge, 0x88, tmp);
347 break;
348
349 case PI7C9X110:
350 pci_read_config_dword(bridge, 0x40, &tmp);
351 tmp |= 1;
352 pci_write_config_dword(bridge, 0x40, tmp);
353 break;
354
355 case XIO2001:
356 pci_read_config_dword(bridge, 0xe8, &tmp);
357 tmp &= ~0xf;
358 tmp &= ~(0xf << 8);
359 tmp |= 1 << 8;
360 pci_write_config_dword(bridge, 0xe8, tmp);
361 break;
362 }
363}
364
365static void oxygen_init(struct oxygen *chip)
366{
367 unsigned int i;
368
369 chip->dac_routing = 1;
370 for (i = 0; i < 8; ++i)
371 chip->dac_volume[i] = chip->model.dac_volume_min;
372 chip->dac_mute = 1;
373 chip->spdif_playback_enable = 0;
374 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
375 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
376 chip->spdif_pcm_bits = chip->spdif_bits;
377
378 if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2))
379 oxygen_set_bits8(chip, OXYGEN_MISC,
380 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
381
382 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
383 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
384 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
385
386 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
387 OXYGEN_FUNCTION_RESET_CODEC |
388 chip->model.function_flags,
389 OXYGEN_FUNCTION_RESET_CODEC |
390 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
391 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
392 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
393 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
394 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
395 OXYGEN_PLAY_CHANNELS_2 |
396 OXYGEN_DMA_A_BURST_8 |
397 OXYGEN_DMA_MULTICH_BURST_8);
398 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
399 oxygen_write8_masked(chip, OXYGEN_MISC,
400 chip->model.misc_flags,
401 OXYGEN_MISC_WRITE_PCI_SUBID |
402 OXYGEN_MISC_REC_C_FROM_SPDIF |
403 OXYGEN_MISC_REC_B_FROM_AC97 |
404 OXYGEN_MISC_REC_A_FROM_MULTICH |
405 OXYGEN_MISC_MIDI);
406 oxygen_write8(chip, OXYGEN_REC_FORMAT,
407 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
408 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
409 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
410 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
411 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
412 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
413 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
414 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
415 OXYGEN_RATE_48000 |
416 chip->model.dac_i2s_format |
417 OXYGEN_I2S_MCLK(chip->model.dac_mclks) |
418 OXYGEN_I2S_BITS_16 |
419 OXYGEN_I2S_MASTER |
420 OXYGEN_I2S_BCLK_64);
421 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
422 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
423 OXYGEN_RATE_48000 |
424 chip->model.adc_i2s_format |
425 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
426 OXYGEN_I2S_BITS_16 |
427 OXYGEN_I2S_MASTER |
428 OXYGEN_I2S_BCLK_64);
429 else
430 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
431 OXYGEN_I2S_MASTER |
432 OXYGEN_I2S_MUTE_MCLK);
433 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
434 CAPTURE_2_FROM_I2S_2))
435 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
436 OXYGEN_RATE_48000 |
437 chip->model.adc_i2s_format |
438 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
439 OXYGEN_I2S_BITS_16 |
440 OXYGEN_I2S_MASTER |
441 OXYGEN_I2S_BCLK_64);
442 else
443 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
444 OXYGEN_I2S_MASTER |
445 OXYGEN_I2S_MUTE_MCLK);
446 if (chip->model.device_config & CAPTURE_3_FROM_I2S_3)
447 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
448 OXYGEN_RATE_48000 |
449 chip->model.adc_i2s_format |
450 OXYGEN_I2S_MCLK(chip->model.adc_mclks) |
451 OXYGEN_I2S_BITS_16 |
452 OXYGEN_I2S_MASTER |
453 OXYGEN_I2S_BCLK_64);
454 else
455 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
456 OXYGEN_I2S_MASTER |
457 OXYGEN_I2S_MUTE_MCLK);
458 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
459 OXYGEN_SPDIF_OUT_ENABLE |
460 OXYGEN_SPDIF_LOOPBACK);
461 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
462 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
463 OXYGEN_SPDIF_SENSE_MASK |
464 OXYGEN_SPDIF_LOCK_MASK |
465 OXYGEN_SPDIF_RATE_MASK |
466 OXYGEN_SPDIF_LOCK_PAR |
467 OXYGEN_SPDIF_IN_CLOCK_96,
468 OXYGEN_SPDIF_SENSE_MASK |
469 OXYGEN_SPDIF_LOCK_MASK |
470 OXYGEN_SPDIF_RATE_MASK |
471 OXYGEN_SPDIF_SENSE_PAR |
472 OXYGEN_SPDIF_LOCK_PAR |
473 OXYGEN_SPDIF_IN_CLOCK_MASK);
474 else
475 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
476 OXYGEN_SPDIF_SENSE_MASK |
477 OXYGEN_SPDIF_LOCK_MASK |
478 OXYGEN_SPDIF_RATE_MASK);
479 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
480 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
481 OXYGEN_2WIRE_LENGTH_8 |
482 OXYGEN_2WIRE_INTERRUPT_MASK |
483 OXYGEN_2WIRE_SPEED_STANDARD);
484 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
485 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
486 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
487 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
488 OXYGEN_PLAY_MULTICH_I2S_DAC |
489 OXYGEN_PLAY_SPDIF_SPDIF |
490 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
491 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
492 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
493 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
494 oxygen_write8(chip, OXYGEN_REC_ROUTING,
495 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
496 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
497 OXYGEN_REC_C_ROUTE_SPDIF);
498 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
499 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
500 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
501 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
502 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
503 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
504
505 if (chip->has_ac97_0 | chip->has_ac97_1)
506 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
507 OXYGEN_AC97_INT_READ_DONE |
508 OXYGEN_AC97_INT_WRITE_DONE);
509 else
510 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
511 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
512 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
513 if (!(chip->has_ac97_0 | chip->has_ac97_1))
514 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
515 OXYGEN_AC97_CLOCK_DISABLE);
516 if (!chip->has_ac97_0) {
517 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
518 OXYGEN_AC97_NO_CODEC_0);
519 } else {
520 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
521 msleep(1);
522 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
523 CM9780_GPIO0IO | CM9780_GPIO1IO);
524 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
525 CM9780_BSTSEL | CM9780_STRO_MIC |
526 CM9780_MIX2FR | CM9780_PCBSW);
527 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
528 CM9780_RSOE | CM9780_CBOE |
529 CM9780_SSOE | CM9780_FROE |
530 CM9780_MIC2MIC | CM9780_LI2LI);
531 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
532 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
533 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
534 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
535 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
536 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
537 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
538 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
539 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
540 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
541 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
542 CM9780_GPO0);
543
544 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
545 AC97_PD_PR0 | AC97_PD_PR1);
546 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
547 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
548 }
549 if (chip->has_ac97_1) {
550 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
551 OXYGEN_AC97_CODEC1_SLOT3 |
552 OXYGEN_AC97_CODEC1_SLOT4);
553 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
554 msleep(1);
555 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
556 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
557 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
558 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
559 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
560 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
561 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
562 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
563 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
564 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
565 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
566 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
567 }
568}
569
570static void oxygen_shutdown(struct oxygen *chip)
571{
572 spin_lock_irq(&chip->reg_lock);
573 chip->interrupt_mask = 0;
574 chip->pcm_running = 0;
575 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
576 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
577 spin_unlock_irq(&chip->reg_lock);
578}
579
580static void oxygen_card_free(struct snd_card *card)
581{
582 struct oxygen *chip = card->private_data;
583
584 oxygen_shutdown(chip);
585 if (chip->irq >= 0)
586 free_irq(chip->irq, chip);
587 flush_work(&chip->spdif_input_bits_work);
588 flush_work(&chip->gpio_work);
589 chip->model.cleanup(chip);
590 kfree(chip->model_data);
591 mutex_destroy(&chip->mutex);
592 pci_release_regions(chip->pci);
593 pci_disable_device(chip->pci);
594}
595
596int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
597 struct module *owner,
598 const struct pci_device_id *ids,
599 int (*get_model)(struct oxygen *chip,
600 const struct pci_device_id *id
601 )
602 )
603{
604 struct snd_card *card;
605 struct oxygen *chip;
606 const struct pci_device_id *pci_id;
607 int err;
608
609 err = snd_card_new(&pci->dev, index, id, owner,
610 sizeof(*chip), &card);
611 if (err < 0)
612 return err;
613
614 chip = card->private_data;
615 chip->card = card;
616 chip->pci = pci;
617 chip->irq = -1;
618 spin_lock_init(&chip->reg_lock);
619 mutex_init(&chip->mutex);
620 INIT_WORK(&chip->spdif_input_bits_work,
621 oxygen_spdif_input_bits_changed);
622 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
623 init_waitqueue_head(&chip->ac97_waitqueue);
624
625 err = pci_enable_device(pci);
626 if (err < 0)
627 goto err_card;
628
629 err = pci_request_regions(pci, DRIVER);
630 if (err < 0) {
631 dev_err(card->dev, "cannot reserve PCI resources\n");
632 goto err_pci_enable;
633 }
634
635 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
636 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
637 dev_err(card->dev, "invalid PCI I/O range\n");
638 err = -ENXIO;
639 goto err_pci_regions;
640 }
641 chip->addr = pci_resource_start(pci, 0);
642
643 pci_id = oxygen_search_pci_id(chip, ids);
644 if (!pci_id) {
645 err = -ENODEV;
646 goto err_pci_regions;
647 }
648 oxygen_restore_eeprom(chip, pci_id);
649 err = get_model(chip, pci_id);
650 if (err < 0)
651 goto err_pci_regions;
652
653 if (chip->model.model_data_size) {
654 chip->model_data = kzalloc(chip->model.model_data_size,
655 GFP_KERNEL);
656 if (!chip->model_data) {
657 err = -ENOMEM;
658 goto err_pci_regions;
659 }
660 }
661
662 pci_set_master(pci);
663 card->private_free = oxygen_card_free;
664
665 configure_pcie_bridge(pci);
666 oxygen_init(chip);
667 chip->model.init(chip);
668
669 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
670 KBUILD_MODNAME, chip);
671 if (err < 0) {
672 dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq);
673 goto err_card;
674 }
675 chip->irq = pci->irq;
676
677 strcpy(card->driver, chip->model.chip);
678 strcpy(card->shortname, chip->model.shortname);
679 sprintf(card->longname, "%s at %#lx, irq %i",
680 chip->model.longname, chip->addr, chip->irq);
681 strcpy(card->mixername, chip->model.chip);
682 snd_component_add(card, chip->model.chip);
683
684 err = oxygen_pcm_init(chip);
685 if (err < 0)
686 goto err_card;
687
688 err = oxygen_mixer_init(chip);
689 if (err < 0)
690 goto err_card;
691
692 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
693 unsigned int info_flags =
694 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK;
695 if (chip->model.device_config & MIDI_OUTPUT)
696 info_flags |= MPU401_INFO_OUTPUT;
697 if (chip->model.device_config & MIDI_INPUT)
698 info_flags |= MPU401_INFO_INPUT;
699 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
700 chip->addr + OXYGEN_MPU401,
701 info_flags, -1, &chip->midi);
702 if (err < 0)
703 goto err_card;
704 }
705
706 oxygen_proc_init(chip);
707
708 spin_lock_irq(&chip->reg_lock);
709 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
710 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
711 if (chip->has_ac97_0 | chip->has_ac97_1)
712 chip->interrupt_mask |= OXYGEN_INT_AC97;
713 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
714 spin_unlock_irq(&chip->reg_lock);
715
716 err = snd_card_register(card);
717 if (err < 0)
718 goto err_card;
719
720 pci_set_drvdata(pci, card);
721 return 0;
722
723err_pci_regions:
724 pci_release_regions(pci);
725err_pci_enable:
726 pci_disable_device(pci);
727err_card:
728 snd_card_free(card);
729 return err;
730}
731EXPORT_SYMBOL(oxygen_pci_probe);
732
733void oxygen_pci_remove(struct pci_dev *pci)
734{
735 snd_card_free(pci_get_drvdata(pci));
736}
737EXPORT_SYMBOL(oxygen_pci_remove);
738
739#ifdef CONFIG_PM_SLEEP
740static int oxygen_pci_suspend(struct device *dev)
741{
742 struct snd_card *card = dev_get_drvdata(dev);
743 struct oxygen *chip = card->private_data;
744 unsigned int i, saved_interrupt_mask;
745
746 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
747
748 for (i = 0; i < PCM_COUNT; ++i)
749 snd_pcm_suspend(chip->streams[i]);
750
751 if (chip->model.suspend)
752 chip->model.suspend(chip);
753
754 spin_lock_irq(&chip->reg_lock);
755 saved_interrupt_mask = chip->interrupt_mask;
756 chip->interrupt_mask = 0;
757 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
758 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
759 spin_unlock_irq(&chip->reg_lock);
760
761 synchronize_irq(chip->irq);
762 flush_work(&chip->spdif_input_bits_work);
763 flush_work(&chip->gpio_work);
764 chip->interrupt_mask = saved_interrupt_mask;
765 return 0;
766}
767
768static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
769 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
770 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
771};
772static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
773 { 0x18284fa2, 0x03060000 },
774 { 0x00007fa6, 0x00200000 }
775};
776
777static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
778{
779 return bitmap[bit / 32] & (1 << (bit & 31));
780}
781
782static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
783{
784 unsigned int i;
785
786 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
787 msleep(1);
788 for (i = 1; i < 0x40; ++i)
789 if (is_bit_set(ac97_registers_to_restore[codec], i))
790 oxygen_write_ac97(chip, codec, i * 2,
791 chip->saved_ac97_registers[codec][i]);
792}
793
794static int oxygen_pci_resume(struct device *dev)
795{
796 struct snd_card *card = dev_get_drvdata(dev);
797 struct oxygen *chip = card->private_data;
798 unsigned int i;
799
800 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
801 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
802 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
803 if (is_bit_set(registers_to_restore, i))
804 oxygen_write8(chip, i, chip->saved_registers._8[i]);
805 if (chip->has_ac97_0)
806 oxygen_restore_ac97(chip, 0);
807 if (chip->has_ac97_1)
808 oxygen_restore_ac97(chip, 1);
809
810 if (chip->model.resume)
811 chip->model.resume(chip);
812
813 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
814
815 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
816 return 0;
817}
818
819SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume);
820EXPORT_SYMBOL(oxygen_pci_pm);
821#endif
822
823void oxygen_pci_shutdown(struct pci_dev *pci)
824{
825 struct snd_card *card = pci_get_drvdata(pci);
826 struct oxygen *chip = card->private_data;
827
828 oxygen_shutdown(chip);
829 chip->model.cleanup(chip);
830}
831EXPORT_SYMBOL(oxygen_pci_shutdown);
832
