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12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
19#include <linux/i2c-gpio.h>
20#include <linux/atmel-mci.h>
21#include <linux/platform_data/crypto-atmel.h>
22
23#include <linux/platform_data/at91_adc.h>
24
25#include <linux/fb.h>
26#include <video/atmel_lcdc.h>
27
28#include <mach/at91_adc.h>
29#include <mach/at91sam9g45.h>
30#include <mach/at91sam9g45_matrix.h>
31#include <mach/at91_matrix.h>
32#include <mach/at91sam9_smc.h>
33#include <linux/platform_data/dma-atmel.h>
34#include <mach/atmel-mci.h>
35
36#include <media/atmel-isi.h>
37
38#include "board.h"
39#include "generic.h"
40#include "clock.h"
41
42
43
44
45
46
47#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
48static u64 hdmac_dmamask = DMA_BIT_MASK(32);
49
50static struct resource hdmac_resources[] = {
51 [0] = {
52 .start = AT91SAM9G45_BASE_DMA,
53 .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
54 .flags = IORESOURCE_MEM,
55 },
56 [1] = {
57 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
58 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
59 .flags = IORESOURCE_IRQ,
60 },
61};
62
63static struct platform_device at_hdmac_device = {
64 .name = "at91sam9g45_dma",
65 .id = -1,
66 .dev = {
67 .dma_mask = &hdmac_dmamask,
68 .coherent_dma_mask = DMA_BIT_MASK(32),
69 },
70 .resource = hdmac_resources,
71 .num_resources = ARRAY_SIZE(hdmac_resources),
72};
73
74void __init at91_add_device_hdmac(void)
75{
76 platform_device_register(&at_hdmac_device);
77}
78#else
79void __init at91_add_device_hdmac(void) {}
80#endif
81
82
83
84
85
86
87#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
88static u64 ohci_dmamask = DMA_BIT_MASK(32);
89static struct at91_usbh_data usbh_ohci_data;
90
91static struct resource usbh_ohci_resources[] = {
92 [0] = {
93 .start = AT91SAM9G45_OHCI_BASE,
94 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
95 .flags = IORESOURCE_MEM,
96 },
97 [1] = {
98 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
99 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
100 .flags = IORESOURCE_IRQ,
101 },
102};
103
104static struct platform_device at91_usbh_ohci_device = {
105 .name = "at91_ohci",
106 .id = -1,
107 .dev = {
108 .dma_mask = &ohci_dmamask,
109 .coherent_dma_mask = DMA_BIT_MASK(32),
110 .platform_data = &usbh_ohci_data,
111 },
112 .resource = usbh_ohci_resources,
113 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
114};
115
116void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
117{
118 int i;
119
120 if (!data)
121 return;
122
123
124 for (i = 0; i < data->ports; i++) {
125 if (gpio_is_valid(data->vbus_pin[i]))
126 at91_set_gpio_output(data->vbus_pin[i],
127 data->vbus_pin_active_low[i]);
128 }
129
130
131 for (i = 0; i < data->ports; i++) {
132 if (gpio_is_valid(data->overcurrent_pin[i]))
133 at91_set_gpio_input(data->overcurrent_pin[i], 1);
134 }
135
136 usbh_ohci_data = *data;
137 platform_device_register(&at91_usbh_ohci_device);
138}
139#else
140void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
141#endif
142
143
144
145
146
147
148
149#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
150static u64 ehci_dmamask = DMA_BIT_MASK(32);
151static struct at91_usbh_data usbh_ehci_data;
152
153static struct resource usbh_ehci_resources[] = {
154 [0] = {
155 .start = AT91SAM9G45_EHCI_BASE,
156 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
157 .flags = IORESOURCE_MEM,
158 },
159 [1] = {
160 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
161 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
162 .flags = IORESOURCE_IRQ,
163 },
164};
165
166static struct platform_device at91_usbh_ehci_device = {
167 .name = "atmel-ehci",
168 .id = -1,
169 .dev = {
170 .dma_mask = &ehci_dmamask,
171 .coherent_dma_mask = DMA_BIT_MASK(32),
172 .platform_data = &usbh_ehci_data,
173 },
174 .resource = usbh_ehci_resources,
175 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
176};
177
178void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
179{
180 int i;
181
182 if (!data)
183 return;
184
185
186 for (i = 0; i < data->ports; i++) {
187 if (gpio_is_valid(data->vbus_pin[i]))
188 at91_set_gpio_output(data->vbus_pin[i],
189 data->vbus_pin_active_low[i]);
190 }
191
192 usbh_ehci_data = *data;
193 platform_device_register(&at91_usbh_ehci_device);
194}
195#else
196void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
197#endif
198
199
200
201
202
203
204#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
205static struct resource usba_udc_resources[] = {
206 [0] = {
207 .start = AT91SAM9G45_UDPHS_FIFO,
208 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
209 .flags = IORESOURCE_MEM,
210 },
211 [1] = {
212 .start = AT91SAM9G45_BASE_UDPHS,
213 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
214 .flags = IORESOURCE_MEM,
215 },
216 [2] = {
217 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
218 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
223#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
224 [idx] = { \
225 .name = nam, \
226 .index = idx, \
227 .fifo_size = maxpkt, \
228 .nr_banks = maxbk, \
229 .can_dma = dma, \
230 .can_isoc = isoc, \
231 }
232
233static struct usba_ep_data usba_udc_ep[] __initdata = {
234 EP("ep0", 0, 64, 1, 0, 0),
235 EP("ep1", 1, 1024, 2, 1, 1),
236 EP("ep2", 2, 1024, 2, 1, 1),
237 EP("ep3", 3, 1024, 3, 1, 0),
238 EP("ep4", 4, 1024, 3, 1, 0),
239 EP("ep5", 5, 1024, 3, 1, 1),
240 EP("ep6", 6, 1024, 3, 1, 1),
241};
242
243#undef EP
244
245
246
247
248
249static struct {
250 struct usba_platform_data pdata;
251 struct usba_ep_data ep[7];
252} usba_udc_data;
253
254static struct platform_device at91_usba_udc_device = {
255 .name = "atmel_usba_udc",
256 .id = -1,
257 .dev = {
258 .platform_data = &usba_udc_data.pdata,
259 },
260 .resource = usba_udc_resources,
261 .num_resources = ARRAY_SIZE(usba_udc_resources),
262};
263
264void __init at91_add_device_usba(struct usba_platform_data *data)
265{
266 usba_udc_data.pdata.vbus_pin = -EINVAL;
267 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
268 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
269
270 if (data && gpio_is_valid(data->vbus_pin)) {
271 at91_set_gpio_input(data->vbus_pin, 0);
272 at91_set_deglitch(data->vbus_pin, 1);
273 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
274 }
275
276
277
278 platform_device_register(&at91_usba_udc_device);
279}
280#else
281void __init at91_add_device_usba(struct usba_platform_data *data) {}
282#endif
283
284
285
286
287
288
289#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
290static u64 eth_dmamask = DMA_BIT_MASK(32);
291static struct macb_platform_data eth_data;
292
293static struct resource eth_resources[] = {
294 [0] = {
295 .start = AT91SAM9G45_BASE_EMAC,
296 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
297 .flags = IORESOURCE_MEM,
298 },
299 [1] = {
300 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
301 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device at91sam9g45_eth_device = {
307 .name = "macb",
308 .id = -1,
309 .dev = {
310 .dma_mask = ð_dmamask,
311 .coherent_dma_mask = DMA_BIT_MASK(32),
312 .platform_data = ð_data,
313 },
314 .resource = eth_resources,
315 .num_resources = ARRAY_SIZE(eth_resources),
316};
317
318void __init at91_add_device_eth(struct macb_platform_data *data)
319{
320 if (!data)
321 return;
322
323 if (gpio_is_valid(data->phy_irq_pin)) {
324 at91_set_gpio_input(data->phy_irq_pin, 0);
325 at91_set_deglitch(data->phy_irq_pin, 1);
326 }
327
328
329 at91_set_A_periph(AT91_PIN_PA17, 0);
330 at91_set_A_periph(AT91_PIN_PA15, 0);
331 at91_set_A_periph(AT91_PIN_PA12, 0);
332 at91_set_A_periph(AT91_PIN_PA13, 0);
333 at91_set_A_periph(AT91_PIN_PA16, 0);
334 at91_set_A_periph(AT91_PIN_PA14, 0);
335 at91_set_A_periph(AT91_PIN_PA10, 0);
336 at91_set_A_periph(AT91_PIN_PA11, 0);
337 at91_set_A_periph(AT91_PIN_PA19, 0);
338 at91_set_A_periph(AT91_PIN_PA18, 0);
339
340 if (!data->is_rmii) {
341 at91_set_B_periph(AT91_PIN_PA29, 0);
342 at91_set_B_periph(AT91_PIN_PA30, 0);
343 at91_set_B_periph(AT91_PIN_PA8, 0);
344 at91_set_B_periph(AT91_PIN_PA9, 0);
345 at91_set_B_periph(AT91_PIN_PA28, 0);
346 at91_set_B_periph(AT91_PIN_PA6, 0);
347 at91_set_B_periph(AT91_PIN_PA7, 0);
348 at91_set_B_periph(AT91_PIN_PA27, 0);
349 }
350
351 eth_data = *data;
352 platform_device_register(&at91sam9g45_eth_device);
353}
354#else
355void __init at91_add_device_eth(struct macb_platform_data *data) {}
356#endif
357
358
359
360
361
362
363#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
364static u64 mmc_dmamask = DMA_BIT_MASK(32);
365static struct mci_platform_data mmc0_data, mmc1_data;
366
367static struct resource mmc0_resources[] = {
368 [0] = {
369 .start = AT91SAM9G45_BASE_MCI0,
370 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
371 .flags = IORESOURCE_MEM,
372 },
373 [1] = {
374 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
375 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
376 .flags = IORESOURCE_IRQ,
377 },
378};
379
380static struct platform_device at91sam9g45_mmc0_device = {
381 .name = "atmel_mci",
382 .id = 0,
383 .dev = {
384 .dma_mask = &mmc_dmamask,
385 .coherent_dma_mask = DMA_BIT_MASK(32),
386 .platform_data = &mmc0_data,
387 },
388 .resource = mmc0_resources,
389 .num_resources = ARRAY_SIZE(mmc0_resources),
390};
391
392static struct resource mmc1_resources[] = {
393 [0] = {
394 .start = AT91SAM9G45_BASE_MCI1,
395 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
396 .flags = IORESOURCE_MEM,
397 },
398 [1] = {
399 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
400 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
401 .flags = IORESOURCE_IRQ,
402 },
403};
404
405static struct platform_device at91sam9g45_mmc1_device = {
406 .name = "atmel_mci",
407 .id = 1,
408 .dev = {
409 .dma_mask = &mmc_dmamask,
410 .coherent_dma_mask = DMA_BIT_MASK(32),
411 .platform_data = &mmc1_data,
412 },
413 .resource = mmc1_resources,
414 .num_resources = ARRAY_SIZE(mmc1_resources),
415};
416
417
418void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
419{
420
421 if (!data)
422 return;
423
424
425 if (!data->slot[0].bus_width)
426 return;
427
428#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
429 {
430 struct at_dma_slave *atslave;
431 struct mci_dma_data *alt_atslave;
432
433 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
434 atslave = &alt_atslave->sdata;
435
436
437 atslave->dma_dev = &at_hdmac_device.dev;
438 atslave->cfg = ATC_FIFOCFG_HALFFIFO
439 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
440 if (mmc_id == 0)
441 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
442 | ATC_DST_PER(AT_DMA_ID_MCI0);
443
444 else
445 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
446 | ATC_DST_PER(AT_DMA_ID_MCI1);
447
448 data->dma_slave = alt_atslave;
449 }
450#endif
451
452
453
454 if (gpio_is_valid(data->slot[0].detect_pin)) {
455 at91_set_gpio_input(data->slot[0].detect_pin, 1);
456 at91_set_deglitch(data->slot[0].detect_pin, 1);
457 }
458 if (gpio_is_valid(data->slot[0].wp_pin))
459 at91_set_gpio_input(data->slot[0].wp_pin, 1);
460
461 if (mmc_id == 0) {
462
463
464 at91_set_A_periph(AT91_PIN_PA0, 0);
465
466
467 at91_set_A_periph(AT91_PIN_PA1, 1);
468
469
470 at91_set_A_periph(AT91_PIN_PA2, 1);
471 if (data->slot[0].bus_width == 4) {
472 at91_set_A_periph(AT91_PIN_PA3, 1);
473 at91_set_A_periph(AT91_PIN_PA4, 1);
474 at91_set_A_periph(AT91_PIN_PA5, 1);
475 if (data->slot[0].bus_width == 8) {
476 at91_set_A_periph(AT91_PIN_PA6, 1);
477 at91_set_A_periph(AT91_PIN_PA7, 1);
478 at91_set_A_periph(AT91_PIN_PA8, 1);
479 at91_set_A_periph(AT91_PIN_PA9, 1);
480 }
481 }
482
483 mmc0_data = *data;
484 platform_device_register(&at91sam9g45_mmc0_device);
485
486 } else {
487
488
489 at91_set_A_periph(AT91_PIN_PA31, 0);
490
491
492 at91_set_A_periph(AT91_PIN_PA22, 1);
493
494
495 at91_set_A_periph(AT91_PIN_PA23, 1);
496 if (data->slot[0].bus_width == 4) {
497 at91_set_A_periph(AT91_PIN_PA24, 1);
498 at91_set_A_periph(AT91_PIN_PA25, 1);
499 at91_set_A_periph(AT91_PIN_PA26, 1);
500 if (data->slot[0].bus_width == 8) {
501 at91_set_A_periph(AT91_PIN_PA27, 1);
502 at91_set_A_periph(AT91_PIN_PA28, 1);
503 at91_set_A_periph(AT91_PIN_PA29, 1);
504 at91_set_A_periph(AT91_PIN_PA30, 1);
505 }
506 }
507
508 mmc1_data = *data;
509 platform_device_register(&at91sam9g45_mmc1_device);
510
511 }
512}
513#else
514void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
515#endif
516
517
518
519
520
521
522#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
523static struct atmel_nand_data nand_data;
524
525#define NAND_BASE AT91_CHIPSELECT_3
526
527static struct resource nand_resources[] = {
528 [0] = {
529 .start = NAND_BASE,
530 .end = NAND_BASE + SZ_256M - 1,
531 .flags = IORESOURCE_MEM,
532 },
533 [1] = {
534 .start = AT91SAM9G45_BASE_ECC,
535 .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
536 .flags = IORESOURCE_MEM,
537 }
538};
539
540static struct platform_device at91sam9g45_nand_device = {
541 .name = "atmel_nand",
542 .id = -1,
543 .dev = {
544 .platform_data = &nand_data,
545 },
546 .resource = nand_resources,
547 .num_resources = ARRAY_SIZE(nand_resources),
548};
549
550void __init at91_add_device_nand(struct atmel_nand_data *data)
551{
552 unsigned long csa;
553
554 if (!data)
555 return;
556
557 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
558 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
559
560
561 if (gpio_is_valid(data->enable_pin))
562 at91_set_gpio_output(data->enable_pin, 1);
563
564
565 if (gpio_is_valid(data->rdy_pin))
566 at91_set_gpio_input(data->rdy_pin, 1);
567
568
569 if (gpio_is_valid(data->det_pin))
570 at91_set_gpio_input(data->det_pin, 1);
571
572 nand_data = *data;
573 platform_device_register(&at91sam9g45_nand_device);
574}
575#else
576void __init at91_add_device_nand(struct atmel_nand_data *data) {}
577#endif
578
579
580
581
582
583
584
585
586
587
588
589#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
590static struct i2c_gpio_platform_data pdata_i2c0 = {
591 .sda_pin = AT91_PIN_PA20,
592 .sda_is_open_drain = 1,
593 .scl_pin = AT91_PIN_PA21,
594 .scl_is_open_drain = 1,
595 .udelay = 5,
596};
597
598static struct platform_device at91sam9g45_twi0_device = {
599 .name = "i2c-gpio",
600 .id = 0,
601 .dev.platform_data = &pdata_i2c0,
602};
603
604static struct i2c_gpio_platform_data pdata_i2c1 = {
605 .sda_pin = AT91_PIN_PB10,
606 .sda_is_open_drain = 1,
607 .scl_pin = AT91_PIN_PB11,
608 .scl_is_open_drain = 1,
609 .udelay = 5,
610};
611
612static struct platform_device at91sam9g45_twi1_device = {
613 .name = "i2c-gpio",
614 .id = 1,
615 .dev.platform_data = &pdata_i2c1,
616};
617
618void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
619{
620 i2c_register_board_info(i2c_id, devices, nr_devices);
621
622 if (i2c_id == 0) {
623 at91_set_GPIO_periph(AT91_PIN_PA20, 1);
624 at91_set_multi_drive(AT91_PIN_PA20, 1);
625
626 at91_set_GPIO_periph(AT91_PIN_PA21, 1);
627 at91_set_multi_drive(AT91_PIN_PA21, 1);
628
629 platform_device_register(&at91sam9g45_twi0_device);
630 } else {
631 at91_set_GPIO_periph(AT91_PIN_PB10, 1);
632 at91_set_multi_drive(AT91_PIN_PB10, 1);
633
634 at91_set_GPIO_periph(AT91_PIN_PB11, 1);
635 at91_set_multi_drive(AT91_PIN_PB11, 1);
636
637 platform_device_register(&at91sam9g45_twi1_device);
638 }
639}
640
641#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
642static struct resource twi0_resources[] = {
643 [0] = {
644 .start = AT91SAM9G45_BASE_TWI0,
645 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
646 .flags = IORESOURCE_MEM,
647 },
648 [1] = {
649 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
650 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
651 .flags = IORESOURCE_IRQ,
652 },
653};
654
655static struct platform_device at91sam9g45_twi0_device = {
656 .name = "i2c-at91sam9g10",
657 .id = 0,
658 .resource = twi0_resources,
659 .num_resources = ARRAY_SIZE(twi0_resources),
660};
661
662static struct resource twi1_resources[] = {
663 [0] = {
664 .start = AT91SAM9G45_BASE_TWI1,
665 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
666 .flags = IORESOURCE_MEM,
667 },
668 [1] = {
669 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
670 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
671 .flags = IORESOURCE_IRQ,
672 },
673};
674
675static struct platform_device at91sam9g45_twi1_device = {
676 .name = "i2c-at91sam9g10",
677 .id = 1,
678 .resource = twi1_resources,
679 .num_resources = ARRAY_SIZE(twi1_resources),
680};
681
682void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
683{
684 i2c_register_board_info(i2c_id, devices, nr_devices);
685
686
687 if (i2c_id == 0) {
688 at91_set_A_periph(AT91_PIN_PA20, 0);
689 at91_set_A_periph(AT91_PIN_PA21, 0);
690
691 platform_device_register(&at91sam9g45_twi0_device);
692 } else {
693 at91_set_A_periph(AT91_PIN_PB10, 0);
694 at91_set_A_periph(AT91_PIN_PB11, 0);
695
696 platform_device_register(&at91sam9g45_twi1_device);
697 }
698}
699#else
700void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
701#endif
702
703
704
705
706
707
708#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
709static u64 spi_dmamask = DMA_BIT_MASK(32);
710
711static struct resource spi0_resources[] = {
712 [0] = {
713 .start = AT91SAM9G45_BASE_SPI0,
714 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
715 .flags = IORESOURCE_MEM,
716 },
717 [1] = {
718 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
719 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
720 .flags = IORESOURCE_IRQ,
721 },
722};
723
724static struct platform_device at91sam9g45_spi0_device = {
725 .name = "atmel_spi",
726 .id = 0,
727 .dev = {
728 .dma_mask = &spi_dmamask,
729 .coherent_dma_mask = DMA_BIT_MASK(32),
730 },
731 .resource = spi0_resources,
732 .num_resources = ARRAY_SIZE(spi0_resources),
733};
734
735static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
736
737static struct resource spi1_resources[] = {
738 [0] = {
739 .start = AT91SAM9G45_BASE_SPI1,
740 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
741 .flags = IORESOURCE_MEM,
742 },
743 [1] = {
744 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
745 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
746 .flags = IORESOURCE_IRQ,
747 },
748};
749
750static struct platform_device at91sam9g45_spi1_device = {
751 .name = "atmel_spi",
752 .id = 1,
753 .dev = {
754 .dma_mask = &spi_dmamask,
755 .coherent_dma_mask = DMA_BIT_MASK(32),
756 },
757 .resource = spi1_resources,
758 .num_resources = ARRAY_SIZE(spi1_resources),
759};
760
761static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
762
763void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
764{
765 int i;
766 unsigned long cs_pin;
767 short enable_spi0 = 0;
768 short enable_spi1 = 0;
769
770
771 for (i = 0; i < nr_devices; i++) {
772 if (devices[i].controller_data)
773 cs_pin = (unsigned long) devices[i].controller_data;
774 else if (devices[i].bus_num == 0)
775 cs_pin = spi0_standard_cs[devices[i].chip_select];
776 else
777 cs_pin = spi1_standard_cs[devices[i].chip_select];
778
779 if (!gpio_is_valid(cs_pin))
780 continue;
781
782 if (devices[i].bus_num == 0)
783 enable_spi0 = 1;
784 else
785 enable_spi1 = 1;
786
787
788 at91_set_gpio_output(cs_pin, 1);
789
790
791 devices[i].controller_data = (void *) cs_pin;
792 }
793
794 spi_register_board_info(devices, nr_devices);
795
796
797 if (enable_spi0) {
798 at91_set_A_periph(AT91_PIN_PB0, 0);
799 at91_set_A_periph(AT91_PIN_PB1, 0);
800 at91_set_A_periph(AT91_PIN_PB2, 0);
801
802 platform_device_register(&at91sam9g45_spi0_device);
803 }
804 if (enable_spi1) {
805 at91_set_A_periph(AT91_PIN_PB14, 0);
806 at91_set_A_periph(AT91_PIN_PB15, 0);
807 at91_set_A_periph(AT91_PIN_PB16, 0);
808
809 platform_device_register(&at91sam9g45_spi1_device);
810 }
811}
812#else
813void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
814#endif
815
816
817
818
819
820
821#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
822static u64 ac97_dmamask = DMA_BIT_MASK(32);
823static struct ac97c_platform_data ac97_data;
824
825static struct resource ac97_resources[] = {
826 [0] = {
827 .start = AT91SAM9G45_BASE_AC97C,
828 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
829 .flags = IORESOURCE_MEM,
830 },
831 [1] = {
832 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
833 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
834 .flags = IORESOURCE_IRQ,
835 },
836};
837
838static struct platform_device at91sam9g45_ac97_device = {
839 .name = "atmel_ac97c",
840 .id = 0,
841 .dev = {
842 .dma_mask = &ac97_dmamask,
843 .coherent_dma_mask = DMA_BIT_MASK(32),
844 .platform_data = &ac97_data,
845 },
846 .resource = ac97_resources,
847 .num_resources = ARRAY_SIZE(ac97_resources),
848};
849
850void __init at91_add_device_ac97(struct ac97c_platform_data *data)
851{
852 if (!data)
853 return;
854
855 at91_set_A_periph(AT91_PIN_PD8, 0);
856 at91_set_A_periph(AT91_PIN_PD9, 0);
857 at91_set_A_periph(AT91_PIN_PD7, 0);
858 at91_set_A_periph(AT91_PIN_PD6, 0);
859
860
861 if (gpio_is_valid(data->reset_pin))
862 at91_set_gpio_output(data->reset_pin, 0);
863
864 ac97_data = *data;
865 platform_device_register(&at91sam9g45_ac97_device);
866}
867#else
868void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
869#endif
870
871
872
873
874#if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
875static u64 isi_dmamask = DMA_BIT_MASK(32);
876static struct isi_platform_data isi_data;
877
878struct resource isi_resources[] = {
879 [0] = {
880 .start = AT91SAM9G45_BASE_ISI,
881 .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
882 .flags = IORESOURCE_MEM,
883 },
884 [1] = {
885 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
886 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
887 .flags = IORESOURCE_IRQ,
888 },
889};
890
891static struct platform_device at91sam9g45_isi_device = {
892 .name = "atmel_isi",
893 .id = 0,
894 .dev = {
895 .dma_mask = &isi_dmamask,
896 .coherent_dma_mask = DMA_BIT_MASK(32),
897 .platform_data = &isi_data,
898 },
899 .resource = isi_resources,
900 .num_resources = ARRAY_SIZE(isi_resources),
901};
902
903static struct clk_lookup isi_mck_lookups[] = {
904 CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
905};
906
907void __init at91_add_device_isi(struct isi_platform_data *data,
908 bool use_pck_as_mck)
909{
910 struct clk *pck;
911 struct clk *parent;
912
913 if (!data)
914 return;
915 isi_data = *data;
916
917 at91_set_A_periph(AT91_PIN_PB20, 0);
918 at91_set_A_periph(AT91_PIN_PB21, 0);
919 at91_set_A_periph(AT91_PIN_PB22, 0);
920 at91_set_A_periph(AT91_PIN_PB23, 0);
921 at91_set_A_periph(AT91_PIN_PB24, 0);
922 at91_set_A_periph(AT91_PIN_PB25, 0);
923 at91_set_A_periph(AT91_PIN_PB26, 0);
924 at91_set_A_periph(AT91_PIN_PB27, 0);
925 at91_set_A_periph(AT91_PIN_PB28, 0);
926 at91_set_A_periph(AT91_PIN_PB30, 0);
927 at91_set_A_periph(AT91_PIN_PB29, 0);
928 at91_set_B_periph(AT91_PIN_PB8, 0);
929 at91_set_B_periph(AT91_PIN_PB9, 0);
930 at91_set_B_periph(AT91_PIN_PB10, 0);
931 at91_set_B_periph(AT91_PIN_PB11, 0);
932
933 platform_device_register(&at91sam9g45_isi_device);
934
935 if (use_pck_as_mck) {
936 at91_set_B_periph(AT91_PIN_PB31, 0);
937
938 pck = clk_get(NULL, "pck1");
939 parent = clk_get(NULL, "plla");
940
941 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
942
943 if (clk_set_parent(pck, parent)) {
944 pr_err("Failed to set PCK's parent\n");
945 } else {
946
947 isi_mck_lookups[0].clk = pck;
948 clkdev_add_table(isi_mck_lookups,
949 ARRAY_SIZE(isi_mck_lookups));
950 }
951
952 clk_put(pck);
953 clk_put(parent);
954 }
955}
956#else
957void __init at91_add_device_isi(struct isi_platform_data *data,
958 bool use_pck_as_mck) {}
959#endif
960
961
962
963
964
965
966#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
967static u64 lcdc_dmamask = DMA_BIT_MASK(32);
968static struct atmel_lcdfb_info lcdc_data;
969
970static struct resource lcdc_resources[] = {
971 [0] = {
972 .start = AT91SAM9G45_LCDC_BASE,
973 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
974 .flags = IORESOURCE_MEM,
975 },
976 [1] = {
977 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
978 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
979 .flags = IORESOURCE_IRQ,
980 },
981};
982
983static struct platform_device at91_lcdc_device = {
984 .id = 0,
985 .dev = {
986 .dma_mask = &lcdc_dmamask,
987 .coherent_dma_mask = DMA_BIT_MASK(32),
988 .platform_data = &lcdc_data,
989 },
990 .resource = lcdc_resources,
991 .num_resources = ARRAY_SIZE(lcdc_resources),
992};
993
994void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
995{
996 if (!data)
997 return;
998
999 if (cpu_is_at91sam9g45es())
1000 at91_lcdc_device.name = "at91sam9g45es-lcdfb";
1001 else
1002 at91_lcdc_device.name = "at91sam9g45-lcdfb";
1003
1004 at91_set_A_periph(AT91_PIN_PE0, 0);
1005
1006 at91_set_A_periph(AT91_PIN_PE2, 0);
1007 at91_set_A_periph(AT91_PIN_PE3, 0);
1008 at91_set_A_periph(AT91_PIN_PE4, 0);
1009 at91_set_A_periph(AT91_PIN_PE5, 0);
1010 at91_set_A_periph(AT91_PIN_PE6, 0);
1011 at91_set_A_periph(AT91_PIN_PE7, 0);
1012 at91_set_A_periph(AT91_PIN_PE8, 0);
1013 at91_set_A_periph(AT91_PIN_PE9, 0);
1014 at91_set_A_periph(AT91_PIN_PE10, 0);
1015 at91_set_A_periph(AT91_PIN_PE11, 0);
1016 at91_set_A_periph(AT91_PIN_PE12, 0);
1017 at91_set_A_periph(AT91_PIN_PE13, 0);
1018 at91_set_A_periph(AT91_PIN_PE14, 0);
1019 at91_set_A_periph(AT91_PIN_PE15, 0);
1020 at91_set_A_periph(AT91_PIN_PE16, 0);
1021 at91_set_A_periph(AT91_PIN_PE17, 0);
1022 at91_set_A_periph(AT91_PIN_PE18, 0);
1023 at91_set_A_periph(AT91_PIN_PE19, 0);
1024 at91_set_A_periph(AT91_PIN_PE20, 0);
1025 at91_set_A_periph(AT91_PIN_PE21, 0);
1026 at91_set_A_periph(AT91_PIN_PE22, 0);
1027 at91_set_A_periph(AT91_PIN_PE23, 0);
1028 at91_set_A_periph(AT91_PIN_PE24, 0);
1029 at91_set_A_periph(AT91_PIN_PE25, 0);
1030 at91_set_A_periph(AT91_PIN_PE26, 0);
1031 at91_set_A_periph(AT91_PIN_PE27, 0);
1032 at91_set_A_periph(AT91_PIN_PE28, 0);
1033 at91_set_A_periph(AT91_PIN_PE29, 0);
1034 at91_set_A_periph(AT91_PIN_PE30, 0);
1035
1036 lcdc_data = *data;
1037 platform_device_register(&at91_lcdc_device);
1038}
1039#else
1040void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1041#endif
1042
1043
1044
1045
1046
1047
1048#ifdef CONFIG_ATMEL_TCLIB
1049static struct resource tcb0_resources[] = {
1050 [0] = {
1051 .start = AT91SAM9G45_BASE_TCB0,
1052 .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1053 .flags = IORESOURCE_MEM,
1054 },
1055 [1] = {
1056 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1057 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1058 .flags = IORESOURCE_IRQ,
1059 },
1060};
1061
1062static struct platform_device at91sam9g45_tcb0_device = {
1063 .name = "atmel_tcb",
1064 .id = 0,
1065 .resource = tcb0_resources,
1066 .num_resources = ARRAY_SIZE(tcb0_resources),
1067};
1068
1069
1070static struct resource tcb1_resources[] = {
1071 [0] = {
1072 .start = AT91SAM9G45_BASE_TCB1,
1073 .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1074 .flags = IORESOURCE_MEM,
1075 },
1076 [1] = {
1077 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1078 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1079 .flags = IORESOURCE_IRQ,
1080 },
1081};
1082
1083static struct platform_device at91sam9g45_tcb1_device = {
1084 .name = "atmel_tcb",
1085 .id = 1,
1086 .resource = tcb1_resources,
1087 .num_resources = ARRAY_SIZE(tcb1_resources),
1088};
1089
1090static void __init at91_add_device_tc(void)
1091{
1092 platform_device_register(&at91sam9g45_tcb0_device);
1093 platform_device_register(&at91sam9g45_tcb1_device);
1094}
1095#else
1096static void __init at91_add_device_tc(void) { }
1097#endif
1098
1099
1100
1101
1102
1103
1104#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1105static struct resource rtc_resources[] = {
1106 [0] = {
1107 .start = AT91SAM9G45_BASE_RTC,
1108 .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1109 .flags = IORESOURCE_MEM,
1110 },
1111 [1] = {
1112 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1113 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1114 .flags = IORESOURCE_IRQ,
1115 },
1116};
1117
1118static struct platform_device at91sam9g45_rtc_device = {
1119 .name = "at91_rtc",
1120 .id = -1,
1121 .resource = rtc_resources,
1122 .num_resources = ARRAY_SIZE(rtc_resources),
1123};
1124
1125static void __init at91_add_device_rtc(void)
1126{
1127 platform_device_register(&at91sam9g45_rtc_device);
1128}
1129#else
1130static void __init at91_add_device_rtc(void) {}
1131#endif
1132
1133
1134
1135
1136
1137
1138#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1139static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1140static struct at91_tsadcc_data tsadcc_data;
1141
1142static struct resource tsadcc_resources[] = {
1143 [0] = {
1144 .start = AT91SAM9G45_BASE_TSC,
1145 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1146 .flags = IORESOURCE_MEM,
1147 },
1148 [1] = {
1149 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1150 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1151 .flags = IORESOURCE_IRQ,
1152 }
1153};
1154
1155static struct platform_device at91sam9g45_tsadcc_device = {
1156 .name = "atmel_tsadcc",
1157 .id = -1,
1158 .dev = {
1159 .dma_mask = &tsadcc_dmamask,
1160 .coherent_dma_mask = DMA_BIT_MASK(32),
1161 .platform_data = &tsadcc_data,
1162 },
1163 .resource = tsadcc_resources,
1164 .num_resources = ARRAY_SIZE(tsadcc_resources),
1165};
1166
1167void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1168{
1169 if (!data)
1170 return;
1171
1172 at91_set_gpio_input(AT91_PIN_PD20, 0);
1173 at91_set_gpio_input(AT91_PIN_PD21, 0);
1174 at91_set_gpio_input(AT91_PIN_PD22, 0);
1175 at91_set_gpio_input(AT91_PIN_PD23, 0);
1176
1177 tsadcc_data = *data;
1178 platform_device_register(&at91sam9g45_tsadcc_device);
1179}
1180#else
1181void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1182#endif
1183
1184
1185
1186
1187
1188
1189#if IS_ENABLED(CONFIG_AT91_ADC)
1190static struct at91_adc_data adc_data;
1191
1192static struct resource adc_resources[] = {
1193 [0] = {
1194 .start = AT91SAM9G45_BASE_TSC,
1195 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1196 .flags = IORESOURCE_MEM,
1197 },
1198 [1] = {
1199 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1200 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1201 .flags = IORESOURCE_IRQ,
1202 }
1203};
1204
1205static struct platform_device at91_adc_device = {
1206 .name = "at91_adc",
1207 .id = -1,
1208 .dev = {
1209 .platform_data = &adc_data,
1210 },
1211 .resource = adc_resources,
1212 .num_resources = ARRAY_SIZE(adc_resources),
1213};
1214
1215static struct at91_adc_trigger at91_adc_triggers[] = {
1216 [0] = {
1217 .name = "external-rising",
1218 .value = 1,
1219 .is_external = true,
1220 },
1221 [1] = {
1222 .name = "external-falling",
1223 .value = 2,
1224 .is_external = true,
1225 },
1226 [2] = {
1227 .name = "external-any",
1228 .value = 3,
1229 .is_external = true,
1230 },
1231 [3] = {
1232 .name = "continuous",
1233 .value = 6,
1234 .is_external = false,
1235 },
1236};
1237
1238static struct at91_adc_reg_desc at91_adc_register_g45 = {
1239 .channel_base = AT91_ADC_CHR(0),
1240 .drdy_mask = AT91_ADC_DRDY,
1241 .status_register = AT91_ADC_SR,
1242 .trigger_register = 0x08,
1243};
1244
1245void __init at91_add_device_adc(struct at91_adc_data *data)
1246{
1247 if (!data)
1248 return;
1249
1250 if (test_bit(0, &data->channels_used))
1251 at91_set_gpio_input(AT91_PIN_PD20, 0);
1252 if (test_bit(1, &data->channels_used))
1253 at91_set_gpio_input(AT91_PIN_PD21, 0);
1254 if (test_bit(2, &data->channels_used))
1255 at91_set_gpio_input(AT91_PIN_PD22, 0);
1256 if (test_bit(3, &data->channels_used))
1257 at91_set_gpio_input(AT91_PIN_PD23, 0);
1258 if (test_bit(4, &data->channels_used))
1259 at91_set_gpio_input(AT91_PIN_PD24, 0);
1260 if (test_bit(5, &data->channels_used))
1261 at91_set_gpio_input(AT91_PIN_PD25, 0);
1262 if (test_bit(6, &data->channels_used))
1263 at91_set_gpio_input(AT91_PIN_PD26, 0);
1264 if (test_bit(7, &data->channels_used))
1265 at91_set_gpio_input(AT91_PIN_PD27, 0);
1266
1267 if (data->use_external_triggers)
1268 at91_set_A_periph(AT91_PIN_PD28, 0);
1269
1270 data->num_channels = 8;
1271 data->startup_time = 40;
1272 data->registers = &at91_adc_register_g45;
1273 data->trigger_number = 4;
1274 data->trigger_list = at91_adc_triggers;
1275
1276 adc_data = *data;
1277 platform_device_register(&at91_adc_device);
1278}
1279#else
1280void __init at91_add_device_adc(struct at91_adc_data *data) {}
1281#endif
1282
1283
1284
1285
1286
1287static struct resource rtt_resources[] = {
1288 {
1289 .start = AT91SAM9G45_BASE_RTT,
1290 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1291 .flags = IORESOURCE_MEM,
1292 }, {
1293 .flags = IORESOURCE_MEM,
1294 }, {
1295 .flags = IORESOURCE_IRQ,
1296 }
1297};
1298
1299static struct platform_device at91sam9g45_rtt_device = {
1300 .name = "at91_rtt",
1301 .id = 0,
1302 .resource = rtt_resources,
1303};
1304
1305#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1306static void __init at91_add_device_rtt_rtc(void)
1307{
1308 at91sam9g45_rtt_device.name = "rtc-at91sam9";
1309
1310
1311
1312
1313 at91sam9g45_rtt_device.num_resources = 3;
1314 rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1315 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1316 rtt_resources[1].end = rtt_resources[1].start + 3;
1317 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
1318 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
1319}
1320#else
1321static void __init at91_add_device_rtt_rtc(void)
1322{
1323
1324 at91sam9g45_rtt_device.num_resources = 1;
1325}
1326#endif
1327
1328static void __init at91_add_device_rtt(void)
1329{
1330 at91_add_device_rtt_rtc();
1331 platform_device_register(&at91sam9g45_rtt_device);
1332}
1333
1334
1335
1336
1337
1338
1339#if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1340static struct resource trng_resources[] = {
1341 {
1342 .start = AT91SAM9G45_BASE_TRNG,
1343 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1344 .flags = IORESOURCE_MEM,
1345 },
1346};
1347
1348static struct platform_device at91sam9g45_trng_device = {
1349 .name = "atmel-trng",
1350 .id = -1,
1351 .resource = trng_resources,
1352 .num_resources = ARRAY_SIZE(trng_resources),
1353};
1354
1355static void __init at91_add_device_trng(void)
1356{
1357 platform_device_register(&at91sam9g45_trng_device);
1358}
1359#else
1360static void __init at91_add_device_trng(void) {}
1361#endif
1362
1363
1364
1365
1366
1367#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1368static struct resource wdt_resources[] = {
1369 {
1370 .start = AT91SAM9G45_BASE_WDT,
1371 .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1372 .flags = IORESOURCE_MEM,
1373 }
1374};
1375
1376static struct platform_device at91sam9g45_wdt_device = {
1377 .name = "at91_wdt",
1378 .id = -1,
1379 .resource = wdt_resources,
1380 .num_resources = ARRAY_SIZE(wdt_resources),
1381};
1382
1383static void __init at91_add_device_watchdog(void)
1384{
1385 platform_device_register(&at91sam9g45_wdt_device);
1386}
1387#else
1388static void __init at91_add_device_watchdog(void) {}
1389#endif
1390
1391
1392
1393
1394
1395
1396#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1397static u32 pwm_mask;
1398
1399static struct resource pwm_resources[] = {
1400 [0] = {
1401 .start = AT91SAM9G45_BASE_PWMC,
1402 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1403 .flags = IORESOURCE_MEM,
1404 },
1405 [1] = {
1406 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1407 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1408 .flags = IORESOURCE_IRQ,
1409 },
1410};
1411
1412static struct platform_device at91sam9g45_pwm0_device = {
1413 .name = "atmel_pwm",
1414 .id = -1,
1415 .dev = {
1416 .platform_data = &pwm_mask,
1417 },
1418 .resource = pwm_resources,
1419 .num_resources = ARRAY_SIZE(pwm_resources),
1420};
1421
1422void __init at91_add_device_pwm(u32 mask)
1423{
1424 if (mask & (1 << AT91_PWM0))
1425 at91_set_B_periph(AT91_PIN_PD24, 1);
1426
1427 if (mask & (1 << AT91_PWM1))
1428 at91_set_B_periph(AT91_PIN_PD31, 1);
1429
1430 if (mask & (1 << AT91_PWM2))
1431 at91_set_B_periph(AT91_PIN_PD26, 1);
1432
1433 if (mask & (1 << AT91_PWM3))
1434 at91_set_B_periph(AT91_PIN_PD0, 1);
1435
1436 pwm_mask = mask;
1437
1438 platform_device_register(&at91sam9g45_pwm0_device);
1439}
1440#else
1441void __init at91_add_device_pwm(u32 mask) {}
1442#endif
1443
1444
1445
1446
1447
1448
1449#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1450static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1451
1452static struct resource ssc0_resources[] = {
1453 [0] = {
1454 .start = AT91SAM9G45_BASE_SSC0,
1455 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1456 .flags = IORESOURCE_MEM,
1457 },
1458 [1] = {
1459 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1460 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1461 .flags = IORESOURCE_IRQ,
1462 },
1463};
1464
1465static struct platform_device at91sam9g45_ssc0_device = {
1466 .name = "at91sam9g45_ssc",
1467 .id = 0,
1468 .dev = {
1469 .dma_mask = &ssc0_dmamask,
1470 .coherent_dma_mask = DMA_BIT_MASK(32),
1471 },
1472 .resource = ssc0_resources,
1473 .num_resources = ARRAY_SIZE(ssc0_resources),
1474};
1475
1476static inline void configure_ssc0_pins(unsigned pins)
1477{
1478 if (pins & ATMEL_SSC_TF)
1479 at91_set_A_periph(AT91_PIN_PD1, 1);
1480 if (pins & ATMEL_SSC_TK)
1481 at91_set_A_periph(AT91_PIN_PD0, 1);
1482 if (pins & ATMEL_SSC_TD)
1483 at91_set_A_periph(AT91_PIN_PD2, 1);
1484 if (pins & ATMEL_SSC_RD)
1485 at91_set_A_periph(AT91_PIN_PD3, 1);
1486 if (pins & ATMEL_SSC_RK)
1487 at91_set_A_periph(AT91_PIN_PD4, 1);
1488 if (pins & ATMEL_SSC_RF)
1489 at91_set_A_periph(AT91_PIN_PD5, 1);
1490}
1491
1492static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1493
1494static struct resource ssc1_resources[] = {
1495 [0] = {
1496 .start = AT91SAM9G45_BASE_SSC1,
1497 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1498 .flags = IORESOURCE_MEM,
1499 },
1500 [1] = {
1501 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1502 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1503 .flags = IORESOURCE_IRQ,
1504 },
1505};
1506
1507static struct platform_device at91sam9g45_ssc1_device = {
1508 .name = "at91sam9g45_ssc",
1509 .id = 1,
1510 .dev = {
1511 .dma_mask = &ssc1_dmamask,
1512 .coherent_dma_mask = DMA_BIT_MASK(32),
1513 },
1514 .resource = ssc1_resources,
1515 .num_resources = ARRAY_SIZE(ssc1_resources),
1516};
1517
1518static inline void configure_ssc1_pins(unsigned pins)
1519{
1520 if (pins & ATMEL_SSC_TF)
1521 at91_set_A_periph(AT91_PIN_PD14, 1);
1522 if (pins & ATMEL_SSC_TK)
1523 at91_set_A_periph(AT91_PIN_PD12, 1);
1524 if (pins & ATMEL_SSC_TD)
1525 at91_set_A_periph(AT91_PIN_PD10, 1);
1526 if (pins & ATMEL_SSC_RD)
1527 at91_set_A_periph(AT91_PIN_PD11, 1);
1528 if (pins & ATMEL_SSC_RK)
1529 at91_set_A_periph(AT91_PIN_PD13, 1);
1530 if (pins & ATMEL_SSC_RF)
1531 at91_set_A_periph(AT91_PIN_PD15, 1);
1532}
1533
1534
1535
1536
1537
1538
1539
1540void __init at91_add_device_ssc(unsigned id, unsigned pins)
1541{
1542 struct platform_device *pdev;
1543
1544
1545
1546
1547
1548 switch (id) {
1549 case AT91SAM9G45_ID_SSC0:
1550 pdev = &at91sam9g45_ssc0_device;
1551 configure_ssc0_pins(pins);
1552 break;
1553 case AT91SAM9G45_ID_SSC1:
1554 pdev = &at91sam9g45_ssc1_device;
1555 configure_ssc1_pins(pins);
1556 break;
1557 default:
1558 return;
1559 }
1560
1561 platform_device_register(pdev);
1562}
1563
1564#else
1565void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1566#endif
1567
1568
1569
1570
1571
1572
1573#if defined(CONFIG_SERIAL_ATMEL)
1574static struct resource dbgu_resources[] = {
1575 [0] = {
1576 .start = AT91SAM9G45_BASE_DBGU,
1577 .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1578 .flags = IORESOURCE_MEM,
1579 },
1580 [1] = {
1581 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1582 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1583 .flags = IORESOURCE_IRQ,
1584 },
1585};
1586
1587static struct atmel_uart_data dbgu_data = {
1588 .use_dma_tx = 0,
1589 .use_dma_rx = 0,
1590};
1591
1592static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1593
1594static struct platform_device at91sam9g45_dbgu_device = {
1595 .name = "atmel_usart",
1596 .id = 0,
1597 .dev = {
1598 .dma_mask = &dbgu_dmamask,
1599 .coherent_dma_mask = DMA_BIT_MASK(32),
1600 .platform_data = &dbgu_data,
1601 },
1602 .resource = dbgu_resources,
1603 .num_resources = ARRAY_SIZE(dbgu_resources),
1604};
1605
1606static inline void configure_dbgu_pins(void)
1607{
1608 at91_set_A_periph(AT91_PIN_PB12, 0);
1609 at91_set_A_periph(AT91_PIN_PB13, 1);
1610}
1611
1612static struct resource uart0_resources[] = {
1613 [0] = {
1614 .start = AT91SAM9G45_BASE_US0,
1615 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1616 .flags = IORESOURCE_MEM,
1617 },
1618 [1] = {
1619 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1620 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1621 .flags = IORESOURCE_IRQ,
1622 },
1623};
1624
1625static struct atmel_uart_data uart0_data = {
1626 .use_dma_tx = 1,
1627 .use_dma_rx = 1,
1628};
1629
1630static u64 uart0_dmamask = DMA_BIT_MASK(32);
1631
1632static struct platform_device at91sam9g45_uart0_device = {
1633 .name = "atmel_usart",
1634 .id = 1,
1635 .dev = {
1636 .dma_mask = &uart0_dmamask,
1637 .coherent_dma_mask = DMA_BIT_MASK(32),
1638 .platform_data = &uart0_data,
1639 },
1640 .resource = uart0_resources,
1641 .num_resources = ARRAY_SIZE(uart0_resources),
1642};
1643
1644static inline void configure_usart0_pins(unsigned pins)
1645{
1646 at91_set_A_periph(AT91_PIN_PB19, 1);
1647 at91_set_A_periph(AT91_PIN_PB18, 0);
1648
1649 if (pins & ATMEL_UART_RTS)
1650 at91_set_B_periph(AT91_PIN_PB17, 0);
1651 if (pins & ATMEL_UART_CTS)
1652 at91_set_B_periph(AT91_PIN_PB15, 0);
1653}
1654
1655static struct resource uart1_resources[] = {
1656 [0] = {
1657 .start = AT91SAM9G45_BASE_US1,
1658 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1659 .flags = IORESOURCE_MEM,
1660 },
1661 [1] = {
1662 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1663 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1664 .flags = IORESOURCE_IRQ,
1665 },
1666};
1667
1668static struct atmel_uart_data uart1_data = {
1669 .use_dma_tx = 1,
1670 .use_dma_rx = 1,
1671};
1672
1673static u64 uart1_dmamask = DMA_BIT_MASK(32);
1674
1675static struct platform_device at91sam9g45_uart1_device = {
1676 .name = "atmel_usart",
1677 .id = 2,
1678 .dev = {
1679 .dma_mask = &uart1_dmamask,
1680 .coherent_dma_mask = DMA_BIT_MASK(32),
1681 .platform_data = &uart1_data,
1682 },
1683 .resource = uart1_resources,
1684 .num_resources = ARRAY_SIZE(uart1_resources),
1685};
1686
1687static inline void configure_usart1_pins(unsigned pins)
1688{
1689 at91_set_A_periph(AT91_PIN_PB4, 1);
1690 at91_set_A_periph(AT91_PIN_PB5, 0);
1691
1692 if (pins & ATMEL_UART_RTS)
1693 at91_set_A_periph(AT91_PIN_PD16, 0);
1694 if (pins & ATMEL_UART_CTS)
1695 at91_set_A_periph(AT91_PIN_PD17, 0);
1696}
1697
1698static struct resource uart2_resources[] = {
1699 [0] = {
1700 .start = AT91SAM9G45_BASE_US2,
1701 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1702 .flags = IORESOURCE_MEM,
1703 },
1704 [1] = {
1705 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1706 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1707 .flags = IORESOURCE_IRQ,
1708 },
1709};
1710
1711static struct atmel_uart_data uart2_data = {
1712 .use_dma_tx = 1,
1713 .use_dma_rx = 1,
1714};
1715
1716static u64 uart2_dmamask = DMA_BIT_MASK(32);
1717
1718static struct platform_device at91sam9g45_uart2_device = {
1719 .name = "atmel_usart",
1720 .id = 3,
1721 .dev = {
1722 .dma_mask = &uart2_dmamask,
1723 .coherent_dma_mask = DMA_BIT_MASK(32),
1724 .platform_data = &uart2_data,
1725 },
1726 .resource = uart2_resources,
1727 .num_resources = ARRAY_SIZE(uart2_resources),
1728};
1729
1730static inline void configure_usart2_pins(unsigned pins)
1731{
1732 at91_set_A_periph(AT91_PIN_PB6, 1);
1733 at91_set_A_periph(AT91_PIN_PB7, 0);
1734
1735 if (pins & ATMEL_UART_RTS)
1736 at91_set_B_periph(AT91_PIN_PC9, 0);
1737 if (pins & ATMEL_UART_CTS)
1738 at91_set_B_periph(AT91_PIN_PC11, 0);
1739}
1740
1741static struct resource uart3_resources[] = {
1742 [0] = {
1743 .start = AT91SAM9G45_BASE_US3,
1744 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1745 .flags = IORESOURCE_MEM,
1746 },
1747 [1] = {
1748 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1749 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1750 .flags = IORESOURCE_IRQ,
1751 },
1752};
1753
1754static struct atmel_uart_data uart3_data = {
1755 .use_dma_tx = 1,
1756 .use_dma_rx = 1,
1757};
1758
1759static u64 uart3_dmamask = DMA_BIT_MASK(32);
1760
1761static struct platform_device at91sam9g45_uart3_device = {
1762 .name = "atmel_usart",
1763 .id = 4,
1764 .dev = {
1765 .dma_mask = &uart3_dmamask,
1766 .coherent_dma_mask = DMA_BIT_MASK(32),
1767 .platform_data = &uart3_data,
1768 },
1769 .resource = uart3_resources,
1770 .num_resources = ARRAY_SIZE(uart3_resources),
1771};
1772
1773static inline void configure_usart3_pins(unsigned pins)
1774{
1775 at91_set_A_periph(AT91_PIN_PB8, 1);
1776 at91_set_A_periph(AT91_PIN_PB9, 0);
1777
1778 if (pins & ATMEL_UART_RTS)
1779 at91_set_B_periph(AT91_PIN_PA23, 0);
1780 if (pins & ATMEL_UART_CTS)
1781 at91_set_B_periph(AT91_PIN_PA24, 0);
1782}
1783
1784static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];
1785
1786void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1787{
1788 struct platform_device *pdev;
1789 struct atmel_uart_data *pdata;
1790
1791 switch (id) {
1792 case 0:
1793 pdev = &at91sam9g45_dbgu_device;
1794 configure_dbgu_pins();
1795 break;
1796 case AT91SAM9G45_ID_US0:
1797 pdev = &at91sam9g45_uart0_device;
1798 configure_usart0_pins(pins);
1799 break;
1800 case AT91SAM9G45_ID_US1:
1801 pdev = &at91sam9g45_uart1_device;
1802 configure_usart1_pins(pins);
1803 break;
1804 case AT91SAM9G45_ID_US2:
1805 pdev = &at91sam9g45_uart2_device;
1806 configure_usart2_pins(pins);
1807 break;
1808 case AT91SAM9G45_ID_US3:
1809 pdev = &at91sam9g45_uart3_device;
1810 configure_usart3_pins(pins);
1811 break;
1812 default:
1813 return;
1814 }
1815 pdata = pdev->dev.platform_data;
1816 pdata->num = portnr;
1817
1818 if (portnr < ATMEL_MAX_UART)
1819 at91_uarts[portnr] = pdev;
1820}
1821
1822void __init at91_add_device_serial(void)
1823{
1824 int i;
1825
1826 for (i = 0; i < ATMEL_MAX_UART; i++) {
1827 if (at91_uarts[i])
1828 platform_device_register(at91_uarts[i]);
1829 }
1830}
1831#else
1832void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1833void __init at91_add_device_serial(void) {}
1834#endif
1835
1836
1837
1838
1839
1840#if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
1841static struct resource sha_resources[] = {
1842 {
1843 .start = AT91SAM9G45_BASE_SHA,
1844 .end = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
1845 .flags = IORESOURCE_MEM,
1846 },
1847 [1] = {
1848 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1849 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1850 .flags = IORESOURCE_IRQ,
1851 },
1852};
1853
1854static struct platform_device at91sam9g45_sha_device = {
1855 .name = "atmel_sha",
1856 .id = -1,
1857 .resource = sha_resources,
1858 .num_resources = ARRAY_SIZE(sha_resources),
1859};
1860
1861static void __init at91_add_device_sha(void)
1862{
1863 platform_device_register(&at91sam9g45_sha_device);
1864}
1865#else
1866static void __init at91_add_device_sha(void) {}
1867#endif
1868
1869
1870
1871
1872
1873#if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
1874static struct resource tdes_resources[] = {
1875 [0] = {
1876 .start = AT91SAM9G45_BASE_TDES,
1877 .end = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
1878 .flags = IORESOURCE_MEM,
1879 },
1880 [1] = {
1881 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1882 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1883 .flags = IORESOURCE_IRQ,
1884 },
1885};
1886
1887static struct platform_device at91sam9g45_tdes_device = {
1888 .name = "atmel_tdes",
1889 .id = -1,
1890 .resource = tdes_resources,
1891 .num_resources = ARRAY_SIZE(tdes_resources),
1892};
1893
1894static void __init at91_add_device_tdes(void)
1895{
1896 platform_device_register(&at91sam9g45_tdes_device);
1897}
1898#else
1899static void __init at91_add_device_tdes(void) {}
1900#endif
1901
1902
1903
1904
1905
1906#if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
1907static struct crypto_platform_data aes_data;
1908static struct crypto_dma_data alt_atslave;
1909static u64 aes_dmamask = DMA_BIT_MASK(32);
1910
1911static struct resource aes_resources[] = {
1912 [0] = {
1913 .start = AT91SAM9G45_BASE_AES,
1914 .end = AT91SAM9G45_BASE_AES + SZ_16K - 1,
1915 .flags = IORESOURCE_MEM,
1916 },
1917 [1] = {
1918 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1919 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1920 .flags = IORESOURCE_IRQ,
1921 },
1922};
1923
1924static struct platform_device at91sam9g45_aes_device = {
1925 .name = "atmel_aes",
1926 .id = -1,
1927 .dev = {
1928 .dma_mask = &aes_dmamask,
1929 .coherent_dma_mask = DMA_BIT_MASK(32),
1930 .platform_data = &aes_data,
1931 },
1932 .resource = aes_resources,
1933 .num_resources = ARRAY_SIZE(aes_resources),
1934};
1935
1936static void __init at91_add_device_aes(void)
1937{
1938 struct at_dma_slave *atslave;
1939
1940
1941 atslave = &alt_atslave.txdata;
1942 atslave->dma_dev = &at_hdmac_device.dev;
1943 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_SRC_H2SEL_HW |
1944 ATC_SRC_PER(AT_DMA_ID_AES_RX);
1945
1946
1947 atslave = &alt_atslave.rxdata;
1948 atslave->dma_dev = &at_hdmac_device.dev;
1949 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_DST_H2SEL_HW |
1950 ATC_DST_PER(AT_DMA_ID_AES_TX);
1951
1952 aes_data.dma_slave = &alt_atslave;
1953 platform_device_register(&at91sam9g45_aes_device);
1954}
1955#else
1956static void __init at91_add_device_aes(void) {}
1957#endif
1958
1959
1960
1961
1962
1963
1964static int __init at91_add_standard_devices(void)
1965{
1966 if (of_have_populated_dt())
1967 return 0;
1968
1969 at91_add_device_hdmac();
1970 at91_add_device_rtc();
1971 at91_add_device_rtt();
1972 at91_add_device_trng();
1973 at91_add_device_watchdog();
1974 at91_add_device_tc();
1975 at91_add_device_sha();
1976 at91_add_device_tdes();
1977 at91_add_device_aes();
1978 return 0;
1979}
1980
1981arch_initcall(at91_add_standard_devices);
1982
