LXR linux/arch/arm/mach-s3c24xx/s3c2412.c

   1/*
   2 * Copyright (c) 2006 Simtec Electronics
   3 *      Ben Dooks <ben@simtec.co.uk>
   4 *
   5 * http://armlinux.simtec.co.uk/.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10*/
  11
  12#include <linux/kernel.h>
  13#include <linux/types.h>
  14#include <linux/interrupt.h>
  15#include <linux/list.h>
  16#include <linux/timer.h>
  17#include <linux/init.h>
  18#include <linux/clk.h>
  19#include <linux/delay.h>
  20#include <linux/device.h>
  21#include <linux/syscore_ops.h>
  22#include <linux/serial_core.h>
  23#include <linux/platform_device.h>
  24#include <linux/io.h>
  25
  26#include <asm/mach/arch.h>
  27#include <asm/mach/map.h>
  28#include <asm/mach/irq.h>
  29
  30#include <asm/proc-fns.h>
  31#include <asm/irq.h>
  32#include <asm/system_misc.h>
  33
  34#include <mach/hardware.h>
  35#include <mach/regs-clock.h>
  36#include <mach/regs-gpio.h>
  37
  38#include <plat/clock.h>
  39#include <plat/cpu.h>
  40#include <plat/cpu-freq.h>
  41#include <plat/devs.h>
  42#include <plat/nand-core.h>
  43#include <plat/pll.h>
  44#include <plat/pm.h>
  45#include <plat/regs-serial.h>
  46#include <plat/regs-spi.h>
  47
  48#include "common.h"
  49#include "regs-dsc.h"
  50#include "s3c2412-power.h"
  51
  52#define S3C2412_SWRST                   (S3C24XX_VA_CLKPWR + 0x30)
  53#define S3C2412_SWRST_RESET             (0x533C2412)
  54
  55#ifndef CONFIG_CPU_S3C2412_ONLY
  56void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
  57
  58static inline void s3c2412_init_gpio2(void)
  59{
  60        s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
  61}
  62#else
  63#define s3c2412_init_gpio2() do { } while(0)
  64#endif
  65
  66/* Initial IO mappings */
  67
  68static struct map_desc s3c2412_iodesc[] __initdata = {
  69        IODESC_ENT(CLKPWR),
  70        IODESC_ENT(TIMER),
  71        IODESC_ENT(WATCHDOG),
  72        {
  73                .virtual = (unsigned long)S3C2412_VA_SSMC,
  74                .pfn     = __phys_to_pfn(S3C2412_PA_SSMC),
  75                .length  = SZ_1M,
  76                .type    = MT_DEVICE,
  77        },
  78        {
  79                .virtual = (unsigned long)S3C2412_VA_EBI,
  80                .pfn     = __phys_to_pfn(S3C2412_PA_EBI),
  81                .length  = SZ_1M,
  82                .type    = MT_DEVICE,
  83        },
  84};
  85
  86/* uart registration process */
  87
  88void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  89{
  90        s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
  91
  92        /* rename devices that are s3c2412/s3c2413 specific */
  93        s3c_device_sdi.name  = "s3c2412-sdi";
  94        s3c_device_lcd.name  = "s3c2412-lcd";
  95        s3c_nand_setname("s3c2412-nand");
  96
  97        /* alter IRQ of SDI controller */
  98
  99        s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
 100        s3c_device_sdi.resource[1].end   = IRQ_S3C2412_SDI;
 101
 102        /* spi channel related changes, s3c2412/13 specific */
 103        s3c_device_spi0.name = "s3c2412-spi";
 104        s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
 105        s3c_device_spi1.name = "s3c2412-spi";
 106        s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
 107        s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
 108
 109}
 110
 111/* s3c2412_idle
 112 *
 113 * use the standard idle call by ensuring the idle mode
 114 * in power config, then issuing the idle co-processor
 115 * instruction
 116*/
 117
 118static void s3c2412_idle(void)
 119{
 120        unsigned long tmp;
 121
 122        /* ensure our idle mode is to go to idle */
 123
 124        tmp = __raw_readl(S3C2412_PWRCFG);
 125        tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
 126        tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
 127        __raw_writel(tmp, S3C2412_PWRCFG);
 128
 129        cpu_do_idle();
 130}
 131
 132void s3c2412_restart(char mode, const char *cmd)
 133{
 134        if (mode == 's')
 135                soft_restart(0);
 136
 137        /* errata "Watch-dog/Software Reset Problem" specifies that
 138         * this reset must be done with the SYSCLK sourced from
 139         * EXTCLK instead of FOUT to avoid a glitch in the reset
 140         * mechanism.
 141         *
 142         * See the watchdog section of the S3C2412 manual for more
 143         * information on this fix.
 144         */
 145
 146        __raw_writel(0x00, S3C2412_CLKSRC);
 147        __raw_writel(S3C2412_SWRST_RESET, S3C2412_SWRST);
 148
 149        mdelay(1);
 150}
 151
 152/* s3c2412_map_io
 153 *
 154 * register the standard cpu IO areas, and any passed in from the
 155 * machine specific initialisation.
 156*/
 157
 158void __init s3c2412_map_io(void)
 159{
 160        /* move base of IO */
 161
 162        s3c2412_init_gpio2();
 163
 164        /* set our idle function */
 165
 166        arm_pm_idle = s3c2412_idle;
 167
 168        /* register our io-tables */
 169
 170        iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
 171}
 172
 173void __init_or_cpufreq s3c2412_setup_clocks(void)
 174{
 175        struct clk *xtal_clk;
 176        unsigned long tmp;
 177        unsigned long xtal;
 178        unsigned long fclk;
 179        unsigned long hclk;
 180        unsigned long pclk;
 181
 182        xtal_clk = clk_get(NULL, "xtal");
 183        xtal = clk_get_rate(xtal_clk);
 184        clk_put(xtal_clk);
 185
 186        /* now we've got our machine bits initialised, work out what
 187         * clocks we've got */
 188
 189        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
 190
 191        clk_mpll.rate = fclk;
 192
 193        tmp = __raw_readl(S3C2410_CLKDIVN);
 194
 195        /* work out clock scalings */
 196
 197        hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
 198        hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
 199        pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
 200
 201        /* print brieft summary of clocks, etc */
 202
 203        printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
 204               print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
 205
 206        s3c24xx_setup_clocks(fclk, hclk, pclk);
 207}
 208
 209void __init s3c2412_init_clocks(int xtal)
 210{
 211        /* initialise the clocks here, to allow other things like the
 212         * console to use them
 213         */
 214
 215        s3c24xx_register_baseclocks(xtal);
 216        s3c2412_setup_clocks();
 217        s3c2412_baseclk_add();
 218}
 219
 220/* need to register the subsystem before we actually register the device, and
 221 * we also need to ensure that it has been initialised before any of the
 222 * drivers even try to use it (even if not on an s3c2412 based system)
 223 * as a driver which may support both 2410 and 2440 may try and use it.
 224*/
 225
 226struct bus_type s3c2412_subsys = {
 227        .name = "s3c2412-core",
 228        .dev_name = "s3c2412-core",
 229};
 230
 231static int __init s3c2412_core_init(void)
 232{
 233        return subsys_system_register(&s3c2412_subsys, NULL);
 234}
 235
 236core_initcall(s3c2412_core_init);
 237
 238static struct device s3c2412_dev = {
 239        .bus            = &s3c2412_subsys,
 240};
 241
 242int __init s3c2412_init(void)
 243{
 244        printk("S3C2412: Initialising architecture\n");
 245
 246#ifdef CONFIG_PM
 247        register_syscore_ops(&s3c2412_pm_syscore_ops);
 248        register_syscore_ops(&s3c24xx_irq_syscore_ops);
 249#endif
 250
 251        return device_register(&s3c2412_dev);
 252}
 253