1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#include <linux/delay.h>
21#include <linux/dma-mapping.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/io.h>
25#include <linux/platform_data/irq-renesas-intc-irqpin.h>
26#include <linux/platform_device.h>
27#include <linux/of_platform.h>
28#include <linux/serial_sci.h>
29#include <linux/sh_dma.h>
30#include <linux/sh_timer.h>
31#include <linux/platform_data/sh_ipmmu.h>
32#include <mach/dma-register.h>
33#include <mach/r8a7740.h>
34#include <mach/pm-rmobile.h>
35#include <mach/common.h>
36#include <mach/irqs.h>
37#include <asm/mach-types.h>
38#include <asm/mach/map.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/time.h>
41
42static struct map_desc r8a7740_io_desc[] __initdata = {
43
44
45
46
47 {
48 .virtual = 0xe6000000,
49 .pfn = __phys_to_pfn(0xe6000000),
50 .length = 160 << 20,
51 .type = MT_DEVICE_NONSHARED
52 },
53#ifdef CONFIG_CACHE_L2X0
54
55
56
57
58 {
59 .virtual = 0xf0002000,
60 .pfn = __phys_to_pfn(0xf0100000),
61 .length = PAGE_SIZE,
62 .type = MT_DEVICE_NONSHARED
63 },
64#endif
65};
66
67void __init r8a7740_map_io(void)
68{
69 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
70}
71
72
73static struct resource r8a7740_pfc_resources[] = {
74 [0] = {
75 .start = 0xe6050000,
76 .end = 0xe6057fff,
77 .flags = IORESOURCE_MEM,
78 },
79 [1] = {
80 .start = 0xe605800c,
81 .end = 0xe605802b,
82 .flags = IORESOURCE_MEM,
83 }
84};
85
86static struct platform_device r8a7740_pfc_device = {
87 .name = "pfc-r8a7740",
88 .id = -1,
89 .resource = r8a7740_pfc_resources,
90 .num_resources = ARRAY_SIZE(r8a7740_pfc_resources),
91};
92
93void __init r8a7740_pinmux_init(void)
94{
95 platform_device_register(&r8a7740_pfc_device);
96}
97
98static struct renesas_intc_irqpin_config irqpin0_platform_data = {
99 .irq_base = irq_pin(0),
100};
101
102static struct resource irqpin0_resources[] = {
103 DEFINE_RES_MEM(0xe6900000, 4),
104 DEFINE_RES_MEM(0xe6900010, 4),
105 DEFINE_RES_MEM(0xe6900020, 1),
106 DEFINE_RES_MEM(0xe6900040, 1),
107 DEFINE_RES_MEM(0xe6900060, 1),
108 DEFINE_RES_IRQ(gic_spi(149)),
109 DEFINE_RES_IRQ(gic_spi(149)),
110 DEFINE_RES_IRQ(gic_spi(149)),
111 DEFINE_RES_IRQ(gic_spi(149)),
112 DEFINE_RES_IRQ(gic_spi(149)),
113 DEFINE_RES_IRQ(gic_spi(149)),
114 DEFINE_RES_IRQ(gic_spi(149)),
115 DEFINE_RES_IRQ(gic_spi(149)),
116};
117
118static struct platform_device irqpin0_device = {
119 .name = "renesas_intc_irqpin",
120 .id = 0,
121 .resource = irqpin0_resources,
122 .num_resources = ARRAY_SIZE(irqpin0_resources),
123 .dev = {
124 .platform_data = &irqpin0_platform_data,
125 },
126};
127
128static struct renesas_intc_irqpin_config irqpin1_platform_data = {
129 .irq_base = irq_pin(8),
130};
131
132static struct resource irqpin1_resources[] = {
133 DEFINE_RES_MEM(0xe6900004, 4),
134 DEFINE_RES_MEM(0xe6900014, 4),
135 DEFINE_RES_MEM(0xe6900024, 1),
136 DEFINE_RES_MEM(0xe6900044, 1),
137 DEFINE_RES_MEM(0xe6900064, 1),
138 DEFINE_RES_IRQ(gic_spi(149)),
139 DEFINE_RES_IRQ(gic_spi(149)),
140 DEFINE_RES_IRQ(gic_spi(149)),
141 DEFINE_RES_IRQ(gic_spi(149)),
142 DEFINE_RES_IRQ(gic_spi(149)),
143 DEFINE_RES_IRQ(gic_spi(149)),
144 DEFINE_RES_IRQ(gic_spi(149)),
145 DEFINE_RES_IRQ(gic_spi(149)),
146};
147
148static struct platform_device irqpin1_device = {
149 .name = "renesas_intc_irqpin",
150 .id = 1,
151 .resource = irqpin1_resources,
152 .num_resources = ARRAY_SIZE(irqpin1_resources),
153 .dev = {
154 .platform_data = &irqpin1_platform_data,
155 },
156};
157
158static struct renesas_intc_irqpin_config irqpin2_platform_data = {
159 .irq_base = irq_pin(16),
160};
161
162static struct resource irqpin2_resources[] = {
163 DEFINE_RES_MEM(0xe6900008, 4),
164 DEFINE_RES_MEM(0xe6900018, 4),
165 DEFINE_RES_MEM(0xe6900028, 1),
166 DEFINE_RES_MEM(0xe6900048, 1),
167 DEFINE_RES_MEM(0xe6900068, 1),
168 DEFINE_RES_IRQ(gic_spi(149)),
169 DEFINE_RES_IRQ(gic_spi(149)),
170 DEFINE_RES_IRQ(gic_spi(149)),
171 DEFINE_RES_IRQ(gic_spi(149)),
172 DEFINE_RES_IRQ(gic_spi(149)),
173 DEFINE_RES_IRQ(gic_spi(149)),
174 DEFINE_RES_IRQ(gic_spi(149)),
175 DEFINE_RES_IRQ(gic_spi(149)),
176};
177
178static struct platform_device irqpin2_device = {
179 .name = "renesas_intc_irqpin",
180 .id = 2,
181 .resource = irqpin2_resources,
182 .num_resources = ARRAY_SIZE(irqpin2_resources),
183 .dev = {
184 .platform_data = &irqpin2_platform_data,
185 },
186};
187
188static struct renesas_intc_irqpin_config irqpin3_platform_data = {
189 .irq_base = irq_pin(24),
190};
191
192static struct resource irqpin3_resources[] = {
193 DEFINE_RES_MEM(0xe690000c, 4),
194 DEFINE_RES_MEM(0xe690001c, 4),
195 DEFINE_RES_MEM(0xe690002c, 1),
196 DEFINE_RES_MEM(0xe690004c, 1),
197 DEFINE_RES_MEM(0xe690006c, 1),
198 DEFINE_RES_IRQ(gic_spi(149)),
199 DEFINE_RES_IRQ(gic_spi(149)),
200 DEFINE_RES_IRQ(gic_spi(149)),
201 DEFINE_RES_IRQ(gic_spi(149)),
202 DEFINE_RES_IRQ(gic_spi(149)),
203 DEFINE_RES_IRQ(gic_spi(149)),
204 DEFINE_RES_IRQ(gic_spi(149)),
205 DEFINE_RES_IRQ(gic_spi(149)),
206};
207
208static struct platform_device irqpin3_device = {
209 .name = "renesas_intc_irqpin",
210 .id = 3,
211 .resource = irqpin3_resources,
212 .num_resources = ARRAY_SIZE(irqpin3_resources),
213 .dev = {
214 .platform_data = &irqpin3_platform_data,
215 },
216};
217
218
219static struct plat_sci_port scif0_platform_data = {
220 .mapbase = 0xe6c40000,
221 .flags = UPF_BOOT_AUTOCONF,
222 .scscr = SCSCR_RE | SCSCR_TE,
223 .scbrr_algo_id = SCBRR_ALGO_4,
224 .type = PORT_SCIFA,
225 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
226};
227
228static struct platform_device scif0_device = {
229 .name = "sh-sci",
230 .id = 0,
231 .dev = {
232 .platform_data = &scif0_platform_data,
233 },
234};
235
236
237static struct plat_sci_port scif1_platform_data = {
238 .mapbase = 0xe6c50000,
239 .flags = UPF_BOOT_AUTOCONF,
240 .scscr = SCSCR_RE | SCSCR_TE,
241 .scbrr_algo_id = SCBRR_ALGO_4,
242 .type = PORT_SCIFA,
243 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
244};
245
246static struct platform_device scif1_device = {
247 .name = "sh-sci",
248 .id = 1,
249 .dev = {
250 .platform_data = &scif1_platform_data,
251 },
252};
253
254
255static struct plat_sci_port scif2_platform_data = {
256 .mapbase = 0xe6c60000,
257 .flags = UPF_BOOT_AUTOCONF,
258 .scscr = SCSCR_RE | SCSCR_TE,
259 .scbrr_algo_id = SCBRR_ALGO_4,
260 .type = PORT_SCIFA,
261 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
262};
263
264static struct platform_device scif2_device = {
265 .name = "sh-sci",
266 .id = 2,
267 .dev = {
268 .platform_data = &scif2_platform_data,
269 },
270};
271
272
273static struct plat_sci_port scif3_platform_data = {
274 .mapbase = 0xe6c70000,
275 .flags = UPF_BOOT_AUTOCONF,
276 .scscr = SCSCR_RE | SCSCR_TE,
277 .scbrr_algo_id = SCBRR_ALGO_4,
278 .type = PORT_SCIFA,
279 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
280};
281
282static struct platform_device scif3_device = {
283 .name = "sh-sci",
284 .id = 3,
285 .dev = {
286 .platform_data = &scif3_platform_data,
287 },
288};
289
290
291static struct plat_sci_port scif4_platform_data = {
292 .mapbase = 0xe6c80000,
293 .flags = UPF_BOOT_AUTOCONF,
294 .scscr = SCSCR_RE | SCSCR_TE,
295 .scbrr_algo_id = SCBRR_ALGO_4,
296 .type = PORT_SCIFA,
297 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
298};
299
300static struct platform_device scif4_device = {
301 .name = "sh-sci",
302 .id = 4,
303 .dev = {
304 .platform_data = &scif4_platform_data,
305 },
306};
307
308
309static struct plat_sci_port scif5_platform_data = {
310 .mapbase = 0xe6cb0000,
311 .flags = UPF_BOOT_AUTOCONF,
312 .scscr = SCSCR_RE | SCSCR_TE,
313 .scbrr_algo_id = SCBRR_ALGO_4,
314 .type = PORT_SCIFA,
315 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
316};
317
318static struct platform_device scif5_device = {
319 .name = "sh-sci",
320 .id = 5,
321 .dev = {
322 .platform_data = &scif5_platform_data,
323 },
324};
325
326
327static struct plat_sci_port scif6_platform_data = {
328 .mapbase = 0xe6cc0000,
329 .flags = UPF_BOOT_AUTOCONF,
330 .scscr = SCSCR_RE | SCSCR_TE,
331 .scbrr_algo_id = SCBRR_ALGO_4,
332 .type = PORT_SCIFA,
333 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
334};
335
336static struct platform_device scif6_device = {
337 .name = "sh-sci",
338 .id = 6,
339 .dev = {
340 .platform_data = &scif6_platform_data,
341 },
342};
343
344
345static struct plat_sci_port scif7_platform_data = {
346 .mapbase = 0xe6cd0000,
347 .flags = UPF_BOOT_AUTOCONF,
348 .scscr = SCSCR_RE | SCSCR_TE,
349 .scbrr_algo_id = SCBRR_ALGO_4,
350 .type = PORT_SCIFA,
351 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
352};
353
354static struct platform_device scif7_device = {
355 .name = "sh-sci",
356 .id = 7,
357 .dev = {
358 .platform_data = &scif7_platform_data,
359 },
360};
361
362
363static struct plat_sci_port scifb_platform_data = {
364 .mapbase = 0xe6c30000,
365 .flags = UPF_BOOT_AUTOCONF,
366 .scscr = SCSCR_RE | SCSCR_TE,
367 .scbrr_algo_id = SCBRR_ALGO_4,
368 .type = PORT_SCIFB,
369 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
370};
371
372static struct platform_device scifb_device = {
373 .name = "sh-sci",
374 .id = 8,
375 .dev = {
376 .platform_data = &scifb_platform_data,
377 },
378};
379
380
381static struct sh_timer_config cmt10_platform_data = {
382 .name = "CMT10",
383 .channel_offset = 0x10,
384 .timer_bit = 0,
385 .clockevent_rating = 125,
386 .clocksource_rating = 125,
387};
388
389static struct resource cmt10_resources[] = {
390 [0] = {
391 .name = "CMT10",
392 .start = 0xe6138010,
393 .end = 0xe613801b,
394 .flags = IORESOURCE_MEM,
395 },
396 [1] = {
397 .start = gic_spi(58),
398 .flags = IORESOURCE_IRQ,
399 },
400};
401
402static struct platform_device cmt10_device = {
403 .name = "sh_cmt",
404 .id = 10,
405 .dev = {
406 .platform_data = &cmt10_platform_data,
407 },
408 .resource = cmt10_resources,
409 .num_resources = ARRAY_SIZE(cmt10_resources),
410};
411
412
413static struct sh_timer_config tmu00_platform_data = {
414 .name = "TMU00",
415 .channel_offset = 0x4,
416 .timer_bit = 0,
417 .clockevent_rating = 200,
418};
419
420static struct resource tmu00_resources[] = {
421 [0] = {
422 .name = "TMU00",
423 .start = 0xfff80008,
424 .end = 0xfff80014 - 1,
425 .flags = IORESOURCE_MEM,
426 },
427 [1] = {
428 .start = gic_spi(198),
429 .flags = IORESOURCE_IRQ,
430 },
431};
432
433static struct platform_device tmu00_device = {
434 .name = "sh_tmu",
435 .id = 0,
436 .dev = {
437 .platform_data = &tmu00_platform_data,
438 },
439 .resource = tmu00_resources,
440 .num_resources = ARRAY_SIZE(tmu00_resources),
441};
442
443static struct sh_timer_config tmu01_platform_data = {
444 .name = "TMU01",
445 .channel_offset = 0x10,
446 .timer_bit = 1,
447 .clocksource_rating = 200,
448};
449
450static struct resource tmu01_resources[] = {
451 [0] = {
452 .name = "TMU01",
453 .start = 0xfff80014,
454 .end = 0xfff80020 - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 [1] = {
458 .start = gic_spi(199),
459 .flags = IORESOURCE_IRQ,
460 },
461};
462
463static struct platform_device tmu01_device = {
464 .name = "sh_tmu",
465 .id = 1,
466 .dev = {
467 .platform_data = &tmu01_platform_data,
468 },
469 .resource = tmu01_resources,
470 .num_resources = ARRAY_SIZE(tmu01_resources),
471};
472
473static struct sh_timer_config tmu02_platform_data = {
474 .name = "TMU02",
475 .channel_offset = 0x1C,
476 .timer_bit = 2,
477 .clocksource_rating = 200,
478};
479
480static struct resource tmu02_resources[] = {
481 [0] = {
482 .name = "TMU02",
483 .start = 0xfff80020,
484 .end = 0xfff8002C - 1,
485 .flags = IORESOURCE_MEM,
486 },
487 [1] = {
488 .start = gic_spi(200),
489 .flags = IORESOURCE_IRQ,
490 },
491};
492
493static struct platform_device tmu02_device = {
494 .name = "sh_tmu",
495 .id = 2,
496 .dev = {
497 .platform_data = &tmu02_platform_data,
498 },
499 .resource = tmu02_resources,
500 .num_resources = ARRAY_SIZE(tmu02_resources),
501};
502
503
504static struct resource ipmmu_resources[] = {
505 [0] = {
506 .name = "IPMMUI",
507 .start = 0xfe951000,
508 .end = 0xfe9510ff,
509 .flags = IORESOURCE_MEM,
510 },
511};
512
513static const char * const ipmmu_dev_names[] = {
514 "sh_mobile_lcdc_fb.0",
515 "sh_mobile_lcdc_fb.1",
516 "sh_mobile_ceu.0",
517};
518
519static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
520 .dev_names = ipmmu_dev_names,
521 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
522};
523
524static struct platform_device ipmmu_device = {
525 .name = "ipmmu",
526 .id = -1,
527 .dev = {
528 .platform_data = &ipmmu_platform_data,
529 },
530 .resource = ipmmu_resources,
531 .num_resources = ARRAY_SIZE(ipmmu_resources),
532};
533
534static struct platform_device *r8a7740_early_devices[] __initdata = {
535 &irqpin0_device,
536 &irqpin1_device,
537 &irqpin2_device,
538 &irqpin3_device,
539 &scif0_device,
540 &scif1_device,
541 &scif2_device,
542 &scif3_device,
543 &scif4_device,
544 &scif5_device,
545 &scif6_device,
546 &scif7_device,
547 &scifb_device,
548 &cmt10_device,
549 &tmu00_device,
550 &tmu01_device,
551 &tmu02_device,
552 &ipmmu_device,
553};
554
555
556static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
557 {
558 .slave_id = SHDMA_SLAVE_SDHI0_TX,
559 .addr = 0xe6850030,
560 .chcr = CHCR_TX(XMIT_SZ_16BIT),
561 .mid_rid = 0xc1,
562 }, {
563 .slave_id = SHDMA_SLAVE_SDHI0_RX,
564 .addr = 0xe6850030,
565 .chcr = CHCR_RX(XMIT_SZ_16BIT),
566 .mid_rid = 0xc2,
567 }, {
568 .slave_id = SHDMA_SLAVE_SDHI1_TX,
569 .addr = 0xe6860030,
570 .chcr = CHCR_TX(XMIT_SZ_16BIT),
571 .mid_rid = 0xc9,
572 }, {
573 .slave_id = SHDMA_SLAVE_SDHI1_RX,
574 .addr = 0xe6860030,
575 .chcr = CHCR_RX(XMIT_SZ_16BIT),
576 .mid_rid = 0xca,
577 }, {
578 .slave_id = SHDMA_SLAVE_SDHI2_TX,
579 .addr = 0xe6870030,
580 .chcr = CHCR_TX(XMIT_SZ_16BIT),
581 .mid_rid = 0xcd,
582 }, {
583 .slave_id = SHDMA_SLAVE_SDHI2_RX,
584 .addr = 0xe6870030,
585 .chcr = CHCR_RX(XMIT_SZ_16BIT),
586 .mid_rid = 0xce,
587 }, {
588 .slave_id = SHDMA_SLAVE_FSIA_TX,
589 .addr = 0xfe1f0024,
590 .chcr = CHCR_TX(XMIT_SZ_32BIT),
591 .mid_rid = 0xb1,
592 }, {
593 .slave_id = SHDMA_SLAVE_FSIA_RX,
594 .addr = 0xfe1f0020,
595 .chcr = CHCR_RX(XMIT_SZ_32BIT),
596 .mid_rid = 0xb2,
597 }, {
598 .slave_id = SHDMA_SLAVE_FSIB_TX,
599 .addr = 0xfe1f0064,
600 .chcr = CHCR_TX(XMIT_SZ_32BIT),
601 .mid_rid = 0xb5,
602 },
603};
604
605#define DMA_CHANNEL(a, b, c) \
606{ \
607 .offset = a, \
608 .dmars = b, \
609 .dmars_bit = c, \
610 .chclr_offset = (0x220 - 0x20) + a \
611}
612
613static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
614 DMA_CHANNEL(0x00, 0, 0),
615 DMA_CHANNEL(0x10, 0, 8),
616 DMA_CHANNEL(0x20, 4, 0),
617 DMA_CHANNEL(0x30, 4, 8),
618 DMA_CHANNEL(0x50, 8, 0),
619 DMA_CHANNEL(0x60, 8, 8),
620};
621
622static struct sh_dmae_pdata dma_platform_data = {
623 .slave = r8a7740_dmae_slaves,
624 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
625 .channel = r8a7740_dmae_channels,
626 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
627 .ts_low_shift = TS_LOW_SHIFT,
628 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
629 .ts_high_shift = TS_HI_SHIFT,
630 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
631 .ts_shift = dma_ts_shift,
632 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
633 .dmaor_init = DMAOR_DME,
634 .chclr_present = 1,
635};
636
637
638static struct resource r8a7740_dmae0_resources[] = {
639 {
640
641 .start = 0xfe008020,
642 .end = 0xfe00828f,
643 .flags = IORESOURCE_MEM,
644 },
645 {
646
647 .start = 0xfe009000,
648 .end = 0xfe00900b,
649 .flags = IORESOURCE_MEM,
650 },
651 {
652 .name = "error_irq",
653 .start = gic_spi(34),
654 .end = gic_spi(34),
655 .flags = IORESOURCE_IRQ,
656 },
657 {
658
659 .start = gic_spi(28),
660 .end = gic_spi(33),
661 .flags = IORESOURCE_IRQ,
662 },
663};
664
665
666static struct resource r8a7740_dmae1_resources[] = {
667 {
668
669 .start = 0xfe018020,
670 .end = 0xfe01828f,
671 .flags = IORESOURCE_MEM,
672 },
673 {
674
675 .start = 0xfe019000,
676 .end = 0xfe01900b,
677 .flags = IORESOURCE_MEM,
678 },
679 {
680 .name = "error_irq",
681 .start = gic_spi(41),
682 .end = gic_spi(41),
683 .flags = IORESOURCE_IRQ,
684 },
685 {
686
687 .start = gic_spi(35),
688 .end = gic_spi(40),
689 .flags = IORESOURCE_IRQ,
690 },
691};
692
693
694static struct resource r8a7740_dmae2_resources[] = {
695 {
696
697 .start = 0xfe028020,
698 .end = 0xfe02828f,
699 .flags = IORESOURCE_MEM,
700 },
701 {
702
703 .start = 0xfe029000,
704 .end = 0xfe02900b,
705 .flags = IORESOURCE_MEM,
706 },
707 {
708 .name = "error_irq",
709 .start = gic_spi(48),
710 .end = gic_spi(48),
711 .flags = IORESOURCE_IRQ,
712 },
713 {
714
715 .start = gic_spi(42),
716 .end = gic_spi(47),
717 .flags = IORESOURCE_IRQ,
718 },
719};
720
721static struct platform_device dma0_device = {
722 .name = "sh-dma-engine",
723 .id = 0,
724 .resource = r8a7740_dmae0_resources,
725 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
726 .dev = {
727 .platform_data = &dma_platform_data,
728 },
729};
730
731static struct platform_device dma1_device = {
732 .name = "sh-dma-engine",
733 .id = 1,
734 .resource = r8a7740_dmae1_resources,
735 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
736 .dev = {
737 .platform_data = &dma_platform_data,
738 },
739};
740
741static struct platform_device dma2_device = {
742 .name = "sh-dma-engine",
743 .id = 2,
744 .resource = r8a7740_dmae2_resources,
745 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
746 .dev = {
747 .platform_data = &dma_platform_data,
748 },
749};
750
751
752static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
753 {
754 .offset = 0,
755 }, {
756 .offset = 0x20,
757 },
758};
759
760static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
761 {
762 .slave_id = SHDMA_SLAVE_USBHS_TX,
763 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
764 }, {
765 .slave_id = SHDMA_SLAVE_USBHS_RX,
766 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
767 },
768};
769
770static struct sh_dmae_pdata usb_dma_platform_data = {
771 .slave = r8a7740_usb_dma_slaves,
772 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
773 .channel = r8a7740_usb_dma_channels,
774 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
775 .ts_low_shift = USBTS_LOW_SHIFT,
776 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
777 .ts_high_shift = USBTS_HI_SHIFT,
778 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
779 .ts_shift = dma_usbts_shift,
780 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
781 .dmaor_init = DMAOR_DME,
782 .chcr_offset = 0x14,
783 .chcr_ie_bit = 1 << 5,
784 .dmaor_is_32bit = 1,
785 .needs_tend_set = 1,
786 .no_dmars = 1,
787 .slave_only = 1,
788};
789
790static struct resource r8a7740_usb_dma_resources[] = {
791 {
792
793 .start = 0xe68a0020,
794 .end = 0xe68a0064 - 1,
795 .flags = IORESOURCE_MEM,
796 },
797 {
798
799 .start = 0xe68a0000,
800 .end = 0xe68a0014 - 1,
801 .flags = IORESOURCE_MEM,
802 },
803 {
804
805 .start = gic_spi(49),
806 .end = gic_spi(49),
807 .flags = IORESOURCE_IRQ,
808 },
809};
810
811static struct platform_device usb_dma_device = {
812 .name = "sh-dma-engine",
813 .id = 3,
814 .resource = r8a7740_usb_dma_resources,
815 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
816 .dev = {
817 .platform_data = &usb_dma_platform_data,
818 },
819};
820
821
822static struct resource i2c0_resources[] = {
823 [0] = {
824 .name = "IIC0",
825 .start = 0xfff20000,
826 .end = 0xfff20425 - 1,
827 .flags = IORESOURCE_MEM,
828 },
829 [1] = {
830 .start = gic_spi(201),
831 .end = gic_spi(204),
832 .flags = IORESOURCE_IRQ,
833 },
834};
835
836static struct resource i2c1_resources[] = {
837 [0] = {
838 .name = "IIC1",
839 .start = 0xe6c20000,
840 .end = 0xe6c20425 - 1,
841 .flags = IORESOURCE_MEM,
842 },
843 [1] = {
844 .start = gic_spi(70),
845 .end = gic_spi(73),
846 .flags = IORESOURCE_IRQ,
847 },
848};
849
850static struct platform_device i2c0_device = {
851 .name = "i2c-sh_mobile",
852 .id = 0,
853 .resource = i2c0_resources,
854 .num_resources = ARRAY_SIZE(i2c0_resources),
855};
856
857static struct platform_device i2c1_device = {
858 .name = "i2c-sh_mobile",
859 .id = 1,
860 .resource = i2c1_resources,
861 .num_resources = ARRAY_SIZE(i2c1_resources),
862};
863
864static struct resource pmu_resources[] = {
865 [0] = {
866 .start = gic_spi(83),
867 .end = gic_spi(83),
868 .flags = IORESOURCE_IRQ,
869 },
870};
871
872static struct platform_device pmu_device = {
873 .name = "arm-pmu",
874 .id = -1,
875 .num_resources = ARRAY_SIZE(pmu_resources),
876 .resource = pmu_resources,
877};
878
879static struct platform_device *r8a7740_late_devices[] __initdata = {
880 &i2c0_device,
881 &i2c1_device,
882 &dma0_device,
883 &dma1_device,
884 &dma2_device,
885 &usb_dma_device,
886 &pmu_device,
887};
888
889
890
891
892
893
894
895#define MEBUFCNTR 0xFE950098
896void r8a7740_meram_workaround(void)
897{
898 void __iomem *reg;
899
900 reg = ioremap_nocache(MEBUFCNTR, 4);
901 if (reg) {
902 iowrite32(0x01600164, reg);
903 iounmap(reg);
904 }
905}
906
907#define ICCR 0x0004
908#define ICSTART 0x0070
909
910#define i2c_read(reg, offset) ioread8(reg + offset)
911#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
912
913
914
915
916
917static void r8a7740_i2c_workaround(struct platform_device *pdev)
918{
919 struct resource *res;
920 void __iomem *reg;
921
922 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
923 if (unlikely(!res)) {
924 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
925 return;
926 }
927
928 reg = ioremap(res->start, resource_size(res));
929 if (unlikely(!reg)) {
930 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
931 return;
932 }
933
934 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
935 i2c_read(reg, ICCR);
936
937 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
938 i2c_read(reg, ICSTART);
939
940 udelay(10);
941
942 i2c_write(reg, ICCR, 0x01);
943 i2c_write(reg, ICSTART, 0x00);
944
945 udelay(10);
946
947 i2c_write(reg, ICCR, 0x10);
948 udelay(10);
949 i2c_write(reg, ICCR, 0x00);
950 udelay(10);
951 i2c_write(reg, ICCR, 0x10);
952 udelay(10);
953
954 iounmap(reg);
955}
956
957void __init r8a7740_add_standard_devices(void)
958{
959
960 r8a7740_i2c_workaround(&i2c0_device);
961 r8a7740_i2c_workaround(&i2c1_device);
962
963 r8a7740_init_pm_domains();
964
965
966 platform_add_devices(r8a7740_early_devices,
967 ARRAY_SIZE(r8a7740_early_devices));
968 platform_add_devices(r8a7740_late_devices,
969 ARRAY_SIZE(r8a7740_late_devices));
970
971
972
973 rmobile_add_device_to_domain("A3SP", &scif0_device);
974 rmobile_add_device_to_domain("A3SP", &scif1_device);
975 rmobile_add_device_to_domain("A3SP", &scif2_device);
976 rmobile_add_device_to_domain("A3SP", &scif3_device);
977 rmobile_add_device_to_domain("A3SP", &scif4_device);
978 rmobile_add_device_to_domain("A3SP", &scif5_device);
979 rmobile_add_device_to_domain("A3SP", &scif6_device);
980 rmobile_add_device_to_domain("A3SP", &scif7_device);
981 rmobile_add_device_to_domain("A3SP", &scifb_device);
982 rmobile_add_device_to_domain("A3SP", &i2c1_device);
983}
984
985void __init r8a7740_add_early_devices(void)
986{
987 early_platform_add_devices(r8a7740_early_devices,
988 ARRAY_SIZE(r8a7740_early_devices));
989
990
991 shmobile_setup_console();
992}
993
994#ifdef CONFIG_USE_OF
995
996void __init r8a7740_add_early_devices_dt(void)
997{
998 shmobile_setup_delay(800, 1, 3);
999
1000 early_platform_add_devices(r8a7740_early_devices,
1001 ARRAY_SIZE(r8a7740_early_devices));
1002
1003
1004 shmobile_setup_console();
1005}
1006
1007static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
1008 { }
1009};
1010
1011void __init r8a7740_add_standard_devices_dt(void)
1012{
1013
1014 r8a7740_clock_init(0);
1015
1016 platform_add_devices(r8a7740_early_devices,
1017 ARRAY_SIZE(r8a7740_early_devices));
1018
1019 of_platform_populate(NULL, of_default_bus_match_table,
1020 r8a7740_auxdata_lookup, NULL);
1021}
1022
1023static const char *r8a7740_boards_compat_dt[] __initdata = {
1024 "renesas,r8a7740",
1025 NULL,
1026};
1027
1028DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
1029 .map_io = r8a7740_map_io,
1030 .init_early = r8a7740_add_early_devices_dt,
1031 .init_irq = r8a7740_init_irq,
1032 .init_machine = r8a7740_add_standard_devices_dt,
1033 .dt_compat = r8a7740_boards_compat_dt,
1034MACHINE_END
1035
1036#endif
1037
