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11#ifndef _ASM_CPU_REGS_H
12#define _ASM_CPU_REGS_H
13
14#ifndef __ASSEMBLY__
15#include <linux/types.h>
16#endif
17
18
19
20
21#ifndef __ASSEMBLY__
22asm(" .am33_2\n");
23#else
24.am33_2
25#endif
26
27#ifdef __KERNEL__
28
29#ifndef __ASSEMBLY__
30#define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR))
31#define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR))
32#else
33#define __SYSREG(ADDR, TYPE) ADDR
34#define __SYSREGC(ADDR, TYPE) ADDR
35#endif
36
37
38#define EPSW_FLAG_Z 0x00000001
39#define EPSW_FLAG_N 0x00000002
40#define EPSW_FLAG_C 0x00000004
41#define EPSW_FLAG_V 0x00000008
42#define EPSW_IM 0x00000700
43#define EPSW_IM_0 0x00000000
44#define EPSW_IM_1 0x00000100
45#define EPSW_IM_2 0x00000200
46#define EPSW_IM_3 0x00000300
47#define EPSW_IM_4 0x00000400
48#define EPSW_IM_5 0x00000500
49#define EPSW_IM_6 0x00000600
50#define EPSW_IM_7 0x00000700
51#define EPSW_IE 0x00000800
52#define EPSW_S 0x00003000
53#define EPSW_T 0x00008000
54#define EPSW_nSL 0x00010000
55#define EPSW_NMID 0x00020000
56#define EPSW_nAR 0x00040000
57#define EPSW_ML 0x00080000
58#define EPSW_FE 0x00100000
59#define EPSW_IM_SHIFT 8
60
61#define NUM2EPSW_IM(num) ((num) << EPSW_IM_SHIFT)
62
63
64#define FPCR_EF_I 0x00000001
65#define FPCR_EF_U 0x00000002
66#define FPCR_EF_O 0x00000004
67#define FPCR_EF_Z 0x00000008
68#define FPCR_EF_V 0x00000010
69#define FPCR_EE_I 0x00000020
70#define FPCR_EE_U 0x00000040
71#define FPCR_EE_O 0x00000080
72#define FPCR_EE_Z 0x00000100
73#define FPCR_EE_V 0x00000200
74#define FPCR_EC_I 0x00000400
75#define FPCR_EC_U 0x00000800
76#define FPCR_EC_O 0x00001000
77#define FPCR_EC_Z 0x00002000
78#define FPCR_EC_V 0x00004000
79#define FPCR_RM 0x00030000
80#define FPCR_RM_NEAREST 0x00000000
81#define FPCR_FCC_U 0x00040000
82#define FPCR_FCC_E 0x00080000
83#define FPCR_FCC_G 0x00100000
84#define FPCR_FCC_L 0x00200000
85#define FPCR_INIT 0x00000000
86
87
88#define CPUP __SYSREG(0xc0000020, u16)
89#define CPUP_DWBD 0x0020
90#define CPUP_IPFD 0x0040
91#define CPUP_EXM 0x0080
92#define CPUP_EXM_AM33V1 0x0000
93#define CPUP_EXM_AM33V2 0x0080
94
95#define CPUM __SYSREG(0xc0000040, u16)
96#define CPUM_SLEEP 0x0004
97#define CPUM_HALT 0x0008
98#define CPUM_STOP 0x0010
99
100#define CPUREV __SYSREGC(0xc0000050, u32)
101#define CPUREV_TYPE 0x0000000f
102#define CPUREV_TYPE_S 0
103#define CPUREV_TYPE_AM33_1 0x00000000
104#define CPUREV_TYPE_AM33_2 0x00000001
105#define CPUREV_TYPE_AM34_1 0x00000002
106#define CPUREV_TYPE_AM33_3 0x00000003
107#define CPUREV_TYPE_AM34_2 0x00000004
108#define CPUREV_REVISION 0x000000f0
109#define CPUREV_REVISION_S 4
110#define CPUREV_ICWAY 0x00000f00
111#define CPUREV_ICWAY_S 8
112#define CPUREV_ICSIZE 0x0000f000
113#define CPUREV_ICSIZE_S 12
114#define CPUREV_DCWAY 0x000f0000
115#define CPUREV_DCWAY_S 16
116#define CPUREV_DCSIZE 0x00f00000
117#define CPUREV_DCSIZE_S 20
118#define CPUREV_FPUTYPE 0x0f000000
119#define CPUREV_FPUTYPE_NONE 0x00000000
120#define CPUREV_OCDCTG 0xf0000000
121
122#define DCR __SYSREG(0xc0000030, u16)
123
124
125#define IVAR0 __SYSREG(0xc0000000, u16)
126#define IVAR1 __SYSREG(0xc0000004, u16)
127#define IVAR2 __SYSREG(0xc0000008, u16)
128#define IVAR3 __SYSREG(0xc000000c, u16)
129#define IVAR4 __SYSREG(0xc0000010, u16)
130#define IVAR5 __SYSREG(0xc0000014, u16)
131#define IVAR6 __SYSREG(0xc0000018, u16)
132
133#define TBR __SYSREG(0xc0000024, u32)
134#define TBR_TB 0xff000000
135#define TBR_INT_CODE 0x00ffffff
136
137#define DEAR __SYSREG(0xc0000038, u32)
138
139#define sISR __SYSREG(0xc0000044, u32)
140#define sISR_IRQICE 0x00000001
141#define sISR_ISTEP 0x00000002
142#define sISR_MISSA 0x00000004
143#define sISR_UNIMP 0x00000008
144#define sISR_PIEXE 0x00000010
145#define sISR_MEMERR 0x00000020
146#define sISR_IBREAK 0x00000040
147#define sISR_DBSRL 0x00000080
148#define sISR_PERIDB 0x00000100
149#define sISR_EXUNIMP 0x00000200
150#define sISR_OBREAK 0x00000400
151#define sISR_PRIV 0x00000800
152#define sISR_BUSERR 0x00001000
153#define sISR_DBLFT 0x00002000
154#define sISR_DBG 0x00008000
155#define sISR_ITMISS 0x00010000
156#define sISR_DTMISS 0x00020000
157#define sISR_ITEX 0x00040000
158#define sISR_DTEX 0x00080000
159#define sISR_ILGIA 0x00100000
160#define sISR_ILGDA 0x00200000
161#define sISR_IOIA 0x00400000
162#define sISR_PRIVA 0x00800000
163#define sISR_PRIDA 0x01000000
164#define sISR_DISA 0x02000000
165#define sISR_SYSC 0x04000000
166#define sISR_FPUD 0x08000000
167#define sISR_FPUUI 0x10000000
168#define sISR_FPUOP 0x20000000
169#define sISR_NE 0x80000000
170
171
172#define CHCTR __SYSREG(0xc0000070, u16)
173#define CHCTR_ICEN 0x0001
174#define CHCTR_DCEN 0x0002
175#define CHCTR_ICBUSY 0x0004
176#define CHCTR_DCBUSY 0x0008
177#define CHCTR_ICINV 0x0010
178#define CHCTR_DCINV 0x0020
179#define CHCTR_DCWTMD 0x0040
180#define CHCTR_DCWTMD_WRBACK 0x0000
181#define CHCTR_DCWTMD_WRTHROUGH 0x0040
182#define CHCTR_DCALMD 0x0080
183#define CHCTR_ICWMD 0x0f00
184#define CHCTR_DCWMD 0xf000
185
186#ifdef CONFIG_AM34_2
187#define ICIVCR __SYSREG(0xc0000c00, u32)
188#define ICIVCR_ICIVBSY 0x00000008
189#define ICIVCR_ICI 0x00000001
190
191#define ICIVMR __SYSREG(0xc0000c04, u32)
192
193#define DCPGCR __SYSREG(0xc0000c10, u32)
194#define DCPGCR_DCPGBSY 0x00000008
195#define DCPGCR_DCP 0x00000002
196#define DCPGCR_DCI 0x00000001
197
198#define DCPGMR __SYSREG(0xc0000c14, u32)
199#endif
200
201
202#define MMUCTR __SYSREG(0xc0000090, u32)
203#define MMUCTR_IRP 0x0000003f
204#define MMUCTR_ITE 0x00000040
205#define MMUCTR_IIV 0x00000080
206#define MMUCTR_ITL 0x00000700
207#define MMUCTR_ITL_NOLOCK 0x00000000
208#define MMUCTR_ITL_LOCK0 0x00000100
209#define MMUCTR_ITL_LOCK0_1 0x00000200
210#define MMUCTR_ITL_LOCK0_3 0x00000300
211#define MMUCTR_ITL_LOCK0_7 0x00000400
212#define MMUCTR_ITL_LOCK0_15 0x00000500
213#define MMUCTR_CE 0x00008000
214#define MMUCTR_DRP 0x003f0000
215#define MMUCTR_DTE 0x00400000
216#define MMUCTR_DIV 0x00800000
217#define MMUCTR_DTL 0x07000000
218#define MMUCTR_DTL_NOLOCK 0x00000000
219#define MMUCTR_DTL_LOCK0 0x01000000
220#define MMUCTR_DTL_LOCK0_1 0x02000000
221#define MMUCTR_DTL_LOCK0_3 0x03000000
222#define MMUCTR_DTL_LOCK0_7 0x04000000
223#define MMUCTR_DTL_LOCK0_15 0x05000000
224#ifdef CONFIG_AM34_2
225#define MMUCTR_WTE 0x80000000
226#endif
227
228#define PIDR __SYSREG(0xc0000094, u16)
229#define PIDR_PID 0x00ff
230
231#define PTBR __SYSREG(0xc0000098, unsigned long)
232
233#define IPTEL __SYSREG(0xc00000a0, u32)
234#define DPTEL __SYSREG(0xc00000b0, u32)
235#define xPTEL_V 0x00000001
236#define xPTEL_UNUSED1 0x00000002
237#define xPTEL_UNUSED2 0x00000004
238#define xPTEL_C 0x00000008
239#define xPTEL_PV 0x00000010
240#define xPTEL_D 0x00000020
241#define xPTEL_PR 0x000001c0
242#define xPTEL_PR_ROK 0x00000000
243#define xPTEL_PR_RWK 0x00000100
244#define xPTEL_PR_ROK_ROU 0x00000080
245#define xPTEL_PR_RWK_ROU 0x00000180
246#define xPTEL_PR_RWK_RWU 0x000001c0
247#define xPTEL_G 0x00000200
248#define xPTEL_PS 0x00000c00
249#define xPTEL_PS_4Kb 0x00000000
250#define xPTEL_PS_128Kb 0x00000400
251#define xPTEL_PS_1Kb 0x00000800
252#define xPTEL_PS_4Mb 0x00000c00
253#define xPTEL_PPN 0xfffff006
254
255#define IPTEU __SYSREG(0xc00000a4, u32)
256#define DPTEU __SYSREG(0xc00000b4, u32)
257#define xPTEU_VPN 0xfffffc00
258#define xPTEU_PID 0x000000ff
259
260#define IPTEL2 __SYSREG(0xc00000a8, u32)
261#define DPTEL2 __SYSREG(0xc00000b8, u32)
262#define xPTEL2_V 0x00000001
263#define xPTEL2_C 0x00000002
264#define xPTEL2_PV 0x00000004
265#define xPTEL2_D 0x00000008
266#define xPTEL2_PR 0x00000070
267#define xPTEL2_PR_ROK 0x00000000
268#define xPTEL2_PR_RWK 0x00000040
269#define xPTEL2_PR_ROK_ROU 0x00000020
270#define xPTEL2_PR_RWK_ROU 0x00000060
271#define xPTEL2_PR_RWK_RWU 0x00000070
272#define xPTEL2_G 0x00000080
273#define xPTEL2_PS 0x00000300
274#define xPTEL2_PS_4Kb 0x00000000
275#define xPTEL2_PS_128Kb 0x00000100
276#define xPTEL2_PS_1Kb 0x00000200
277#define xPTEL2_PS_4Mb 0x00000300
278#define xPTEL2_CWT 0x00000400
279#define xPTEL2_UNUSED1 0x00000800
280#define xPTEL2_PPN 0xfffff000
281
282#define xPTEL2_V_BIT 0
283#define xPTEL2_C_BIT 1
284#define xPTEL2_PV_BIT 2
285#define xPTEL2_D_BIT 3
286#define xPTEL2_G_BIT 7
287#define xPTEL2_UNUSED1_BIT 11
288
289#define MMUFCR __SYSREGC(0xc000009c, u32)
290#define MMUFCR_IFC __SYSREGC(0xc000009c, u16)
291#define MMUFCR_DFC __SYSREGC(0xc000009e, u16)
292#define MMUFCR_xFC_TLBMISS 0x0001
293#define MMUFCR_xFC_INITWR 0x0002
294#define MMUFCR_xFC_PGINVAL 0x0004
295#define MMUFCR_xFC_PROTVIOL 0x0008
296#define MMUFCR_xFC_ACCESS 0x0010
297#define MMUFCR_xFC_ACCESS_USR 0x0000
298#define MMUFCR_xFC_ACCESS_SR 0x0010
299#define MMUFCR_xFC_TYPE 0x0020
300#define MMUFCR_xFC_TYPE_READ 0x0000
301#define MMUFCR_xFC_TYPE_WRITE 0x0020
302#define MMUFCR_xFC_PR 0x01c0
303#define MMUFCR_xFC_PR_ROK 0x0000
304#define MMUFCR_xFC_PR_RWK 0x0100
305#define MMUFCR_xFC_PR_ROK_ROU 0x0080
306#define MMUFCR_xFC_PR_RWK_ROU 0x0180
307#define MMUFCR_xFC_PR_RWK_RWU 0x01c0
308#define MMUFCR_xFC_ILLADDR 0x0200
309
310#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
311
312#define AAR __SYSREG(0xc0000a00, u32)
313#define AAR2 __SYSREG(0xc0000a04, u32)
314#define ADR __SYSREG(0xc0000a08, u32)
315#define ASR __SYSREG(0xc0000a0c, u32)
316#define AARU __SYSREG(0xd400aa00, u32)
317#define ADRU __SYSREG(0xd400aa08, u32)
318#define ASRU __SYSREG(0xd400aa0c, u32)
319
320#define ASR_RW 0x00000008
321#define ASR_BW 0x00000004
322#define ASR_IW 0x00000002
323#define ASR_LW 0x00000001
324
325#define ASRU_RW ASR_RW
326#define ASRU_BW ASR_BW
327#define ASRU_IW ASR_IW
328#define ASRU_LW ASR_LW
329
330
331
332#define ATOMIC_OPS_BASE_ADDR 0xc0000a00
333#ifndef __ASSEMBLY__
334asm(
335 "_AAR = 0\n"
336 "_AAR2 = 4\n"
337 "_ADR = 8\n"
338 "_ASR = 12\n");
339#else
340#define _AAR 0
341#define _AAR2 4
342#define _ADR 8
343#define _ASR 12
344#endif
345
346
347#define USER_ATOMIC_OPS_PAGE_ADDR 0xd400a000
348
349#endif
350
351#endif
352
353#endif
354