LXR linux/arch/powerpc/sysdev/ppc4xx

   1/*
   2 * PPC4xx gpio driver
   3 *
   4 * Copyright (c) 2008 Harris Corporation
   5 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
   6 * Copyright (c) MontaVista Software, Inc. 2008.
   7 *
   8 * Author: Steve Falco <sfalco@harris.com>
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2
  12 * as published by the Free Software Foundation.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22 */
  23
  24#include <linux/kernel.h>
  25#include <linux/init.h>
  26#include <linux/spinlock.h>
  27#include <linux/io.h>
  28#include <linux/of.h>
  29#include <linux/of_gpio.h>
  30#include <linux/gpio.h>
  31#include <linux/types.h>
  32#include <linux/slab.h>
  33
  34#define GPIO_MASK(gpio)         (0x80000000 >> (gpio))
  35#define GPIO_MASK2(gpio)        (0xc0000000 >> ((gpio) * 2))
  36
  37/* Physical GPIO register layout */
  38struct ppc4xx_gpio {
  39        __be32 or;
  40        __be32 tcr;
  41        __be32 osrl;
  42        __be32 osrh;
  43        __be32 tsrl;
  44        __be32 tsrh;
  45        __be32 odr;
  46        __be32 ir;
  47        __be32 rr1;
  48        __be32 rr2;
  49        __be32 rr3;
  50        __be32 reserved1;
  51        __be32 isr1l;
  52        __be32 isr1h;
  53        __be32 isr2l;
  54        __be32 isr2h;
  55        __be32 isr3l;
  56        __be32 isr3h;
  57};
  58
  59struct ppc4xx_gpio_chip {
  60        struct of_mm_gpio_chip mm_gc;
  61        spinlock_t lock;
  62};
  63
  64/*
  65 * GPIO LIB API implementation for GPIOs
  66 *
  67 * There are a maximum of 32 gpios in each gpio controller.
  68 */
  69
  70static inline struct ppc4xx_gpio_chip *
  71to_ppc4xx_gpiochip(struct of_mm_gpio_chip *mm_gc)
  72{
  73        return container_of(mm_gc, struct ppc4xx_gpio_chip, mm_gc);
  74}
  75
  76static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  77{
  78        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  79        struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
  80
  81        return in_be32(&regs->ir) & GPIO_MASK(gpio);
  82}
  83
  84static inline void
  85__ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  86{
  87        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  88        struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
  89
  90        if (val)
  91                setbits32(&regs->or, GPIO_MASK(gpio));
  92        else
  93                clrbits32(&regs->or, GPIO_MASK(gpio));
  94}
  95
  96static void
  97ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  98{
  99        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 100        struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc);
 101        unsigned long flags;
 102
 103        spin_lock_irqsave(&chip->lock, flags);
 104
 105        __ppc4xx_gpio_set(gc, gpio, val);
 106
 107        spin_unlock_irqrestore(&chip->lock, flags);
 108
 109        pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
 110}
 111
 112static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 113{
 114        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 115        struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc);
 116        struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
 117        unsigned long flags;
 118
 119        spin_lock_irqsave(&chip->lock, flags);
 120
 121        /* Disable open-drain function */
 122        clrbits32(&regs->odr, GPIO_MASK(gpio));
 123
 124        /* Float the pin */
 125        clrbits32(&regs->tcr, GPIO_MASK(gpio));
 126
 127        /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
 128        if (gpio < 16) {
 129                clrbits32(&regs->osrl, GPIO_MASK2(gpio));
 130                clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
 131        } else {
 132                clrbits32(&regs->osrh, GPIO_MASK2(gpio));
 133                clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
 134        }
 135
 136        spin_unlock_irqrestore(&chip->lock, flags);
 137
 138        return 0;
 139}
 140
 141static int
 142ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 143{
 144        struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 145        struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc);
 146        struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
 147        unsigned long flags;
 148
 149        spin_lock_irqsave(&chip->lock, flags);
 150
 151        /* First set initial value */
 152        __ppc4xx_gpio_set(gc, gpio, val);
 153
 154        /* Disable open-drain function */
 155        clrbits32(&regs->odr, GPIO_MASK(gpio));
 156
 157        /* Drive the pin */
 158        setbits32(&regs->tcr, GPIO_MASK(gpio));
 159
 160        /* Bits 0-15 use TSRL, bits 16-31 use TSRH */
 161        if (gpio < 16) {
 162                clrbits32(&regs->osrl, GPIO_MASK2(gpio));
 163                clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
 164        } else {
 165                clrbits32(&regs->osrh, GPIO_MASK2(gpio));
 166                clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
 167        }
 168
 169        spin_unlock_irqrestore(&chip->lock, flags);
 170
 171        pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
 172
 173        return 0;
 174}
 175
 176static int __init ppc4xx_add_gpiochips(void)
 177{
 178        struct device_node *np;
 179
 180        for_each_compatible_node(np, NULL, "ibm,ppc4xx-gpio") {
 181                int ret;
 182                struct ppc4xx_gpio_chip *ppc4xx_gc;
 183                struct of_mm_gpio_chip *mm_gc;
 184                struct gpio_chip *gc;
 185
 186                ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL);
 187                if (!ppc4xx_gc) {
 188                        ret = -ENOMEM;
 189                        goto err;
 190                }
 191
 192                spin_lock_init(&ppc4xx_gc->lock);
 193
 194                mm_gc = &ppc4xx_gc->mm_gc;
 195                gc = &mm_gc->gc;
 196
 197                gc->ngpio = 32;
 198                gc->direction_input = ppc4xx_gpio_dir_in;
 199                gc->direction_output = ppc4xx_gpio_dir_out;
 200                gc->get = ppc4xx_gpio_get;
 201                gc->set = ppc4xx_gpio_set;
 202
 203                ret = of_mm_gpiochip_add(np, mm_gc);
 204                if (ret)
 205                        goto err;
 206                continue;
 207err:
 208                pr_err("%s: registration failed with status %d\n",
 209                       np->full_name, ret);
 210                kfree(ppc4xx_gc);
 211                /* try others anyway */
 212        }
 213        return 0;
 214}
 215arch_initcall(ppc4xx_add_gpiochips);
 216