1
2
3
4
5#include <linux/interrupt.h>
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/smp.h>
9
10#include <asm/processor.h>
11#include <asm/mce.h>
12#include <asm/msr.h>
13
14
15int mce_p5_enabled __read_mostly;
16
17
18static void pentium_machine_check(struct pt_regs *regs, long error_code)
19{
20 u32 loaddr, hi, lotype;
21
22 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
23 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
24
25 printk(KERN_EMERG
26 "CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
27 smp_processor_id(), loaddr, lotype);
28
29 if (lotype & (1<<5)) {
30 printk(KERN_EMERG
31 "CPU#%d: Possible thermal failure (CPU on fire ?).\n",
32 smp_processor_id());
33 }
34
35 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
36}
37
38
39void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
40{
41 u32 l, h;
42
43
44 if (!mce_p5_enabled)
45 return;
46
47
48 if (!cpu_has(c, X86_FEATURE_MCE))
49 return;
50
51 machine_check_vector = pentium_machine_check;
52
53 wmb();
54
55
56 rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
57 rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
58 printk(KERN_INFO
59 "Intel old style machine check architecture supported.\n");
60
61
62 set_in_cr4(X86_CR4_MCE);
63 printk(KERN_INFO
64 "Intel old style machine check reporting enabled on CPU#%d.\n",
65 smp_processor_id());
66}
67