LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2008 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 * Copyright 2009 Jerome Glisse.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors: Dave Airlie
  25 *          Alex Deucher
  26 *          Jerome Glisse
  27 */
  28#ifndef __AMDGPU_OBJECT_H__
  29#define __AMDGPU_OBJECT_H__
  30
  31#include <drm/amdgpu_drm.h>
  32#include "amdgpu.h"
  33
  34#define AMDGPU_BO_INVALID_OFFSET        LONG_MAX
  35
  36/**
  37 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type
  38 * @mem_type:   ttm memory type
  39 *
  40 * Returns corresponding domain of the ttm mem_type
  41 */
  42static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
  43{
  44        switch (mem_type) {
  45        case TTM_PL_VRAM:
  46                return AMDGPU_GEM_DOMAIN_VRAM;
  47        case TTM_PL_TT:
  48                return AMDGPU_GEM_DOMAIN_GTT;
  49        case TTM_PL_SYSTEM:
  50                return AMDGPU_GEM_DOMAIN_CPU;
  51        case AMDGPU_PL_GDS:
  52                return AMDGPU_GEM_DOMAIN_GDS;
  53        case AMDGPU_PL_GWS:
  54                return AMDGPU_GEM_DOMAIN_GWS;
  55        case AMDGPU_PL_OA:
  56                return AMDGPU_GEM_DOMAIN_OA;
  57        default:
  58                break;
  59        }
  60        return 0;
  61}
  62
  63/**
  64 * amdgpu_bo_reserve - reserve bo
  65 * @bo:         bo structure
  66 * @no_intr:    don't return -ERESTARTSYS on pending signal
  67 *
  68 * Returns:
  69 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
  70 * a signal. Release all buffer reservations and return to user-space.
  71 */
  72static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
  73{
  74        struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
  75        int r;
  76
  77        r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
  78        if (unlikely(r != 0)) {
  79                if (r != -ERESTARTSYS)
  80                        dev_err(adev->dev, "%p reserve failed\n", bo);
  81                return r;
  82        }
  83        return 0;
  84}
  85
  86static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
  87{
  88        ttm_bo_unreserve(&bo->tbo);
  89}
  90
  91static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
  92{
  93        return bo->tbo.num_pages << PAGE_SHIFT;
  94}
  95
  96static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
  97{
  98        return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
  99}
 100
 101static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
 102{
 103        return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
 104}
 105
 106/**
 107 * amdgpu_bo_mmap_offset - return mmap offset of bo
 108 * @bo: amdgpu object for which we query the offset
 109 *
 110 * Returns mmap offset of the object.
 111 */
 112static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
 113{
 114        return drm_vma_node_offset_addr(&bo->tbo.vma_node);
 115}
 116
 117int amdgpu_bo_create(struct amdgpu_device *adev,
 118                            unsigned long size, int byte_align,
 119                            bool kernel, u32 domain, u64 flags,
 120                            struct sg_table *sg,
 121                            struct reservation_object *resv,
 122                            struct amdgpu_bo **bo_ptr);
 123int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 124                                unsigned long size, int byte_align,
 125                                bool kernel, u32 domain, u64 flags,
 126                                struct sg_table *sg,
 127                                struct ttm_placement *placement,
 128                                struct reservation_object *resv,
 129                                struct amdgpu_bo **bo_ptr);
 130int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 131                            unsigned long size, int align,
 132                            u32 domain, struct amdgpu_bo **bo_ptr,
 133                            u64 *gpu_addr, void **cpu_addr);
 134void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 135                           void **cpu_addr);
 136int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
 137void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
 138struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
 139void amdgpu_bo_unref(struct amdgpu_bo **bo);
 140int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
 141int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 142                             u64 min_offset, u64 max_offset,
 143                             u64 *gpu_addr);
 144int amdgpu_bo_unpin(struct amdgpu_bo *bo);
 145int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
 146int amdgpu_bo_init(struct amdgpu_device *adev);
 147void amdgpu_bo_fini(struct amdgpu_device *adev);
 148int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 149                                struct vm_area_struct *vma);
 150int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
 151void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
 152int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 153                            uint32_t metadata_size, uint64_t flags);
 154int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 155                           size_t buffer_size, uint32_t *metadata_size,
 156                           uint64_t *flags);
 157void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 158                                  struct ttm_mem_reg *new_mem);
 159int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
 160void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
 161                     bool shared);
 162u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
 163int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 164                               struct amdgpu_ring *ring,
 165                               struct amdgpu_bo *bo,
 166                               struct reservation_object *resv,
 167                               struct dma_fence **fence, bool direct);
 168int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 169                                  struct amdgpu_ring *ring,
 170                                  struct amdgpu_bo *bo,
 171                                  struct reservation_object *resv,
 172                                  struct dma_fence **fence,
 173                                  bool direct);
 174
 175
 176/*
 177 * sub allocation
 178 */
 179
 180static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
 181{
 182        return sa_bo->manager->gpu_addr + sa_bo->soffset;
 183}
 184
 185static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
 186{
 187        return sa_bo->manager->cpu_ptr + sa_bo->soffset;
 188}
 189
 190int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
 191                                     struct amdgpu_sa_manager *sa_manager,
 192                                     unsigned size, u32 align, u32 domain);
 193void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
 194                                      struct amdgpu_sa_manager *sa_manager);
 195int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
 196                                      struct amdgpu_sa_manager *sa_manager);
 197int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
 198                                        struct amdgpu_sa_manager *sa_manager);
 199int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
 200                     struct amdgpu_sa_bo **sa_bo,
 201                     unsigned size, unsigned align);
 202void amdgpu_sa_bo_free(struct amdgpu_device *adev,
 203                              struct amdgpu_sa_bo **sa_bo,
 204                              struct dma_fence *fence);
 205#if defined(CONFIG_DEBUG_FS)
 206void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
 207                                         struct seq_file *m);
 208#endif
 209
 210
 211#endif
 212