LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include <engine/sec.h>
  25#include <engine/fifo.h>
  26#include "fuc/g98.fuc0s.h"
  27
  28#include <core/client.h>
  29#include <core/enum.h>
  30#include <core/gpuobj.h>
  31
  32#include <nvif/class.h>
  33
  34static const struct nvkm_enum g98_sec_isr_error_name[] = {
  35        { 0x0000, "ILLEGAL_MTHD" },
  36        { 0x0001, "INVALID_BITFIELD" },
  37        { 0x0002, "INVALID_ENUM" },
  38        { 0x0003, "QUERY" },
  39        {}
  40};
  41
  42static void
  43g98_sec_intr(struct nvkm_falcon *sec, struct nvkm_fifo_chan *chan)
  44{
  45        struct nvkm_subdev *subdev = &sec->engine.subdev;
  46        struct nvkm_device *device = subdev->device;
  47        u32 ssta = nvkm_rd32(device, 0x087040) & 0x0000ffff;
  48        u32 addr = nvkm_rd32(device, 0x087040) >> 16;
  49        u32 mthd = (addr & 0x07ff) << 2;
  50        u32 subc = (addr & 0x3800) >> 11;
  51        u32 data = nvkm_rd32(device, 0x087044);
  52        const struct nvkm_enum *en =
  53                nvkm_enum_find(g98_sec_isr_error_name, ssta);
  54
  55        nvkm_error(subdev, "DISPATCH_ERROR %04x [%s] ch %d [%010llx %s] "
  56                           "subc %d mthd %04x data %08x\n", ssta,
  57                   en ? en->name : "UNKNOWN", chan ? chan->chid : -1,
  58                   chan ? chan->inst->addr : 0,
  59                   chan ? chan->object.client->name : "unknown",
  60                   subc, mthd, data);
  61}
  62
  63static const struct nvkm_falcon_func
  64g98_sec = {
  65        .code.data = g98_sec_code,
  66        .code.size = sizeof(g98_sec_code),
  67        .data.data = g98_sec_data,
  68        .data.size = sizeof(g98_sec_data),
  69        .intr = g98_sec_intr,
  70        .sclass = {
  71                { -1, -1, G98_SEC },
  72                {}
  73        }
  74};
  75
  76int
  77g98_sec_new(struct nvkm_device *device, int index,
  78            struct nvkm_engine **pengine)
  79{
  80        return nvkm_falcon_new_(&g98_sec, device, index,
  81                                true, 0x087000, pengine);
  82}
  83