linux/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
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   1/*
   2 * Copyright 2007-8 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26#include <drm/drmP.h>
  27#include <drm/drm_crtc_helper.h>
  28#include <drm/drm_fb_helper.h>
  29#include <drm/radeon_drm.h>
  30#include <drm/drm_fixed.h>
  31#include "radeon.h"
  32#include "atom.h"
  33
  34static void radeon_overscan_setup(struct drm_crtc *crtc,
  35                                  struct drm_display_mode *mode)
  36{
  37        struct drm_device *dev = crtc->dev;
  38        struct radeon_device *rdev = dev->dev_private;
  39        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  40
  41        WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
  42        WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
  43        WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
  44}
  45
  46static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  47                                       struct drm_display_mode *mode)
  48{
  49        struct drm_device *dev = crtc->dev;
  50        struct radeon_device *rdev = dev->dev_private;
  51        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  52        int xres = mode->hdisplay;
  53        int yres = mode->vdisplay;
  54        bool hscale = true, vscale = true;
  55        int hsync_wid;
  56        int vsync_wid;
  57        int hsync_start;
  58        int blank_width;
  59        u32 scale, inc, crtc_more_cntl;
  60        u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  61        u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  62        u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  63        struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  64
  65        fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  66                (RADEON_VERT_STRETCH_RESERVED |
  67                 RADEON_VERT_AUTO_RATIO_INC);
  68        fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  69                (RADEON_HORZ_FP_LOOP_STRETCH |
  70                 RADEON_HORZ_AUTO_RATIO_INC);
  71
  72        crtc_more_cntl = 0;
  73        if ((rdev->family == CHIP_RS100) ||
  74            (rdev->family == CHIP_RS200)) {
  75                /* This is to workaround the asic bug for RMX, some versions
  76                   of BIOS dosen't have this register initialized correctly. */
  77                crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  78        }
  79
  80
  81        fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  82                                | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  83
  84        hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  85        if (!hsync_wid)
  86                hsync_wid = 1;
  87        hsync_start = mode->crtc_hsync_start - 8;
  88
  89        fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  90                              | ((hsync_wid & 0x3f) << 16)
  91                              | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  92                                 ? RADEON_CRTC_H_SYNC_POL
  93                                 : 0));
  94
  95        fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  96                                | ((mode->crtc_vdisplay - 1) << 16));
  97
  98        vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  99        if (!vsync_wid)
 100                vsync_wid = 1;
 101
 102        fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 103                              | ((vsync_wid & 0x1f) << 16)
 104                              | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 105                                 ? RADEON_CRTC_V_SYNC_POL
 106                                 : 0));
 107
 108        fp_horz_vert_active = 0;
 109
 110        if (native_mode->hdisplay == 0 ||
 111            native_mode->vdisplay == 0) {
 112                hscale = false;
 113                vscale = false;
 114        } else {
 115                if (xres > native_mode->hdisplay)
 116                        xres = native_mode->hdisplay;
 117                if (yres > native_mode->vdisplay)
 118                        yres = native_mode->vdisplay;
 119
 120                if (xres == native_mode->hdisplay)
 121                        hscale = false;
 122                if (yres == native_mode->vdisplay)
 123                        vscale = false;
 124        }
 125
 126        switch (radeon_crtc->rmx_type) {
 127        case RMX_FULL:
 128        case RMX_ASPECT:
 129                if (!hscale)
 130                        fp_horz_stretch |= ((xres/8-1) << 16);
 131                else {
 132                        inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 133                        scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 134                                / native_mode->hdisplay + 1;
 135                        fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 136                                        RADEON_HORZ_STRETCH_BLEND |
 137                                        RADEON_HORZ_STRETCH_ENABLE |
 138                                        ((native_mode->hdisplay/8-1) << 16));
 139                }
 140
 141                if (!vscale)
 142                        fp_vert_stretch |= ((yres-1) << 12);
 143                else {
 144                        inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 145                        scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 146                                / native_mode->vdisplay + 1;
 147                        fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 148                                        RADEON_VERT_STRETCH_ENABLE |
 149                                        RADEON_VERT_STRETCH_BLEND |
 150                                        ((native_mode->vdisplay-1) << 12));
 151                }
 152                break;
 153        case RMX_CENTER:
 154                fp_horz_stretch |= ((xres/8-1) << 16);
 155                fp_vert_stretch |= ((yres-1) << 12);
 156
 157                crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 158                                RADEON_CRTC_AUTO_VERT_CENTER_EN);
 159
 160                blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 161                if (blank_width > 110)
 162                        blank_width = 110;
 163
 164                fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 165                                | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 166
 167                hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 168                if (!hsync_wid)
 169                        hsync_wid = 1;
 170
 171                fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 172                                | ((hsync_wid & 0x3f) << 16)
 173                                | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 174                                        ? RADEON_CRTC_H_SYNC_POL
 175                                        : 0));
 176
 177                fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 178                                | ((mode->crtc_vdisplay - 1) << 16));
 179
 180                vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 181                if (!vsync_wid)
 182                        vsync_wid = 1;
 183
 184                fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 185                                        | ((vsync_wid & 0x1f) << 16)
 186                                        | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 187                                                ? RADEON_CRTC_V_SYNC_POL
 188                                                : 0)));
 189
 190                fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 191                                (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 192                break;
 193        case RMX_OFF:
 194        default:
 195                fp_horz_stretch |= ((xres/8-1) << 16);
 196                fp_vert_stretch |= ((yres-1) << 12);
 197                break;
 198        }
 199
 200        WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 201        WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 202        WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 203        WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 204        WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 205        WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 206        WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 207        WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 208}
 209
 210static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 211{
 212        struct radeon_device *rdev = dev->dev_private;
 213        int i = 0;
 214
 215        /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 216           the cause yet, but this workaround will mask the problem for now.
 217           Other chips usually will pass at the very first test, so the
 218           workaround shouldn't have any effect on them. */
 219        for (i = 0;
 220             (i < 10000 &&
 221              RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 222             i++);
 223}
 224
 225static void radeon_pll_write_update(struct drm_device *dev)
 226{
 227        struct radeon_device *rdev = dev->dev_private;
 228
 229        while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 230
 231        WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 232                           RADEON_PPLL_ATOMIC_UPDATE_W,
 233                           ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 234}
 235
 236static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 237{
 238        struct radeon_device *rdev = dev->dev_private;
 239        int i = 0;
 240
 241
 242        /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 243           the cause yet, but this workaround will mask the problem for now.
 244           Other chips usually will pass at the very first test, so the
 245           workaround shouldn't have any effect on them. */
 246        for (i = 0;
 247             (i < 10000 &&
 248              RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 249             i++);
 250}
 251
 252static void radeon_pll2_write_update(struct drm_device *dev)
 253{
 254        struct radeon_device *rdev = dev->dev_private;
 255
 256        while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 257
 258        WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 259                           RADEON_P2PLL_ATOMIC_UPDATE_W,
 260                           ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 261}
 262
 263static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 264                                       uint16_t fb_div)
 265{
 266        unsigned int vcoFreq;
 267
 268        if (!ref_div)
 269                return 1;
 270
 271        vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div;
 272
 273        /*
 274         * This is horribly crude: the VCO frequency range is divided into
 275         * 3 parts, each part having a fixed PLL gain value.
 276         */
 277        if (vcoFreq >= 30000)
 278                /*
 279                 * [300..max] MHz : 7
 280                 */
 281                return 7;
 282        else if (vcoFreq >= 18000)
 283                /*
 284                 * [180..300) MHz : 4
 285                 */
 286                return 4;
 287        else
 288                /*
 289                 * [0..180) MHz : 1
 290                 */
 291                return 1;
 292}
 293
 294static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 295{
 296        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 297        struct drm_device *dev = crtc->dev;
 298        struct radeon_device *rdev = dev->dev_private;
 299        uint32_t crtc_ext_cntl = 0;
 300        uint32_t mask;
 301
 302        if (radeon_crtc->crtc_id)
 303                mask = (RADEON_CRTC2_DISP_DIS |
 304                        RADEON_CRTC2_VSYNC_DIS |
 305                        RADEON_CRTC2_HSYNC_DIS |
 306                        RADEON_CRTC2_DISP_REQ_EN_B);
 307        else
 308                mask = (RADEON_CRTC_DISPLAY_DIS |
 309                        RADEON_CRTC_VSYNC_DIS |
 310                        RADEON_CRTC_HSYNC_DIS);
 311
 312        /*
 313         * On all dual CRTC GPUs this bit controls the CRTC of the primary DAC.
 314         * Therefore it is set in the DAC DMPS function.
 315         * This is different for GPU's with a single CRTC but a primary and a
 316         * TV DAC: here it controls the single CRTC no matter where it is
 317         * routed. Therefore we set it here.
 318         */
 319        if (rdev->flags & RADEON_SINGLE_CRTC)
 320                crtc_ext_cntl = RADEON_CRTC_CRT_ON;
 321        
 322        switch (mode) {
 323        case DRM_MODE_DPMS_ON:
 324                radeon_crtc->enabled = true;
 325                /* adjust pm to dpms changes BEFORE enabling crtcs */
 326                radeon_pm_compute_clocks(rdev);
 327                if (radeon_crtc->crtc_id)
 328                        WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 329                else {
 330                        WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 331                                                                         RADEON_CRTC_DISP_REQ_EN_B));
 332                        WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
 333                }
 334                if (dev->num_crtcs > radeon_crtc->crtc_id)
 335                        drm_crtc_vblank_on(crtc);
 336                radeon_crtc_load_lut(crtc);
 337                break;
 338        case DRM_MODE_DPMS_STANDBY:
 339        case DRM_MODE_DPMS_SUSPEND:
 340        case DRM_MODE_DPMS_OFF:
 341                if (dev->num_crtcs > radeon_crtc->crtc_id)
 342                        drm_crtc_vblank_off(crtc);
 343                if (radeon_crtc->crtc_id)
 344                        WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 345                else {
 346                        WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 347                                                                                    RADEON_CRTC_DISP_REQ_EN_B));
 348                        WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl));
 349                }
 350                radeon_crtc->enabled = false;
 351                /* adjust pm to dpms changes AFTER disabling crtcs */
 352                radeon_pm_compute_clocks(rdev);
 353                break;
 354        }
 355}
 356
 357int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 358                         struct drm_framebuffer *old_fb)
 359{
 360        return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
 361}
 362
 363int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
 364                                struct drm_framebuffer *fb,
 365                                int x, int y, enum mode_set_atomic state)
 366{
 367        return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
 368}
 369
 370int radeon_crtc_do_set_base(struct drm_crtc *crtc,
 371                         struct drm_framebuffer *fb,
 372                         int x, int y, int atomic)
 373{
 374        struct drm_device *dev = crtc->dev;
 375        struct radeon_device *rdev = dev->dev_private;
 376        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 377        struct radeon_framebuffer *radeon_fb;
 378        struct drm_framebuffer *target_fb;
 379        struct drm_gem_object *obj;
 380        struct radeon_bo *rbo;
 381        uint64_t base;
 382        uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 383        uint32_t crtc_pitch, pitch_pixels;
 384        uint32_t tiling_flags;
 385        int format;
 386        uint32_t gen_cntl_reg, gen_cntl_val;
 387        int r;
 388
 389        DRM_DEBUG_KMS("\n");
 390        /* no fb bound */
 391        if (!atomic && !crtc->primary->fb) {
 392                DRM_DEBUG_KMS("No FB bound\n");
 393                return 0;
 394        }
 395
 396        if (atomic) {
 397                radeon_fb = to_radeon_framebuffer(fb);
 398                target_fb = fb;
 399        }
 400        else {
 401                radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 402                target_fb = crtc->primary->fb;
 403        }
 404
 405        switch (target_fb->bits_per_pixel) {
 406        case 8:
 407                format = 2;
 408                break;
 409        case 15:      /*  555 */
 410                format = 3;
 411                break;
 412        case 16:      /*  565 */
 413                format = 4;
 414                break;
 415        case 24:      /*  RGB */
 416                format = 5;
 417                break;
 418        case 32:      /* xRGB */
 419                format = 6;
 420                break;
 421        default:
 422                return false;
 423        }
 424
 425        /* Pin framebuffer & get tilling informations */
 426        obj = radeon_fb->obj;
 427        rbo = gem_to_radeon_bo(obj);
 428retry:
 429        r = radeon_bo_reserve(rbo, false);
 430        if (unlikely(r != 0))
 431                return r;
 432        /* Only 27 bit offset for legacy CRTC */
 433        r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
 434                                     &base);
 435        if (unlikely(r != 0)) {
 436                radeon_bo_unreserve(rbo);
 437
 438                /* On old GPU like RN50 with little vram pining can fails because
 439                 * current fb is taking all space needed. So instead of unpining
 440                 * the old buffer after pining the new one, first unpin old one
 441                 * and then retry pining new one.
 442                 *
 443                 * As only master can set mode only master can pin and it is
 444                 * unlikely the master client will race with itself especialy
 445                 * on those old gpu with single crtc.
 446                 *
 447                 * We don't shutdown the display controller because new buffer
 448                 * will end up in same spot.
 449                 */
 450                if (!atomic && fb && fb != crtc->primary->fb) {
 451                        struct radeon_bo *old_rbo;
 452                        unsigned long nsize, osize;
 453
 454                        old_rbo = gem_to_radeon_bo(to_radeon_framebuffer(fb)->obj);
 455                        osize = radeon_bo_size(old_rbo);
 456                        nsize = radeon_bo_size(rbo);
 457                        if (nsize <= osize && !radeon_bo_reserve(old_rbo, false)) {
 458                                radeon_bo_unpin(old_rbo);
 459                                radeon_bo_unreserve(old_rbo);
 460                                fb = NULL;
 461                                goto retry;
 462                        }
 463                }
 464                return -EINVAL;
 465        }
 466        radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 467        radeon_bo_unreserve(rbo);
 468        if (tiling_flags & RADEON_TILING_MICRO)
 469                DRM_ERROR("trying to scanout microtiled buffer\n");
 470
 471        /* if scanout was in GTT this really wouldn't work */
 472        /* crtc offset is from display base addr not FB location */
 473        radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 474
 475        base -= radeon_crtc->legacy_display_base_addr;
 476
 477        crtc_offset_cntl = 0;
 478
 479        pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
 480        crtc_pitch  = (((pitch_pixels * target_fb->bits_per_pixel) +
 481                        ((target_fb->bits_per_pixel * 8) - 1)) /
 482                       (target_fb->bits_per_pixel * 8));
 483        crtc_pitch |= crtc_pitch << 16;
 484
 485        crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
 486        if (tiling_flags & RADEON_TILING_MACRO) {
 487                if (ASIC_IS_R300(rdev))
 488                        crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 489                                             R300_CRTC_MICRO_TILE_BUFFER_DIS |
 490                                             R300_CRTC_MACRO_TILE_EN);
 491                else
 492                        crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 493        } else {
 494                if (ASIC_IS_R300(rdev))
 495                        crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 496                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 497                                              R300_CRTC_MACRO_TILE_EN);
 498                else
 499                        crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 500        }
 501
 502        if (tiling_flags & RADEON_TILING_MACRO) {
 503                if (ASIC_IS_R300(rdev)) {
 504                        crtc_tile_x0_y0 = x | (y << 16);
 505                        base &= ~0x7ff;
 506                } else {
 507                        int byteshift = target_fb->bits_per_pixel >> 4;
 508                        int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 509                        base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 510                        crtc_offset_cntl |= (y % 16);
 511                }
 512        } else {
 513                int offset = y * pitch_pixels + x;
 514                switch (target_fb->bits_per_pixel) {
 515                case 8:
 516                        offset *= 1;
 517                        break;
 518                case 15:
 519                case 16:
 520                        offset *= 2;
 521                        break;
 522                case 24:
 523                        offset *= 3;
 524                        break;
 525                case 32:
 526                        offset *= 4;
 527                        break;
 528                default:
 529                        return false;
 530                }
 531                base += offset;
 532        }
 533
 534        base &= ~7;
 535
 536        if (radeon_crtc->crtc_id == 1)
 537                gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 538        else
 539                gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 540
 541        gen_cntl_val = RREG32(gen_cntl_reg);
 542        gen_cntl_val &= ~(0xf << 8);
 543        gen_cntl_val |= (format << 8);
 544        gen_cntl_val &= ~RADEON_CRTC_VSTAT_MODE_MASK;
 545        WREG32(gen_cntl_reg, gen_cntl_val);
 546
 547        crtc_offset = (u32)base;
 548
 549        WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 550
 551        if (ASIC_IS_R300(rdev)) {
 552                if (radeon_crtc->crtc_id)
 553                        WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 554                else
 555                        WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 556        }
 557        WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 558        WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 559        WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 560
 561        if (!atomic && fb && fb != crtc->primary->fb) {
 562                radeon_fb = to_radeon_framebuffer(fb);
 563                rbo = gem_to_radeon_bo(radeon_fb->obj);
 564                r = radeon_bo_reserve(rbo, false);
 565                if (unlikely(r != 0))
 566                        return r;
 567                radeon_bo_unpin(rbo);
 568                radeon_bo_unreserve(rbo);
 569        }
 570
 571        /* Bytes per pixel may have changed */
 572        radeon_bandwidth_update(rdev);
 573
 574        return 0;
 575}
 576
 577static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 578{
 579        struct drm_device *dev = crtc->dev;
 580        struct radeon_device *rdev = dev->dev_private;
 581        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 582        struct drm_encoder *encoder;
 583        int format;
 584        int hsync_start;
 585        int hsync_wid;
 586        int vsync_wid;
 587        uint32_t crtc_h_total_disp;
 588        uint32_t crtc_h_sync_strt_wid;
 589        uint32_t crtc_v_total_disp;
 590        uint32_t crtc_v_sync_strt_wid;
 591        bool is_tv = false;
 592
 593        DRM_DEBUG_KMS("\n");
 594        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 595                if (encoder->crtc == crtc) {
 596                        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 597                        if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 598                                is_tv = true;
 599                                DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 600                                break;
 601                        }
 602                }
 603        }
 604
 605        switch (crtc->primary->fb->bits_per_pixel) {
 606        case 8:
 607                format = 2;
 608                break;
 609        case 15:      /*  555 */
 610                format = 3;
 611                break;
 612        case 16:      /*  565 */
 613                format = 4;
 614                break;
 615        case 24:      /*  RGB */
 616                format = 5;
 617                break;
 618        case 32:      /* xRGB */
 619                format = 6;
 620                break;
 621        default:
 622                return false;
 623        }
 624
 625        crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 626                             | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 627
 628        hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 629        if (!hsync_wid)
 630                hsync_wid = 1;
 631        hsync_start = mode->crtc_hsync_start - 8;
 632
 633        crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 634                                | ((hsync_wid & 0x3f) << 16)
 635                                | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 636                                   ? RADEON_CRTC_H_SYNC_POL
 637                                   : 0));
 638
 639        /* This works for double scan mode. */
 640        crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 641                             | ((mode->crtc_vdisplay - 1) << 16));
 642
 643        vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 644        if (!vsync_wid)
 645                vsync_wid = 1;
 646
 647        crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 648                                | ((vsync_wid & 0x1f) << 16)
 649                                | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 650                                   ? RADEON_CRTC_V_SYNC_POL
 651                                   : 0));
 652
 653        if (radeon_crtc->crtc_id) {
 654                uint32_t crtc2_gen_cntl;
 655                uint32_t disp2_merge_cntl;
 656
 657                /* if TV DAC is enabled for another crtc and keep it enabled */
 658                crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 659                crtc2_gen_cntl |= ((format << 8)
 660                                   | RADEON_CRTC2_VSYNC_DIS
 661                                   | RADEON_CRTC2_HSYNC_DIS
 662                                   | RADEON_CRTC2_DISP_DIS
 663                                   | RADEON_CRTC2_DISP_REQ_EN_B
 664                                   | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 665                                      ? RADEON_CRTC2_DBL_SCAN_EN
 666                                      : 0)
 667                                   | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 668                                      ? RADEON_CRTC2_CSYNC_EN
 669                                      : 0)
 670                                   | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 671                                      ? RADEON_CRTC2_INTERLACE_EN
 672                                      : 0));
 673
 674                /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 675                if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 676                        crtc2_gen_cntl |= RADEON_CRTC2_EN;
 677
 678                disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 679                disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 680
 681                WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 682                WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 683
 684                WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 685                WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 686        } else {
 687                uint32_t crtc_gen_cntl;
 688                uint32_t crtc_ext_cntl;
 689                uint32_t disp_merge_cntl;
 690
 691                crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 692                crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 693                                 | (format << 8)
 694                                 | RADEON_CRTC_DISP_REQ_EN_B
 695                                 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 696                                    ? RADEON_CRTC_DBL_SCAN_EN
 697                                    : 0)
 698                                 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 699                                    ? RADEON_CRTC_CSYNC_EN
 700                                    : 0)
 701                                 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 702                                    ? RADEON_CRTC_INTERLACE_EN
 703                                    : 0));
 704
 705                /* rs4xx chips seem to like to have the crtc enabled when the timing is set */
 706                if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480))
 707                        crtc_gen_cntl |= RADEON_CRTC_EN;
 708
 709                crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 710                crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 711                                  RADEON_CRTC_VSYNC_DIS |
 712                                  RADEON_CRTC_HSYNC_DIS |
 713                                  RADEON_CRTC_DISPLAY_DIS);
 714
 715                disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 716                disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 717
 718                WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 719                WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 720                WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 721        }
 722
 723        if (is_tv)
 724                radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 725                                                 &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 726                                                 &crtc_v_sync_strt_wid);
 727
 728        WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 729        WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 730        WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 731        WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 732
 733        return true;
 734}
 735
 736static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 737{
 738        struct drm_device *dev = crtc->dev;
 739        struct radeon_device *rdev = dev->dev_private;
 740        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 741        struct drm_encoder *encoder;
 742        uint32_t feedback_div = 0;
 743        uint32_t frac_fb_div = 0;
 744        uint32_t reference_div = 0;
 745        uint32_t post_divider = 0;
 746        uint32_t freq = 0;
 747        uint8_t pll_gain;
 748        bool use_bios_divs = false;
 749        /* PLL registers */
 750        uint32_t pll_ref_div = 0;
 751        uint32_t pll_fb_post_div = 0;
 752        uint32_t htotal_cntl = 0;
 753        bool is_tv = false;
 754        struct radeon_pll *pll;
 755
 756        struct {
 757                int divider;
 758                int bitvalue;
 759        } *post_div, post_divs[]   = {
 760                /* From RAGE 128 VR/RAGE 128 GL Register
 761                 * Reference Manual (Technical Reference
 762                 * Manual P/N RRG-G04100-C Rev. 0.04), page
 763                 * 3-17 (PLL_DIV_[3:0]).
 764                 */
 765                {  1, 0 },              /* VCLK_SRC                 */
 766                {  2, 1 },              /* VCLK_SRC/2               */
 767                {  4, 2 },              /* VCLK_SRC/4               */
 768                {  8, 3 },              /* VCLK_SRC/8               */
 769                {  3, 4 },              /* VCLK_SRC/3               */
 770                { 16, 5 },              /* VCLK_SRC/16              */
 771                {  6, 6 },              /* VCLK_SRC/6               */
 772                { 12, 7 },              /* VCLK_SRC/12              */
 773                {  0, 0 }
 774        };
 775
 776        if (radeon_crtc->crtc_id)
 777                pll = &rdev->clock.p2pll;
 778        else
 779                pll = &rdev->clock.p1pll;
 780
 781        pll->flags = RADEON_PLL_LEGACY;
 782
 783        if (mode->clock > 200000) /* range limits??? */
 784                pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 785        else
 786                pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 787
 788        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 789                if (encoder->crtc == crtc) {
 790                        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 791
 792                        if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 793                                is_tv = true;
 794                                break;
 795                        }
 796
 797                        if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 798                                pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 799                        if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 800                                if (!rdev->is_atom_bios) {
 801                                        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 802                                        struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 803                                        if (lvds) {
 804                                                if (lvds->use_bios_dividers) {
 805                                                        pll_ref_div = lvds->panel_ref_divider;
 806                                                        pll_fb_post_div   = (lvds->panel_fb_divider |
 807                                                                             (lvds->panel_post_divider << 16));
 808                                                        htotal_cntl  = 0;
 809                                                        use_bios_divs = true;
 810                                                }
 811                                        }
 812                                }
 813                                pll->flags |= RADEON_PLL_USE_REF_DIV;
 814                        }
 815                }
 816        }
 817
 818        DRM_DEBUG_KMS("\n");
 819
 820        if (!use_bios_divs) {
 821                radeon_compute_pll_legacy(pll, mode->clock,
 822                                          &freq, &feedback_div, &frac_fb_div,
 823                                          &reference_div, &post_divider);
 824
 825                for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 826                        if (post_div->divider == post_divider)
 827                                break;
 828                }
 829
 830                if (!post_div->divider)
 831                        post_div = &post_divs[0];
 832
 833                DRM_DEBUG_KMS("dc=%u, fd=%d, rd=%d, pd=%d\n",
 834                          (unsigned)freq,
 835                          feedback_div,
 836                          reference_div,
 837                          post_divider);
 838
 839                pll_ref_div   = reference_div;
 840#if defined(__powerpc__) && (0) /* TODO */
 841                /* apparently programming this otherwise causes a hang??? */
 842                if (info->MacModel == RADEON_MAC_IBOOK)
 843                        pll_fb_post_div = 0x000600ad;
 844                else
 845#endif
 846                        pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 847
 848                htotal_cntl    = mode->htotal & 0x7;
 849
 850        }
 851
 852        pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 853                                           pll_ref_div & 0x3ff,
 854                                           pll_fb_post_div & 0x7ff);
 855
 856        if (radeon_crtc->crtc_id) {
 857                uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 858                                          ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 859                                         RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 860
 861                if (is_tv) {
 862                        radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 863                                                     &pll_ref_div, &pll_fb_post_div,
 864                                                     &pixclks_cntl);
 865                }
 866
 867                WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 868                             RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 869                             ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 870
 871                WREG32_PLL_P(RADEON_P2PLL_CNTL,
 872                             RADEON_P2PLL_RESET
 873                             | RADEON_P2PLL_ATOMIC_UPDATE_EN
 874                             | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 875                             ~(RADEON_P2PLL_RESET
 876                               | RADEON_P2PLL_ATOMIC_UPDATE_EN
 877                               | RADEON_P2PLL_PVG_MASK));
 878
 879                WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 880                             pll_ref_div,
 881                             ~RADEON_P2PLL_REF_DIV_MASK);
 882
 883                WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 884                             pll_fb_post_div,
 885                             ~RADEON_P2PLL_FB0_DIV_MASK);
 886
 887                WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 888                             pll_fb_post_div,
 889                             ~RADEON_P2PLL_POST0_DIV_MASK);
 890
 891                radeon_pll2_write_update(dev);
 892                radeon_pll2_wait_for_read_update_complete(dev);
 893
 894                WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 895
 896                WREG32_PLL_P(RADEON_P2PLL_CNTL,
 897                             0,
 898                             ~(RADEON_P2PLL_RESET
 899                               | RADEON_P2PLL_SLEEP
 900                               | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 901
 902                DRM_DEBUG_KMS("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 903                          (unsigned)pll_ref_div,
 904                          (unsigned)pll_fb_post_div,
 905                          (unsigned)htotal_cntl,
 906                          RREG32_PLL(RADEON_P2PLL_CNTL));
 907                DRM_DEBUG_KMS("Wrote2: rd=%u, fd=%u, pd=%u\n",
 908                          (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 909                          (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 910                          (unsigned)((pll_fb_post_div &
 911                                      RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 912
 913                mdelay(50); /* Let the clock to lock */
 914
 915                WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 916                             RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 917                             ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 918
 919                WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 920        } else {
 921                uint32_t pixclks_cntl;
 922
 923
 924                if (is_tv) {
 925                        pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 926                        radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 927                                                     &pll_fb_post_div, &pixclks_cntl);
 928                }
 929
 930                if (rdev->flags & RADEON_IS_MOBILITY) {
 931                        /* A temporal workaround for the occasional blanking on certain laptop panels.
 932                           This appears to related to the PLL divider registers (fail to lock?).
 933                           It occurs even when all dividers are the same with their old settings.
 934                           In this case we really don't need to fiddle with PLL registers.
 935                           By doing this we can avoid the blanking problem with some panels.
 936                        */
 937                        if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 938                            (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 939                                                 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 940                                WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 941                                         RADEON_PLL_DIV_SEL,
 942                                         ~(RADEON_PLL_DIV_SEL));
 943                                r100_pll_errata_after_index(rdev);
 944                                return;
 945                        }
 946                }
 947
 948                WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 949                             RADEON_VCLK_SRC_SEL_CPUCLK,
 950                             ~(RADEON_VCLK_SRC_SEL_MASK));
 951                WREG32_PLL_P(RADEON_PPLL_CNTL,
 952                             RADEON_PPLL_RESET
 953                             | RADEON_PPLL_ATOMIC_UPDATE_EN
 954                             | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 955                             | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 956                             ~(RADEON_PPLL_RESET
 957                               | RADEON_PPLL_ATOMIC_UPDATE_EN
 958                               | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 959                               | RADEON_PPLL_PVG_MASK));
 960
 961                WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 962                         RADEON_PLL_DIV_SEL,
 963                         ~(RADEON_PLL_DIV_SEL));
 964                r100_pll_errata_after_index(rdev);
 965
 966                if (ASIC_IS_R300(rdev) ||
 967                    (rdev->family == CHIP_RS300) ||
 968                    (rdev->family == CHIP_RS400) ||
 969                    (rdev->family == CHIP_RS480)) {
 970                        if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 971                                /* When restoring console mode, use saved PPLL_REF_DIV
 972                                 * setting.
 973                                 */
 974                                WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 975                                             pll_ref_div,
 976                                             0);
 977                        } else {
 978                                /* R300 uses ref_div_acc field as real ref divider */
 979                                WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 980                                             (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 981                                             ~R300_PPLL_REF_DIV_ACC_MASK);
 982                        }
 983                } else
 984                        WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 985                                     pll_ref_div,
 986                                     ~RADEON_PPLL_REF_DIV_MASK);
 987
 988                WREG32_PLL_P(RADEON_PPLL_DIV_3,
 989                             pll_fb_post_div,
 990                             ~RADEON_PPLL_FB3_DIV_MASK);
 991
 992                WREG32_PLL_P(RADEON_PPLL_DIV_3,
 993                             pll_fb_post_div,
 994                             ~RADEON_PPLL_POST3_DIV_MASK);
 995
 996                radeon_pll_write_update(dev);
 997                radeon_pll_wait_for_read_update_complete(dev);
 998
 999                WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
1000
1001                WREG32_PLL_P(RADEON_PPLL_CNTL,
1002                             0,
1003                             ~(RADEON_PPLL_RESET
1004                               | RADEON_PPLL_SLEEP
1005                               | RADEON_PPLL_ATOMIC_UPDATE_EN
1006                               | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1007
1008                DRM_DEBUG_KMS("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
1009                          pll_ref_div,
1010                          pll_fb_post_div,
1011                          (unsigned)htotal_cntl,
1012                          RREG32_PLL(RADEON_PPLL_CNTL));
1013                DRM_DEBUG_KMS("Wrote: rd=%d, fd=%d, pd=%d\n",
1014                          pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
1015                          pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
1016                          (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
1017
1018                mdelay(50); /* Let the clock to lock */
1019
1020                WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
1021                             RADEON_VCLK_SRC_SEL_PPLLCLK,
1022                             ~(RADEON_VCLK_SRC_SEL_MASK));
1023
1024                if (is_tv)
1025                        WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1026        }
1027}
1028
1029static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1030                                   const struct drm_display_mode *mode,
1031                                   struct drm_display_mode *adjusted_mode)
1032{
1033        if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1034                return false;
1035        return true;
1036}
1037
1038static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1039                                 struct drm_display_mode *mode,
1040                                 struct drm_display_mode *adjusted_mode,
1041                                 int x, int y, struct drm_framebuffer *old_fb)
1042{
1043        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1044
1045        /* TODO TV */
1046        radeon_crtc_set_base(crtc, x, y, old_fb);
1047        radeon_set_crtc_timing(crtc, adjusted_mode);
1048        radeon_set_pll(crtc, adjusted_mode);
1049        radeon_overscan_setup(crtc, adjusted_mode);
1050        if (radeon_crtc->crtc_id == 0) {
1051                radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
1052        } else {
1053                if (radeon_crtc->rmx_type != RMX_OFF) {
1054                        /* FIXME: only first crtc has rmx what should we
1055                         * do ?
1056                         */
1057                        DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1058                }
1059        }
1060        radeon_cursor_reset(crtc);
1061        return 0;
1062}
1063
1064static void radeon_crtc_prepare(struct drm_crtc *crtc)
1065{
1066        struct drm_device *dev = crtc->dev;
1067        struct drm_crtc *crtci;
1068
1069        /*
1070        * The hardware wedges sometimes if you reconfigure one CRTC
1071        * whilst another is running (see fdo bug #24611).
1072        */
1073        list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1074                radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1075}
1076
1077static void radeon_crtc_commit(struct drm_crtc *crtc)
1078{
1079        struct drm_device *dev = crtc->dev;
1080        struct drm_crtc *crtci;
1081
1082        /*
1083        * Reenable the CRTCs that should be running.
1084        */
1085        list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1086                if (crtci->enabled)
1087                        radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1088        }
1089}
1090
1091static void radeon_crtc_disable(struct drm_crtc *crtc)
1092{
1093        radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1094        if (crtc->primary->fb) {
1095                int r;
1096                struct radeon_framebuffer *radeon_fb;
1097                struct radeon_bo *rbo;
1098
1099                radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1100                rbo = gem_to_radeon_bo(radeon_fb->obj);
1101                r = radeon_bo_reserve(rbo, false);
1102                if (unlikely(r))
1103                        DRM_ERROR("failed to reserve rbo before unpin\n");
1104                else {
1105                        radeon_bo_unpin(rbo);
1106                        radeon_bo_unreserve(rbo);
1107                }
1108        }
1109}
1110
1111static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1112        .dpms = radeon_crtc_dpms,
1113        .mode_fixup = radeon_crtc_mode_fixup,
1114        .mode_set = radeon_crtc_mode_set,
1115        .mode_set_base = radeon_crtc_set_base,
1116        .mode_set_base_atomic = radeon_crtc_set_base_atomic,
1117        .prepare = radeon_crtc_prepare,
1118        .commit = radeon_crtc_commit,
1119        .load_lut = radeon_crtc_load_lut,
1120        .disable = radeon_crtc_disable
1121};
1122
1123
1124void radeon_legacy_init_crtc(struct drm_device *dev,
1125                               struct radeon_crtc *radeon_crtc)
1126{
1127        if (radeon_crtc->crtc_id == 1)
1128                radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1129        drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1130}
1131