linux/drivers/iio/dac/ad5755.c
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   1/*
   2 * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
   3 *
   4 * Copyright 2012 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2.
   7 */
   8
   9#include <linux/device.h>
  10#include <linux/err.h>
  11#include <linux/module.h>
  12#include <linux/kernel.h>
  13#include <linux/spi/spi.h>
  14#include <linux/slab.h>
  15#include <linux/sysfs.h>
  16#include <linux/delay.h>
  17#include <linux/iio/iio.h>
  18#include <linux/iio/sysfs.h>
  19#include <linux/platform_data/ad5755.h>
  20
  21#define AD5755_NUM_CHANNELS 4
  22
  23#define AD5755_ADDR(x)                  ((x) << 16)
  24
  25#define AD5755_WRITE_REG_DATA(chan)     (chan)
  26#define AD5755_WRITE_REG_GAIN(chan)     (0x08 | (chan))
  27#define AD5755_WRITE_REG_OFFSET(chan)   (0x10 | (chan))
  28#define AD5755_WRITE_REG_CTRL(chan)     (0x1c | (chan))
  29
  30#define AD5755_READ_REG_DATA(chan)      (chan)
  31#define AD5755_READ_REG_CTRL(chan)      (0x4 | (chan))
  32#define AD5755_READ_REG_GAIN(chan)      (0x8 | (chan))
  33#define AD5755_READ_REG_OFFSET(chan)    (0xc | (chan))
  34#define AD5755_READ_REG_CLEAR(chan)     (0x10 | (chan))
  35#define AD5755_READ_REG_SLEW(chan)      (0x14 | (chan))
  36#define AD5755_READ_REG_STATUS          0x18
  37#define AD5755_READ_REG_MAIN            0x19
  38#define AD5755_READ_REG_DC_DC           0x1a
  39
  40#define AD5755_CTRL_REG_SLEW    0x0
  41#define AD5755_CTRL_REG_MAIN    0x1
  42#define AD5755_CTRL_REG_DAC     0x2
  43#define AD5755_CTRL_REG_DC_DC   0x3
  44#define AD5755_CTRL_REG_SW      0x4
  45
  46#define AD5755_READ_FLAG 0x800000
  47
  48#define AD5755_NOOP 0x1CE000
  49
  50#define AD5755_DAC_INT_EN                       BIT(8)
  51#define AD5755_DAC_CLR_EN                       BIT(7)
  52#define AD5755_DAC_OUT_EN                       BIT(6)
  53#define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR   BIT(5)
  54#define AD5755_DAC_DC_DC_EN                     BIT(4)
  55#define AD5755_DAC_VOLTAGE_OVERRANGE_EN         BIT(3)
  56
  57#define AD5755_DC_DC_MAXV                       0
  58#define AD5755_DC_DC_FREQ_SHIFT                 2
  59#define AD5755_DC_DC_PHASE_SHIFT                4
  60#define AD5755_EXT_DC_DC_COMP_RES               BIT(6)
  61
  62#define AD5755_SLEW_STEP_SIZE_SHIFT             0
  63#define AD5755_SLEW_RATE_SHIFT                  3
  64#define AD5755_SLEW_ENABLE                      BIT(12)
  65
  66/**
  67 * struct ad5755_chip_info - chip specific information
  68 * @channel_template:   channel specification
  69 * @calib_shift:        shift for the calibration data registers
  70 * @has_voltage_out:    whether the chip has voltage outputs
  71 */
  72struct ad5755_chip_info {
  73        const struct iio_chan_spec channel_template;
  74        unsigned int calib_shift;
  75        bool has_voltage_out;
  76};
  77
  78/**
  79 * struct ad5755_state - driver instance specific data
  80 * @spi:        spi device the driver is attached to
  81 * @chip_info:  chip model specific constants, available modes etc
  82 * @pwr_down:   bitmask which contains  hether a channel is powered down or not
  83 * @ctrl:       software shadow of the channel ctrl registers
  84 * @channels:   iio channel spec for the device
  85 * @data:       spi transfer buffers
  86 */
  87struct ad5755_state {
  88        struct spi_device               *spi;
  89        const struct ad5755_chip_info   *chip_info;
  90        unsigned int                    pwr_down;
  91        unsigned int                    ctrl[AD5755_NUM_CHANNELS];
  92        struct iio_chan_spec            channels[AD5755_NUM_CHANNELS];
  93
  94        /*
  95         * DMA (thus cache coherency maintenance) requires the
  96         * transfer buffers to live in their own cache lines.
  97         */
  98
  99        union {
 100                u32 d32;
 101                u8 d8[4];
 102        } data[2] ____cacheline_aligned;
 103};
 104
 105enum ad5755_type {
 106        ID_AD5755,
 107        ID_AD5757,
 108        ID_AD5735,
 109        ID_AD5737,
 110};
 111
 112static int ad5755_write_unlocked(struct iio_dev *indio_dev,
 113        unsigned int reg, unsigned int val)
 114{
 115        struct ad5755_state *st = iio_priv(indio_dev);
 116
 117        st->data[0].d32 = cpu_to_be32((reg << 16) | val);
 118
 119        return spi_write(st->spi, &st->data[0].d8[1], 3);
 120}
 121
 122static int ad5755_write_ctrl_unlocked(struct iio_dev *indio_dev,
 123        unsigned int channel, unsigned int reg, unsigned int val)
 124{
 125        return ad5755_write_unlocked(indio_dev,
 126                AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val);
 127}
 128
 129static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg,
 130        unsigned int val)
 131{
 132        int ret;
 133
 134        mutex_lock(&indio_dev->mlock);
 135        ret = ad5755_write_unlocked(indio_dev, reg, val);
 136        mutex_unlock(&indio_dev->mlock);
 137
 138        return ret;
 139}
 140
 141static int ad5755_write_ctrl(struct iio_dev *indio_dev, unsigned int channel,
 142        unsigned int reg, unsigned int val)
 143{
 144        int ret;
 145
 146        mutex_lock(&indio_dev->mlock);
 147        ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val);
 148        mutex_unlock(&indio_dev->mlock);
 149
 150        return ret;
 151}
 152
 153static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr)
 154{
 155        struct ad5755_state *st = iio_priv(indio_dev);
 156        int ret;
 157        struct spi_transfer t[] = {
 158                {
 159                        .tx_buf = &st->data[0].d8[1],
 160                        .len = 3,
 161                        .cs_change = 1,
 162                }, {
 163                        .tx_buf = &st->data[1].d8[1],
 164                        .rx_buf = &st->data[1].d8[1],
 165                        .len = 3,
 166                },
 167        };
 168
 169        mutex_lock(&indio_dev->mlock);
 170
 171        st->data[0].d32 = cpu_to_be32(AD5755_READ_FLAG | (addr << 16));
 172        st->data[1].d32 = cpu_to_be32(AD5755_NOOP);
 173
 174        ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
 175        if (ret >= 0)
 176                ret = be32_to_cpu(st->data[1].d32) & 0xffff;
 177
 178        mutex_unlock(&indio_dev->mlock);
 179
 180        return ret;
 181}
 182
 183static int ad5755_update_dac_ctrl(struct iio_dev *indio_dev,
 184        unsigned int channel, unsigned int set, unsigned int clr)
 185{
 186        struct ad5755_state *st = iio_priv(indio_dev);
 187        int ret;
 188
 189        st->ctrl[channel] |= set;
 190        st->ctrl[channel] &= ~clr;
 191
 192        ret = ad5755_write_ctrl_unlocked(indio_dev, channel,
 193                AD5755_CTRL_REG_DAC, st->ctrl[channel]);
 194
 195        return ret;
 196}
 197
 198static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev,
 199        unsigned int channel, bool pwr_down)
 200{
 201        struct ad5755_state *st = iio_priv(indio_dev);
 202        unsigned int mask = BIT(channel);
 203
 204        mutex_lock(&indio_dev->mlock);
 205
 206        if ((bool)(st->pwr_down & mask) == pwr_down)
 207                goto out_unlock;
 208
 209        if (!pwr_down) {
 210                st->pwr_down &= ~mask;
 211                ad5755_update_dac_ctrl(indio_dev, channel,
 212                        AD5755_DAC_INT_EN | AD5755_DAC_DC_DC_EN, 0);
 213                udelay(200);
 214                ad5755_update_dac_ctrl(indio_dev, channel,
 215                        AD5755_DAC_OUT_EN, 0);
 216        } else {
 217                st->pwr_down |= mask;
 218                ad5755_update_dac_ctrl(indio_dev, channel,
 219                        0, AD5755_DAC_INT_EN | AD5755_DAC_OUT_EN |
 220                                AD5755_DAC_DC_DC_EN);
 221        }
 222
 223out_unlock:
 224        mutex_unlock(&indio_dev->mlock);
 225
 226        return 0;
 227}
 228
 229static const int ad5755_min_max_table[][2] = {
 230        [AD5755_MODE_VOLTAGE_0V_5V] = { 0, 5000 },
 231        [AD5755_MODE_VOLTAGE_0V_10V] = { 0, 10000 },
 232        [AD5755_MODE_VOLTAGE_PLUSMINUS_5V] = { -5000, 5000 },
 233        [AD5755_MODE_VOLTAGE_PLUSMINUS_10V] = { -10000, 10000 },
 234        [AD5755_MODE_CURRENT_4mA_20mA] = { 4, 20 },
 235        [AD5755_MODE_CURRENT_0mA_20mA] = { 0, 20 },
 236        [AD5755_MODE_CURRENT_0mA_24mA] = { 0, 24 },
 237};
 238
 239static void ad5755_get_min_max(struct ad5755_state *st,
 240        struct iio_chan_spec const *chan, int *min, int *max)
 241{
 242        enum ad5755_mode mode = st->ctrl[chan->channel] & 7;
 243        *min = ad5755_min_max_table[mode][0];
 244        *max = ad5755_min_max_table[mode][1];
 245}
 246
 247static inline int ad5755_get_offset(struct ad5755_state *st,
 248        struct iio_chan_spec const *chan)
 249{
 250        int min, max;
 251
 252        ad5755_get_min_max(st, chan, &min, &max);
 253        return (min * (1 << chan->scan_type.realbits)) / (max - min);
 254}
 255
 256static inline int ad5755_get_scale(struct ad5755_state *st,
 257        struct iio_chan_spec const *chan)
 258{
 259        int min, max;
 260
 261        ad5755_get_min_max(st, chan, &min, &max);
 262        return ((max - min) * 1000000000ULL) >> chan->scan_type.realbits;
 263}
 264
 265static int ad5755_chan_reg_info(struct ad5755_state *st,
 266        struct iio_chan_spec const *chan, long info, bool write,
 267        unsigned int *reg, unsigned int *shift, unsigned int *offset)
 268{
 269        switch (info) {
 270        case IIO_CHAN_INFO_RAW:
 271                if (write)
 272                        *reg = AD5755_WRITE_REG_DATA(chan->address);
 273                else
 274                        *reg = AD5755_READ_REG_DATA(chan->address);
 275                *shift = chan->scan_type.shift;
 276                *offset = 0;
 277                break;
 278        case IIO_CHAN_INFO_CALIBBIAS:
 279                if (write)
 280                        *reg = AD5755_WRITE_REG_OFFSET(chan->address);
 281                else
 282                        *reg = AD5755_READ_REG_OFFSET(chan->address);
 283                *shift = st->chip_info->calib_shift;
 284                *offset = 32768;
 285                break;
 286        case IIO_CHAN_INFO_CALIBSCALE:
 287                if (write)
 288                        *reg =  AD5755_WRITE_REG_GAIN(chan->address);
 289                else
 290                        *reg =  AD5755_READ_REG_GAIN(chan->address);
 291                *shift = st->chip_info->calib_shift;
 292                *offset = 0;
 293                break;
 294        default:
 295                return -EINVAL;
 296        }
 297
 298        return 0;
 299}
 300
 301static int ad5755_read_raw(struct iio_dev *indio_dev,
 302        const struct iio_chan_spec *chan, int *val, int *val2, long info)
 303{
 304        struct ad5755_state *st = iio_priv(indio_dev);
 305        unsigned int reg, shift, offset;
 306        int ret;
 307
 308        switch (info) {
 309        case IIO_CHAN_INFO_SCALE:
 310                *val = 0;
 311                *val2 = ad5755_get_scale(st, chan);
 312                return IIO_VAL_INT_PLUS_NANO;
 313        case IIO_CHAN_INFO_OFFSET:
 314                *val = ad5755_get_offset(st, chan);
 315                return IIO_VAL_INT;
 316        default:
 317                ret = ad5755_chan_reg_info(st, chan, info, false,
 318                                                &reg, &shift, &offset);
 319                if (ret)
 320                        return ret;
 321
 322                ret = ad5755_read(indio_dev, reg);
 323                if (ret < 0)
 324                        return ret;
 325
 326                *val = (ret - offset) >> shift;
 327
 328                return IIO_VAL_INT;
 329        }
 330
 331        return -EINVAL;
 332}
 333
 334static int ad5755_write_raw(struct iio_dev *indio_dev,
 335        const struct iio_chan_spec *chan, int val, int val2, long info)
 336{
 337        struct ad5755_state *st = iio_priv(indio_dev);
 338        unsigned int shift, reg, offset;
 339        int ret;
 340
 341        ret = ad5755_chan_reg_info(st, chan, info, true,
 342                                        &reg, &shift, &offset);
 343        if (ret)
 344                return ret;
 345
 346        val <<= shift;
 347        val += offset;
 348
 349        if (val < 0 || val > 0xffff)
 350                return -EINVAL;
 351
 352        return ad5755_write(indio_dev, reg, val);
 353}
 354
 355static ssize_t ad5755_read_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
 356        const struct iio_chan_spec *chan, char *buf)
 357{
 358        struct ad5755_state *st = iio_priv(indio_dev);
 359
 360        return sprintf(buf, "%d\n",
 361                       (bool)(st->pwr_down & (1 << chan->channel)));
 362}
 363
 364static ssize_t ad5755_write_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
 365        struct iio_chan_spec const *chan, const char *buf, size_t len)
 366{
 367        bool pwr_down;
 368        int ret;
 369
 370        ret = strtobool(buf, &pwr_down);
 371        if (ret)
 372                return ret;
 373
 374        ret = ad5755_set_channel_pwr_down(indio_dev, chan->channel, pwr_down);
 375        return ret ? ret : len;
 376}
 377
 378static const struct iio_info ad5755_info = {
 379        .read_raw = ad5755_read_raw,
 380        .write_raw = ad5755_write_raw,
 381        .driver_module = THIS_MODULE,
 382};
 383
 384static const struct iio_chan_spec_ext_info ad5755_ext_info[] = {
 385        {
 386                .name = "powerdown",
 387                .read = ad5755_read_powerdown,
 388                .write = ad5755_write_powerdown,
 389        },
 390        { },
 391};
 392
 393#define AD5755_CHANNEL(_bits) {                                 \
 394        .indexed = 1,                                           \
 395        .output = 1,                                            \
 396        .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 397                BIT(IIO_CHAN_INFO_SCALE) |                      \
 398                BIT(IIO_CHAN_INFO_OFFSET) |                     \
 399                BIT(IIO_CHAN_INFO_CALIBSCALE) |                 \
 400                BIT(IIO_CHAN_INFO_CALIBBIAS),                   \
 401        .scan_type = IIO_ST('u', (_bits), 16, 16 - (_bits)),    \
 402        .ext_info = ad5755_ext_info,                            \
 403}
 404
 405static const struct ad5755_chip_info ad5755_chip_info_tbl[] = {
 406        [ID_AD5735] = {
 407                .channel_template = AD5755_CHANNEL(14),
 408                .has_voltage_out = true,
 409                .calib_shift = 4,
 410        },
 411        [ID_AD5737] = {
 412                .channel_template = AD5755_CHANNEL(14),
 413                .has_voltage_out = false,
 414                .calib_shift = 4,
 415        },
 416        [ID_AD5755] = {
 417                .channel_template = AD5755_CHANNEL(16),
 418                .has_voltage_out = true,
 419                .calib_shift = 0,
 420        },
 421        [ID_AD5757] = {
 422                .channel_template = AD5755_CHANNEL(16),
 423                .has_voltage_out = false,
 424                .calib_shift = 0,
 425        },
 426};
 427
 428static bool ad5755_is_valid_mode(struct ad5755_state *st, enum ad5755_mode mode)
 429{
 430        switch (mode) {
 431        case AD5755_MODE_VOLTAGE_0V_5V:
 432        case AD5755_MODE_VOLTAGE_0V_10V:
 433        case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
 434        case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
 435                return st->chip_info->has_voltage_out;
 436        case AD5755_MODE_CURRENT_4mA_20mA:
 437        case AD5755_MODE_CURRENT_0mA_20mA:
 438        case AD5755_MODE_CURRENT_0mA_24mA:
 439                return true;
 440        default:
 441                return false;
 442        }
 443}
 444
 445static int ad5755_setup_pdata(struct iio_dev *indio_dev,
 446                              const struct ad5755_platform_data *pdata)
 447{
 448        struct ad5755_state *st = iio_priv(indio_dev);
 449        unsigned int val;
 450        unsigned int i;
 451        int ret;
 452
 453        if (pdata->dc_dc_phase > AD5755_DC_DC_PHASE_90_DEGREE ||
 454                pdata->dc_dc_freq > AD5755_DC_DC_FREQ_650kHZ ||
 455                pdata->dc_dc_maxv > AD5755_DC_DC_MAXV_29V5)
 456                return -EINVAL;
 457
 458        val = pdata->dc_dc_maxv << AD5755_DC_DC_MAXV;
 459        val |= pdata->dc_dc_freq << AD5755_DC_DC_FREQ_SHIFT;
 460        val |= pdata->dc_dc_phase << AD5755_DC_DC_PHASE_SHIFT;
 461        if (pdata->ext_dc_dc_compenstation_resistor)
 462                val |= AD5755_EXT_DC_DC_COMP_RES;
 463
 464        ret = ad5755_write_ctrl(indio_dev, 0, AD5755_CTRL_REG_DC_DC, val);
 465        if (ret < 0)
 466                return ret;
 467
 468        for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
 469                val = pdata->dac[i].slew.step_size <<
 470                        AD5755_SLEW_STEP_SIZE_SHIFT;
 471                val |= pdata->dac[i].slew.rate <<
 472                        AD5755_SLEW_RATE_SHIFT;
 473                if (pdata->dac[i].slew.enable)
 474                        val |= AD5755_SLEW_ENABLE;
 475
 476                ret = ad5755_write_ctrl(indio_dev, i,
 477                                        AD5755_CTRL_REG_SLEW, val);
 478                if (ret < 0)
 479                        return ret;
 480        }
 481
 482        for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
 483                if (!ad5755_is_valid_mode(st, pdata->dac[i].mode))
 484                        return -EINVAL;
 485
 486                val = 0;
 487                if (!pdata->dac[i].ext_current_sense_resistor)
 488                        val |= AD5755_DAC_INT_CURRENT_SENSE_RESISTOR;
 489                if (pdata->dac[i].enable_voltage_overrange)
 490                        val |= AD5755_DAC_VOLTAGE_OVERRANGE_EN;
 491                val |= pdata->dac[i].mode;
 492
 493                ret = ad5755_update_dac_ctrl(indio_dev, i, val, 0);
 494                if (ret < 0)
 495                        return ret;
 496        }
 497
 498        return 0;
 499}
 500
 501static bool ad5755_is_voltage_mode(enum ad5755_mode mode)
 502{
 503        switch (mode) {
 504        case AD5755_MODE_VOLTAGE_0V_5V:
 505        case AD5755_MODE_VOLTAGE_0V_10V:
 506        case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
 507        case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
 508                return true;
 509        default:
 510                return false;
 511        }
 512}
 513
 514static int ad5755_init_channels(struct iio_dev *indio_dev,
 515                                const struct ad5755_platform_data *pdata)
 516{
 517        struct ad5755_state *st = iio_priv(indio_dev);
 518        struct iio_chan_spec *channels = st->channels;
 519        unsigned int i;
 520
 521        for (i = 0; i < AD5755_NUM_CHANNELS; ++i) {
 522                channels[i] = st->chip_info->channel_template;
 523                channels[i].channel = i;
 524                channels[i].address = i;
 525                if (pdata && ad5755_is_voltage_mode(pdata->dac[i].mode))
 526                        channels[i].type = IIO_VOLTAGE;
 527                else
 528                        channels[i].type = IIO_CURRENT;
 529        }
 530
 531        indio_dev->channels = channels;
 532
 533        return 0;
 534}
 535
 536#define AD5755_DEFAULT_DAC_PDATA { \
 537                .mode = AD5755_MODE_CURRENT_4mA_20mA, \
 538                .ext_current_sense_resistor = true, \
 539                .enable_voltage_overrange = false, \
 540                .slew = { \
 541                        .enable = false, \
 542                        .rate = AD5755_SLEW_RATE_64k, \
 543                        .step_size = AD5755_SLEW_STEP_SIZE_1, \
 544                }, \
 545        }
 546
 547static const struct ad5755_platform_data ad5755_default_pdata = {
 548        .ext_dc_dc_compenstation_resistor = false,
 549        .dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE,
 550        .dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ,
 551        .dc_dc_maxv = AD5755_DC_DC_MAXV_23V,
 552        .dac = {
 553                [0] = AD5755_DEFAULT_DAC_PDATA,
 554                [1] = AD5755_DEFAULT_DAC_PDATA,
 555                [2] = AD5755_DEFAULT_DAC_PDATA,
 556                [3] = AD5755_DEFAULT_DAC_PDATA,
 557        },
 558};
 559
 560static int ad5755_probe(struct spi_device *spi)
 561{
 562        enum ad5755_type type = spi_get_device_id(spi)->driver_data;
 563        const struct ad5755_platform_data *pdata = dev_get_platdata(&spi->dev);
 564        struct iio_dev *indio_dev;
 565        struct ad5755_state *st;
 566        int ret;
 567
 568        indio_dev = iio_device_alloc(sizeof(*st));
 569        if (indio_dev == NULL) {
 570                dev_err(&spi->dev, "Failed to allocate iio device\n");
 571                return  -ENOMEM;
 572        }
 573
 574        st = iio_priv(indio_dev);
 575        spi_set_drvdata(spi, indio_dev);
 576
 577        st->chip_info = &ad5755_chip_info_tbl[type];
 578        st->spi = spi;
 579        st->pwr_down = 0xf;
 580
 581        indio_dev->dev.parent = &spi->dev;
 582        indio_dev->name = spi_get_device_id(spi)->name;
 583        indio_dev->info = &ad5755_info;
 584        indio_dev->modes = INDIO_DIRECT_MODE;
 585        indio_dev->num_channels = AD5755_NUM_CHANNELS;
 586
 587        if (!pdata)
 588                pdata = &ad5755_default_pdata;
 589
 590        ret = ad5755_init_channels(indio_dev, pdata);
 591        if (ret)
 592                goto error_free;
 593
 594        ret = ad5755_setup_pdata(indio_dev, pdata);
 595        if (ret)
 596                goto error_free;
 597
 598        ret = iio_device_register(indio_dev);
 599        if (ret) {
 600                dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
 601                goto error_free;
 602        }
 603
 604        return 0;
 605
 606error_free:
 607        iio_device_free(indio_dev);
 608
 609        return ret;
 610}
 611
 612static int ad5755_remove(struct spi_device *spi)
 613{
 614        struct iio_dev *indio_dev = spi_get_drvdata(spi);
 615
 616        iio_device_unregister(indio_dev);
 617        iio_device_free(indio_dev);
 618
 619        return 0;
 620}
 621
 622static const struct spi_device_id ad5755_id[] = {
 623        { "ad5755", ID_AD5755 },
 624        { "ad5755-1", ID_AD5755 },
 625        { "ad5757", ID_AD5757 },
 626        { "ad5735", ID_AD5735 },
 627        { "ad5737", ID_AD5737 },
 628        {}
 629};
 630MODULE_DEVICE_TABLE(spi, ad5755_id);
 631
 632static struct spi_driver ad5755_driver = {
 633        .driver = {
 634                .name = "ad5755",
 635                .owner = THIS_MODULE,
 636        },
 637        .probe = ad5755_probe,
 638        .remove = ad5755_remove,
 639        .id_table = ad5755_id,
 640};
 641module_spi_driver(ad5755_driver);
 642
 643MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 644MODULE_DESCRIPTION("Analog Devices AD5755/55-1/57/35/37 DAC");
 645MODULE_LICENSE("GPL v2");
 646