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35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/ip.h>
40#include <linux/tcp.h>
41#include <linux/if_vlan.h>
42#include <net/addrconf.h>
43
44#include "i40iw.h"
45#include "i40iw_register.h"
46#include <net/netevent.h>
47#define CLIENT_IW_INTERFACE_VERSION_MAJOR 0
48#define CLIENT_IW_INTERFACE_VERSION_MINOR 01
49#define CLIENT_IW_INTERFACE_VERSION_BUILD 00
50
51#define DRV_VERSION_MAJOR 0
52#define DRV_VERSION_MINOR 5
53#define DRV_VERSION_BUILD 123
54#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
55 __stringify(DRV_VERSION_MINOR) "." __stringify(DRV_VERSION_BUILD)
56
57static int push_mode;
58module_param(push_mode, int, 0644);
59MODULE_PARM_DESC(push_mode, "Low latency mode: 0=disabled (default), 1=enabled)");
60
61static int debug;
62module_param(debug, int, 0644);
63MODULE_PARM_DESC(debug, "debug flags: 0=disabled (default), 0x7fffffff=all");
64
65static int resource_profile;
66module_param(resource_profile, int, 0644);
67MODULE_PARM_DESC(resource_profile,
68 "Resource Profile: 0=no VF RDMA support (default), 1=Weighted VF, 2=Even Distribution");
69
70static int max_rdma_vfs = 32;
71module_param(max_rdma_vfs, int, 0644);
72MODULE_PARM_DESC(max_rdma_vfs, "Maximum VF count: 0-32 32=default");
73static int mpa_version = 2;
74module_param(mpa_version, int, 0644);
75MODULE_PARM_DESC(mpa_version, "MPA version to be used in MPA Req/Resp 1 or 2");
76
77MODULE_AUTHOR("Intel Corporation, <e1000-rdma@lists.sourceforge.net>");
78MODULE_DESCRIPTION("Intel(R) Ethernet Connection X722 iWARP RDMA Driver");
79MODULE_LICENSE("Dual BSD/GPL");
80MODULE_VERSION(DRV_VERSION);
81
82static struct i40e_client i40iw_client;
83static char i40iw_client_name[I40E_CLIENT_STR_LENGTH] = "i40iw";
84
85static LIST_HEAD(i40iw_handlers);
86static spinlock_t i40iw_handler_lock;
87
88static enum i40iw_status_code i40iw_virtchnl_send(struct i40iw_sc_dev *dev,
89 u32 vf_id, u8 *msg, u16 len);
90
91static struct notifier_block i40iw_inetaddr_notifier = {
92 .notifier_call = i40iw_inetaddr_event
93};
94
95static struct notifier_block i40iw_inetaddr6_notifier = {
96 .notifier_call = i40iw_inet6addr_event
97};
98
99static struct notifier_block i40iw_net_notifier = {
100 .notifier_call = i40iw_net_event
101};
102
103static atomic_t i40iw_notifiers_registered;
104
105
106
107
108
109static struct i40iw_handler *i40iw_find_i40e_handler(struct i40e_info *ldev)
110{
111 struct i40iw_handler *hdl;
112 unsigned long flags;
113
114 spin_lock_irqsave(&i40iw_handler_lock, flags);
115 list_for_each_entry(hdl, &i40iw_handlers, list) {
116 if (hdl->ldev.netdev == ldev->netdev) {
117 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
118 return hdl;
119 }
120 }
121 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
122 return NULL;
123}
124
125
126
127
128
129struct i40iw_handler *i40iw_find_netdev(struct net_device *netdev)
130{
131 struct i40iw_handler *hdl;
132 unsigned long flags;
133
134 spin_lock_irqsave(&i40iw_handler_lock, flags);
135 list_for_each_entry(hdl, &i40iw_handlers, list) {
136 if (hdl->ldev.netdev == netdev) {
137 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
138 return hdl;
139 }
140 }
141 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
142 return NULL;
143}
144
145
146
147
148
149static void i40iw_add_handler(struct i40iw_handler *hdl)
150{
151 unsigned long flags;
152
153 spin_lock_irqsave(&i40iw_handler_lock, flags);
154 list_add(&hdl->list, &i40iw_handlers);
155 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
156}
157
158
159
160
161
162static int i40iw_del_handler(struct i40iw_handler *hdl)
163{
164 unsigned long flags;
165
166 spin_lock_irqsave(&i40iw_handler_lock, flags);
167 list_del(&hdl->list);
168 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
169 return 0;
170}
171
172
173
174
175
176
177static void i40iw_enable_intr(struct i40iw_sc_dev *dev, u32 msix_id)
178{
179 u32 val;
180
181 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
182 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
183 (3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
184 if (dev->is_pf)
185 i40iw_wr32(dev->hw, I40E_PFINT_DYN_CTLN(msix_id - 1), val);
186 else
187 i40iw_wr32(dev->hw, I40E_VFINT_DYN_CTLN1(msix_id - 1), val);
188}
189
190
191
192
193
194static void i40iw_dpc(unsigned long data)
195{
196 struct i40iw_device *iwdev = (struct i40iw_device *)data;
197
198 if (iwdev->msix_shared)
199 i40iw_process_ceq(iwdev, iwdev->ceqlist);
200 i40iw_process_aeq(iwdev);
201 i40iw_enable_intr(&iwdev->sc_dev, iwdev->iw_msixtbl[0].idx);
202}
203
204
205
206
207
208static void i40iw_ceq_dpc(unsigned long data)
209{
210 struct i40iw_ceq *iwceq = (struct i40iw_ceq *)data;
211 struct i40iw_device *iwdev = iwceq->iwdev;
212
213 i40iw_process_ceq(iwdev, iwceq);
214 i40iw_enable_intr(&iwdev->sc_dev, iwceq->msix_idx);
215}
216
217
218
219
220
221
222static irqreturn_t i40iw_irq_handler(int irq, void *data)
223{
224 struct i40iw_device *iwdev = (struct i40iw_device *)data;
225
226 tasklet_schedule(&iwdev->dpc_tasklet);
227 return IRQ_HANDLED;
228}
229
230
231
232
233
234
235
236
237
238static void i40iw_destroy_cqp(struct i40iw_device *iwdev, bool free_hwcqp)
239{
240 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
241 struct i40iw_cqp *cqp = &iwdev->cqp;
242
243 if (free_hwcqp)
244 dev->cqp_ops->cqp_destroy(dev->cqp);
245
246 i40iw_free_dma_mem(dev->hw, &cqp->sq);
247 kfree(cqp->scratch_array);
248 iwdev->cqp.scratch_array = NULL;
249
250 kfree(cqp->cqp_requests);
251 cqp->cqp_requests = NULL;
252}
253
254
255
256
257
258
259
260
261
262static void i40iw_disable_irq(struct i40iw_sc_dev *dev,
263 struct i40iw_msix_vector *msix_vec,
264 void *dev_id)
265{
266 if (dev->is_pf)
267 i40iw_wr32(dev->hw, I40E_PFINT_DYN_CTLN(msix_vec->idx - 1), 0);
268 else
269 i40iw_wr32(dev->hw, I40E_VFINT_DYN_CTLN1(msix_vec->idx - 1), 0);
270 irq_set_affinity_hint(msix_vec->irq, NULL);
271 free_irq(msix_vec->irq, dev_id);
272}
273
274
275
276
277
278
279
280
281
282
283static void i40iw_destroy_aeq(struct i40iw_device *iwdev, bool reset)
284{
285 enum i40iw_status_code status = I40IW_ERR_NOT_READY;
286 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
287 struct i40iw_aeq *aeq = &iwdev->aeq;
288
289 if (!iwdev->msix_shared)
290 i40iw_disable_irq(dev, iwdev->iw_msixtbl, (void *)iwdev);
291 if (reset)
292 goto exit;
293
294 if (!dev->aeq_ops->aeq_destroy(&aeq->sc_aeq, 0, 1))
295 status = dev->aeq_ops->aeq_destroy_done(&aeq->sc_aeq);
296 if (status)
297 i40iw_pr_err("destroy aeq failed %d\n", status);
298
299exit:
300 i40iw_free_dma_mem(dev->hw, &aeq->mem);
301}
302
303
304
305
306
307
308
309
310
311
312static void i40iw_destroy_ceq(struct i40iw_device *iwdev,
313 struct i40iw_ceq *iwceq,
314 bool reset)
315{
316 enum i40iw_status_code status;
317 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
318
319 if (reset)
320 goto exit;
321
322 status = dev->ceq_ops->ceq_destroy(&iwceq->sc_ceq, 0, 1);
323 if (status) {
324 i40iw_pr_err("ceq destroy command failed %d\n", status);
325 goto exit;
326 }
327
328 status = dev->ceq_ops->cceq_destroy_done(&iwceq->sc_ceq);
329 if (status)
330 i40iw_pr_err("ceq destroy completion failed %d\n", status);
331exit:
332 i40iw_free_dma_mem(dev->hw, &iwceq->mem);
333}
334
335
336
337
338
339
340
341
342
343static void i40iw_dele_ceqs(struct i40iw_device *iwdev, bool reset)
344{
345 u32 i = 0;
346 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
347 struct i40iw_ceq *iwceq = iwdev->ceqlist;
348 struct i40iw_msix_vector *msix_vec = iwdev->iw_msixtbl;
349
350 if (iwdev->msix_shared) {
351 i40iw_disable_irq(dev, msix_vec, (void *)iwdev);
352 i40iw_destroy_ceq(iwdev, iwceq, reset);
353 iwceq++;
354 i++;
355 }
356
357 for (msix_vec++; i < iwdev->ceqs_count; i++, msix_vec++, iwceq++) {
358 i40iw_disable_irq(dev, msix_vec, (void *)iwceq);
359 i40iw_destroy_ceq(iwdev, iwceq, reset);
360 }
361}
362
363
364
365
366
367
368
369
370
371static void i40iw_destroy_ccq(struct i40iw_device *iwdev, bool reset)
372{
373 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
374 struct i40iw_ccq *ccq = &iwdev->ccq;
375 enum i40iw_status_code status = 0;
376
377 if (!reset)
378 status = dev->ccq_ops->ccq_destroy(dev->ccq, 0, true);
379 if (status)
380 i40iw_pr_err("ccq destroy failed %d\n", status);
381 i40iw_free_dma_mem(dev->hw, &ccq->mem_cq);
382}
383
384
385static enum i40iw_hmc_rsrc_type iw_hmc_obj_types[] = {
386 I40IW_HMC_IW_QP,
387 I40IW_HMC_IW_CQ,
388 I40IW_HMC_IW_HTE,
389 I40IW_HMC_IW_ARP,
390 I40IW_HMC_IW_APBVT_ENTRY,
391 I40IW_HMC_IW_MR,
392 I40IW_HMC_IW_XF,
393 I40IW_HMC_IW_XFFL,
394 I40IW_HMC_IW_Q1,
395 I40IW_HMC_IW_Q1FL,
396 I40IW_HMC_IW_TIMER,
397};
398
399
400
401
402
403
404
405
406static void i40iw_close_hmc_objects_type(struct i40iw_sc_dev *dev,
407 enum i40iw_hmc_rsrc_type obj_type,
408 struct i40iw_hmc_info *hmc_info,
409 bool is_pf,
410 bool reset)
411{
412 struct i40iw_hmc_del_obj_info info;
413
414 memset(&info, 0, sizeof(info));
415 info.hmc_info = hmc_info;
416 info.rsrc_type = obj_type;
417 info.count = hmc_info->hmc_obj[obj_type].cnt;
418 info.is_pf = is_pf;
419 if (dev->hmc_ops->del_hmc_object(dev, &info, reset))
420 i40iw_pr_err("del obj of type %d failed\n", obj_type);
421}
422
423
424
425
426
427
428
429
430
431static void i40iw_del_hmc_objects(struct i40iw_sc_dev *dev,
432 struct i40iw_hmc_info *hmc_info,
433 bool is_pf,
434 bool reset)
435{
436 unsigned int i;
437
438 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++)
439 i40iw_close_hmc_objects_type(dev, iw_hmc_obj_types[i], hmc_info, is_pf, reset);
440}
441
442
443
444
445
446static irqreturn_t i40iw_ceq_handler(int irq, void *data)
447{
448 struct i40iw_ceq *iwceq = (struct i40iw_ceq *)data;
449
450 if (iwceq->irq != irq)
451 i40iw_pr_err("expected irq = %d received irq = %d\n", iwceq->irq, irq);
452 tasklet_schedule(&iwceq->dpc_tasklet);
453 return IRQ_HANDLED;
454}
455
456
457
458
459
460
461static enum i40iw_status_code i40iw_create_hmc_obj_type(struct i40iw_sc_dev *dev,
462 struct i40iw_hmc_create_obj_info *info)
463{
464 return dev->hmc_ops->create_hmc_object(dev, info);
465}
466
467
468
469
470
471
472
473
474
475static enum i40iw_status_code i40iw_create_hmc_objs(struct i40iw_device *iwdev,
476 bool is_pf)
477{
478 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
479 struct i40iw_hmc_create_obj_info info;
480 enum i40iw_status_code status;
481 int i;
482
483 memset(&info, 0, sizeof(info));
484 info.hmc_info = dev->hmc_info;
485 info.is_pf = is_pf;
486 info.entry_type = iwdev->sd_type;
487 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
488 info.rsrc_type = iw_hmc_obj_types[i];
489 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt;
490 status = i40iw_create_hmc_obj_type(dev, &info);
491 if (status) {
492 i40iw_pr_err("create obj type %d status = %d\n",
493 iw_hmc_obj_types[i], status);
494 break;
495 }
496 }
497 if (!status)
498 return (dev->cqp_misc_ops->static_hmc_pages_allocated(dev->cqp, 0,
499 dev->hmc_fn_id,
500 true, true));
501
502 while (i) {
503 i--;
504
505 i40iw_close_hmc_objects_type(dev,
506 iw_hmc_obj_types[i],
507 dev->hmc_info,
508 is_pf,
509 false);
510 }
511 return status;
512}
513
514
515
516
517
518
519
520
521
522
523
524
525enum i40iw_status_code i40iw_obj_aligned_mem(struct i40iw_device *iwdev,
526 struct i40iw_dma_mem *memptr,
527 u32 size,
528 u32 mask)
529{
530 unsigned long va, newva;
531 unsigned long extra;
532
533 va = (unsigned long)iwdev->obj_next.va;
534 newva = va;
535 if (mask)
536 newva = ALIGN(va, (mask + 1));
537 extra = newva - va;
538 memptr->va = (u8 *)va + extra;
539 memptr->pa = iwdev->obj_next.pa + extra;
540 memptr->size = size;
541 if ((memptr->va + size) > (iwdev->obj_mem.va + iwdev->obj_mem.size))
542 return I40IW_ERR_NO_MEMORY;
543
544 iwdev->obj_next.va = memptr->va + size;
545 iwdev->obj_next.pa = memptr->pa + size;
546 return 0;
547}
548
549
550
551
552
553
554
555
556static enum i40iw_status_code i40iw_create_cqp(struct i40iw_device *iwdev)
557{
558 enum i40iw_status_code status;
559 u32 sqsize = I40IW_CQP_SW_SQSIZE_2048;
560 struct i40iw_dma_mem mem;
561 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
562 struct i40iw_cqp_init_info cqp_init_info;
563 struct i40iw_cqp *cqp = &iwdev->cqp;
564 u16 maj_err, min_err;
565 int i;
566
567 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL);
568 if (!cqp->cqp_requests)
569 return I40IW_ERR_NO_MEMORY;
570 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL);
571 if (!cqp->scratch_array) {
572 kfree(cqp->cqp_requests);
573 return I40IW_ERR_NO_MEMORY;
574 }
575 dev->cqp = &cqp->sc_cqp;
576 dev->cqp->dev = dev;
577 memset(&cqp_init_info, 0, sizeof(cqp_init_info));
578 status = i40iw_allocate_dma_mem(dev->hw, &cqp->sq,
579 (sizeof(struct i40iw_cqp_sq_wqe) * sqsize),
580 I40IW_CQP_ALIGNMENT);
581 if (status)
582 goto exit;
583 status = i40iw_obj_aligned_mem(iwdev, &mem, sizeof(struct i40iw_cqp_ctx),
584 I40IW_HOST_CTX_ALIGNMENT_MASK);
585 if (status)
586 goto exit;
587 dev->cqp->host_ctx_pa = mem.pa;
588 dev->cqp->host_ctx = mem.va;
589
590 cqp_init_info.dev = dev;
591 cqp_init_info.sq_size = sqsize;
592 cqp_init_info.sq = cqp->sq.va;
593 cqp_init_info.sq_pa = cqp->sq.pa;
594 cqp_init_info.host_ctx_pa = mem.pa;
595 cqp_init_info.host_ctx = mem.va;
596 cqp_init_info.hmc_profile = iwdev->resource_profile;
597 cqp_init_info.enabled_vf_count = iwdev->max_rdma_vfs;
598 cqp_init_info.scratch_array = cqp->scratch_array;
599 status = dev->cqp_ops->cqp_init(dev->cqp, &cqp_init_info);
600 if (status) {
601 i40iw_pr_err("cqp init status %d\n", status);
602 goto exit;
603 }
604 status = dev->cqp_ops->cqp_create(dev->cqp, &maj_err, &min_err);
605 if (status) {
606 i40iw_pr_err("cqp create status %d maj_err %d min_err %d\n",
607 status, maj_err, min_err);
608 goto exit;
609 }
610 spin_lock_init(&cqp->req_lock);
611 INIT_LIST_HEAD(&cqp->cqp_avail_reqs);
612 INIT_LIST_HEAD(&cqp->cqp_pending_reqs);
613
614 for (i = 0; i < I40IW_CQP_SW_SQSIZE_2048; i++) {
615 init_waitqueue_head(&cqp->cqp_requests[i].waitq);
616 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs);
617 }
618 return 0;
619exit:
620
621 i40iw_destroy_cqp(iwdev, false);
622 return status;
623}
624
625
626
627
628
629
630
631
632static enum i40iw_status_code i40iw_create_ccq(struct i40iw_device *iwdev)
633{
634 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
635 struct i40iw_dma_mem mem;
636 enum i40iw_status_code status;
637 struct i40iw_ccq_init_info info;
638 struct i40iw_ccq *ccq = &iwdev->ccq;
639
640 memset(&info, 0, sizeof(info));
641 dev->ccq = &ccq->sc_cq;
642 dev->ccq->dev = dev;
643 info.dev = dev;
644 ccq->shadow_area.size = sizeof(struct i40iw_cq_shadow_area);
645 ccq->mem_cq.size = sizeof(struct i40iw_cqe) * IW_CCQ_SIZE;
646 status = i40iw_allocate_dma_mem(dev->hw, &ccq->mem_cq,
647 ccq->mem_cq.size, I40IW_CQ0_ALIGNMENT);
648 if (status)
649 goto exit;
650 status = i40iw_obj_aligned_mem(iwdev, &mem, ccq->shadow_area.size,
651 I40IW_SHADOWAREA_MASK);
652 if (status)
653 goto exit;
654 ccq->sc_cq.back_cq = (void *)ccq;
655
656 info.cq_base = ccq->mem_cq.va;
657 info.cq_pa = ccq->mem_cq.pa;
658 info.num_elem = IW_CCQ_SIZE;
659 info.shadow_area = mem.va;
660 info.shadow_area_pa = mem.pa;
661 info.ceqe_mask = false;
662 info.ceq_id_valid = true;
663 info.shadow_read_threshold = 16;
664 status = dev->ccq_ops->ccq_init(dev->ccq, &info);
665 if (!status)
666 status = dev->ccq_ops->ccq_create(dev->ccq, 0, true, true);
667exit:
668 if (status)
669 i40iw_free_dma_mem(dev->hw, &ccq->mem_cq);
670 return status;
671}
672
673
674
675
676
677
678
679
680
681
682
683static enum i40iw_status_code i40iw_configure_ceq_vector(struct i40iw_device *iwdev,
684 struct i40iw_ceq *iwceq,
685 u32 ceq_id,
686 struct i40iw_msix_vector *msix_vec)
687{
688 enum i40iw_status_code status;
689 cpumask_t mask;
690
691 if (iwdev->msix_shared && !ceq_id) {
692 tasklet_init(&iwdev->dpc_tasklet, i40iw_dpc, (unsigned long)iwdev);
693 status = request_irq(msix_vec->irq, i40iw_irq_handler, 0, "AEQCEQ", iwdev);
694 } else {
695 tasklet_init(&iwceq->dpc_tasklet, i40iw_ceq_dpc, (unsigned long)iwceq);
696 status = request_irq(msix_vec->irq, i40iw_ceq_handler, 0, "CEQ", iwceq);
697 }
698
699 cpumask_clear(&mask);
700 cpumask_set_cpu(msix_vec->cpu_affinity, &mask);
701 irq_set_affinity_hint(msix_vec->irq, &mask);
702
703 if (status) {
704 i40iw_pr_err("ceq irq config fail\n");
705 return I40IW_ERR_CONFIG;
706 }
707 msix_vec->ceq_id = ceq_id;
708
709 return 0;
710}
711
712
713
714
715
716
717
718
719
720
721static enum i40iw_status_code i40iw_create_ceq(struct i40iw_device *iwdev,
722 struct i40iw_ceq *iwceq,
723 u32 ceq_id)
724{
725 enum i40iw_status_code status;
726 struct i40iw_ceq_init_info info;
727 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
728 u64 scratch;
729
730 memset(&info, 0, sizeof(info));
731 info.ceq_id = ceq_id;
732 iwceq->iwdev = iwdev;
733 iwceq->mem.size = sizeof(struct i40iw_ceqe) *
734 iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
735 status = i40iw_allocate_dma_mem(dev->hw, &iwceq->mem, iwceq->mem.size,
736 I40IW_CEQ_ALIGNMENT);
737 if (status)
738 goto exit;
739 info.ceq_id = ceq_id;
740 info.ceqe_base = iwceq->mem.va;
741 info.ceqe_pa = iwceq->mem.pa;
742
743 info.elem_cnt = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
744 iwceq->sc_ceq.ceq_id = ceq_id;
745 info.dev = dev;
746 scratch = (uintptr_t)&iwdev->cqp.sc_cqp;
747 status = dev->ceq_ops->ceq_init(&iwceq->sc_ceq, &info);
748 if (!status)
749 status = dev->ceq_ops->cceq_create(&iwceq->sc_ceq, scratch);
750
751exit:
752 if (status)
753 i40iw_free_dma_mem(dev->hw, &iwceq->mem);
754 return status;
755}
756
757void i40iw_request_reset(struct i40iw_device *iwdev)
758{
759 struct i40e_info *ldev = iwdev->ldev;
760
761 ldev->ops->request_reset(ldev, iwdev->client, 1);
762}
763
764
765
766
767
768
769
770
771
772
773static enum i40iw_status_code i40iw_setup_ceqs(struct i40iw_device *iwdev,
774 struct i40e_info *ldev)
775{
776 u32 i;
777 u32 ceq_id;
778 struct i40iw_ceq *iwceq;
779 struct i40iw_msix_vector *msix_vec;
780 enum i40iw_status_code status = 0;
781 u32 num_ceqs;
782
783 if (ldev && ldev->ops && ldev->ops->setup_qvlist) {
784 status = ldev->ops->setup_qvlist(ldev, &i40iw_client,
785 iwdev->iw_qvlist);
786 if (status)
787 goto exit;
788 } else {
789 status = I40IW_ERR_BAD_PTR;
790 goto exit;
791 }
792
793 num_ceqs = min(iwdev->msix_count, iwdev->sc_dev.hmc_fpm_misc.max_ceqs);
794 iwdev->ceqlist = kcalloc(num_ceqs, sizeof(*iwdev->ceqlist), GFP_KERNEL);
795 if (!iwdev->ceqlist) {
796 status = I40IW_ERR_NO_MEMORY;
797 goto exit;
798 }
799 i = (iwdev->msix_shared) ? 0 : 1;
800 for (ceq_id = 0; i < num_ceqs; i++, ceq_id++) {
801 iwceq = &iwdev->ceqlist[ceq_id];
802 status = i40iw_create_ceq(iwdev, iwceq, ceq_id);
803 if (status) {
804 i40iw_pr_err("create ceq status = %d\n", status);
805 break;
806 }
807
808 msix_vec = &iwdev->iw_msixtbl[i];
809 iwceq->irq = msix_vec->irq;
810 iwceq->msix_idx = msix_vec->idx;
811 status = i40iw_configure_ceq_vector(iwdev, iwceq, ceq_id, msix_vec);
812 if (status) {
813 i40iw_destroy_ceq(iwdev, iwceq, false);
814 break;
815 }
816 i40iw_enable_intr(&iwdev->sc_dev, msix_vec->idx);
817 iwdev->ceqs_count++;
818 }
819
820exit:
821 if (status) {
822 if (!iwdev->ceqs_count) {
823 kfree(iwdev->ceqlist);
824 iwdev->ceqlist = NULL;
825 } else {
826 status = 0;
827 }
828 }
829 return status;
830}
831
832
833
834
835
836
837
838
839static enum i40iw_status_code i40iw_configure_aeq_vector(struct i40iw_device *iwdev)
840{
841 struct i40iw_msix_vector *msix_vec = iwdev->iw_msixtbl;
842 u32 ret = 0;
843
844 if (!iwdev->msix_shared) {
845 tasklet_init(&iwdev->dpc_tasklet, i40iw_dpc, (unsigned long)iwdev);
846 ret = request_irq(msix_vec->irq, i40iw_irq_handler, 0, "i40iw", iwdev);
847 }
848 if (ret) {
849 i40iw_pr_err("aeq irq config fail\n");
850 return I40IW_ERR_CONFIG;
851 }
852
853 return 0;
854}
855
856
857
858
859
860
861
862
863static enum i40iw_status_code i40iw_create_aeq(struct i40iw_device *iwdev)
864{
865 enum i40iw_status_code status;
866 struct i40iw_aeq_init_info info;
867 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
868 struct i40iw_aeq *aeq = &iwdev->aeq;
869 u64 scratch = 0;
870 u32 aeq_size;
871
872 aeq_size = 2 * iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt +
873 iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
874 memset(&info, 0, sizeof(info));
875 aeq->mem.size = sizeof(struct i40iw_sc_aeqe) * aeq_size;
876 status = i40iw_allocate_dma_mem(dev->hw, &aeq->mem, aeq->mem.size,
877 I40IW_AEQ_ALIGNMENT);
878 if (status)
879 goto exit;
880
881 info.aeqe_base = aeq->mem.va;
882 info.aeq_elem_pa = aeq->mem.pa;
883 info.elem_cnt = aeq_size;
884 info.dev = dev;
885 status = dev->aeq_ops->aeq_init(&aeq->sc_aeq, &info);
886 if (status)
887 goto exit;
888 status = dev->aeq_ops->aeq_create(&aeq->sc_aeq, scratch, 1);
889 if (!status)
890 status = dev->aeq_ops->aeq_create_done(&aeq->sc_aeq);
891exit:
892 if (status)
893 i40iw_free_dma_mem(dev->hw, &aeq->mem);
894 return status;
895}
896
897
898
899
900
901
902
903
904static enum i40iw_status_code i40iw_setup_aeq(struct i40iw_device *iwdev)
905{
906 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
907 enum i40iw_status_code status;
908
909 status = i40iw_create_aeq(iwdev);
910 if (status)
911 return status;
912
913 status = i40iw_configure_aeq_vector(iwdev);
914 if (status) {
915 i40iw_destroy_aeq(iwdev, false);
916 return status;
917 }
918
919 if (!iwdev->msix_shared)
920 i40iw_enable_intr(dev, iwdev->iw_msixtbl[0].idx);
921 return 0;
922}
923
924
925
926
927
928
929
930static enum i40iw_status_code i40iw_initialize_ilq(struct i40iw_device *iwdev)
931{
932 struct i40iw_puda_rsrc_info info;
933 enum i40iw_status_code status;
934
935 memset(&info, 0, sizeof(info));
936 info.type = I40IW_PUDA_RSRC_TYPE_ILQ;
937 info.cq_id = 1;
938 info.qp_id = 0;
939 info.count = 1;
940 info.pd_id = 1;
941 info.sq_size = 8192;
942 info.rq_size = 8192;
943 info.buf_size = 1024;
944 info.tx_buf_cnt = 16384;
945 info.receive = i40iw_receive_ilq;
946 info.xmit_complete = i40iw_free_sqbuf;
947 status = i40iw_puda_create_rsrc(&iwdev->vsi, &info);
948 if (status)
949 i40iw_pr_err("ilq create fail\n");
950 return status;
951}
952
953
954
955
956
957
958
959static enum i40iw_status_code i40iw_initialize_ieq(struct i40iw_device *iwdev)
960{
961 struct i40iw_puda_rsrc_info info;
962 enum i40iw_status_code status;
963
964 memset(&info, 0, sizeof(info));
965 info.type = I40IW_PUDA_RSRC_TYPE_IEQ;
966 info.cq_id = 2;
967 info.qp_id = iwdev->sc_dev.exception_lan_queue;
968 info.count = 1;
969 info.pd_id = 2;
970 info.sq_size = 8192;
971 info.rq_size = 8192;
972 info.buf_size = 2048;
973 info.tx_buf_cnt = 16384;
974 status = i40iw_puda_create_rsrc(&iwdev->vsi, &info);
975 if (status)
976 i40iw_pr_err("ieq create fail\n");
977 return status;
978}
979
980
981
982
983
984
985
986
987
988static enum i40iw_status_code i40iw_hmc_setup(struct i40iw_device *iwdev)
989{
990 enum i40iw_status_code status;
991
992 iwdev->sd_type = I40IW_SD_TYPE_DIRECT;
993 status = i40iw_config_fpm_values(&iwdev->sc_dev, IW_CFG_FPM_QP_COUNT);
994 if (status)
995 goto exit;
996 status = i40iw_create_hmc_objs(iwdev, true);
997 if (status)
998 goto exit;
999 iwdev->init_state = HMC_OBJS_CREATED;
1000exit:
1001 return status;
1002}
1003
1004
1005
1006
1007
1008static void i40iw_del_init_mem(struct i40iw_device *iwdev)
1009{
1010 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1011
1012 i40iw_free_dma_mem(&iwdev->hw, &iwdev->obj_mem);
1013 kfree(dev->hmc_info->sd_table.sd_entry);
1014 dev->hmc_info->sd_table.sd_entry = NULL;
1015 kfree(iwdev->mem_resources);
1016 iwdev->mem_resources = NULL;
1017 kfree(iwdev->ceqlist);
1018 iwdev->ceqlist = NULL;
1019 kfree(iwdev->iw_msixtbl);
1020 iwdev->iw_msixtbl = NULL;
1021 kfree(iwdev->hmc_info_mem);
1022 iwdev->hmc_info_mem = NULL;
1023}
1024
1025
1026
1027
1028
1029
1030static void i40iw_del_macip_entry(struct i40iw_device *iwdev, u8 idx)
1031{
1032 struct i40iw_cqp *iwcqp = &iwdev->cqp;
1033 struct i40iw_cqp_request *cqp_request;
1034 struct cqp_commands_info *cqp_info;
1035 enum i40iw_status_code status = 0;
1036
1037 cqp_request = i40iw_get_cqp_request(iwcqp, true);
1038 if (!cqp_request) {
1039 i40iw_pr_err("cqp_request memory failed\n");
1040 return;
1041 }
1042 cqp_info = &cqp_request->info;
1043 cqp_info->cqp_cmd = OP_DELETE_LOCAL_MAC_IPADDR_ENTRY;
1044 cqp_info->post_sq = 1;
1045 cqp_info->in.u.del_local_mac_ipaddr_entry.cqp = &iwcqp->sc_cqp;
1046 cqp_info->in.u.del_local_mac_ipaddr_entry.scratch = (uintptr_t)cqp_request;
1047 cqp_info->in.u.del_local_mac_ipaddr_entry.entry_idx = idx;
1048 cqp_info->in.u.del_local_mac_ipaddr_entry.ignore_ref_count = 0;
1049 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1050 if (status)
1051 i40iw_pr_err("CQP-OP Del MAC Ip entry fail");
1052}
1053
1054
1055
1056
1057
1058
1059
1060static enum i40iw_status_code i40iw_add_mac_ipaddr_entry(struct i40iw_device *iwdev,
1061 u8 *mac_addr,
1062 u8 idx)
1063{
1064 struct i40iw_local_mac_ipaddr_entry_info *info;
1065 struct i40iw_cqp *iwcqp = &iwdev->cqp;
1066 struct i40iw_cqp_request *cqp_request;
1067 struct cqp_commands_info *cqp_info;
1068 enum i40iw_status_code status = 0;
1069
1070 cqp_request = i40iw_get_cqp_request(iwcqp, true);
1071 if (!cqp_request) {
1072 i40iw_pr_err("cqp_request memory failed\n");
1073 return I40IW_ERR_NO_MEMORY;
1074 }
1075
1076 cqp_info = &cqp_request->info;
1077
1078 cqp_info->post_sq = 1;
1079 info = &cqp_info->in.u.add_local_mac_ipaddr_entry.info;
1080 ether_addr_copy(info->mac_addr, mac_addr);
1081 info->entry_idx = idx;
1082 cqp_info->in.u.add_local_mac_ipaddr_entry.scratch = (uintptr_t)cqp_request;
1083 cqp_info->cqp_cmd = OP_ADD_LOCAL_MAC_IPADDR_ENTRY;
1084 cqp_info->in.u.add_local_mac_ipaddr_entry.cqp = &iwcqp->sc_cqp;
1085 cqp_info->in.u.add_local_mac_ipaddr_entry.scratch = (uintptr_t)cqp_request;
1086 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1087 if (status)
1088 i40iw_pr_err("CQP-OP Add MAC Ip entry fail");
1089 return status;
1090}
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101static enum i40iw_status_code i40iw_alloc_local_mac_ipaddr_entry(struct i40iw_device *iwdev,
1102 u16 *mac_ip_tbl_idx)
1103{
1104 struct i40iw_cqp *iwcqp = &iwdev->cqp;
1105 struct i40iw_cqp_request *cqp_request;
1106 struct cqp_commands_info *cqp_info;
1107 enum i40iw_status_code status = 0;
1108
1109 cqp_request = i40iw_get_cqp_request(iwcqp, true);
1110 if (!cqp_request) {
1111 i40iw_pr_err("cqp_request memory failed\n");
1112 return I40IW_ERR_NO_MEMORY;
1113 }
1114
1115
1116 atomic_inc(&cqp_request->refcount);
1117
1118 cqp_info = &cqp_request->info;
1119 cqp_info->cqp_cmd = OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY;
1120 cqp_info->post_sq = 1;
1121 cqp_info->in.u.alloc_local_mac_ipaddr_entry.cqp = &iwcqp->sc_cqp;
1122 cqp_info->in.u.alloc_local_mac_ipaddr_entry.scratch = (uintptr_t)cqp_request;
1123 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1124 if (!status)
1125 *mac_ip_tbl_idx = cqp_request->compl_info.op_ret_val;
1126 else
1127 i40iw_pr_err("CQP-OP Alloc MAC Ip entry fail");
1128
1129 i40iw_put_cqp_request(iwcqp, cqp_request);
1130 return status;
1131}
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141static enum i40iw_status_code i40iw_alloc_set_mac_ipaddr(struct i40iw_device *iwdev,
1142 u8 *macaddr)
1143{
1144 enum i40iw_status_code status;
1145
1146 status = i40iw_alloc_local_mac_ipaddr_entry(iwdev, &iwdev->mac_ip_table_idx);
1147 if (!status) {
1148 status = i40iw_add_mac_ipaddr_entry(iwdev, macaddr,
1149 (u8)iwdev->mac_ip_table_idx);
1150 if (status)
1151 i40iw_del_macip_entry(iwdev, (u8)iwdev->mac_ip_table_idx);
1152 }
1153 return status;
1154}
1155
1156
1157
1158
1159
1160static void i40iw_add_ipv6_addr(struct i40iw_device *iwdev)
1161{
1162 struct net_device *ip_dev;
1163 struct inet6_dev *idev;
1164 struct inet6_ifaddr *ifp, *tmp;
1165 u32 local_ipaddr6[4];
1166
1167 rcu_read_lock();
1168 for_each_netdev_rcu(&init_net, ip_dev) {
1169 if ((((rdma_vlan_dev_vlan_id(ip_dev) < 0xFFFF) &&
1170 (rdma_vlan_dev_real_dev(ip_dev) == iwdev->netdev)) ||
1171 (ip_dev == iwdev->netdev)) && (ip_dev->flags & IFF_UP)) {
1172 idev = __in6_dev_get(ip_dev);
1173 if (!idev) {
1174 i40iw_pr_err("ipv6 inet device not found\n");
1175 break;
1176 }
1177 list_for_each_entry_safe(ifp, tmp, &idev->addr_list, if_list) {
1178 i40iw_pr_info("IP=%pI6, vlan_id=%d, MAC=%pM\n", &ifp->addr,
1179 rdma_vlan_dev_vlan_id(ip_dev), ip_dev->dev_addr);
1180 i40iw_copy_ip_ntohl(local_ipaddr6,
1181 ifp->addr.in6_u.u6_addr32);
1182 i40iw_manage_arp_cache(iwdev,
1183 ip_dev->dev_addr,
1184 local_ipaddr6,
1185 false,
1186 I40IW_ARP_ADD);
1187 }
1188 }
1189 }
1190 rcu_read_unlock();
1191}
1192
1193
1194
1195
1196
1197static void i40iw_add_ipv4_addr(struct i40iw_device *iwdev)
1198{
1199 struct net_device *dev;
1200 struct in_device *idev;
1201 bool got_lock = true;
1202 u32 ip_addr;
1203
1204 if (!rtnl_trylock())
1205 got_lock = false;
1206
1207 for_each_netdev(&init_net, dev) {
1208 if ((((rdma_vlan_dev_vlan_id(dev) < 0xFFFF) &&
1209 (rdma_vlan_dev_real_dev(dev) == iwdev->netdev)) ||
1210 (dev == iwdev->netdev)) && (dev->flags & IFF_UP)) {
1211 idev = in_dev_get(dev);
1212 for_ifa(idev) {
1213 i40iw_debug(&iwdev->sc_dev, I40IW_DEBUG_CM,
1214 "IP=%pI4, vlan_id=%d, MAC=%pM\n", &ifa->ifa_address,
1215 rdma_vlan_dev_vlan_id(dev), dev->dev_addr);
1216
1217 ip_addr = ntohl(ifa->ifa_address);
1218 i40iw_manage_arp_cache(iwdev,
1219 dev->dev_addr,
1220 &ip_addr,
1221 true,
1222 I40IW_ARP_ADD);
1223 }
1224 endfor_ifa(idev);
1225 in_dev_put(idev);
1226 }
1227 }
1228 if (got_lock)
1229 rtnl_unlock();
1230}
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240static enum i40iw_status_code i40iw_add_mac_ip(struct i40iw_device *iwdev)
1241{
1242 struct net_device *netdev = iwdev->netdev;
1243 enum i40iw_status_code status;
1244
1245 status = i40iw_alloc_set_mac_ipaddr(iwdev, (u8 *)netdev->dev_addr);
1246 if (status)
1247 return status;
1248 i40iw_add_ipv4_addr(iwdev);
1249 i40iw_add_ipv6_addr(iwdev);
1250 return 0;
1251}
1252
1253
1254
1255
1256
1257static void i40iw_wait_pe_ready(struct i40iw_hw *hw)
1258{
1259 u32 statusfw;
1260 u32 statuscpu0;
1261 u32 statuscpu1;
1262 u32 statuscpu2;
1263 u32 retrycount = 0;
1264
1265 do {
1266 statusfw = i40iw_rd32(hw, I40E_GLPE_FWLDSTATUS);
1267 i40iw_pr_info("[%04d] fm load status[x%04X]\n", __LINE__, statusfw);
1268 statuscpu0 = i40iw_rd32(hw, I40E_GLPE_CPUSTATUS0);
1269 i40iw_pr_info("[%04d] CSR_CQP status[x%04X]\n", __LINE__, statuscpu0);
1270 statuscpu1 = i40iw_rd32(hw, I40E_GLPE_CPUSTATUS1);
1271 i40iw_pr_info("[%04d] I40E_GLPE_CPUSTATUS1 status[x%04X]\n",
1272 __LINE__, statuscpu1);
1273 statuscpu2 = i40iw_rd32(hw, I40E_GLPE_CPUSTATUS2);
1274 i40iw_pr_info("[%04d] I40E_GLPE_CPUSTATUS2 status[x%04X]\n",
1275 __LINE__, statuscpu2);
1276 if ((statuscpu0 == 0x80) && (statuscpu1 == 0x80) && (statuscpu2 == 0x80))
1277 break;
1278 mdelay(1000);
1279 retrycount++;
1280 } while (retrycount < 14);
1281 i40iw_wr32(hw, 0xb4040, 0x4C104C5);
1282}
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293static enum i40iw_status_code i40iw_initialize_dev(struct i40iw_device *iwdev,
1294 struct i40e_info *ldev)
1295{
1296 enum i40iw_status_code status;
1297 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1298 struct i40iw_device_init_info info;
1299 struct i40iw_vsi_init_info vsi_info;
1300 struct i40iw_dma_mem mem;
1301 struct i40iw_l2params l2params;
1302 u32 size;
1303 struct i40iw_vsi_stats_info stats_info;
1304 u16 last_qset = I40IW_NO_QSET;
1305 u16 qset;
1306 u32 i;
1307
1308 memset(&l2params, 0, sizeof(l2params));
1309 memset(&info, 0, sizeof(info));
1310 size = sizeof(struct i40iw_hmc_pble_rsrc) + sizeof(struct i40iw_hmc_info) +
1311 (sizeof(struct i40iw_hmc_obj_info) * I40IW_HMC_IW_MAX);
1312 iwdev->hmc_info_mem = kzalloc(size, GFP_KERNEL);
1313 if (!iwdev->hmc_info_mem)
1314 return I40IW_ERR_NO_MEMORY;
1315
1316 iwdev->pble_rsrc = (struct i40iw_hmc_pble_rsrc *)iwdev->hmc_info_mem;
1317 dev->hmc_info = &iwdev->hw.hmc;
1318 dev->hmc_info->hmc_obj = (struct i40iw_hmc_obj_info *)(iwdev->pble_rsrc + 1);
1319 status = i40iw_obj_aligned_mem(iwdev, &mem, I40IW_QUERY_FPM_BUF_SIZE,
1320 I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK);
1321 if (status)
1322 goto exit;
1323 info.fpm_query_buf_pa = mem.pa;
1324 info.fpm_query_buf = mem.va;
1325 status = i40iw_obj_aligned_mem(iwdev, &mem, I40IW_COMMIT_FPM_BUF_SIZE,
1326 I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK);
1327 if (status)
1328 goto exit;
1329 info.fpm_commit_buf_pa = mem.pa;
1330 info.fpm_commit_buf = mem.va;
1331 info.hmc_fn_id = ldev->fid;
1332 info.is_pf = (ldev->ftype) ? false : true;
1333 info.bar0 = ldev->hw_addr;
1334 info.hw = &iwdev->hw;
1335 info.debug_mask = debug;
1336 l2params.mss =
1337 (ldev->params.mtu) ? ldev->params.mtu - I40IW_MTU_TO_MSS : I40IW_DEFAULT_MSS;
1338 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++) {
1339 qset = ldev->params.qos.prio_qos[i].qs_handle;
1340 l2params.qs_handle_list[i] = qset;
1341 if (last_qset == I40IW_NO_QSET)
1342 last_qset = qset;
1343 else if ((qset != last_qset) && (qset != I40IW_NO_QSET))
1344 iwdev->dcb = true;
1345 }
1346 i40iw_pr_info("DCB is set/clear = %d\n", iwdev->dcb);
1347 info.exception_lan_queue = 1;
1348 info.vchnl_send = i40iw_virtchnl_send;
1349 status = i40iw_device_init(&iwdev->sc_dev, &info);
1350exit:
1351 if (status) {
1352 kfree(iwdev->hmc_info_mem);
1353 iwdev->hmc_info_mem = NULL;
1354 }
1355 memset(&vsi_info, 0, sizeof(vsi_info));
1356 vsi_info.dev = &iwdev->sc_dev;
1357 vsi_info.back_vsi = (void *)iwdev;
1358 vsi_info.params = &l2params;
1359 i40iw_sc_vsi_init(&iwdev->vsi, &vsi_info);
1360
1361 if (dev->is_pf) {
1362 memset(&stats_info, 0, sizeof(stats_info));
1363 stats_info.fcn_id = ldev->fid;
1364 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
1365 stats_info.stats_initialize = true;
1366 if (stats_info.pestat)
1367 i40iw_vsi_stats_init(&iwdev->vsi, &stats_info);
1368 }
1369 return status;
1370}
1371
1372
1373
1374
1375static void i40iw_register_notifiers(void)
1376{
1377 if (atomic_inc_return(&i40iw_notifiers_registered) == 1) {
1378 register_inetaddr_notifier(&i40iw_inetaddr_notifier);
1379 register_inet6addr_notifier(&i40iw_inetaddr6_notifier);
1380 register_netevent_notifier(&i40iw_net_notifier);
1381 }
1382}
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392static enum i40iw_status_code i40iw_save_msix_info(struct i40iw_device *iwdev,
1393 struct i40e_info *ldev)
1394{
1395 struct i40e_qvlist_info *iw_qvlist;
1396 struct i40e_qv_info *iw_qvinfo;
1397 u32 ceq_idx;
1398 u32 i;
1399 u32 size;
1400
1401 iwdev->msix_count = ldev->msix_count;
1402
1403 size = sizeof(struct i40iw_msix_vector) * iwdev->msix_count;
1404 size += sizeof(struct i40e_qvlist_info);
1405 size += sizeof(struct i40e_qv_info) * iwdev->msix_count - 1;
1406 iwdev->iw_msixtbl = kzalloc(size, GFP_KERNEL);
1407
1408 if (!iwdev->iw_msixtbl)
1409 return I40IW_ERR_NO_MEMORY;
1410 iwdev->iw_qvlist = (struct i40e_qvlist_info *)(&iwdev->iw_msixtbl[iwdev->msix_count]);
1411 iw_qvlist = iwdev->iw_qvlist;
1412 iw_qvinfo = iw_qvlist->qv_info;
1413 iw_qvlist->num_vectors = iwdev->msix_count;
1414 if (iwdev->msix_count <= num_online_cpus())
1415 iwdev->msix_shared = true;
1416 for (i = 0, ceq_idx = 0; i < iwdev->msix_count; i++, iw_qvinfo++) {
1417 iwdev->iw_msixtbl[i].idx = ldev->msix_entries[i].entry;
1418 iwdev->iw_msixtbl[i].irq = ldev->msix_entries[i].vector;
1419 iwdev->iw_msixtbl[i].cpu_affinity = ceq_idx;
1420 if (i == 0) {
1421 iw_qvinfo->aeq_idx = 0;
1422 if (iwdev->msix_shared)
1423 iw_qvinfo->ceq_idx = ceq_idx++;
1424 else
1425 iw_qvinfo->ceq_idx = I40E_QUEUE_INVALID_IDX;
1426 } else {
1427 iw_qvinfo->aeq_idx = I40E_QUEUE_INVALID_IDX;
1428 iw_qvinfo->ceq_idx = ceq_idx++;
1429 }
1430 iw_qvinfo->itr_idx = 3;
1431 iw_qvinfo->v_idx = iwdev->iw_msixtbl[i].idx;
1432 }
1433 return 0;
1434}
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444static void i40iw_deinit_device(struct i40iw_device *iwdev, bool reset)
1445{
1446 struct i40e_info *ldev = iwdev->ldev;
1447
1448 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1449
1450 i40iw_pr_info("state = %d\n", iwdev->init_state);
1451 if (iwdev->param_wq)
1452 destroy_workqueue(iwdev->param_wq);
1453
1454 switch (iwdev->init_state) {
1455 case RDMA_DEV_REGISTERED:
1456 iwdev->iw_status = 0;
1457 i40iw_port_ibevent(iwdev);
1458 i40iw_destroy_rdma_device(iwdev->iwibdev);
1459
1460 case IP_ADDR_REGISTERED:
1461 if (!reset)
1462 i40iw_del_macip_entry(iwdev, (u8)iwdev->mac_ip_table_idx);
1463
1464 case INET_NOTIFIER:
1465 if (!atomic_dec_return(&i40iw_notifiers_registered)) {
1466 unregister_netevent_notifier(&i40iw_net_notifier);
1467 unregister_inetaddr_notifier(&i40iw_inetaddr_notifier);
1468 unregister_inet6addr_notifier(&i40iw_inetaddr6_notifier);
1469 }
1470
1471 case CEQ_CREATED:
1472 i40iw_dele_ceqs(iwdev, reset);
1473
1474 case AEQ_CREATED:
1475 i40iw_destroy_aeq(iwdev, reset);
1476
1477 case IEQ_CREATED:
1478 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_IEQ, reset);
1479
1480 case ILQ_CREATED:
1481 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_ILQ, reset);
1482
1483 case CCQ_CREATED:
1484 i40iw_destroy_ccq(iwdev, reset);
1485
1486 case PBLE_CHUNK_MEM:
1487 i40iw_destroy_pble_pool(dev, iwdev->pble_rsrc);
1488
1489 case HMC_OBJS_CREATED:
1490 i40iw_del_hmc_objects(dev, dev->hmc_info, true, reset);
1491
1492 case CQP_CREATED:
1493 i40iw_destroy_cqp(iwdev, true);
1494
1495 case INITIAL_STATE:
1496 i40iw_cleanup_cm_core(&iwdev->cm_core);
1497 if (iwdev->vsi.pestat) {
1498 i40iw_vsi_stats_free(&iwdev->vsi);
1499 kfree(iwdev->vsi.pestat);
1500 }
1501 i40iw_del_init_mem(iwdev);
1502 break;
1503 case INVALID_STATE:
1504
1505 default:
1506 i40iw_pr_err("bad init_state = %d\n", iwdev->init_state);
1507 break;
1508 }
1509
1510 i40iw_del_handler(i40iw_find_i40e_handler(ldev));
1511 kfree(iwdev->hdl);
1512}
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524static enum i40iw_status_code i40iw_setup_init_state(struct i40iw_handler *hdl,
1525 struct i40e_info *ldev,
1526 struct i40e_client *client)
1527{
1528 struct i40iw_device *iwdev = &hdl->device;
1529 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1530 enum i40iw_status_code status;
1531
1532 memcpy(&hdl->ldev, ldev, sizeof(*ldev));
1533 if (resource_profile == 1)
1534 resource_profile = 2;
1535
1536 iwdev->mpa_version = mpa_version;
1537 iwdev->resource_profile = (resource_profile < I40IW_HMC_PROFILE_EQUAL) ?
1538 (u8)resource_profile + I40IW_HMC_PROFILE_DEFAULT :
1539 I40IW_HMC_PROFILE_DEFAULT;
1540 iwdev->max_rdma_vfs =
1541 (iwdev->resource_profile != I40IW_HMC_PROFILE_DEFAULT) ? max_rdma_vfs : 0;
1542 iwdev->max_enabled_vfs = iwdev->max_rdma_vfs;
1543 iwdev->netdev = ldev->netdev;
1544 hdl->client = client;
1545 if (!ldev->ftype)
1546 iwdev->db_start = pci_resource_start(ldev->pcidev, 0) + I40IW_DB_ADDR_OFFSET;
1547 else
1548 iwdev->db_start = pci_resource_start(ldev->pcidev, 0) + I40IW_VF_DB_ADDR_OFFSET;
1549
1550 status = i40iw_save_msix_info(iwdev, ldev);
1551 if (status)
1552 goto exit;
1553 iwdev->hw.dev_context = (void *)ldev->pcidev;
1554 iwdev->hw.hw_addr = ldev->hw_addr;
1555 status = i40iw_allocate_dma_mem(&iwdev->hw,
1556 &iwdev->obj_mem, 8192, 4096);
1557 if (status)
1558 goto exit;
1559 iwdev->obj_next = iwdev->obj_mem;
1560 iwdev->push_mode = push_mode;
1561
1562 init_waitqueue_head(&iwdev->vchnl_waitq);
1563 init_waitqueue_head(&dev->vf_reqs);
1564 init_waitqueue_head(&iwdev->close_wq);
1565
1566 status = i40iw_initialize_dev(iwdev, ldev);
1567exit:
1568 if (status) {
1569 kfree(iwdev->iw_msixtbl);
1570 i40iw_free_dma_mem(dev->hw, &iwdev->obj_mem);
1571 iwdev->iw_msixtbl = NULL;
1572 }
1573 return status;
1574}
1575
1576
1577
1578
1579
1580
1581
1582static void i40iw_get_used_rsrc(struct i40iw_device *iwdev)
1583{
1584 iwdev->used_pds = find_next_zero_bit(iwdev->allocated_pds, iwdev->max_pd, 0);
1585 iwdev->used_qps = find_next_zero_bit(iwdev->allocated_qps, iwdev->max_qp, 0);
1586 iwdev->used_cqs = find_next_zero_bit(iwdev->allocated_cqs, iwdev->max_cq, 0);
1587 iwdev->used_mrs = find_next_zero_bit(iwdev->allocated_mrs, iwdev->max_mr, 0);
1588}
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600static int i40iw_open(struct i40e_info *ldev, struct i40e_client *client)
1601{
1602 struct i40iw_device *iwdev;
1603 struct i40iw_sc_dev *dev;
1604 enum i40iw_status_code status;
1605 struct i40iw_handler *hdl;
1606
1607 hdl = i40iw_find_netdev(ldev->netdev);
1608 if (hdl)
1609 return 0;
1610
1611 hdl = kzalloc(sizeof(*hdl), GFP_KERNEL);
1612 if (!hdl)
1613 return -ENOMEM;
1614 iwdev = &hdl->device;
1615 iwdev->hdl = hdl;
1616 dev = &iwdev->sc_dev;
1617 i40iw_setup_cm_core(iwdev);
1618
1619 dev->back_dev = (void *)iwdev;
1620 iwdev->ldev = &hdl->ldev;
1621 iwdev->client = client;
1622 mutex_init(&iwdev->pbl_mutex);
1623 i40iw_add_handler(hdl);
1624
1625 do {
1626 status = i40iw_setup_init_state(hdl, ldev, client);
1627 if (status)
1628 break;
1629 iwdev->init_state = INITIAL_STATE;
1630 if (dev->is_pf)
1631 i40iw_wait_pe_ready(dev->hw);
1632 status = i40iw_create_cqp(iwdev);
1633 if (status)
1634 break;
1635 iwdev->init_state = CQP_CREATED;
1636 status = i40iw_hmc_setup(iwdev);
1637 if (status)
1638 break;
1639 status = i40iw_create_ccq(iwdev);
1640 if (status)
1641 break;
1642 iwdev->init_state = CCQ_CREATED;
1643 status = i40iw_initialize_ilq(iwdev);
1644 if (status)
1645 break;
1646 iwdev->init_state = ILQ_CREATED;
1647 status = i40iw_initialize_ieq(iwdev);
1648 if (status)
1649 break;
1650 iwdev->init_state = IEQ_CREATED;
1651 status = i40iw_setup_aeq(iwdev);
1652 if (status)
1653 break;
1654 iwdev->init_state = AEQ_CREATED;
1655 status = i40iw_setup_ceqs(iwdev, ldev);
1656 if (status)
1657 break;
1658 iwdev->init_state = CEQ_CREATED;
1659 status = i40iw_initialize_hw_resources(iwdev);
1660 if (status)
1661 break;
1662 i40iw_get_used_rsrc(iwdev);
1663 dev->ccq_ops->ccq_arm(dev->ccq);
1664 status = i40iw_hmc_init_pble(&iwdev->sc_dev, iwdev->pble_rsrc);
1665 if (status)
1666 break;
1667 iwdev->virtchnl_wq = alloc_ordered_workqueue("iwvch", WQ_MEM_RECLAIM);
1668 i40iw_register_notifiers();
1669 iwdev->init_state = INET_NOTIFIER;
1670 status = i40iw_add_mac_ip(iwdev);
1671 if (status)
1672 break;
1673 iwdev->init_state = IP_ADDR_REGISTERED;
1674 if (i40iw_register_rdma_device(iwdev)) {
1675 i40iw_pr_err("register rdma device fail\n");
1676 break;
1677 };
1678
1679 iwdev->init_state = RDMA_DEV_REGISTERED;
1680 iwdev->iw_status = 1;
1681 i40iw_port_ibevent(iwdev);
1682 iwdev->param_wq = alloc_ordered_workqueue("l2params", WQ_MEM_RECLAIM);
1683 if(iwdev->param_wq == NULL)
1684 break;
1685 i40iw_pr_info("i40iw_open completed\n");
1686 return 0;
1687 } while (0);
1688
1689 i40iw_pr_err("status = %d last completion = %d\n", status, iwdev->init_state);
1690 i40iw_deinit_device(iwdev, false);
1691 return -ERESTART;
1692}
1693
1694
1695
1696
1697
1698static void i40iw_l2params_worker(struct work_struct *work)
1699{
1700 struct l2params_work *dwork =
1701 container_of(work, struct l2params_work, work);
1702 struct i40iw_device *iwdev = dwork->iwdev;
1703
1704 i40iw_change_l2params(&iwdev->vsi, &dwork->l2params);
1705 atomic_dec(&iwdev->params_busy);
1706 kfree(work);
1707}
1708
1709
1710
1711
1712
1713
1714
1715static void i40iw_l2param_change(struct i40e_info *ldev, struct i40e_client *client,
1716 struct i40e_params *params)
1717{
1718 struct i40iw_handler *hdl;
1719 struct i40iw_l2params *l2params;
1720 struct l2params_work *work;
1721 struct i40iw_device *iwdev;
1722 int i;
1723
1724 hdl = i40iw_find_i40e_handler(ldev);
1725 if (!hdl)
1726 return;
1727
1728 iwdev = &hdl->device;
1729
1730 if (atomic_read(&iwdev->params_busy))
1731 return;
1732
1733
1734 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1735 if (!work)
1736 return;
1737
1738 atomic_inc(&iwdev->params_busy);
1739
1740 work->iwdev = iwdev;
1741 l2params = &work->l2params;
1742 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++)
1743 l2params->qs_handle_list[i] = params->qos.prio_qos[i].qs_handle;
1744
1745 l2params->mss = (params->mtu) ? params->mtu - I40IW_MTU_TO_MSS : iwdev->vsi.mss;
1746
1747 INIT_WORK(&work->work, i40iw_l2params_worker);
1748 queue_work(iwdev->param_wq, &work->work);
1749}
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759static void i40iw_close(struct i40e_info *ldev, struct i40e_client *client, bool reset)
1760{
1761 struct i40iw_device *iwdev;
1762 struct i40iw_handler *hdl;
1763
1764 hdl = i40iw_find_i40e_handler(ldev);
1765 if (!hdl)
1766 return;
1767
1768 iwdev = &hdl->device;
1769 iwdev->closing = true;
1770
1771 i40iw_cm_disconnect_all(iwdev);
1772 destroy_workqueue(iwdev->virtchnl_wq);
1773 i40iw_deinit_device(iwdev, reset);
1774}
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785static void i40iw_vf_reset(struct i40e_info *ldev, struct i40e_client *client, u32 vf_id)
1786{
1787 struct i40iw_handler *hdl;
1788 struct i40iw_sc_dev *dev;
1789 struct i40iw_hmc_fcn_info hmc_fcn_info;
1790 struct i40iw_virt_mem vf_dev_mem;
1791 struct i40iw_vfdev *tmp_vfdev;
1792 unsigned int i;
1793 unsigned long flags;
1794 struct i40iw_device *iwdev;
1795
1796 hdl = i40iw_find_i40e_handler(ldev);
1797 if (!hdl)
1798 return;
1799
1800 dev = &hdl->device.sc_dev;
1801 iwdev = (struct i40iw_device *)dev->back_dev;
1802
1803 for (i = 0; i < I40IW_MAX_PE_ENABLED_VF_COUNT; i++) {
1804 if (!dev->vf_dev[i] || (dev->vf_dev[i]->vf_id != vf_id))
1805 continue;
1806
1807 tmp_vfdev = dev->vf_dev[i];
1808 spin_lock_irqsave(&iwdev->vsi.pestat->lock, flags);
1809 dev->vf_dev[i] = NULL;
1810 spin_unlock_irqrestore(&iwdev->vsi.pestat->lock, flags);
1811 i40iw_del_hmc_objects(dev, &tmp_vfdev->hmc_info, false, false);
1812
1813 memset(&hmc_fcn_info, 0, sizeof(hmc_fcn_info));
1814 hmc_fcn_info.vf_id = vf_id;
1815 hmc_fcn_info.iw_vf_idx = tmp_vfdev->iw_vf_idx;
1816 hmc_fcn_info.free_fcn = true;
1817 i40iw_cqp_manage_hmc_fcn_cmd(dev, &hmc_fcn_info);
1818
1819 vf_dev_mem.va = tmp_vfdev;
1820 vf_dev_mem.size = sizeof(struct i40iw_vfdev) +
1821 sizeof(struct i40iw_hmc_obj_info) * I40IW_HMC_IW_MAX;
1822 i40iw_free_virt_mem(dev->hw, &vf_dev_mem);
1823 break;
1824 }
1825}
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835static void i40iw_vf_enable(struct i40e_info *ldev,
1836 struct i40e_client *client,
1837 u32 num_vfs)
1838{
1839 struct i40iw_handler *hdl;
1840
1841 hdl = i40iw_find_i40e_handler(ldev);
1842 if (!hdl)
1843 return;
1844
1845 if (num_vfs > I40IW_MAX_PE_ENABLED_VF_COUNT)
1846 hdl->device.max_enabled_vfs = I40IW_MAX_PE_ENABLED_VF_COUNT;
1847 else
1848 hdl->device.max_enabled_vfs = num_vfs;
1849}
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860static int i40iw_vf_capable(struct i40e_info *ldev,
1861 struct i40e_client *client,
1862 u32 vf_id)
1863{
1864 struct i40iw_handler *hdl;
1865 struct i40iw_sc_dev *dev;
1866 unsigned int i;
1867
1868 hdl = i40iw_find_i40e_handler(ldev);
1869 if (!hdl)
1870 return 0;
1871
1872 dev = &hdl->device.sc_dev;
1873
1874 for (i = 0; i < hdl->device.max_enabled_vfs; i++) {
1875 if (!dev->vf_dev[i] || (dev->vf_dev[i]->vf_id == vf_id))
1876 return 1;
1877 }
1878
1879 return 0;
1880}
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893static int i40iw_virtchnl_receive(struct i40e_info *ldev,
1894 struct i40e_client *client,
1895 u32 vf_id,
1896 u8 *msg,
1897 u16 len)
1898{
1899 struct i40iw_handler *hdl;
1900 struct i40iw_sc_dev *dev;
1901 struct i40iw_device *iwdev;
1902 int ret_code = I40IW_NOT_SUPPORTED;
1903
1904 if (!len || !msg)
1905 return I40IW_ERR_PARAM;
1906
1907 hdl = i40iw_find_i40e_handler(ldev);
1908 if (!hdl)
1909 return I40IW_ERR_PARAM;
1910
1911 dev = &hdl->device.sc_dev;
1912 iwdev = dev->back_dev;
1913
1914 if (dev->vchnl_if.vchnl_recv) {
1915 ret_code = dev->vchnl_if.vchnl_recv(dev, vf_id, msg, len);
1916 if (!dev->is_pf) {
1917 atomic_dec(&iwdev->vchnl_msgs);
1918 wake_up(&iwdev->vchnl_waitq);
1919 }
1920 }
1921 return ret_code;
1922}
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933bool i40iw_vf_clear_to_send(struct i40iw_sc_dev *dev)
1934{
1935 struct i40iw_device *iwdev;
1936 wait_queue_t wait;
1937
1938 iwdev = dev->back_dev;
1939
1940 smp_mb();
1941 if (!waitqueue_active(&dev->vf_reqs) &&
1942 (atomic_read(&iwdev->vchnl_msgs) == 0))
1943 return true;
1944
1945 init_wait(&wait);
1946 add_wait_queue_exclusive(&dev->vf_reqs, &wait);
1947
1948 if (!wait_event_timeout(dev->vf_reqs,
1949 (atomic_read(&iwdev->vchnl_msgs) == 0),
1950 I40IW_VCHNL_EVENT_TIMEOUT))
1951 dev->vchnl_up = false;
1952
1953 remove_wait_queue(&dev->vf_reqs, &wait);
1954
1955 return dev->vchnl_up;
1956}
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968static enum i40iw_status_code i40iw_virtchnl_send(struct i40iw_sc_dev *dev,
1969 u32 vf_id,
1970 u8 *msg,
1971 u16 len)
1972{
1973 struct i40iw_device *iwdev;
1974 struct i40e_info *ldev;
1975
1976 if (!dev || !dev->back_dev)
1977 return I40IW_ERR_BAD_PTR;
1978
1979 iwdev = dev->back_dev;
1980 ldev = iwdev->ldev;
1981
1982 if (ldev && ldev->ops && ldev->ops->virtchnl_send)
1983 return ldev->ops->virtchnl_send(ldev, &i40iw_client, vf_id, msg, len);
1984 return I40IW_ERR_BAD_PTR;
1985}
1986
1987
1988static const struct i40e_client_ops i40e_ops = {
1989 .open = i40iw_open,
1990 .close = i40iw_close,
1991 .l2_param_change = i40iw_l2param_change,
1992 .virtchnl_receive = i40iw_virtchnl_receive,
1993 .vf_reset = i40iw_vf_reset,
1994 .vf_enable = i40iw_vf_enable,
1995 .vf_capable = i40iw_vf_capable
1996};
1997
1998
1999
2000
2001
2002
2003
2004static int __init i40iw_init_module(void)
2005{
2006 int ret;
2007
2008 memset(&i40iw_client, 0, sizeof(i40iw_client));
2009 i40iw_client.version.major = CLIENT_IW_INTERFACE_VERSION_MAJOR;
2010 i40iw_client.version.minor = CLIENT_IW_INTERFACE_VERSION_MINOR;
2011 i40iw_client.version.build = CLIENT_IW_INTERFACE_VERSION_BUILD;
2012 i40iw_client.ops = &i40e_ops;
2013 memcpy(i40iw_client.name, i40iw_client_name, I40E_CLIENT_STR_LENGTH);
2014 i40iw_client.type = I40E_CLIENT_IWARP;
2015 spin_lock_init(&i40iw_handler_lock);
2016 ret = i40e_register_client(&i40iw_client);
2017 return ret;
2018}
2019
2020
2021
2022
2023
2024
2025
2026static void __exit i40iw_exit_module(void)
2027{
2028 i40e_unregister_client(&i40iw_client);
2029}
2030
2031module_init(i40iw_init_module);
2032module_exit(i40iw_exit_module);
2033