LXR linux/drivers/infiniband/hw/i40iw/i40iw

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   2*
   3* Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
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   5* This software is available to you under a choice of one of two
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   7* General Public License (GPL) Version 2, available from the file
   8* COPYING in the main directory of this source tree, or the
   9* OpenFabrics.org BSD license below:
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  11*   Redistribution and use in source and binary forms, with or
  12*   without modification, are permitted provided that the following
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  15*    - Redistributions of source code must retain the above
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  33*******************************************************************************/
  34
  35#ifndef I40IW_PBLE_H
  36#define I40IW_PBLE_H
  37
  38#define POOL_SHIFT      6
  39#define PBLE_PER_PAGE   512
  40#define I40IW_HMC_PAGED_BP_SHIFT 12
  41#define PBLE_512_SHIFT  9
  42
  43enum i40iw_pble_level {
  44        I40IW_LEVEL_0 = 0,
  45        I40IW_LEVEL_1 = 1,
  46        I40IW_LEVEL_2 = 2
  47};
  48
  49enum i40iw_alloc_type {
  50        I40IW_NO_ALLOC = 0,
  51        I40IW_DMA_COHERENT = 1,
  52        I40IW_VMALLOC = 2
  53};
  54
  55struct i40iw_pble_info {
  56        unsigned long addr;
  57        u32 idx;
  58        u32 cnt;
  59};
  60
  61struct i40iw_pble_level2 {
  62        struct i40iw_pble_info root;
  63        struct i40iw_pble_info *leaf;
  64        u32 leaf_cnt;
  65};
  66
  67struct i40iw_pble_alloc {
  68        u32 total_cnt;
  69        enum i40iw_pble_level level;
  70        union {
  71                struct i40iw_pble_info level1;
  72                struct i40iw_pble_level2 level2;
  73        };
  74};
  75
  76struct sd_pd_idx {
  77        u32 sd_idx;
  78        u32 pd_idx;
  79        u32 rel_pd_idx;
  80};
  81
  82struct i40iw_add_page_info {
  83        struct i40iw_chunk *chunk;
  84        struct i40iw_hmc_sd_entry *sd_entry;
  85        struct i40iw_hmc_info *hmc_info;
  86        struct sd_pd_idx idx;
  87        u32 pages;
  88};
  89
  90struct i40iw_chunk {
  91        struct list_head list;
  92        u32 size;
  93        void *vaddr;
  94        u64 fpm_addr;
  95        u32 pg_cnt;
  96        dma_addr_t *dmaaddrs;
  97        enum i40iw_alloc_type type;
  98};
  99
 100struct i40iw_pble_pool {
 101        struct gen_pool *pool;
 102        struct list_head clist;
 103        u32 total_pble_alloc;
 104        u32 free_pble_cnt;
 105        u32 pool_shift;
 106};
 107
 108struct i40iw_hmc_pble_rsrc {
 109        u32 unallocated_pble;
 110        u64 fpm_base_addr;
 111        u64 next_fpm_addr;
 112        struct i40iw_pble_pool pinfo;
 113
 114        u32 stats_direct_sds;
 115        u32 stats_paged_sds;
 116        u64 stats_alloc_ok;
 117        u64 stats_alloc_fail;
 118        u64 stats_alloc_freed;
 119        u64 stats_lvl1;
 120        u64 stats_lvl2;
 121};
 122
 123void i40iw_destroy_pble_pool(struct i40iw_sc_dev *dev, struct i40iw_hmc_pble_rsrc *pble_rsrc);
 124enum i40iw_status_code i40iw_hmc_init_pble(struct i40iw_sc_dev *dev,
 125                                           struct i40iw_hmc_pble_rsrc *pble_rsrc);
 126void i40iw_free_pble(struct i40iw_hmc_pble_rsrc *pble_rsrc, struct i40iw_pble_alloc *palloc);
 127enum i40iw_status_code i40iw_get_pble(struct i40iw_sc_dev *dev,
 128                                      struct i40iw_hmc_pble_rsrc *pble_rsrc,
 129                                      struct i40iw_pble_alloc *palloc,
 130                                      u32 pble_cnt);
 131#endif
 132