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11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/slab.h>
14#include <linux/v4l2-mediabus.h>
15#include <linux/videodev2.h>
16#include <linux/module.h>
17
18#include <media/rj54n1cb0c.h>
19#include <media/soc_camera.h>
20#include <media/v4l2-subdev.h>
21#include <media/v4l2-chip-ident.h>
22#include <media/v4l2-ctrls.h>
23
24#define RJ54N1_DEV_CODE 0x0400
25#define RJ54N1_DEV_CODE2 0x0401
26#define RJ54N1_OUT_SEL 0x0403
27#define RJ54N1_XY_OUTPUT_SIZE_S_H 0x0404
28#define RJ54N1_X_OUTPUT_SIZE_S_L 0x0405
29#define RJ54N1_Y_OUTPUT_SIZE_S_L 0x0406
30#define RJ54N1_XY_OUTPUT_SIZE_P_H 0x0407
31#define RJ54N1_X_OUTPUT_SIZE_P_L 0x0408
32#define RJ54N1_Y_OUTPUT_SIZE_P_L 0x0409
33#define RJ54N1_LINE_LENGTH_PCK_S_H 0x040a
34#define RJ54N1_LINE_LENGTH_PCK_S_L 0x040b
35#define RJ54N1_LINE_LENGTH_PCK_P_H 0x040c
36#define RJ54N1_LINE_LENGTH_PCK_P_L 0x040d
37#define RJ54N1_RESIZE_N 0x040e
38#define RJ54N1_RESIZE_N_STEP 0x040f
39#define RJ54N1_RESIZE_STEP 0x0410
40#define RJ54N1_RESIZE_HOLD_H 0x0411
41#define RJ54N1_RESIZE_HOLD_L 0x0412
42#define RJ54N1_H_OBEN_OFS 0x0413
43#define RJ54N1_V_OBEN_OFS 0x0414
44#define RJ54N1_RESIZE_CONTROL 0x0415
45#define RJ54N1_STILL_CONTROL 0x0417
46#define RJ54N1_INC_USE_SEL_H 0x0425
47#define RJ54N1_INC_USE_SEL_L 0x0426
48#define RJ54N1_MIRROR_STILL_MODE 0x0427
49#define RJ54N1_INIT_START 0x0428
50#define RJ54N1_SCALE_1_2_LEV 0x0429
51#define RJ54N1_SCALE_4_LEV 0x042a
52#define RJ54N1_Y_GAIN 0x04d8
53#define RJ54N1_APT_GAIN_UP 0x04fa
54#define RJ54N1_RA_SEL_UL 0x0530
55#define RJ54N1_BYTE_SWAP 0x0531
56#define RJ54N1_OUT_SIGPO 0x053b
57#define RJ54N1_WB_SEL_WEIGHT_I 0x054e
58#define RJ54N1_BIT8_WB 0x0569
59#define RJ54N1_HCAPS_WB 0x056a
60#define RJ54N1_VCAPS_WB 0x056b
61#define RJ54N1_HCAPE_WB 0x056c
62#define RJ54N1_VCAPE_WB 0x056d
63#define RJ54N1_EXPOSURE_CONTROL 0x058c
64#define RJ54N1_FRAME_LENGTH_S_H 0x0595
65#define RJ54N1_FRAME_LENGTH_S_L 0x0596
66#define RJ54N1_FRAME_LENGTH_P_H 0x0597
67#define RJ54N1_FRAME_LENGTH_P_L 0x0598
68#define RJ54N1_PEAK_H 0x05b7
69#define RJ54N1_PEAK_50 0x05b8
70#define RJ54N1_PEAK_60 0x05b9
71#define RJ54N1_PEAK_DIFF 0x05ba
72#define RJ54N1_IOC 0x05ef
73#define RJ54N1_TG_BYPASS 0x0700
74#define RJ54N1_PLL_L 0x0701
75#define RJ54N1_PLL_N 0x0702
76#define RJ54N1_PLL_EN 0x0704
77#define RJ54N1_RATIO_TG 0x0706
78#define RJ54N1_RATIO_T 0x0707
79#define RJ54N1_RATIO_R 0x0708
80#define RJ54N1_RAMP_TGCLK_EN 0x0709
81#define RJ54N1_OCLK_DSP 0x0710
82#define RJ54N1_RATIO_OP 0x0711
83#define RJ54N1_RATIO_O 0x0712
84#define RJ54N1_OCLK_SEL_EN 0x0713
85#define RJ54N1_CLK_RST 0x0717
86#define RJ54N1_RESET_STANDBY 0x0718
87#define RJ54N1_FWFLG 0x07fe
88
89#define E_EXCLK (1 << 7)
90#define SOFT_STDBY (1 << 4)
91#define SEN_RSTX (1 << 2)
92#define TG_RSTX (1 << 1)
93#define DSP_RSTX (1 << 0)
94
95#define RESIZE_HOLD_SEL (1 << 2)
96#define RESIZE_GO (1 << 1)
97
98
99
100
101
102#define RJ54N1_COLUMN_SKIP 0
103#define RJ54N1_ROW_SKIP 0
104#define RJ54N1_MAX_WIDTH 1600
105#define RJ54N1_MAX_HEIGHT 1200
106
107#define PLL_L 2
108#define PLL_N 0x31
109
110
111
112
113struct rj54n1_datafmt {
114 enum v4l2_mbus_pixelcode code;
115 enum v4l2_colorspace colorspace;
116};
117
118
119static const struct rj54n1_datafmt *rj54n1_find_datafmt(
120 enum v4l2_mbus_pixelcode code, const struct rj54n1_datafmt *fmt,
121 int n)
122{
123 int i;
124 for (i = 0; i < n; i++)
125 if (fmt[i].code == code)
126 return fmt + i;
127
128 return NULL;
129}
130
131static const struct rj54n1_datafmt rj54n1_colour_fmts[] = {
132 {V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
133 {V4L2_MBUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
134 {V4L2_MBUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
135 {V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
136 {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
137 {V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE, V4L2_COLORSPACE_SRGB},
138 {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
139 {V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE, V4L2_COLORSPACE_SRGB},
140 {V4L2_MBUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
141};
142
143struct rj54n1_clock_div {
144 u8 ratio_tg;
145 u8 ratio_t;
146 u8 ratio_r;
147 u8 ratio_op;
148 u8 ratio_o;
149};
150
151struct rj54n1 {
152 struct v4l2_subdev subdev;
153 struct v4l2_ctrl_handler hdl;
154 struct rj54n1_clock_div clk_div;
155 const struct rj54n1_datafmt *fmt;
156 struct v4l2_rect rect;
157 unsigned int tgclk_mhz;
158 bool auto_wb;
159 unsigned short width;
160 unsigned short height;
161 unsigned short resize;
162 unsigned short scale;
163 u8 bank;
164};
165
166struct rj54n1_reg_val {
167 u16 reg;
168 u8 val;
169};
170
171static const struct rj54n1_reg_val bank_4[] = {
172 {0x417, 0},
173 {0x42c, 0},
174 {0x42d, 0xf0},
175 {0x42e, 0},
176 {0x42f, 0x50},
177 {0x430, 0xf5},
178 {0x431, 0x16},
179 {0x432, 0x20},
180 {0x433, 0},
181 {0x434, 0xc8},
182 {0x43c, 8},
183 {0x43e, 0x90},
184 {0x445, 0x83},
185 {0x4ba, 0x58},
186 {0x4bb, 4},
187 {0x4bc, 0x20},
188 {0x4db, 4},
189 {0x4fe, 2},
190};
191
192static const struct rj54n1_reg_val bank_5[] = {
193 {0x514, 0},
194 {0x516, 0},
195 {0x518, 0},
196 {0x51a, 0},
197 {0x51d, 0xff},
198 {0x56f, 0x28},
199 {0x575, 0x40},
200 {0x5bc, 0x48},
201 {0x5c1, 6},
202 {0x5e5, 0x11},
203 {0x5e6, 0x43},
204 {0x5e7, 0x33},
205 {0x5e8, 0x21},
206 {0x5e9, 0x30},
207 {0x5ea, 0x0},
208 {0x5eb, 0xa5},
209 {0x5ec, 0xff},
210 {0x5fe, 2},
211};
212
213static const struct rj54n1_reg_val bank_7[] = {
214 {0x70a, 0},
215 {0x714, 0xff},
216 {0x715, 0xff},
217 {0x716, 0x1f},
218 {0x7FE, 2},
219};
220
221static const struct rj54n1_reg_val bank_8[] = {
222 {0x800, 0x00},
223 {0x801, 0x01},
224 {0x802, 0x61},
225 {0x805, 0x00},
226 {0x806, 0x00},
227 {0x807, 0x00},
228 {0x808, 0x00},
229 {0x809, 0x01},
230 {0x80A, 0x61},
231 {0x80B, 0x00},
232 {0x80C, 0x01},
233 {0x80D, 0x00},
234 {0x80E, 0x00},
235 {0x80F, 0x00},
236 {0x810, 0x00},
237 {0x811, 0x01},
238 {0x812, 0x61},
239 {0x813, 0x00},
240 {0x814, 0x11},
241 {0x815, 0x00},
242 {0x816, 0x41},
243 {0x817, 0x00},
244 {0x818, 0x51},
245 {0x819, 0x01},
246 {0x81A, 0x1F},
247 {0x81B, 0x00},
248 {0x81C, 0x01},
249 {0x81D, 0x00},
250 {0x81E, 0x11},
251 {0x81F, 0x00},
252 {0x820, 0x41},
253 {0x821, 0x00},
254 {0x822, 0x51},
255 {0x823, 0x00},
256 {0x824, 0x00},
257 {0x825, 0x00},
258 {0x826, 0x47},
259 {0x827, 0x01},
260 {0x828, 0x4F},
261 {0x829, 0x00},
262 {0x82A, 0x00},
263 {0x82B, 0x00},
264 {0x82C, 0x30},
265 {0x82D, 0x00},
266 {0x82E, 0x40},
267 {0x82F, 0x00},
268 {0x830, 0xB3},
269 {0x831, 0x00},
270 {0x832, 0xE3},
271 {0x833, 0x00},
272 {0x834, 0x00},
273 {0x835, 0x00},
274 {0x836, 0x00},
275 {0x837, 0x00},
276 {0x838, 0x00},
277 {0x839, 0x01},
278 {0x83A, 0x61},
279 {0x83B, 0x00},
280 {0x83C, 0x01},
281 {0x83D, 0x00},
282 {0x83E, 0x00},
283 {0x83F, 0x00},
284 {0x840, 0x00},
285 {0x841, 0x01},
286 {0x842, 0x61},
287 {0x843, 0x00},
288 {0x844, 0x1D},
289 {0x845, 0x00},
290 {0x846, 0x00},
291 {0x847, 0x00},
292 {0x848, 0x00},
293 {0x849, 0x01},
294 {0x84A, 0x1F},
295 {0x84B, 0x00},
296 {0x84C, 0x05},
297 {0x84D, 0x00},
298 {0x84E, 0x19},
299 {0x84F, 0x01},
300 {0x850, 0x21},
301 {0x851, 0x01},
302 {0x852, 0x5D},
303 {0x853, 0x00},
304 {0x854, 0x00},
305 {0x855, 0x00},
306 {0x856, 0x19},
307 {0x857, 0x01},
308 {0x858, 0x21},
309 {0x859, 0x00},
310 {0x85A, 0x00},
311 {0x85B, 0x00},
312 {0x85C, 0x00},
313 {0x85D, 0x00},
314 {0x85E, 0x00},
315 {0x85F, 0x00},
316 {0x860, 0xB3},
317 {0x861, 0x00},
318 {0x862, 0xE3},
319 {0x863, 0x00},
320 {0x864, 0x00},
321 {0x865, 0x00},
322 {0x866, 0x00},
323 {0x867, 0x00},
324 {0x868, 0x00},
325 {0x869, 0xE2},
326 {0x86A, 0x00},
327 {0x86B, 0x01},
328 {0x86C, 0x06},
329 {0x86D, 0x00},
330 {0x86E, 0x00},
331 {0x86F, 0x00},
332 {0x870, 0x60},
333 {0x871, 0x8C},
334 {0x872, 0x10},
335 {0x873, 0x00},
336 {0x874, 0xE0},
337 {0x875, 0x00},
338 {0x876, 0x27},
339 {0x877, 0x01},
340 {0x878, 0x00},
341 {0x879, 0x00},
342 {0x87A, 0x00},
343 {0x87B, 0x03},
344 {0x87C, 0x00},
345 {0x87D, 0x00},
346 {0x87E, 0x00},
347 {0x87F, 0x00},
348 {0x880, 0x00},
349 {0x881, 0x00},
350 {0x882, 0x00},
351 {0x883, 0x00},
352 {0x884, 0x00},
353 {0x885, 0x00},
354 {0x886, 0xF8},
355 {0x887, 0x00},
356 {0x888, 0x03},
357 {0x889, 0x00},
358 {0x88A, 0x64},
359 {0x88B, 0x00},
360 {0x88C, 0x03},
361 {0x88D, 0x00},
362 {0x88E, 0xB1},
363 {0x88F, 0x00},
364 {0x890, 0x03},
365 {0x891, 0x01},
366 {0x892, 0x1D},
367 {0x893, 0x00},
368 {0x894, 0x03},
369 {0x895, 0x01},
370 {0x896, 0x4B},
371 {0x897, 0x00},
372 {0x898, 0xE5},
373 {0x899, 0x00},
374 {0x89A, 0x01},
375 {0x89B, 0x00},
376 {0x89C, 0x01},
377 {0x89D, 0x04},
378 {0x89E, 0xC8},
379 {0x89F, 0x00},
380 {0x8A0, 0x01},
381 {0x8A1, 0x01},
382 {0x8A2, 0x61},
383 {0x8A3, 0x00},
384 {0x8A4, 0x01},
385 {0x8A5, 0x00},
386 {0x8A6, 0x00},
387 {0x8A7, 0x00},
388 {0x8A8, 0x00},
389 {0x8A9, 0x00},
390 {0x8AA, 0x7F},
391 {0x8AB, 0x03},
392 {0x8AC, 0x00},
393 {0x8AD, 0x00},
394 {0x8AE, 0x00},
395 {0x8AF, 0x00},
396 {0x8B0, 0x00},
397 {0x8B1, 0x00},
398 {0x8B6, 0x00},
399 {0x8B7, 0x01},
400 {0x8B8, 0x00},
401 {0x8B9, 0x00},
402 {0x8BA, 0x02},
403 {0x8BB, 0x00},
404 {0x8BC, 0xFF},
405 {0x8BD, 0x00},
406 {0x8FE, 2},
407};
408
409static const struct rj54n1_reg_val bank_10[] = {
410 {0x10bf, 0x69}
411};
412
413
414static const struct rj54n1_clock_div clk_div = {
415 .ratio_tg = 3 ,
416 .ratio_t = 4 ,
417 .ratio_r = 4 ,
418 .ratio_op = 1 ,
419 .ratio_o = 9 ,
420};
421
422static struct rj54n1 *to_rj54n1(const struct i2c_client *client)
423{
424 return container_of(i2c_get_clientdata(client), struct rj54n1, subdev);
425}
426
427static int reg_read(struct i2c_client *client, const u16 reg)
428{
429 struct rj54n1 *rj54n1 = to_rj54n1(client);
430 int ret;
431
432
433 if (rj54n1->bank != reg >> 8) {
434 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
435 ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
436 if (ret < 0)
437 return ret;
438 rj54n1->bank = reg >> 8;
439 }
440 return i2c_smbus_read_byte_data(client, reg & 0xff);
441}
442
443static int reg_write(struct i2c_client *client, const u16 reg,
444 const u8 data)
445{
446 struct rj54n1 *rj54n1 = to_rj54n1(client);
447 int ret;
448
449
450 if (rj54n1->bank != reg >> 8) {
451 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
452 ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
453 if (ret < 0)
454 return ret;
455 rj54n1->bank = reg >> 8;
456 }
457 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", reg & 0xff, data);
458 return i2c_smbus_write_byte_data(client, reg & 0xff, data);
459}
460
461static int reg_set(struct i2c_client *client, const u16 reg,
462 const u8 data, const u8 mask)
463{
464 int ret;
465
466 ret = reg_read(client, reg);
467 if (ret < 0)
468 return ret;
469 return reg_write(client, reg, (ret & ~mask) | (data & mask));
470}
471
472static int reg_write_multiple(struct i2c_client *client,
473 const struct rj54n1_reg_val *rv, const int n)
474{
475 int i, ret;
476
477 for (i = 0; i < n; i++) {
478 ret = reg_write(client, rv->reg, rv->val);
479 if (ret < 0)
480 return ret;
481 rv++;
482 }
483
484 return 0;
485}
486
487static int rj54n1_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
488 enum v4l2_mbus_pixelcode *code)
489{
490 if (index >= ARRAY_SIZE(rj54n1_colour_fmts))
491 return -EINVAL;
492
493 *code = rj54n1_colour_fmts[index].code;
494 return 0;
495}
496
497static int rj54n1_s_stream(struct v4l2_subdev *sd, int enable)
498{
499 struct i2c_client *client = v4l2_get_subdevdata(sd);
500
501
502 return reg_set(client, RJ54N1_STILL_CONTROL, (!enable) << 7, 0x80);
503}
504
505static int rj54n1_set_rect(struct i2c_client *client,
506 u16 reg_x, u16 reg_y, u16 reg_xy,
507 u32 width, u32 height)
508{
509 int ret;
510
511 ret = reg_write(client, reg_xy,
512 ((width >> 4) & 0x70) |
513 ((height >> 8) & 7));
514
515 if (!ret)
516 ret = reg_write(client, reg_x, width & 0xff);
517 if (!ret)
518 ret = reg_write(client, reg_y, height & 0xff);
519
520 return ret;
521}
522
523
524
525
526
527static int rj54n1_commit(struct i2c_client *client)
528{
529 int ret = reg_write(client, RJ54N1_INIT_START, 1);
530 msleep(10);
531 if (!ret)
532 ret = reg_write(client, RJ54N1_INIT_START, 0);
533 return ret;
534}
535
536static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
537 s32 *out_w, s32 *out_h);
538
539static int rj54n1_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
540{
541 struct i2c_client *client = v4l2_get_subdevdata(sd);
542 struct rj54n1 *rj54n1 = to_rj54n1(client);
543 const struct v4l2_rect *rect = &a->c;
544 int dummy = 0, output_w, output_h,
545 input_w = rect->width, input_h = rect->height;
546 int ret;
547
548
549 soc_camera_limit_side(&dummy, &input_w,
550 RJ54N1_COLUMN_SKIP, 8, RJ54N1_MAX_WIDTH);
551
552 soc_camera_limit_side(&dummy, &input_h,
553 RJ54N1_ROW_SKIP, 8, RJ54N1_MAX_HEIGHT);
554
555 output_w = (input_w * 1024 + rj54n1->resize / 2) / rj54n1->resize;
556 output_h = (input_h * 1024 + rj54n1->resize / 2) / rj54n1->resize;
557
558 dev_dbg(&client->dev, "Scaling for %dx%d : %u = %dx%d\n",
559 input_w, input_h, rj54n1->resize, output_w, output_h);
560
561 ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
562 if (ret < 0)
563 return ret;
564
565 rj54n1->width = output_w;
566 rj54n1->height = output_h;
567 rj54n1->resize = ret;
568 rj54n1->rect.width = input_w;
569 rj54n1->rect.height = input_h;
570
571 return 0;
572}
573
574static int rj54n1_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
575{
576 struct i2c_client *client = v4l2_get_subdevdata(sd);
577 struct rj54n1 *rj54n1 = to_rj54n1(client);
578
579 a->c = rj54n1->rect;
580 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
581
582 return 0;
583}
584
585static int rj54n1_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
586{
587 a->bounds.left = RJ54N1_COLUMN_SKIP;
588 a->bounds.top = RJ54N1_ROW_SKIP;
589 a->bounds.width = RJ54N1_MAX_WIDTH;
590 a->bounds.height = RJ54N1_MAX_HEIGHT;
591 a->defrect = a->bounds;
592 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
593 a->pixelaspect.numerator = 1;
594 a->pixelaspect.denominator = 1;
595
596 return 0;
597}
598
599static int rj54n1_g_fmt(struct v4l2_subdev *sd,
600 struct v4l2_mbus_framefmt *mf)
601{
602 struct i2c_client *client = v4l2_get_subdevdata(sd);
603 struct rj54n1 *rj54n1 = to_rj54n1(client);
604
605 mf->code = rj54n1->fmt->code;
606 mf->colorspace = rj54n1->fmt->colorspace;
607 mf->field = V4L2_FIELD_NONE;
608 mf->width = rj54n1->width;
609 mf->height = rj54n1->height;
610
611 return 0;
612}
613
614
615
616
617
618
619static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
620 s32 *out_w, s32 *out_h)
621{
622 struct i2c_client *client = v4l2_get_subdevdata(sd);
623 struct rj54n1 *rj54n1 = to_rj54n1(client);
624 unsigned int skip, resize, input_w = *in_w, input_h = *in_h,
625 output_w = *out_w, output_h = *out_h;
626 u16 inc_sel, wb_bit8, wb_left, wb_right, wb_top, wb_bottom;
627 unsigned int peak, peak_50, peak_60;
628 int ret;
629
630
631
632
633
634
635
636 if (output_w > max(512U, input_w / 2)) {
637 if (2 * output_w > RJ54N1_MAX_WIDTH) {
638 input_w = RJ54N1_MAX_WIDTH;
639 output_w = RJ54N1_MAX_WIDTH / 2;
640 } else {
641 input_w = output_w * 2;
642 }
643
644 dev_dbg(&client->dev, "Adjusted output width: in %u, out %u\n",
645 input_w, output_w);
646 }
647
648 if (output_h > max(384U, input_h / 2)) {
649 if (2 * output_h > RJ54N1_MAX_HEIGHT) {
650 input_h = RJ54N1_MAX_HEIGHT;
651 output_h = RJ54N1_MAX_HEIGHT / 2;
652 } else {
653 input_h = output_h * 2;
654 }
655
656 dev_dbg(&client->dev, "Adjusted output height: in %u, out %u\n",
657 input_h, output_h);
658 }
659
660
661 ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_S_L,
662 RJ54N1_Y_OUTPUT_SIZE_S_L,
663 RJ54N1_XY_OUTPUT_SIZE_S_H, output_w, output_h);
664 if (!ret)
665 ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_P_L,
666 RJ54N1_Y_OUTPUT_SIZE_P_L,
667 RJ54N1_XY_OUTPUT_SIZE_P_H, output_w, output_h);
668
669 if (ret < 0)
670 return ret;
671
672 if (output_w > input_w && output_h > input_h) {
673 input_w = output_w;
674 input_h = output_h;
675
676 resize = 1024;
677 } else {
678 unsigned int resize_x, resize_y;
679 resize_x = (input_w * 1024 + output_w / 2) / output_w;
680 resize_y = (input_h * 1024 + output_h / 2) / output_h;
681
682
683 if (resize_x > resize_y &&
684 (output_h * resize_x + 512) / 1024 > RJ54N1_MAX_HEIGHT)
685 resize = (RJ54N1_MAX_HEIGHT * 1024 + output_h / 2) /
686 output_h;
687 else if (resize_y > resize_x &&
688 (output_w * resize_y + 512) / 1024 > RJ54N1_MAX_WIDTH)
689 resize = (RJ54N1_MAX_WIDTH * 1024 + output_w / 2) /
690 output_w;
691 else
692 resize = max(resize_x, resize_y);
693
694
695 switch (resize) {
696 case 2040 ... 2047:
697 resize = 2039;
698 break;
699 case 4080 ... 4095:
700 resize = 4079;
701 break;
702 case 8160 ... 8191:
703 resize = 8159;
704 break;
705 case 16320 ... 16384:
706 resize = 16319;
707 }
708 }
709
710
711 ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff);
712 if (!ret)
713 ret = reg_write(client, RJ54N1_RESIZE_HOLD_H, resize >> 8);
714
715 if (ret < 0)
716 return ret;
717
718
719
720
721
722
723
724
725
726
727
728
729
730 skip = min(resize / 1024, 15U);
731
732 inc_sel = 1 << skip;
733
734 if (inc_sel <= 2)
735 inc_sel = 0xc;
736 else if (resize & 1023 && skip < 15)
737 inc_sel |= 1 << (skip + 1);
738
739 ret = reg_write(client, RJ54N1_INC_USE_SEL_L, inc_sel & 0xfc);
740 if (!ret)
741 ret = reg_write(client, RJ54N1_INC_USE_SEL_H, inc_sel >> 8);
742
743 if (!rj54n1->auto_wb) {
744
745 wb_left = output_w / 16;
746 wb_right = (3 * output_w / 4 - 3) / 4;
747 wb_top = output_h / 16;
748 wb_bottom = (3 * output_h / 4 - 3) / 4;
749 wb_bit8 = ((wb_left >> 2) & 0x40) | ((wb_top >> 4) & 0x10) |
750 ((wb_right >> 6) & 4) | ((wb_bottom >> 8) & 1);
751
752 if (!ret)
753 ret = reg_write(client, RJ54N1_BIT8_WB, wb_bit8);
754 if (!ret)
755 ret = reg_write(client, RJ54N1_HCAPS_WB, wb_left);
756 if (!ret)
757 ret = reg_write(client, RJ54N1_VCAPS_WB, wb_top);
758 if (!ret)
759 ret = reg_write(client, RJ54N1_HCAPE_WB, wb_right);
760 if (!ret)
761 ret = reg_write(client, RJ54N1_VCAPE_WB, wb_bottom);
762 }
763
764
765 peak = 12 * RJ54N1_MAX_WIDTH * (1 << 14) * resize / rj54n1->tgclk_mhz /
766 10000;
767 peak_50 = peak / 6;
768 peak_60 = peak / 5;
769
770 if (!ret)
771 ret = reg_write(client, RJ54N1_PEAK_H,
772 ((peak_50 >> 4) & 0xf0) | (peak_60 >> 8));
773 if (!ret)
774 ret = reg_write(client, RJ54N1_PEAK_50, peak_50);
775 if (!ret)
776 ret = reg_write(client, RJ54N1_PEAK_60, peak_60);
777 if (!ret)
778 ret = reg_write(client, RJ54N1_PEAK_DIFF, peak / 150);
779
780
781 if (!ret)
782 ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
783 RESIZE_HOLD_SEL | RESIZE_GO | 1);
784
785 if (ret < 0)
786 return ret;
787
788
789 msleep(230);
790
791 ret = reg_write(client, RJ54N1_RESIZE_CONTROL, RESIZE_HOLD_SEL | 1);
792 if (ret < 0)
793 return ret;
794
795 *in_w = (output_w * resize + 512) / 1024;
796 *in_h = (output_h * resize + 512) / 1024;
797 *out_w = output_w;
798 *out_h = output_h;
799
800 dev_dbg(&client->dev, "Scaled for %dx%d : %u = %ux%u, skip %u\n",
801 *in_w, *in_h, resize, output_w, output_h, skip);
802
803 return resize;
804}
805
806static int rj54n1_set_clock(struct i2c_client *client)
807{
808 struct rj54n1 *rj54n1 = to_rj54n1(client);
809 int ret;
810
811
812 ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK | SOFT_STDBY);
813
814 if (!ret)
815 ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK);
816
817 if (!ret)
818 ret = reg_write(client, RJ54N1_PLL_L, PLL_L);
819 if (!ret)
820 ret = reg_write(client, RJ54N1_PLL_N, PLL_N);
821
822
823 if (!ret)
824 ret = reg_write(client, RJ54N1_RATIO_TG,
825 rj54n1->clk_div.ratio_tg);
826 if (!ret)
827 ret = reg_write(client, RJ54N1_RATIO_T,
828 rj54n1->clk_div.ratio_t);
829 if (!ret)
830 ret = reg_write(client, RJ54N1_RATIO_R,
831 rj54n1->clk_div.ratio_r);
832
833
834 if (!ret)
835 ret = reg_write(client, RJ54N1_RAMP_TGCLK_EN, 3);
836
837
838 if (!ret)
839 ret = reg_write(client, RJ54N1_OCLK_DSP, 0);
840
841
842 if (!ret)
843 ret = reg_write(client, RJ54N1_RATIO_OP,
844 rj54n1->clk_div.ratio_op);
845 if (!ret)
846 ret = reg_write(client, RJ54N1_RATIO_O,
847 rj54n1->clk_div.ratio_o);
848
849
850 if (!ret)
851 ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
852
853
854 if (!ret)
855 ret = reg_write(client, RJ54N1_TG_BYPASS, 2);
856
857
858 if (!ret)
859 ret = reg_write(client, RJ54N1_RESET_STANDBY,
860 E_EXCLK | SEN_RSTX);
861
862 if (!ret)
863 ret = reg_write(client, RJ54N1_PLL_EN, 1);
864
865
866 msleep(10);
867
868
869 if (!ret)
870 ret = reg_write(client, RJ54N1_CLK_RST, 1);
871
872 if (!ret)
873 ret = reg_read(client, RJ54N1_CLK_RST);
874 if (ret != 1) {
875 dev_err(&client->dev,
876 "Resetting RJ54N1CB0C clock failed: %d!\n", ret);
877 return -EIO;
878 }
879
880
881 ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1);
882
883
884 if (!ret)
885 ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
886
887 return ret;
888}
889
890static int rj54n1_reg_init(struct i2c_client *client)
891{
892 struct rj54n1 *rj54n1 = to_rj54n1(client);
893 int ret = rj54n1_set_clock(client);
894
895 if (!ret)
896 ret = reg_write_multiple(client, bank_7, ARRAY_SIZE(bank_7));
897 if (!ret)
898 ret = reg_write_multiple(client, bank_10, ARRAY_SIZE(bank_10));
899
900
901 if (!ret)
902 ret = reg_write(client, RJ54N1_SCALE_1_2_LEV, 3 | (7 << 4));
903 if (!ret)
904 ret = reg_write(client, RJ54N1_SCALE_4_LEV, 0xf);
905
906
907 if (!ret)
908 ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
909 RESIZE_HOLD_SEL | 1);
910
911
912 if (!ret)
913 ret = reg_write(client, RJ54N1_Y_GAIN, 0x84);
914
915
916
917
918
919 if (!ret)
920 ret = reg_write(client, RJ54N1_MIRROR_STILL_MODE, 0x27);
921
922 if (!ret)
923 ret = reg_write_multiple(client, bank_4, ARRAY_SIZE(bank_4));
924
925
926 if (!ret)
927 ret = reg_write(client, RJ54N1_EXPOSURE_CONTROL, 0x80);
928
929 if (!ret)
930 ret = reg_read(client, RJ54N1_WB_SEL_WEIGHT_I);
931 if (ret >= 0) {
932 rj54n1->auto_wb = ret & 0x80;
933 ret = reg_write_multiple(client, bank_5, ARRAY_SIZE(bank_5));
934 }
935 if (!ret)
936 ret = reg_write_multiple(client, bank_8, ARRAY_SIZE(bank_8));
937
938 if (!ret)
939 ret = reg_write(client, RJ54N1_RESET_STANDBY,
940 E_EXCLK | DSP_RSTX | SEN_RSTX);
941
942
943 if (!ret)
944 ret = rj54n1_commit(client);
945
946
947 if (!ret)
948 ret = reg_write(client, RJ54N1_RESET_STANDBY,
949 E_EXCLK | DSP_RSTX | TG_RSTX | SEN_RSTX);
950
951
952 if (!ret)
953 ret = reg_write(client, RJ54N1_FWFLG, 2);
954
955
956 msleep(700);
957
958 return ret;
959}
960
961static int rj54n1_try_fmt(struct v4l2_subdev *sd,
962 struct v4l2_mbus_framefmt *mf)
963{
964 struct i2c_client *client = v4l2_get_subdevdata(sd);
965 struct rj54n1 *rj54n1 = to_rj54n1(client);
966 const struct rj54n1_datafmt *fmt;
967 int align = mf->code == V4L2_MBUS_FMT_SBGGR10_1X10 ||
968 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE ||
969 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE ||
970 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE ||
971 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE;
972
973 dev_dbg(&client->dev, "%s: code = %d, width = %u, height = %u\n",
974 __func__, mf->code, mf->width, mf->height);
975
976 fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
977 ARRAY_SIZE(rj54n1_colour_fmts));
978 if (!fmt) {
979 fmt = rj54n1->fmt;
980 mf->code = fmt->code;
981 }
982
983 mf->field = V4L2_FIELD_NONE;
984 mf->colorspace = fmt->colorspace;
985
986 v4l_bound_align_image(&mf->width, 112, RJ54N1_MAX_WIDTH, align,
987 &mf->height, 84, RJ54N1_MAX_HEIGHT, align, 0);
988
989 return 0;
990}
991
992static int rj54n1_s_fmt(struct v4l2_subdev *sd,
993 struct v4l2_mbus_framefmt *mf)
994{
995 struct i2c_client *client = v4l2_get_subdevdata(sd);
996 struct rj54n1 *rj54n1 = to_rj54n1(client);
997 const struct rj54n1_datafmt *fmt;
998 int output_w, output_h, max_w, max_h,
999 input_w = rj54n1->rect.width, input_h = rj54n1->rect.height;
1000 int ret;
1001
1002
1003
1004
1005
1006 rj54n1_try_fmt(sd, mf);
1007
1008
1009
1010
1011
1012 ret = reg_read(client, RJ54N1_RESET_STANDBY);
1013 if (ret < 0)
1014 return ret;
1015
1016 if (!(ret & E_EXCLK)) {
1017 ret = rj54n1_reg_init(client);
1018 if (ret < 0)
1019 return ret;
1020 }
1021
1022 dev_dbg(&client->dev, "%s: code = %d, width = %u, height = %u\n",
1023 __func__, mf->code, mf->width, mf->height);
1024
1025
1026 switch (mf->code) {
1027 case V4L2_MBUS_FMT_YUYV8_2X8:
1028 ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1029 if (!ret)
1030 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1031 break;
1032 case V4L2_MBUS_FMT_YVYU8_2X8:
1033 ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1034 if (!ret)
1035 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1036 break;
1037 case V4L2_MBUS_FMT_RGB565_2X8_LE:
1038 ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1039 if (!ret)
1040 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1041 break;
1042 case V4L2_MBUS_FMT_RGB565_2X8_BE:
1043 ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1044 if (!ret)
1045 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1046 break;
1047 case V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE:
1048 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1049 if (!ret)
1050 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1051 if (!ret)
1052 ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1053 break;
1054 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE:
1055 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1056 if (!ret)
1057 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1058 if (!ret)
1059 ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1060 break;
1061 case V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE:
1062 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1063 if (!ret)
1064 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1065 if (!ret)
1066 ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1067 break;
1068 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE:
1069 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1070 if (!ret)
1071 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1072 if (!ret)
1073 ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1074 break;
1075 case V4L2_MBUS_FMT_SBGGR10_1X10:
1076 ret = reg_write(client, RJ54N1_OUT_SEL, 5);
1077 break;
1078 default:
1079 ret = -EINVAL;
1080 }
1081
1082
1083 if (!ret)
1084 ret = reg_set(client, RJ54N1_OCLK_SEL_EN,
1085 (mf->code == V4L2_MBUS_FMT_SBGGR10_1X10) << 1, 2);
1086
1087 if (ret < 0)
1088 return ret;
1089
1090
1091 max_w = mf->width * (16 * 1024 - 1) / 1024;
1092 if (input_w > max_w)
1093 input_w = max_w;
1094 max_h = mf->height * (16 * 1024 - 1) / 1024;
1095 if (input_h > max_h)
1096 input_h = max_h;
1097
1098 output_w = mf->width;
1099 output_h = mf->height;
1100
1101 ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
1102 if (ret < 0)
1103 return ret;
1104
1105 fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
1106 ARRAY_SIZE(rj54n1_colour_fmts));
1107
1108 rj54n1->fmt = fmt;
1109 rj54n1->resize = ret;
1110 rj54n1->rect.width = input_w;
1111 rj54n1->rect.height = input_h;
1112 rj54n1->width = output_w;
1113 rj54n1->height = output_h;
1114
1115 mf->width = output_w;
1116 mf->height = output_h;
1117 mf->field = V4L2_FIELD_NONE;
1118 mf->colorspace = fmt->colorspace;
1119
1120 return 0;
1121}
1122
1123static int rj54n1_g_chip_ident(struct v4l2_subdev *sd,
1124 struct v4l2_dbg_chip_ident *id)
1125{
1126 struct i2c_client *client = v4l2_get_subdevdata(sd);
1127
1128 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
1129 return -EINVAL;
1130
1131 if (id->match.addr != client->addr)
1132 return -ENODEV;
1133
1134 id->ident = V4L2_IDENT_RJ54N1CB0C;
1135 id->revision = 0;
1136
1137 return 0;
1138}
1139
1140#ifdef CONFIG_VIDEO_ADV_DEBUG
1141static int rj54n1_g_register(struct v4l2_subdev *sd,
1142 struct v4l2_dbg_register *reg)
1143{
1144 struct i2c_client *client = v4l2_get_subdevdata(sd);
1145
1146 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR ||
1147 reg->reg < 0x400 || reg->reg > 0x1fff)
1148
1149 return -EINVAL;
1150
1151 if (reg->match.addr != client->addr)
1152 return -ENODEV;
1153
1154 reg->size = 1;
1155 reg->val = reg_read(client, reg->reg);
1156
1157 if (reg->val > 0xff)
1158 return -EIO;
1159
1160 return 0;
1161}
1162
1163static int rj54n1_s_register(struct v4l2_subdev *sd,
1164 const struct v4l2_dbg_register *reg)
1165{
1166 struct i2c_client *client = v4l2_get_subdevdata(sd);
1167
1168 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR ||
1169 reg->reg < 0x400 || reg->reg > 0x1fff)
1170
1171 return -EINVAL;
1172
1173 if (reg->match.addr != client->addr)
1174 return -ENODEV;
1175
1176 if (reg_write(client, reg->reg, reg->val) < 0)
1177 return -EIO;
1178
1179 return 0;
1180}
1181#endif
1182
1183static int rj54n1_s_power(struct v4l2_subdev *sd, int on)
1184{
1185 struct i2c_client *client = v4l2_get_subdevdata(sd);
1186 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1187
1188 return soc_camera_set_power(&client->dev, ssdd, on);
1189}
1190
1191static int rj54n1_s_ctrl(struct v4l2_ctrl *ctrl)
1192{
1193 struct rj54n1 *rj54n1 = container_of(ctrl->handler, struct rj54n1, hdl);
1194 struct v4l2_subdev *sd = &rj54n1->subdev;
1195 struct i2c_client *client = v4l2_get_subdevdata(sd);
1196 int data;
1197
1198 switch (ctrl->id) {
1199 case V4L2_CID_VFLIP:
1200 if (ctrl->val)
1201 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 1);
1202 else
1203 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 1, 1);
1204 if (data < 0)
1205 return -EIO;
1206 return 0;
1207 case V4L2_CID_HFLIP:
1208 if (ctrl->val)
1209 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 2);
1210 else
1211 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 2, 2);
1212 if (data < 0)
1213 return -EIO;
1214 return 0;
1215 case V4L2_CID_GAIN:
1216 if (reg_write(client, RJ54N1_Y_GAIN, ctrl->val * 2) < 0)
1217 return -EIO;
1218 return 0;
1219 case V4L2_CID_AUTO_WHITE_BALANCE:
1220
1221 if (reg_set(client, RJ54N1_WB_SEL_WEIGHT_I, ctrl->val << 7,
1222 0x80) < 0)
1223 return -EIO;
1224 rj54n1->auto_wb = ctrl->val;
1225 return 0;
1226 }
1227
1228 return -EINVAL;
1229}
1230
1231static const struct v4l2_ctrl_ops rj54n1_ctrl_ops = {
1232 .s_ctrl = rj54n1_s_ctrl,
1233};
1234
1235static struct v4l2_subdev_core_ops rj54n1_subdev_core_ops = {
1236 .g_chip_ident = rj54n1_g_chip_ident,
1237#ifdef CONFIG_VIDEO_ADV_DEBUG
1238 .g_register = rj54n1_g_register,
1239 .s_register = rj54n1_s_register,
1240#endif
1241 .s_power = rj54n1_s_power,
1242};
1243
1244static int rj54n1_g_mbus_config(struct v4l2_subdev *sd,
1245 struct v4l2_mbus_config *cfg)
1246{
1247 struct i2c_client *client = v4l2_get_subdevdata(sd);
1248 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1249
1250 cfg->flags =
1251 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
1252 V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH |
1253 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1254 cfg->type = V4L2_MBUS_PARALLEL;
1255 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
1256
1257 return 0;
1258}
1259
1260static int rj54n1_s_mbus_config(struct v4l2_subdev *sd,
1261 const struct v4l2_mbus_config *cfg)
1262{
1263 struct i2c_client *client = v4l2_get_subdevdata(sd);
1264 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1265
1266
1267 if (soc_camera_apply_board_flags(ssdd, cfg) &
1268 V4L2_MBUS_PCLK_SAMPLE_RISING)
1269 return reg_write(client, RJ54N1_OUT_SIGPO, 1 << 4);
1270 else
1271 return reg_write(client, RJ54N1_OUT_SIGPO, 0);
1272}
1273
1274static struct v4l2_subdev_video_ops rj54n1_subdev_video_ops = {
1275 .s_stream = rj54n1_s_stream,
1276 .s_mbus_fmt = rj54n1_s_fmt,
1277 .g_mbus_fmt = rj54n1_g_fmt,
1278 .try_mbus_fmt = rj54n1_try_fmt,
1279 .enum_mbus_fmt = rj54n1_enum_fmt,
1280 .g_crop = rj54n1_g_crop,
1281 .s_crop = rj54n1_s_crop,
1282 .cropcap = rj54n1_cropcap,
1283 .g_mbus_config = rj54n1_g_mbus_config,
1284 .s_mbus_config = rj54n1_s_mbus_config,
1285};
1286
1287static struct v4l2_subdev_ops rj54n1_subdev_ops = {
1288 .core = &rj54n1_subdev_core_ops,
1289 .video = &rj54n1_subdev_video_ops,
1290};
1291
1292
1293
1294
1295
1296static int rj54n1_video_probe(struct i2c_client *client,
1297 struct rj54n1_pdata *priv)
1298{
1299 struct rj54n1 *rj54n1 = to_rj54n1(client);
1300 int data1, data2;
1301 int ret;
1302
1303 ret = rj54n1_s_power(&rj54n1->subdev, 1);
1304 if (ret < 0)
1305 return ret;
1306
1307
1308 data1 = reg_read(client, RJ54N1_DEV_CODE);
1309 data2 = reg_read(client, RJ54N1_DEV_CODE2);
1310
1311 if (data1 != 0x51 || data2 != 0x10) {
1312 ret = -ENODEV;
1313 dev_info(&client->dev, "No RJ54N1CB0C found, read 0x%x:0x%x\n",
1314 data1, data2);
1315 goto done;
1316 }
1317
1318
1319 ret = reg_write(client, RJ54N1_IOC, priv->ioctl_high << 7);
1320 if (ret < 0)
1321 goto done;
1322
1323 dev_info(&client->dev, "Detected a RJ54N1CB0C chip ID 0x%x:0x%x\n",
1324 data1, data2);
1325
1326 ret = v4l2_ctrl_handler_setup(&rj54n1->hdl);
1327
1328done:
1329 rj54n1_s_power(&rj54n1->subdev, 0);
1330 return ret;
1331}
1332
1333static int rj54n1_probe(struct i2c_client *client,
1334 const struct i2c_device_id *did)
1335{
1336 struct rj54n1 *rj54n1;
1337 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1338 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1339 struct rj54n1_pdata *rj54n1_priv;
1340 int ret;
1341
1342 if (!ssdd || !ssdd->drv_priv) {
1343 dev_err(&client->dev, "RJ54N1CB0C: missing platform data!\n");
1344 return -EINVAL;
1345 }
1346
1347 rj54n1_priv = ssdd->drv_priv;
1348
1349 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1350 dev_warn(&adapter->dev,
1351 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
1352 return -EIO;
1353 }
1354
1355 rj54n1 = devm_kzalloc(&client->dev, sizeof(struct rj54n1), GFP_KERNEL);
1356 if (!rj54n1)
1357 return -ENOMEM;
1358
1359 v4l2_i2c_subdev_init(&rj54n1->subdev, client, &rj54n1_subdev_ops);
1360 v4l2_ctrl_handler_init(&rj54n1->hdl, 4);
1361 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1362 V4L2_CID_VFLIP, 0, 1, 1, 0);
1363 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1364 V4L2_CID_HFLIP, 0, 1, 1, 0);
1365 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1366 V4L2_CID_GAIN, 0, 127, 1, 66);
1367 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1368 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1369 rj54n1->subdev.ctrl_handler = &rj54n1->hdl;
1370 if (rj54n1->hdl.error)
1371 return rj54n1->hdl.error;
1372
1373 rj54n1->clk_div = clk_div;
1374 rj54n1->rect.left = RJ54N1_COLUMN_SKIP;
1375 rj54n1->rect.top = RJ54N1_ROW_SKIP;
1376 rj54n1->rect.width = RJ54N1_MAX_WIDTH;
1377 rj54n1->rect.height = RJ54N1_MAX_HEIGHT;
1378 rj54n1->width = RJ54N1_MAX_WIDTH;
1379 rj54n1->height = RJ54N1_MAX_HEIGHT;
1380 rj54n1->fmt = &rj54n1_colour_fmts[0];
1381 rj54n1->resize = 1024;
1382 rj54n1->tgclk_mhz = (rj54n1_priv->mclk_freq / PLL_L * PLL_N) /
1383 (clk_div.ratio_tg + 1) / (clk_div.ratio_t + 1);
1384
1385 ret = rj54n1_video_probe(client, rj54n1_priv);
1386 if (ret < 0)
1387 v4l2_ctrl_handler_free(&rj54n1->hdl);
1388
1389 return ret;
1390}
1391
1392static int rj54n1_remove(struct i2c_client *client)
1393{
1394 struct rj54n1 *rj54n1 = to_rj54n1(client);
1395 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1396
1397 v4l2_device_unregister_subdev(&rj54n1->subdev);
1398 if (ssdd->free_bus)
1399 ssdd->free_bus(ssdd);
1400 v4l2_ctrl_handler_free(&rj54n1->hdl);
1401
1402 return 0;
1403}
1404
1405static const struct i2c_device_id rj54n1_id[] = {
1406 { "rj54n1cb0c", 0 },
1407 { }
1408};
1409MODULE_DEVICE_TABLE(i2c, rj54n1_id);
1410
1411static struct i2c_driver rj54n1_i2c_driver = {
1412 .driver = {
1413 .name = "rj54n1cb0c",
1414 },
1415 .probe = rj54n1_probe,
1416 .remove = rj54n1_remove,
1417 .id_table = rj54n1_id,
1418};
1419
1420module_i2c_driver(rj54n1_i2c_driver);
1421
1422MODULE_DESCRIPTION("Sharp RJ54N1CB0C Camera driver");
1423MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1424MODULE_LICENSE("GPL v2");
1425
