linux/drivers/net/ethernet/freescale/fsl_pq_mdio.c
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   1/*
   2 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
   3 * Provides Bus interface for MIIM regs
   4 *
   5 * Author: Andy Fleming <afleming@freescale.com>
   6 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
   7 *
   8 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
   9 *
  10 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
  11 *
  12 * This program is free software; you can redistribute  it and/or modify it
  13 * under  the terms of  the GNU General  Public License as published by the
  14 * Free Software Foundation;  either version 2 of the  License, or (at your
  15 * option) any later version.
  16 *
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/string.h>
  21#include <linux/errno.h>
  22#include <linux/slab.h>
  23#include <linux/init.h>
  24#include <linux/delay.h>
  25#include <linux/module.h>
  26#include <linux/mii.h>
  27#include <linux/of_address.h>
  28#include <linux/of_mdio.h>
  29#include <linux/of_device.h>
  30
  31#include <asm/io.h>
  32#include <asm/ucc.h>    /* for ucc_set_qe_mux_mii_mng() */
  33
  34#include "gianfar.h"
  35
  36#define MIIMIND_BUSY            0x00000001
  37#define MIIMIND_NOTVALID        0x00000004
  38#define MIIMCFG_INIT_VALUE      0x00000007
  39#define MIIMCFG_RESET           0x80000000
  40
  41#define MII_READ_COMMAND        0x00000001
  42
  43struct fsl_pq_mii {
  44        u32 miimcfg;    /* MII management configuration reg */
  45        u32 miimcom;    /* MII management command reg */
  46        u32 miimadd;    /* MII management address reg */
  47        u32 miimcon;    /* MII management control reg */
  48        u32 miimstat;   /* MII management status reg */
  49        u32 miimind;    /* MII management indication reg */
  50};
  51
  52struct fsl_pq_mdio {
  53        u8 res1[16];
  54        u32 ieventm;    /* MDIO Interrupt event register (for etsec2)*/
  55        u32 imaskm;     /* MDIO Interrupt mask register (for etsec2)*/
  56        u8 res2[4];
  57        u32 emapm;      /* MDIO Event mapping register (for etsec2)*/
  58        u8 res3[1280];
  59        struct fsl_pq_mii mii;
  60        u8 res4[28];
  61        u32 utbipar;    /* TBI phy address reg (only on UCC) */
  62        u8 res5[2728];
  63} __packed;
  64
  65/* Number of microseconds to wait for an MII register to respond */
  66#define MII_TIMEOUT     1000
  67
  68struct fsl_pq_mdio_priv {
  69        void __iomem *map;
  70        struct fsl_pq_mii __iomem *regs;
  71        int irqs[PHY_MAX_ADDR];
  72};
  73
  74/*
  75 * Per-device-type data.  Each type of device tree node that we support gets
  76 * one of these.
  77 *
  78 * @mii_offset: the offset of the MII registers within the memory map of the
  79 * node.  Some nodes define only the MII registers, and some define the whole
  80 * MAC (which includes the MII registers).
  81 *
  82 * @get_tbipa: determines the address of the TBIPA register
  83 *
  84 * @ucc_configure: a special function for extra QE configuration
  85 */
  86struct fsl_pq_mdio_data {
  87        unsigned int mii_offset;        /* offset of the MII registers */
  88        uint32_t __iomem * (*get_tbipa)(void __iomem *p);
  89        void (*ucc_configure)(phys_addr_t start, phys_addr_t end);
  90};
  91
  92/*
  93 * Write value to the PHY at mii_id at register regnum, on the bus attached
  94 * to the local interface, which may be different from the generic mdio bus
  95 * (tied to a single interface), waiting until the write is done before
  96 * returning. This is helpful in programming interfaces like the TBI which
  97 * control interfaces like onchip SERDES and are always tied to the local
  98 * mdio pins, which may not be the same as system mdio bus, used for
  99 * controlling the external PHYs, for example.
 100 */
 101static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
 102                u16 value)
 103{
 104        struct fsl_pq_mdio_priv *priv = bus->priv;
 105        struct fsl_pq_mii __iomem *regs = priv->regs;
 106        u32 status;
 107
 108        /* Set the PHY address and the register address we want to write */
 109        out_be32(&regs->miimadd, (mii_id << 8) | regnum);
 110
 111        /* Write out the value we want */
 112        out_be32(&regs->miimcon, value);
 113
 114        /* Wait for the transaction to finish */
 115        status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
 116                                    MII_TIMEOUT, 0);
 117
 118        return status ? 0 : -ETIMEDOUT;
 119}
 120
 121/*
 122 * Read the bus for PHY at addr mii_id, register regnum, and return the value.
 123 * Clears miimcom first.
 124 *
 125 * All PHY operation done on the bus attached to the local interface, which
 126 * may be different from the generic mdio bus.  This is helpful in programming
 127 * interfaces like the TBI which, in turn, control interfaces like on-chip
 128 * SERDES and are always tied to the local mdio pins, which may not be the
 129 * same as system mdio bus, used for controlling the external PHYs, for eg.
 130 */
 131static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 132{
 133        struct fsl_pq_mdio_priv *priv = bus->priv;
 134        struct fsl_pq_mii __iomem *regs = priv->regs;
 135        u32 status;
 136        u16 value;
 137
 138        /* Set the PHY address and the register address we want to read */
 139        out_be32(&regs->miimadd, (mii_id << 8) | regnum);
 140
 141        /* Clear miimcom, and then initiate a read */
 142        out_be32(&regs->miimcom, 0);
 143        out_be32(&regs->miimcom, MII_READ_COMMAND);
 144
 145        /* Wait for the transaction to finish, normally less than 100us */
 146        status = spin_event_timeout(!(in_be32(&regs->miimind) &
 147                                    (MIIMIND_NOTVALID | MIIMIND_BUSY)),
 148                                    MII_TIMEOUT, 0);
 149        if (!status)
 150                return -ETIMEDOUT;
 151
 152        /* Grab the value of the register from miimstat */
 153        value = in_be32(&regs->miimstat);
 154
 155        dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum);
 156        return value;
 157}
 158
 159/* Reset the MIIM registers, and wait for the bus to free */
 160static int fsl_pq_mdio_reset(struct mii_bus *bus)
 161{
 162        struct fsl_pq_mdio_priv *priv = bus->priv;
 163        struct fsl_pq_mii __iomem *regs = priv->regs;
 164        u32 status;
 165
 166        mutex_lock(&bus->mdio_lock);
 167
 168        /* Reset the management interface */
 169        out_be32(&regs->miimcfg, MIIMCFG_RESET);
 170
 171        /* Setup the MII Mgmt clock speed */
 172        out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
 173
 174        /* Wait until the bus is free */
 175        status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
 176                                    MII_TIMEOUT, 0);
 177
 178        mutex_unlock(&bus->mdio_lock);
 179
 180        if (!status) {
 181                dev_err(&bus->dev, "timeout waiting for MII bus\n");
 182                return -EBUSY;
 183        }
 184
 185        return 0;
 186}
 187
 188#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
 189/*
 190 * This is mildly evil, but so is our hardware for doing this.
 191 * Also, we have to cast back to struct gfar because of
 192 * definition weirdness done in gianfar.h.
 193 */
 194static uint32_t __iomem *get_gfar_tbipa(void __iomem *p)
 195{
 196        struct gfar __iomem *enet_regs = p;
 197
 198        return &enet_regs->tbipa;
 199}
 200
 201/*
 202 * Return the TBIPAR address for an eTSEC2 node
 203 */
 204static uint32_t __iomem *get_etsec_tbipa(void __iomem *p)
 205{
 206        return p;
 207}
 208#endif
 209
 210#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
 211/*
 212 * Return the TBIPAR address for a QE MDIO node
 213 */
 214static uint32_t __iomem *get_ucc_tbipa(void __iomem *p)
 215{
 216        struct fsl_pq_mdio __iomem *mdio = p;
 217
 218        return &mdio->utbipar;
 219}
 220
 221/*
 222 * Find the UCC node that controls the given MDIO node
 223 *
 224 * For some reason, the QE MDIO nodes are not children of the UCC devices
 225 * that control them.  Therefore, we need to scan all UCC nodes looking for
 226 * the one that encompases the given MDIO node.  We do this by comparing
 227 * physical addresses.  The 'start' and 'end' addresses of the MDIO node are
 228 * passed, and the correct UCC node will cover the entire address range.
 229 *
 230 * This assumes that there is only one QE MDIO node in the entire device tree.
 231 */
 232static void ucc_configure(phys_addr_t start, phys_addr_t end)
 233{
 234        static bool found_mii_master;
 235        struct device_node *np = NULL;
 236
 237        if (found_mii_master)
 238                return;
 239
 240        for_each_compatible_node(np, NULL, "ucc_geth") {
 241                struct resource res;
 242                const uint32_t *iprop;
 243                uint32_t id;
 244                int ret;
 245
 246                ret = of_address_to_resource(np, 0, &res);
 247                if (ret < 0) {
 248                        pr_debug("fsl-pq-mdio: no address range in node %s\n",
 249                                 np->full_name);
 250                        continue;
 251                }
 252
 253                /* if our mdio regs fall within this UCC regs range */
 254                if ((start < res.start) || (end > res.end))
 255                        continue;
 256
 257                iprop = of_get_property(np, "cell-index", NULL);
 258                if (!iprop) {
 259                        iprop = of_get_property(np, "device-id", NULL);
 260                        if (!iprop) {
 261                                pr_debug("fsl-pq-mdio: no UCC ID in node %s\n",
 262                                         np->full_name);
 263                                continue;
 264                        }
 265                }
 266
 267                id = be32_to_cpup(iprop);
 268
 269                /*
 270                 * cell-index and device-id for QE nodes are
 271                 * numbered from 1, not 0.
 272                 */
 273                if (ucc_set_qe_mux_mii_mng(id - 1) < 0) {
 274                        pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n",
 275                                 np->full_name);
 276                        continue;
 277                }
 278
 279                pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id);
 280                found_mii_master = true;
 281        }
 282}
 283
 284#endif
 285
 286static struct of_device_id fsl_pq_mdio_match[] = {
 287#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
 288        {
 289                .compatible = "fsl,gianfar-tbi",
 290                .data = &(struct fsl_pq_mdio_data) {
 291                        .mii_offset = 0,
 292                        .get_tbipa = get_gfar_tbipa,
 293                },
 294        },
 295        {
 296                .compatible = "fsl,gianfar-mdio",
 297                .data = &(struct fsl_pq_mdio_data) {
 298                        .mii_offset = 0,
 299                        .get_tbipa = get_gfar_tbipa,
 300                },
 301        },
 302        {
 303                .type = "mdio",
 304                .compatible = "gianfar",
 305                .data = &(struct fsl_pq_mdio_data) {
 306                        .mii_offset = offsetof(struct fsl_pq_mdio, mii),
 307                        .get_tbipa = get_gfar_tbipa,
 308                },
 309        },
 310        {
 311                .compatible = "fsl,etsec2-tbi",
 312                .data = &(struct fsl_pq_mdio_data) {
 313                        .mii_offset = offsetof(struct fsl_pq_mdio, mii),
 314                        .get_tbipa = get_etsec_tbipa,
 315                },
 316        },
 317        {
 318                .compatible = "fsl,etsec2-mdio",
 319                .data = &(struct fsl_pq_mdio_data) {
 320                        .mii_offset = offsetof(struct fsl_pq_mdio, mii),
 321                        .get_tbipa = get_etsec_tbipa,
 322                },
 323        },
 324#endif
 325#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
 326        {
 327                .compatible = "fsl,ucc-mdio",
 328                .data = &(struct fsl_pq_mdio_data) {
 329                        .mii_offset = 0,
 330                        .get_tbipa = get_ucc_tbipa,
 331                        .ucc_configure = ucc_configure,
 332                },
 333        },
 334        {
 335                /* Legacy UCC MDIO node */
 336                .type = "mdio",
 337                .compatible = "ucc_geth_phy",
 338                .data = &(struct fsl_pq_mdio_data) {
 339                        .mii_offset = 0,
 340                        .get_tbipa = get_ucc_tbipa,
 341                        .ucc_configure = ucc_configure,
 342                },
 343        },
 344#endif
 345        /* No Kconfig option for Fman support yet */
 346        {
 347                .compatible = "fsl,fman-mdio",
 348                .data = &(struct fsl_pq_mdio_data) {
 349                        .mii_offset = 0,
 350                        /* Fman TBI operations are handled elsewhere */
 351                },
 352        },
 353
 354        {},
 355};
 356MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
 357
 358static int fsl_pq_mdio_probe(struct platform_device *pdev)
 359{
 360        const struct of_device_id *id =
 361                of_match_device(fsl_pq_mdio_match, &pdev->dev);
 362        const struct fsl_pq_mdio_data *data = id->data;
 363        struct device_node *np = pdev->dev.of_node;
 364        struct resource res;
 365        struct device_node *tbi;
 366        struct fsl_pq_mdio_priv *priv;
 367        struct mii_bus *new_bus;
 368        int err;
 369
 370        dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible);
 371
 372        new_bus = mdiobus_alloc_size(sizeof(*priv));
 373        if (!new_bus)
 374                return -ENOMEM;
 375
 376        priv = new_bus->priv;
 377        new_bus->name = "Freescale PowerQUICC MII Bus",
 378        new_bus->read = &fsl_pq_mdio_read;
 379        new_bus->write = &fsl_pq_mdio_write;
 380        new_bus->reset = &fsl_pq_mdio_reset;
 381        new_bus->irq = priv->irqs;
 382
 383        err = of_address_to_resource(np, 0, &res);
 384        if (err < 0) {
 385                dev_err(&pdev->dev, "could not obtain address information\n");
 386                goto error;
 387        }
 388
 389        snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name,
 390                (unsigned long long)res.start);
 391
 392        priv->map = of_iomap(np, 0);
 393        if (!priv->map) {
 394                err = -ENOMEM;
 395                goto error;
 396        }
 397
 398        /*
 399         * Some device tree nodes represent only the MII registers, and
 400         * others represent the MAC and MII registers.  The 'mii_offset' field
 401         * contains the offset of the MII registers inside the mapped register
 402         * space.
 403         */
 404        if (data->mii_offset > resource_size(&res)) {
 405                dev_err(&pdev->dev, "invalid register map\n");
 406                err = -EINVAL;
 407                goto error;
 408        }
 409        priv->regs = priv->map + data->mii_offset;
 410
 411        new_bus->parent = &pdev->dev;
 412        dev_set_drvdata(&pdev->dev, new_bus);
 413
 414        if (data->get_tbipa) {
 415                for_each_child_of_node(np, tbi) {
 416                        if (strcmp(tbi->type, "tbi-phy") == 0) {
 417                                dev_dbg(&pdev->dev, "found TBI PHY node %s\n",
 418                                        strrchr(tbi->full_name, '/') + 1);
 419                                break;
 420                        }
 421                }
 422
 423                if (tbi) {
 424                        const u32 *prop = of_get_property(tbi, "reg", NULL);
 425                        uint32_t __iomem *tbipa;
 426
 427                        if (!prop) {
 428                                dev_err(&pdev->dev,
 429                                        "missing 'reg' property in node %s\n",
 430                                        tbi->full_name);
 431                                err = -EBUSY;
 432                                goto error;
 433                        }
 434
 435                        tbipa = data->get_tbipa(priv->map);
 436
 437                        out_be32(tbipa, be32_to_cpup(prop));
 438                }
 439        }
 440
 441        if (data->ucc_configure)
 442                data->ucc_configure(res.start, res.end);
 443
 444        err = of_mdiobus_register(new_bus, np);
 445        if (err) {
 446                dev_err(&pdev->dev, "cannot register %s as MDIO bus\n",
 447                        new_bus->name);
 448                goto error;
 449        }
 450
 451        return 0;
 452
 453error:
 454        if (priv->map)
 455                iounmap(priv->map);
 456
 457        kfree(new_bus);
 458
 459        return err;
 460}
 461
 462
 463static int fsl_pq_mdio_remove(struct platform_device *pdev)
 464{
 465        struct device *device = &pdev->dev;
 466        struct mii_bus *bus = dev_get_drvdata(device);
 467        struct fsl_pq_mdio_priv *priv = bus->priv;
 468
 469        mdiobus_unregister(bus);
 470
 471        dev_set_drvdata(device, NULL);
 472
 473        iounmap(priv->map);
 474        mdiobus_free(bus);
 475
 476        return 0;
 477}
 478
 479static struct platform_driver fsl_pq_mdio_driver = {
 480        .driver = {
 481                .name = "fsl-pq_mdio",
 482                .owner = THIS_MODULE,
 483                .of_match_table = fsl_pq_mdio_match,
 484        },
 485        .probe = fsl_pq_mdio_probe,
 486        .remove = fsl_pq_mdio_remove,
 487};
 488
 489module_platform_driver(fsl_pq_mdio_driver);
 490
 491MODULE_LICENSE("GPL");
 492