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27#ifndef _VMXNET3_DEFS_H_
28#define _VMXNET3_DEFS_H_
29
30#include "upt1_defs.h"
31
32
33
34enum {
35 VMXNET3_REG_VRRS = 0x0,
36 VMXNET3_REG_UVRS = 0x8,
37 VMXNET3_REG_DSAL = 0x10,
38 VMXNET3_REG_DSAH = 0x18,
39 VMXNET3_REG_CMD = 0x20,
40 VMXNET3_REG_MACL = 0x28,
41 VMXNET3_REG_MACH = 0x30,
42 VMXNET3_REG_ICR = 0x38,
43 VMXNET3_REG_ECR = 0x40
44};
45
46
47enum {
48 VMXNET3_REG_IMR = 0x0,
49 VMXNET3_REG_TXPROD = 0x600,
50 VMXNET3_REG_RXPROD = 0x800,
51 VMXNET3_REG_RXPROD2 = 0xA00
52};
53
54#define VMXNET3_PT_REG_SIZE 4096
55#define VMXNET3_VD_REG_SIZE 4096
56
57#define VMXNET3_REG_ALIGN 8
58#define VMXNET3_REG_ALIGN_MASK 0x7
59
60
61#define VMXNET3_IO_TYPE_PT 0
62#define VMXNET3_IO_TYPE_VD 1
63#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
64#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
65#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
66
67enum {
68 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
69 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
70 VMXNET3_CMD_QUIESCE_DEV,
71 VMXNET3_CMD_RESET_DEV,
72 VMXNET3_CMD_UPDATE_RX_MODE,
73 VMXNET3_CMD_UPDATE_MAC_FILTERS,
74 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
75 VMXNET3_CMD_UPDATE_RSSIDT,
76 VMXNET3_CMD_UPDATE_IML,
77 VMXNET3_CMD_UPDATE_PMCFG,
78 VMXNET3_CMD_UPDATE_FEATURE,
79 VMXNET3_CMD_LOAD_PLUGIN,
80
81 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
82 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
83 VMXNET3_CMD_GET_STATS,
84 VMXNET3_CMD_GET_LINK,
85 VMXNET3_CMD_GET_PERM_MAC_LO,
86 VMXNET3_CMD_GET_PERM_MAC_HI,
87 VMXNET3_CMD_GET_DID_LO,
88 VMXNET3_CMD_GET_DID_HI,
89 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
90 VMXNET3_CMD_GET_CONF_INTR
91};
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110
111struct Vmxnet3_TxDesc {
112 __le64 addr;
113
114#ifdef __BIG_ENDIAN_BITFIELD
115 u32 msscof:14;
116 u32 ext1:1;
117 u32 dtype:1;
118 u32 rsvd:1;
119 u32 gen:1;
120 u32 len:14;
121#else
122 u32 len:14;
123 u32 gen:1;
124 u32 rsvd:1;
125 u32 dtype:1;
126 u32 ext1:1;
127 u32 msscof:14;
128#endif
129
130#ifdef __BIG_ENDIAN_BITFIELD
131 u32 tci:16;
132 u32 ti:1;
133 u32 ext2:1;
134 u32 cq:1;
135 u32 eop:1;
136 u32 om:2;
137 u32 hlen:10;
138#else
139 u32 hlen:10;
140 u32 om:2;
141 u32 eop:1;
142 u32 cq:1;
143 u32 ext2:1;
144 u32 ti:1;
145 u32 tci:16;
146#endif
147};
148
149
150#define VMXNET3_OM_NONE 0
151#define VMXNET3_OM_CSUM 2
152#define VMXNET3_OM_TSO 3
153
154
155#define VMXNET3_TXD_EOP_SHIFT 12
156#define VMXNET3_TXD_CQ_SHIFT 13
157#define VMXNET3_TXD_GEN_SHIFT 14
158#define VMXNET3_TXD_EOP_DWORD_SHIFT 3
159#define VMXNET3_TXD_GEN_DWORD_SHIFT 2
160
161#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
162#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
163#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
164
165#define VMXNET3_HDR_COPY_SIZE 128
166
167
168struct Vmxnet3_TxDataDesc {
169 u8 data[VMXNET3_HDR_COPY_SIZE];
170};
171
172#define VMXNET3_TCD_GEN_SHIFT 31
173#define VMXNET3_TCD_GEN_SIZE 1
174#define VMXNET3_TCD_TXIDX_SHIFT 0
175#define VMXNET3_TCD_TXIDX_SIZE 12
176#define VMXNET3_TCD_GEN_DWORD_SHIFT 3
177
178struct Vmxnet3_TxCompDesc {
179 u32 txdIdx:12;
180 u32 ext1:20;
181
182 __le32 ext2;
183 __le32 ext3;
184
185 u32 rsvd:24;
186 u32 type:7;
187 u32 gen:1;
188};
189
190struct Vmxnet3_RxDesc {
191 __le64 addr;
192
193#ifdef __BIG_ENDIAN_BITFIELD
194 u32 gen:1;
195 u32 rsvd:15;
196 u32 dtype:1;
197 u32 btype:1;
198 u32 len:14;
199#else
200 u32 len:14;
201 u32 btype:1;
202 u32 dtype:1;
203 u32 rsvd:15;
204 u32 gen:1;
205#endif
206 u32 ext1;
207};
208
209
210#define VMXNET3_RXD_BTYPE_HEAD 0
211#define VMXNET3_RXD_BTYPE_BODY 1
212
213
214#define VMXNET3_RXD_BTYPE_SHIFT 14
215#define VMXNET3_RXD_GEN_SHIFT 31
216
217struct Vmxnet3_RxCompDesc {
218#ifdef __BIG_ENDIAN_BITFIELD
219 u32 ext2:1;
220 u32 cnc:1;
221 u32 rssType:4;
222 u32 rqID:10;
223 u32 sop:1;
224 u32 eop:1;
225 u32 ext1:2;
226 u32 rxdIdx:12;
227#else
228 u32 rxdIdx:12;
229 u32 ext1:2;
230 u32 eop:1;
231 u32 sop:1;
232 u32 rqID:10;
233 u32 rssType:4;
234 u32 cnc:1;
235 u32 ext2:1;
236#endif
237
238 __le32 rssHash;
239
240#ifdef __BIG_ENDIAN_BITFIELD
241 u32 tci:16;
242 u32 ts:1;
243 u32 err:1;
244 u32 len:14;
245#else
246 u32 len:14;
247 u32 err:1;
248 u32 ts:1;
249 u32 tci:16;
250#endif
251
252
253#ifdef __BIG_ENDIAN_BITFIELD
254 u32 gen:1;
255 u32 type:7;
256 u32 fcs:1;
257 u32 frg:1;
258 u32 v4:1;
259 u32 v6:1;
260 u32 ipc:1;
261 u32 tcp:1;
262 u32 udp:1;
263 u32 tuc:1;
264 u32 csum:16;
265#else
266 u32 csum:16;
267 u32 tuc:1;
268 u32 udp:1;
269 u32 tcp:1;
270 u32 ipc:1;
271 u32 v6:1;
272 u32 v4:1;
273 u32 frg:1;
274 u32 fcs:1;
275 u32 type:7;
276 u32 gen:1;
277#endif
278};
279
280struct Vmxnet3_RxCompDescExt {
281 __le32 dword1;
282 u8 segCnt;
283 u8 dupAckCnt;
284 __le16 tsDelta;
285 __le32 dword2;
286#ifdef __BIG_ENDIAN_BITFIELD
287 u32 gen:1;
288 u32 type:7;
289 u32 fcs:1;
290 u32 frg:1;
291 u32 v4:1;
292 u32 v6:1;
293 u32 ipc:1;
294 u32 tcp:1;
295 u32 udp:1;
296 u32 tuc:1;
297 u32 mss:16;
298#else
299 u32 mss:16;
300 u32 tuc:1;
301 u32 udp:1;
302 u32 tcp:1;
303 u32 ipc:1;
304 u32 v6:1;
305 u32 v4:1;
306 u32 frg:1;
307 u32 fcs:1;
308 u32 type:7;
309 u32 gen:1;
310#endif
311};
312
313
314
315#define VMXNET3_RCD_TUC_SHIFT 16
316#define VMXNET3_RCD_IPC_SHIFT 19
317
318
319#define VMXNET3_RCD_TYPE_SHIFT 56
320#define VMXNET3_RCD_GEN_SHIFT 63
321
322
323#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
324 1 << VMXNET3_RCD_IPC_SHIFT)
325#define VMXNET3_TXD_GEN_SIZE 1
326#define VMXNET3_TXD_EOP_SIZE 1
327
328
329enum {
330 VMXNET3_RCD_RSS_TYPE_NONE = 0,
331 VMXNET3_RCD_RSS_TYPE_IPV4 = 1,
332 VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2,
333 VMXNET3_RCD_RSS_TYPE_IPV6 = 3,
334 VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4,
335};
336
337
338
339union Vmxnet3_GenericDesc {
340 __le64 qword[2];
341 __le32 dword[4];
342 __le16 word[8];
343 struct Vmxnet3_TxDesc txd;
344 struct Vmxnet3_RxDesc rxd;
345 struct Vmxnet3_TxCompDesc tcd;
346 struct Vmxnet3_RxCompDesc rcd;
347 struct Vmxnet3_RxCompDescExt rcdExt;
348};
349
350#define VMXNET3_INIT_GEN 1
351
352
353#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
354
355
356#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
357 VMXNET3_MAX_TX_BUF_SIZE)
358
359
360#define VMXNET3_MAX_TXD_PER_PKT 16
361
362
363#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
364
365#define VMXNET3_MIN_T0_BUF_SIZE 128
366#define VMXNET3_MAX_CSUM_OFFSET 1024
367
368
369#define VMXNET3_RING_BA_ALIGN 512
370#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
371
372
373#define VMXNET3_RING_SIZE_ALIGN 32
374#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
375
376
377#define VMXNET3_TX_RING_MAX_SIZE 4096
378#define VMXNET3_TC_RING_MAX_SIZE 4096
379#define VMXNET3_RX_RING_MAX_SIZE 4096
380#define VMXNET3_RX_RING2_MAX_SIZE 4096
381#define VMXNET3_RC_RING_MAX_SIZE 8192
382
383
384
385enum {
386 VMXNET3_ERR_NOEOP = 0x80000000,
387 VMXNET3_ERR_TXD_REUSE = 0x80000001,
388 VMXNET3_ERR_BIG_PKT = 0x80000002,
389 VMXNET3_ERR_DESC_NOT_SPT = 0x80000003,
390 VMXNET3_ERR_SMALL_BUF = 0x80000004,
391 VMXNET3_ERR_STRESS = 0x80000005,
392 VMXNET3_ERR_SWITCH = 0x80000006,
393 VMXNET3_ERR_TXD_INVALID = 0x80000007,
394};
395
396
397#define VMXNET3_CDTYPE_TXCOMP 0
398#define VMXNET3_CDTYPE_RXCOMP 3
399#define VMXNET3_CDTYPE_RXCOMP_LRO 4
400
401enum {
402 VMXNET3_GOS_BITS_UNK = 0,
403 VMXNET3_GOS_BITS_32 = 1,
404 VMXNET3_GOS_BITS_64 = 2,
405};
406
407#define VMXNET3_GOS_TYPE_LINUX 1
408
409
410struct Vmxnet3_GOSInfo {
411#ifdef __BIG_ENDIAN_BITFIELD
412 u32 gosMisc:10;
413 u32 gosVer:16;
414 u32 gosType:4;
415 u32 gosBits:2;
416#else
417 u32 gosBits:2;
418 u32 gosType:4;
419 u32 gosVer:16;
420 u32 gosMisc:10;
421#endif
422};
423
424struct Vmxnet3_DriverInfo {
425 __le32 version;
426 struct Vmxnet3_GOSInfo gos;
427 __le32 vmxnet3RevSpt;
428 __le32 uptVerSpt;
429};
430
431
432#define VMXNET3_REV1_MAGIC 3133079265u
433
434
435
436
437
438
439
440#define VMXNET3_QUEUE_DESC_ALIGN 128
441
442
443struct Vmxnet3_MiscConf {
444 struct Vmxnet3_DriverInfo driverInfo;
445 __le64 uptFeatures;
446 __le64 ddPA;
447 __le64 queueDescPA;
448 __le32 ddLen;
449 __le32 queueDescLen;
450 __le32 mtu;
451 __le16 maxNumRxSG;
452 u8 numTxQueues;
453 u8 numRxQueues;
454 __le32 reserved[4];
455};
456
457
458struct Vmxnet3_TxQueueConf {
459 __le64 txRingBasePA;
460 __le64 dataRingBasePA;
461 __le64 compRingBasePA;
462 __le64 ddPA;
463 __le64 reserved;
464 __le32 txRingSize;
465 __le32 dataRingSize;
466 __le32 compRingSize;
467 __le32 ddLen;
468 u8 intrIdx;
469 u8 _pad[7];
470};
471
472
473struct Vmxnet3_RxQueueConf {
474 __le64 rxRingBasePA[2];
475 __le64 compRingBasePA;
476 __le64 ddPA;
477 __le64 reserved;
478 __le32 rxRingSize[2];
479 __le32 compRingSize;
480 __le32 ddLen;
481 u8 intrIdx;
482 u8 _pad[7];
483};
484
485
486enum vmxnet3_intr_mask_mode {
487 VMXNET3_IMM_AUTO = 0,
488 VMXNET3_IMM_ACTIVE = 1,
489 VMXNET3_IMM_LAZY = 2
490};
491
492enum vmxnet3_intr_type {
493 VMXNET3_IT_AUTO = 0,
494 VMXNET3_IT_INTX = 1,
495 VMXNET3_IT_MSI = 2,
496 VMXNET3_IT_MSIX = 3
497};
498
499#define VMXNET3_MAX_TX_QUEUES 8
500#define VMXNET3_MAX_RX_QUEUES 16
501
502#define VMXNET3_MAX_INTRS 25
503
504
505#define VMXNET3_IC_DISABLE_ALL 0x1
506
507
508struct Vmxnet3_IntrConf {
509 bool autoMask;
510 u8 numIntrs;
511 u8 eventIntrIdx;
512 u8 modLevels[VMXNET3_MAX_INTRS];
513
514 __le32 intrCtrl;
515 __le32 reserved[2];
516};
517
518
519#define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8))
520
521
522struct Vmxnet3_QueueStatus {
523 bool stopped;
524 u8 _pad[3];
525 __le32 error;
526};
527
528
529struct Vmxnet3_TxQueueCtrl {
530 __le32 txNumDeferred;
531 __le32 txThreshold;
532 __le64 reserved;
533};
534
535
536struct Vmxnet3_RxQueueCtrl {
537 bool updateRxProd;
538 u8 _pad[7];
539 __le64 reserved;
540};
541
542enum {
543 VMXNET3_RXM_UCAST = 0x01,
544 VMXNET3_RXM_MCAST = 0x02,
545 VMXNET3_RXM_BCAST = 0x04,
546 VMXNET3_RXM_ALL_MULTI = 0x08,
547 VMXNET3_RXM_PROMISC = 0x10
548};
549
550struct Vmxnet3_RxFilterConf {
551 __le32 rxMode;
552 __le16 mfTableLen;
553 __le16 _pad1;
554 __le64 mfTablePA;
555 __le32 vfTable[VMXNET3_VFT_SIZE];
556};
557
558
559#define VMXNET3_PM_MAX_FILTERS 6
560#define VMXNET3_PM_MAX_PATTERN_SIZE 128
561#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
562
563#define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01)
564#define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02)
565
566
567
568struct Vmxnet3_PM_PktFilter {
569 u8 maskSize;
570 u8 patternSize;
571 u8 mask[VMXNET3_PM_MAX_MASK_SIZE];
572 u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
573 u8 pad[6];
574};
575
576
577struct Vmxnet3_PMConf {
578 __le16 wakeUpEvents;
579 u8 numFilters;
580 u8 pad[5];
581 struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
582};
583
584
585struct Vmxnet3_VariableLenConfDesc {
586 __le32 confVer;
587 __le32 confLen;
588 __le64 confPA;
589};
590
591
592struct Vmxnet3_TxQueueDesc {
593 struct Vmxnet3_TxQueueCtrl ctrl;
594 struct Vmxnet3_TxQueueConf conf;
595
596
597 struct Vmxnet3_QueueStatus status;
598 struct UPT1_TxStats stats;
599 u8 _pad[88];
600};
601
602
603struct Vmxnet3_RxQueueDesc {
604 struct Vmxnet3_RxQueueCtrl ctrl;
605 struct Vmxnet3_RxQueueConf conf;
606
607 struct Vmxnet3_QueueStatus status;
608 struct UPT1_RxStats stats;
609 u8 __pad[88];
610};
611
612
613struct Vmxnet3_DSDevRead {
614
615 struct Vmxnet3_MiscConf misc;
616 struct Vmxnet3_IntrConf intrConf;
617 struct Vmxnet3_RxFilterConf rxFilterConf;
618 struct Vmxnet3_VariableLenConfDesc rssConfDesc;
619 struct Vmxnet3_VariableLenConfDesc pmConfDesc;
620 struct Vmxnet3_VariableLenConfDesc pluginConfDesc;
621};
622
623
624struct Vmxnet3_DriverShared {
625 __le32 magic;
626
627 __le32 pad;
628 struct Vmxnet3_DSDevRead devRead;
629 __le32 ecr;
630 __le32 reserved[5];
631};
632
633
634#define VMXNET3_ECR_RQERR (1 << 0)
635#define VMXNET3_ECR_TQERR (1 << 1)
636#define VMXNET3_ECR_LINK (1 << 2)
637#define VMXNET3_ECR_DIC (1 << 3)
638#define VMXNET3_ECR_DEBUG (1 << 4)
639
640
641#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
642
643
644#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
645 do {\
646 (idx)++;\
647 if (unlikely((idx) == (ring_size))) {\
648 (idx) = 0;\
649 } \
650 } while (0)
651
652#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
653 (vfTable[vid >> 5] |= (1 << (vid & 31)))
654#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
655 (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
656
657#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
658 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
659
660#define VMXNET3_MAX_MTU 9000
661#define VMXNET3_MIN_MTU 60
662
663#define VMXNET3_LINK_UP (10000 << 16 | 1)
664#define VMXNET3_LINK_DOWN 0
665
666#endif
667