1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26#ifndef __RTL8723E_REG_H__ 27#define __RTL8723E_REG_H__ 28 29#define REG_SYS_ISO_CTRL 0x0000 30#define REG_SYS_FUNC_EN 0x0002 31#define REG_APS_FSMCO 0x0004 32#define REG_SYS_CLKR 0x0008 33#define REG_9346CR 0x000A 34#define REG_EE_VPD 0x000C 35#define REG_AFE_MISC 0x0010 36#define REG_SPS0_CTRL 0x0011 37#define REG_SPS_OCP_CFG 0x0018 38#define REG_RSV_CTRL 0x001C 39#define REG_RF_CTRL 0x001F 40#define REG_LDOA15_CTRL 0x0020 41#define REG_LDOV12D_CTRL 0x0021 42#define REG_LDOHCI12_CTRL 0x0022 43#define REG_LPLDO_CTRL 0x0023 44#define REG_AFE_XTAL_CTRL 0x0024 45#define REG_AFE_PLL_CTRL 0x0028 46#define REG_EFUSE_CTRL 0x0030 47#define REG_EFUSE_TEST 0x0034 48#define REG_PWR_DATA 0x0038 49#define REG_CAL_TIMER 0x003C 50#define REG_ACLK_MON 0x003E 51#define REG_GPIO_MUXCFG 0x0040 52#define REG_GPIO_IO_SEL 0x0042 53#define REG_MAC_PINMUX_CFG 0x0043 54#define REG_GPIO_PIN_CTRL 0x0044 55#define REG_GPIO_INTM 0x0048 56#define REG_LEDCFG0 0x004C 57#define REG_LEDCFG1 0x004D 58#define REG_LEDCFG2 0x004E 59#define REG_LEDCFG3 0x004F 60#define REG_FSIMR 0x0050 61#define REG_FSISR 0x0054 62#define REG_GPIO_PIN_CTRL_2 0x0060 63#define REG_GPIO_IO_SEL_2 0x0062 64#define REG_MULTI_FUNC_CTRL 0x0068 65 66#define REG_MCUFWDL 0x0080 67 68#define REG_HMEBOX_EXT_0 0x0088 69#define REG_HMEBOX_EXT_1 0x008A 70#define REG_HMEBOX_EXT_2 0x008C 71#define REG_HMEBOX_EXT_3 0x008E 72 73#define REG_BIST_SCAN 0x00D0 74#define REG_BIST_RPT 0x00D4 75#define REG_BIST_ROM_RPT 0x00D8 76#define REG_USB_SIE_INTF 0x00E0 77#define REG_PCIE_MIO_INTF 0x00E4 78#define REG_PCIE_MIO_INTD 0x00E8 79#define REG_SYS_CFG 0x00F0 80#define REG_GPIO_OUTSTS 0x00F4 81 82#define REG_CR 0x0100 83#define REG_PBP 0x0104 84#define REG_TRXDMA_CTRL 0x010C 85#define REG_TRXFF_BNDY 0x0114 86#define REG_TRXFF_STATUS 0x0118 87#define REG_RXFF_PTR 0x011C 88#define REG_HIMR 0x0120 89#define REG_HISR 0x0124 90#define REG_HIMRE 0x0128 91#define REG_HISRE 0x012C 92#define REG_CPWM 0x012F 93#define REG_FWIMR 0x0130 94#define REG_FWISR 0x0134 95#define REG_PKTBUF_DBG_CTRL 0x0140 96#define REG_PKTBUF_DBG_DATA_L 0x0144 97#define REG_PKTBUF_DBG_DATA_H 0x0148 98 99#define REG_TC0_CTRL 0x0150 100#define REG_TC1_CTRL 0x0154 101#define REG_TC2_CTRL 0x0158 102#define REG_TC3_CTRL 0x015C 103#define REG_TC4_CTRL 0x0160 104#define REG_TCUNIT_BASE 0x0164 105#define REG_MBIST_START 0x0174 106#define REG_MBIST_DONE 0x0178 107#define REG_MBIST_FAIL 0x017C 108#define REG_C2HEVT_MSG_NORMAL 0x01A0 109#define REG_C2HEVT_MSG_TEST 0x01B8 110#define REG_MCUTST_1 0x01c0 111#define REG_FMETHR 0x01C8 112#define REG_HMETFR 0x01CC 113#define REG_HMEBOX_0 0x01D0 114#define REG_HMEBOX_1 0x01D4 115#define REG_HMEBOX_2 0x01D8 116#define REG_HMEBOX_3 0x01DC 117 118#define REG_LLT_INIT 0x01E0 119#define REG_BB_ACCEESS_CTRL 0x01E8 120#define REG_BB_ACCESS_DATA 0x01EC 121 122#define REG_RQPN 0x0200 123#define REG_FIFOPAGE 0x0204 124#define REG_TDECTRL 0x0208 125#define REG_TXDMA_OFFSET_CHK 0x020C 126#define REG_TXDMA_STATUS 0x0210 127#define REG_RQPN_NPQ 0x0214 128 129#define REG_RXDMA_AGG_PG_TH 0x0280 130#define REG_RXPKT_NUM 0x0284 131#define REG_RXDMA_STATUS 0x0288 132 133#define REG_PCIE_CTRL_REG 0x0300 134#define REG_INT_MIG 0x0304 135#define REG_BCNQ_DESA 0x0308 136#define REG_HQ_DESA 0x0310 137#define REG_MGQ_DESA 0x0318 138#define REG_VOQ_DESA 0x0320 139#define REG_VIQ_DESA 0x0328 140#define REG_BEQ_DESA 0x0330 141#define REG_BKQ_DESA 0x0338 142#define REG_RX_DESA 0x0340 143#define REG_DBI 0x0348 144#define REG_MDIO 0x0354 145#define REG_DBG_SEL 0x0360 146#define REG_PCIE_HRPWM 0x0361 147#define REG_PCIE_HCPWM 0x0363 148#define REG_UART_CTRL 0x0364 149#define REG_UART_TX_DESA 0x0370 150#define REG_UART_RX_DESA 0x0378 151 152#define REG_HDAQ_DESA_NODEF 0x0000 153#define REG_CMDQ_DESA_NODEF 0x0000 154 155#define REG_VOQ_INFORMATION 0x0400 156#define REG_VIQ_INFORMATION 0x0404 157#define REG_BEQ_INFORMATION 0x0408 158#define REG_BKQ_INFORMATION 0x040C 159#define REG_MGQ_INFORMATION 0x0410 160#define REG_HGQ_INFORMATION 0x0414 161#define REG_BCNQ_INFORMATION 0x0418 162 163#define REG_CPU_MGQ_INFORMATION 0x041C 164#define REG_FWHW_TXQ_CTRL 0x0420 165#define REG_HWSEQ_CTRL 0x0423 166#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 167#define REG_TXPKTBUF_MGQ_BDNY 0x0425 168#define REG_MULTI_BCNQ_EN 0x0426 169#define REG_MULTI_BCNQ_OFFSET 0x0427 170#define REG_SPEC_SIFS 0x0428 171#define REG_RL 0x042A 172#define REG_DARFRC 0x0430 173#define REG_RARFRC 0x0438 174#define REG_RRSR 0x0440 175#define REG_ARFR0 0x0444 176#define REG_ARFR1 0x0448 177#define REG_ARFR2 0x044C 178#define REG_ARFR3 0x0450 179#define REG_AGGLEN_LMT 0x0458 180#define REG_AMPDU_MIN_SPACE 0x045C 181#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 182#define REG_FAST_EDCA_CTRL 0x0460 183#define REG_RD_RESP_PKT_TH 0x0463 184#define REG_INIRTS_RATE_SEL 0x0480 185#define REG_INIDATA_RATE_SEL 0x0484 186#define REG_POWER_STATUS 0x04A4 187#define REG_POWER_STAGE1 0x04B4 188#define REG_POWER_STAGE2 0x04B8 189#define REG_PKT_LIFE_TIME 0x04C0 190#define REG_STBC_SETTING 0x04C4 191#define REG_PROT_MODE_CTRL 0x04C8 192#define REG_BAR_MODE_CTRL 0x04CC 193#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 194#define REG_NQOS_SEQ 0x04DC 195#define REG_QOS_SEQ 0x04DE 196#define REG_NEED_CPU_HANDLE 0x04E0 197#define REG_PKT_LOSE_RPT 0x04E1 198#define REG_PTCL_ERR_STATUS 0x04E2 199#define REG_DUMMY 0x04FC 200 201#define REG_EDCA_VO_PARAM 0x0500 202#define REG_EDCA_VI_PARAM 0x0504 203#define REG_EDCA_BE_PARAM 0x0508 204#define REG_EDCA_BK_PARAM 0x050C 205#define REG_BCNTCFG 0x0510 206#define REG_PIFS 0x0512 207#define REG_RDG_PIFS 0x0513 208#define REG_SIFS_CTX 0x0514 209#define REG_SIFS_TRX 0x0516 210#define REG_AGGR_BREAK_TIME 0x051A 211#define REG_SLOT 0x051B 212#define REG_TX_PTCL_CTRL 0x0520 213#define REG_TXPAUSE 0x0522 214#define REG_DIS_TXREQ_CLR 0x0523 215#define REG_RD_CTRL 0x0524 216#define REG_TBTT_PROHIBIT 0x0540 217#define REG_RD_NAV_NXT 0x0544 218#define REG_NAV_PROT_LEN 0x0546 219#define REG_BCN_CTRL 0x0550 220#define REG_USTIME_TSF 0x0551 221#define REG_MBID_NUM 0x0552 222#define REG_DUAL_TSF_RST 0x0553 223#define REG_BCN_INTERVAL 0x0554 224#define REG_MBSSID_BCN_SPACE 0x0554 225#define REG_DRVERLYINT 0x0558 226#define REG_BCNDMATIM 0x0559 227#define REG_ATIMWND 0x055A 228#define REG_BCN_MAX_ERR 0x055D 229#define REG_RXTSF_OFFSET_CCK 0x055E 230#define REG_RXTSF_OFFSET_OFDM 0x055F 231#define REG_TSFTR 0x0560 232#define REG_INIT_TSFTR 0x0564 233#define REG_PSTIMER 0x0580 234#define REG_TIMER0 0x0584 235#define REG_TIMER1 0x0588 236#define REG_ACMHWCTRL 0x05C0 237#define REG_ACMRSTCTRL 0x05C1 238#define REG_ACMAVG 0x05C2 239#define REG_VO_ADMTIME 0x05C4 240#define REG_VI_ADMTIME 0x05C6 241#define REG_BE_ADMTIME 0x05C8 242#define REG_EDCA_RANDOM_GEN 0x05CC 243#define REG_SCH_TXCMD 0x05D0 244 245#define REG_APSD_CTRL 0x0600 246#define REG_BWOPMODE 0x0603 247#define REG_TCR 0x0604 248#define REG_RCR 0x0608 249#define REG_RX_PKT_LIMIT 0x060C 250#define REG_RX_DLK_TIME 0x060D 251#define REG_RX_DRVINFO_SZ 0x060F 252 253#define REG_MACID 0x0610 254#define REG_BSSID 0x0618 255#define REG_MAR 0x0620 256#define REG_MBIDCAMCFG 0x0628 257 258#define REG_USTIME_EDCA 0x0638 259#define REG_MAC_SPEC_SIFS 0x063A 260#define REG_RESP_SIFS_CCK 0x063C 261#define REG_RESP_SIFS_OFDM 0x063E 262#define REG_ACKTO 0x0640 263#define REG_CTS2TO 0x0641 264#define REG_EIFS 0x0642 265 266#define REG_NAV_CTRL 0x0650 267#define REG_BACAMCMD 0x0654 268#define REG_BACAMCONTENT 0x0658 269#define REG_LBDLY 0x0660 270#define REG_FWDLY 0x0661 271#define REG_RXERR_RPT 0x0664 272#define REG_WMAC_TRXPTCL_CTL 0x0668 273 274#define REG_CAMCMD 0x0670 275#define REG_CAMWRITE 0x0674 276#define REG_CAMREAD 0x0678 277#define REG_CAMDBG 0x067C 278#define REG_SECCFG 0x0680 279 280#define REG_WOW_CTRL 0x0690 281#define REG_PSSTATUS 0x0691 282#define REG_PS_RX_INFO 0x0692 283#define REG_LPNAV_CTRL 0x0694 284#define REG_WKFMCAM_CMD 0x0698 285#define REG_WKFMCAM_RWD 0x069C 286#define REG_RXFLTMAP0 0x06A0 287#define REG_RXFLTMAP1 0x06A2 288#define REG_RXFLTMAP2 0x06A4 289#define REG_BCN_PSR_RPT 0x06A8 290#define REG_CALB32K_CTRL 0x06AC 291#define REG_PKT_MON_CTRL 0x06B4 292#define REG_BT_COEX_TABLE 0x06C0 293#define REG_WMAC_RESP_TXINFO 0x06D8 294 295#define REG_USB_INFO 0xFE17 296#define REG_USB_SPECIAL_OPTION 0xFE55 297#define REG_USB_DMA_AGG_TO 0xFE5B 298#define REG_USB_AGG_TO 0xFE5C 299#define REG_USB_AGG_TH 0xFE5D 300 301#define REG_TEST_USB_TXQS 0xFE48 302#define REG_TEST_SIE_VID 0xFE60 303#define REG_TEST_SIE_PID 0xFE62 304#define REG_TEST_SIE_OPTIONAL 0xFE64 305#define REG_TEST_SIE_CHIRP_K 0xFE65 306#define REG_TEST_SIE_PHY 0xFE66 307#define REG_TEST_SIE_MAC_ADDR 0xFE70 308#define REG_TEST_SIE_STRING 0xFE80 309 310#define REG_NORMAL_SIE_VID 0xFE60 311#define REG_NORMAL_SIE_PID 0xFE62 312#define REG_NORMAL_SIE_OPTIONAL 0xFE64 313#define REG_NORMAL_SIE_EP 0xFE65 314#define REG_NORMAL_SIE_PHY 0xFE68 315#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 316#define REG_NORMAL_SIE_STRING 0xFE80 317 318#define CR9346 REG_9346CR 319#define MSR (REG_CR + 2) 320#define ISR REG_HISR 321#define TSFR REG_TSFTR 322 323#define MACIDR0 REG_MACID 324#define MACIDR4 (REG_MACID + 4) 325 326#define PBP REG_PBP 327 328#define IDR0 MACIDR0 329#define IDR4 MACIDR4 330 331#define UNUSED_REGISTER 0x1BF 332#define DCAM UNUSED_REGISTER 333#define PSR UNUSED_REGISTER 334#define BBADDR UNUSED_REGISTER 335#define PHYDATAR UNUSED_REGISTER 336 337#define INVALID_BBRF_VALUE 0x12345678 338 339#define MAX_MSS_DENSITY_2T 0x13 340#define MAX_MSS_DENSITY_1T 0x0A 341 342#define CMDEEPROM_EN BIT(5) 343#define CMDEEPROM_SEL BIT(4) 344#define CMD9346CR_9356SEL BIT(4) 345#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 346#define AUTOLOAD_EFUSE CMDEEPROM_EN 347 348#define GPIOSEL_GPIO 0 349#define GPIOSEL_ENBT BIT(5) 350 351#define GPIO_IN REG_GPIO_PIN_CTRL 352#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 353#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 354#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 355 356#define MSR_NOLINK 0x00 357#define MSR_ADHOC 0x01 358#define MSR_INFRA 0x02 359#define MSR_AP 0x03 360 361#define RRSR_RSC_OFFSET 21 362#define RRSR_SHORT_OFFSET 23 363#define RRSR_RSC_BW_40M 0x600000 364#define RRSR_RSC_UPSUBCHNL 0x400000 365#define RRSR_RSC_LOWSUBCHNL 0x200000 366#define RRSR_SHORT 0x800000 367#define RRSR_1M BIT(0) 368#define RRSR_2M BIT(1) 369#define RRSR_5_5M BIT(2) 370#define RRSR_11M BIT(3) 371#define RRSR_6M BIT(4) 372#define RRSR_9M BIT(5) 373#define RRSR_12M BIT(6) 374#define RRSR_18M BIT(7) 375#define RRSR_24M BIT(8) 376#define RRSR_36M BIT(9) 377#define RRSR_48M BIT(10) 378#define RRSR_54M BIT(11) 379#define RRSR_MCS0 BIT(12) 380#define RRSR_MCS1 BIT(13) 381#define RRSR_MCS2 BIT(14) 382#define RRSR_MCS3 BIT(15) 383#define RRSR_MCS4 BIT(16) 384#define RRSR_MCS5 BIT(17) 385#define RRSR_MCS6 BIT(18) 386#define RRSR_MCS7 BIT(19) 387#define BRSR_ACKSHORTPMB BIT(23) 388 389#define RATR_1M 0x00000001 390#define RATR_2M 0x00000002 391#define RATR_55M 0x00000004 392#define RATR_11M 0x00000008 393#define RATR_6M 0x00000010 394#define RATR_9M 0x00000020 395#define RATR_12M 0x00000040 396#define RATR_18M 0x00000080 397#define RATR_24M 0x00000100 398#define RATR_36M 0x00000200 399#define RATR_48M 0x00000400 400#define RATR_54M 0x00000800 401#define RATR_MCS0 0x00001000 402#define RATR_MCS1 0x00002000 403#define RATR_MCS2 0x00004000 404#define RATR_MCS3 0x00008000 405#define RATR_MCS4 0x00010000 406#define RATR_MCS5 0x00020000 407#define RATR_MCS6 0x00040000 408#define RATR_MCS7 0x00080000 409#define RATR_MCS8 0x00100000 410#define RATR_MCS9 0x00200000 411#define RATR_MCS10 0x00400000 412#define RATR_MCS11 0x00800000 413#define RATR_MCS12 0x01000000 414#define RATR_MCS13 0x02000000 415#define RATR_MCS14 0x04000000 416#define RATR_MCS15 0x08000000 417 418#define RATE_1M BIT(0) 419#define RATE_2M BIT(1) 420#define RATE_5_5M BIT(2) 421#define RATE_11M BIT(3) 422#define RATE_6M BIT(4) 423#define RATE_9M BIT(5) 424#define RATE_12M BIT(6) 425#define RATE_18M BIT(7) 426#define RATE_24M BIT(8) 427#define RATE_36M BIT(9) 428#define RATE_48M BIT(10) 429#define RATE_54M BIT(11) 430#define RATE_MCS0 BIT(12) 431#define RATE_MCS1 BIT(13) 432#define RATE_MCS2 BIT(14) 433#define RATE_MCS3 BIT(15) 434#define RATE_MCS4 BIT(16) 435#define RATE_MCS5 BIT(17) 436#define RATE_MCS6 BIT(18) 437#define RATE_MCS7 BIT(19) 438#define RATE_MCS8 BIT(20) 439#define RATE_MCS9 BIT(21) 440#define RATE_MCS10 BIT(22) 441#define RATE_MCS11 BIT(23) 442#define RATE_MCS12 BIT(24) 443#define RATE_MCS13 BIT(25) 444#define RATE_MCS14 BIT(26) 445#define RATE_MCS15 BIT(27) 446 447#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 448#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ 449 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 450#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\ 451 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\ 452 RATR_MCS6 | RATR_MCS7) 453#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\ 454 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\ 455 RATR_MCS14 | RATR_MCS15) 456 457#define BW_OPMODE_20MHZ BIT(2) 458#define BW_OPMODE_5G BIT(1) 459#define BW_OPMODE_11J BIT(0) 460 461#define CAM_VALID BIT(15) 462#define CAM_NOTVALID 0x0000 463#define CAM_USEDK BIT(5) 464 465#define CAM_NONE 0x0 466#define CAM_WEP40 0x01 467#define CAM_TKIP 0x02 468#define CAM_AES 0x04 469#define CAM_WEP104 0x05 470 471#define TOTAL_CAM_ENTRY 32 472#define HALF_CAM_ENTRY 16 473 474#define CAM_WRITE BIT(16) 475#define CAM_READ 0x00000000 476#define CAM_POLLINIG BIT(31) 477 478#define SCR_USEDK 0x01 479#define SCR_TXSEC_ENABLE 0x02 480#define SCR_RXSEC_ENABLE 0x04 481 482#define WOW_PMEN BIT(0) 483#define WOW_WOMEN BIT(1) 484#define WOW_MAGIC BIT(2) 485#define WOW_UWF BIT(3) 486 487#define IMR8190_DISABLED 0x0 488#define IMR_BCNDMAINT6 BIT(31) 489#define IMR_BCNDMAINT5 BIT(30) 490#define IMR_BCNDMAINT4 BIT(29) 491#define IMR_BCNDMAINT3 BIT(28) 492#define IMR_BCNDMAINT2 BIT(27) 493#define IMR_BCNDMAINT1 BIT(26) 494#define IMR_BCNDOK8 BIT(25) 495#define IMR_BCNDOK7 BIT(24) 496#define IMR_BCNDOK6 BIT(23) 497#define IMR_BCNDOK5 BIT(22) 498#define IMR_BCNDOK4 BIT(21) 499#define IMR_BCNDOK3 BIT(20) 500#define IMR_BCNDOK2 BIT(19) 501#define IMR_BCNDOK1 BIT(18) 502#define IMR_TIMEOUT2 BIT(17) 503#define IMR_TIMEOUT1 BIT(16) 504#define IMR_TXFOVW BIT(15) 505#define IMR_PSTIMEOUT BIT(14) 506#define IMR_BCNINT BIT(13) 507#define IMR_RXFOVW BIT(12) 508#define IMR_RDU BIT(11) 509#define IMR_ATIMEND BIT(10) 510#define IMR_BDOK BIT(9) 511#define IMR_HIGHDOK BIT(8) 512#define IMR_TBDOK BIT(7) 513#define IMR_MGNTDOK BIT(6) 514#define IMR_TBDER BIT(5) 515#define IMR_BKDOK BIT(4) 516#define IMR_BEDOK BIT(3) 517#define IMR_VIDOK BIT(2) 518#define IMR_VODOK BIT(1) 519#define IMR_ROK BIT(0) 520 521#define IMR_TXERR BIT(11) 522#define IMR_RXERR BIT(10) 523#define IMR_CPWM BIT(8) 524#define IMR_OCPINT BIT(1) 525#define IMR_WLANOFF BIT(0) 526 527/* 8723E series PCIE Host IMR/ISR bit */ 528/* IMR DW0 Bit 0-31 */ 529#define PHIMR_TIMEOUT2 BIT(31) 530#define PHIMR_TIMEOUT1 BIT(30) 531#define PHIMR_PSTIMEOUT BIT(29) 532#define PHIMR_GTINT4 BIT(28) 533#define PHIMR_GTINT3 BIT(27) 534#define PHIMR_TXBCNERR BIT(26) 535#define PHIMR_TXBCNOK BIT(25) 536#define PHIMR_TSF_BIT32_TOGGLE BIT(24) 537#define PHIMR_BCNDMAINT3 BIT(23) 538#define PHIMR_BCNDMAINT2 BIT(22) 539#define PHIMR_BCNDMAINT1 BIT(21) 540#define PHIMR_BCNDMAINT0 BIT(20) 541#define PHIMR_BCNDOK3 BIT(19) 542#define PHIMR_BCNDOK2 BIT(18) 543#define PHIMR_BCNDOK1 BIT(17) 544#define PHIMR_BCNDOK0 BIT(16) 545#define PHIMR_HSISR_IND_ON BIT(15) 546#define PHIMR_BCNDMAINT_E BIT(14) 547#define PHIMR_ATIMEND_E BIT(13) 548#define PHIMR_ATIM_CTW_END BIT(12) 549#define PHIMR_HISRE_IND BIT(11) 550#define PHIMR_C2HCMD BIT(10) 551#define PHIMR_CPWM2 BIT(9) 552#define PHIMR_CPWM BIT(8) 553#define PHIMR_HIGHDOK BIT(7) 554#define PHIMR_MGNTDOK BIT(6) 555#define PHIMR_BKDOK BIT(5) 556#define PHIMR_BEDOK BIT(4) 557#define PHIMR_VIDOK BIT(3) 558#define PHIMR_VODOK BIT(2) 559#define PHIMR_RDU BIT(1) 560#define PHIMR_ROK BIT(0) 561 562/* PCIE Host Interrupt Status Extension bit */ 563#define PHIMR_BCNDMAINT7 BIT(23) 564#define PHIMR_BCNDMAINT6 BIT(22) 565#define PHIMR_BCNDMAINT5 BIT(21) 566#define PHIMR_BCNDMAINT4 BIT(20) 567#define PHIMR_BCNDOK7 BIT(19) 568#define PHIMR_BCNDOK6 BIT(18) 569#define PHIMR_BCNDOK5 BIT(17) 570#define PHIMR_BCNDOK4 BIT(16) 571/* bit12-15: RSVD */ 572#define PHIMR_TXERR BIT(11) 573#define PHIMR_RXERR BIT(10) 574#define PHIMR_TXFOVW BIT(9) 575#define PHIMR_RXFOVW BIT(8) 576/* bit2-7: RSVD */ 577#define PHIMR_OCPINT BIT(1) 578 579#define HWSET_MAX_SIZE 256 580#define EFUSE_MAX_SECTION 32 581#define EFUSE_REAL_CONTENT_LEN 512 582#define EFUSE_OOB_PROTECT_BYTES 15 583 584#define EEPROM_DEFAULT_TSSI 0x0 585#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 586#define EEPROM_DEFAULT_CRYSTALCAP 0x5 587#define EEPROM_DEFAULT_BOARDTYPE 0x02 588#define EEPROM_DEFAULT_TXPOWER 0x1010 589#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 590 591#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 592#define EEPROM_DEFAULT_THERMALMETER 0x12 593#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 594#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 595#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 596#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 597#define EEPROM_DEFAULT_HT20_DIFF 2 598#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 599#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 600#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 601 602#define EEPROM_DEFAULT_PID 0x1234 603#define EEPROM_DEFAULT_VID 0x5678 604#define EEPROM_DEFAULT_CUSTOMERID 0xAB 605#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 606#define EEPROM_DEFAULT_VERSION 0 607 608#define EEPROM_CHANNEL_PLAN_FCC 0x0 609#define EEPROM_CHANNEL_PLAN_IC 0x1 610#define EEPROM_CHANNEL_PLAN_ETSI 0x2 611#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 612#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 613#define EEPROM_CHANNEL_PLAN_MKK 0x5 614#define EEPROM_CHANNEL_PLAN_MKK1 0x6 615#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 616#define EEPROM_CHANNEL_PLAN_TELEC 0x8 617#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 618#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 619#define EEPROM_CHANNEL_PLAN_NCC 0xB 620#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 621 622#define EEPROM_CID_DEFAULT 0x0 623#define EEPROM_CID_TOSHIBA 0x4 624#define EEPROM_CID_CCX 0x10 625#define EEPROM_CID_QMI 0x0D 626#define EEPROM_CID_WHQL 0xFE 627 628#define RTL8192_EEPROM_ID 0x8129 629 630#define RTL8190_EEPROM_ID 0x8129 631#define EEPROM_HPON 0x02 632#define EEPROM_CLK 0x06 633#define EEPROM_TESTR 0x08 634 635#define EEPROM_VID 0x49 636#define EEPROM_DID 0x4B 637#define EEPROM_SVID 0x4D 638#define EEPROM_SMID 0x4F 639 640#define EEPROM_MAC_ADDR 0x67 641 642#define EEPROM_CCK_TX_PWR_INX 0x5A 643#define EEPROM_HT40_1S_TX_PWR_INX 0x60 644#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 645#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 646#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C 647#define EEPROM_HT40_MAX_PWR_OFFSET 0x25 648#define EEPROM_HT20_MAX_PWR_OFFSET 0x22 649 650#define EEPROM_THERMAL_METER 0x2a 651#define EEPROM_XTAL_K 0x78 652#define EEPROM_RF_OPT1 0x79 653#define EEPROM_RF_OPT2 0x7A 654#define EEPROM_RF_OPT3 0x7B 655#define EEPROM_RF_OPT4 0x7C 656#define EEPROM_CHANNEL_PLAN 0x28 657#define EEPROM_VERSION 0x30 658#define EEPROM_CUSTOMER_ID 0x31 659 660#define EEPROM_PWRDIFF 0x54 661 662#define EEPROM_TXPOWERCCK 0x10 663#define EEPROM_TXPOWERHT40_1S 0x16 664#define EEPROM_TXPOWERHT40_2SDIFF 0x66 665#define EEPROM_TXPOWERHT20DIFF 0x1C 666#define EEPROM_TXPOWER_OFDMDIFF 0x1F 667 668#define EEPROM_TXPWR_GROUP 0x22 669 670#define EEPROM_TSSI_A 0x29 671#define EEPROM_TSSI_B 0x77 672 673#define EEPROM_CHANNELPLAN 0x28 674 675#define RF_OPTION1 0x2B 676#define RF_OPTION2 0x2C 677#define RF_OPTION3 0x2D 678#define RF_OPTION4 0x2E 679 680#define STOPBECON BIT(6) 681#define STOPHIGHT BIT(5) 682#define STOPMGT BIT(4) 683#define STOPVO BIT(3) 684#define STOPVI BIT(2) 685#define STOPBE BIT(1) 686#define STOPBK BIT(0) 687 688#define RCR_APPFCS BIT(31) 689#define RCR_APP_MIC BIT(30) 690#define RCR_APP_ICV BIT(29) 691#define RCR_APP_PHYST_RXFF BIT(28) 692#define RCR_APP_BA_SSN BIT(27) 693#define RCR_ENMBID BIT(24) 694#define RCR_LSIGEN BIT(23) 695#define RCR_MFBEN BIT(22) 696#define RCR_HTC_LOC_CTRL BIT(14) 697#define RCR_AMF BIT(13) 698#define RCR_ACF BIT(12) 699#define RCR_ADF BIT(11) 700#define RCR_AICV BIT(9) 701#define RCR_ACRC32 BIT(8) 702#define RCR_CBSSID_BCN BIT(7) 703#define RCR_CBSSID_DATA BIT(6) 704#define RCR_CBSSID RCR_CBSSID_DATA 705#define RCR_APWRMGT BIT(5) 706#define RCR_ADD3 BIT(4) 707#define RCR_AB BIT(3) 708#define RCR_AM BIT(2) 709#define RCR_APM BIT(1) 710#define RCR_AAP BIT(0) 711#define RCR_MXDMA_OFFSET 8 712#define RCR_FIFO_OFFSET 13 713 714#define RSV_CTRL 0x001C 715#define RD_CTRL 0x0524 716 717#define REG_USB_INFO 0xFE17 718#define REG_USB_SPECIAL_OPTION 0xFE55 719#define REG_USB_DMA_AGG_TO 0xFE5B 720#define REG_USB_AGG_TO 0xFE5C 721#define REG_USB_AGG_TH 0xFE5D 722 723#define REG_USB_VID 0xFE60 724#define REG_USB_PID 0xFE62 725#define REG_USB_OPTIONAL 0xFE64 726#define REG_USB_CHIRP_K 0xFE65 727#define REG_USB_PHY 0xFE66 728#define REG_USB_MAC_ADDR 0xFE70 729#define REG_USB_HRPWM 0xFE58 730#define REG_USB_HCPWM 0xFE57 731 732#define SW18_FPWM BIT(3) 733 734#define ISO_MD2PP BIT(0) 735#define ISO_UA2USB BIT(1) 736#define ISO_UD2CORE BIT(2) 737#define ISO_PA2PCIE BIT(3) 738#define ISO_PD2CORE BIT(4) 739#define ISO_IP2MAC BIT(5) 740#define ISO_DIOP BIT(6) 741#define ISO_DIOE BIT(7) 742#define ISO_EB2CORE BIT(8) 743#define ISO_DIOR BIT(9) 744 745#define PWC_EV25V BIT(14) 746#define PWC_EV12V BIT(15) 747 748#define FEN_BBRSTB BIT(0) 749#define FEN_BB_GLB_RSTN BIT(1) 750#define FEN_USBA BIT(2) 751#define FEN_UPLL BIT(3) 752#define FEN_USBD BIT(4) 753#define FEN_DIO_PCIE BIT(5) 754#define FEN_PCIEA BIT(6) 755#define FEN_PPLL BIT(7) 756#define FEN_PCIED BIT(8) 757#define FEN_DIOE BIT(9) 758#define FEN_CPUEN BIT(10) 759#define FEN_DCORE BIT(11) 760#define FEN_ELDR BIT(12) 761#define FEN_DIO_RF BIT(13) 762#define FEN_HWPDN BIT(14) 763#define FEN_MREGEN BIT(15) 764 765#define PFM_LDALL BIT(0) 766#define PFM_ALDN BIT(1) 767#define PFM_LDKP BIT(2) 768#define PFM_WOWL BIT(3) 769#define ENPDN BIT(4) 770#define PDN_PL BIT(5) 771#define APFM_ONMAC BIT(8) 772#define APFM_OFF BIT(9) 773#define APFM_RSM BIT(10) 774#define AFSM_HSUS BIT(11) 775#define AFSM_PCIE BIT(12) 776#define APDM_MAC BIT(13) 777#define APDM_HOST BIT(14) 778#define APDM_HPDN BIT(15) 779#define RDY_MACON BIT(16) 780#define SUS_HOST BIT(17) 781#define ROP_ALD BIT(20) 782#define ROP_PWR BIT(21) 783#define ROP_SPS BIT(22) 784#define SOP_MRST BIT(25) 785#define SOP_FUSE BIT(26) 786#define SOP_ABG BIT(27) 787#define SOP_AMB BIT(28) 788#define SOP_RCK BIT(29) 789#define SOP_A8M BIT(30) 790#define XOP_BTCK BIT(31) 791 792#define ANAD16V_EN BIT(0) 793#define ANA8M BIT(1) 794#define MACSLP BIT(4) 795#define LOADER_CLK_EN BIT(5) 796#define _80M_SSC_DIS BIT(7) 797#define _80M_SSC_EN_HO BIT(8) 798#define PHY_SSC_RSTB BIT(9) 799#define SEC_CLK_EN BIT(10) 800#define MAC_CLK_EN BIT(11) 801#define SYS_CLK_EN BIT(12) 802#define RING_CLK_EN BIT(13) 803 804#define BOOT_FROM_EEPROM BIT(4) 805#define EEPROM_EN BIT(5) 806 807#define AFE_BGEN BIT(0) 808#define AFE_MBEN BIT(1) 809#define MAC_ID_EN BIT(7) 810 811#define WLOCK_ALL BIT(0) 812#define WLOCK_00 BIT(1) 813#define WLOCK_04 BIT(2) 814#define WLOCK_08 BIT(3) 815#define WLOCK_40 BIT(4) 816#define R_DIS_PRST_0 BIT(5) 817#define R_DIS_PRST_1 BIT(6) 818#define LOCK_ALL_EN BIT(7) 819 820#define RF_EN BIT(0) 821#define RF_RSTB BIT(1) 822#define RF_SDMRSTB BIT(2) 823 824#define LDA15_EN BIT(0) 825#define LDA15_STBY BIT(1) 826#define LDA15_OBUF BIT(2) 827#define LDA15_REG_VOS BIT(3) 828#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 829 830#define LDV12_EN BIT(0) 831#define LDV12_SDBY BIT(1) 832#define LPLDO_HSM BIT(2) 833#define LPLDO_LSM_DIS BIT(3) 834#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 835 836#define XTAL_EN BIT(0) 837#define XTAL_BSEL BIT(1) 838#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 839#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 840#define XTAL_GATE_USB BIT(8) 841#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 842#define XTAL_GATE_AFE BIT(11) 843#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 844#define XTAL_RF_GATE BIT(14) 845#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 846#define XTAL_GATE_DIG BIT(17) 847#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 848#define XTAL_BT_GATE BIT(20) 849#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 850#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 851 852#define CKDLY_AFE BIT(26) 853#define CKDLY_USB BIT(27) 854#define CKDLY_DIG BIT(28) 855#define CKDLY_BT BIT(29) 856 857#define APLL_EN BIT(0) 858#define APLL_320_EN BIT(1) 859#define APLL_FREF_SEL BIT(2) 860#define APLL_EDGE_SEL BIT(3) 861#define APLL_WDOGB BIT(4) 862#define APLL_LPFEN BIT(5) 863 864#define APLL_REF_CLK_13MHZ 0x1 865#define APLL_REF_CLK_19_2MHZ 0x2 866#define APLL_REF_CLK_20MHZ 0x3 867#define APLL_REF_CLK_25MHZ 0x4 868#define APLL_REF_CLK_26MHZ 0x5 869#define APLL_REF_CLK_38_4MHZ 0x6 870#define APLL_REF_CLK_40MHZ 0x7 871 872#define APLL_320EN BIT(14) 873#define APLL_80EN BIT(15) 874#define APLL_1MEN BIT(24) 875 876#define ALD_EN BIT(18) 877#define EF_PD BIT(19) 878#define EF_FLAG BIT(31) 879 880#define EF_TRPT BIT(7) 881#define LDOE25_EN BIT(31) 882 883#define RSM_EN BIT(0) 884#define TIMER_EN BIT(4) 885 886#define TRSW0EN BIT(2) 887#define TRSW1EN BIT(3) 888#define EROM_EN BIT(4) 889#define ENBT BIT(5) 890#define ENUART BIT(8) 891#define UART_910 BIT(9) 892#define ENPMAC BIT(10) 893#define SIC_SWRST BIT(11) 894#define ENSIC BIT(12) 895#define SIC_23 BIT(13) 896#define ENHDP BIT(14) 897#define SIC_LBK BIT(15) 898 899#define LED0PL BIT(4) 900#define LED1PL BIT(12) 901#define LED0DIS BIT(7) 902 903#define MCUFWDL_EN BIT(0) 904#define MCUFWDL_RDY BIT(1) 905#define FWDL_CHKSUM_RPT BIT(2) 906#define MACINI_RDY BIT(3) 907#define BBINI_RDY BIT(4) 908#define RFINI_RDY BIT(5) 909#define WINTINI_RDY BIT(6) 910#define CPRST BIT(23) 911 912#define XCLK_VLD BIT(0) 913#define ACLK_VLD BIT(1) 914#define UCLK_VLD BIT(2) 915#define PCLK_VLD BIT(3) 916#define PCIRSTB BIT(4) 917#define V15_VLD BIT(5) 918#define TRP_B15V_EN BIT(7) 919#define SIC_IDLE BIT(8) 920#define BD_MAC2 BIT(9) 921#define BD_MAC1 BIT(10) 922#define IC_MACPHY_MODE BIT(11) 923#define BT_FUNC BIT(16) 924#define VENDOR_ID BIT(19) 925#define PAD_HWPD_IDN BIT(22) 926#define TRP_VAUX_EN BIT(23) 927#define TRP_BT_EN BIT(24) 928#define BD_PKG_SEL BIT(25) 929#define BD_HCI_SEL BIT(26) 930#define TYPE_ID BIT(27) 931 932#define CHIP_VER_RTL_MASK 0xF000 933#define CHIP_VER_RTL_SHIFT 12 934 935#define REG_LBMODE (REG_CR + 3) 936 937#define HCI_TXDMA_EN BIT(0) 938#define HCI_RXDMA_EN BIT(1) 939#define TXDMA_EN BIT(2) 940#define RXDMA_EN BIT(3) 941#define PROTOCOL_EN BIT(4) 942#define SCHEDULE_EN BIT(5) 943#define MACTXEN BIT(6) 944#define MACRXEN BIT(7) 945#define ENSWBCN BIT(8) 946#define ENSEC BIT(9) 947 948#define _NETTYPE(x) (((x) & 0x3) << 16) 949#define MASK_NETTYPE 0x30000 950#define NT_NO_LINK 0x0 951#define NT_LINK_AD_HOC 0x1 952#define NT_LINK_AP 0x2 953#define NT_AS_AP 0x3 954 955#define _LBMODE(x) (((x) & 0xF) << 24) 956#define MASK_LBMODE 0xF000000 957#define LOOPBACK_NORMAL 0x0 958#define LOOPBACK_IMMEDIATELY 0xB 959#define LOOPBACK_MAC_DELAY 0x3 960#define LOOPBACK_PHY 0x1 961#define LOOPBACK_DMA 0x7 962 963#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 964#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 965#define _PSRX_MASK 0xF 966#define _PSTX_MASK 0xF0 967#define _PSRX(x) (x) 968#define _PSTX(x) ((x) << 4) 969 970#define PBP_64 0x0 971#define PBP_128 0x1 972#define PBP_256 0x2 973#define PBP_512 0x3 974#define PBP_1024 0x4 975 976#define RXDMA_ARBBW_EN BIT(0) 977#define RXSHFT_EN BIT(1) 978#define RXDMA_AGG_EN BIT(2) 979#define QS_VO_QUEUE BIT(8) 980#define QS_VI_QUEUE BIT(9) 981#define QS_BE_QUEUE BIT(10) 982#define QS_BK_QUEUE BIT(11) 983#define QS_MANAGER_QUEUE BIT(12) 984#define QS_HIGH_QUEUE BIT(13) 985 986#define HQSEL_VOQ BIT(0) 987#define HQSEL_VIQ BIT(1) 988#define HQSEL_BEQ BIT(2) 989#define HQSEL_BKQ BIT(3) 990#define HQSEL_MGTQ BIT(4) 991#define HQSEL_HIQ BIT(5) 992 993#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 994#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 995#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 996#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 997#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 998#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 999 1000#define QUEUE_LOW 1
1001#define QUEUE_NORMAL 2 1002#define QUEUE_HIGH 3 1003 1004#define _LLT_NO_ACTIVE 0x0 1005#define _LLT_WRITE_ACCESS 0x1 1006#define _LLT_READ_ACCESS 0x2 1007 1008#define _LLT_INIT_DATA(x) ((x) & 0xFF) 1009#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1010#define _LLT_OP(x) (((x) & 0x3) << 30) 1011#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1012 1013#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 1014#define BB_WRITE_EN BIT(30) 1015#define BB_READ_EN BIT(31) 1016 1017#define _HPQ(x) ((x) & 0xFF) 1018#define _LPQ(x) (((x) & 0xFF) << 8) 1019#define _PUBQ(x) (((x) & 0xFF) << 16) 1020#define _NPQ(x) ((x) & 0xFF) 1021 1022#define HPQ_PUBLIC_DIS BIT(24) 1023#define LPQ_PUBLIC_DIS BIT(25) 1024#define LD_RQPN BIT(31) 1025 1026#define BCN_VALID BIT(16) 1027#define BCN_HEAD(x) (((x) & 0xFF) << 8) 1028#define BCN_HEAD_MASK 0xFF00 1029 1030#define BLK_DESC_NUM_SHIFT 4 1031#define BLK_DESC_NUM_MASK 0xF 1032 1033#define DROP_DATA_EN BIT(9) 1034 1035#define EN_AMPDU_RTY_NEW BIT(7) 1036 1037#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1038 1039#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1040#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1041 1042#define RATE_REG_BITMAP_ALL 0xFFFFF 1043 1044#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1045 1046#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1047#define RRSR_RSC_RESERVED 0x0 1048#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1049#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1050#define RRSR_RSC_DUPLICATE_MODE 0x3 1051 1052#define USE_SHORT_G1 BIT(20) 1053 1054#define _AGGLMT_MCS0(x) ((x) & 0xF) 1055#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1056#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1057#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1058#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1059#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1060#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1061#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1062 1063#define RETRY_LIMIT_SHORT_SHIFT 8 1064#define RETRY_LIMIT_LONG_SHIFT 0 1065 1066#define _DARF_RC1(x) ((x) & 0x1F) 1067#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1068#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1069#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1070#define _DARF_RC5(x) ((x) & 0x1F) 1071#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1072#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1073#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1074 1075#define _RARF_RC1(x) ((x) & 0x1F) 1076#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1077#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1078#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1079#define _RARF_RC5(x) ((x) & 0x1F) 1080#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1081#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1082#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1083 1084#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1085#define AC_PARAM_ECW_MAX_OFFSET 12 1086#define AC_PARAM_ECW_MIN_OFFSET 8 1087#define AC_PARAM_AIFS_OFFSET 0 1088 1089#define _AIFS(x) (x) 1090#define _ECW_MAX_MIN(x) ((x) << 8) 1091#define _TXOP_LIMIT(x) ((x) << 16) 1092 1093#define _BCNIFS(x) ((x) & 0xFF) 1094#define _BCNECW(x) ((((x) & 0xF)) << 8) 1095 1096#define _LRL(x) ((x) & 0x3F) 1097#define _SRL(x) (((x) & 0x3F) << 8) 1098 1099#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1100#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) 1101 1102#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1103#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) 1104 1105#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1106 1107#define DIS_EDCA_CNT_DWN BIT(11) 1108 1109#define EN_MBSSID BIT(1) 1110#define EN_TXBCN_RPT BIT(2) 1111#define EN_BCN_FUNCTION BIT(3) 1112 1113#define TSFTR_RST BIT(0) 1114#define TSFTR1_RST BIT(1) 1115 1116#define STOP_BCNQ BIT(6) 1117 1118#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1119#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1120 1121#define ACMHW_HWEN BIT(0) 1122#define ACMHW_BEQEN BIT(1) 1123#define ACMHW_VIQEN BIT(2) 1124#define ACMHW_VOQEN BIT(3) 1125#define ACMHW_BEQSTATUS BIT(4) 1126#define ACMHW_VIQSTATUS BIT(5) 1127#define ACMHW_VOQSTATUS BIT(6) 1128 1129#define APSDOFF BIT(6) 1130#define APSDOFF_STATUS BIT(7) 1131 1132#define BW_20MHZ BIT(2) 1133 1134#define RATE_BITMAP_ALL 0xFFFFF 1135 1136#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1137 1138#define TSFRST BIT(0) 1139#define DIS_GCLK BIT(1) 1140#define PAD_SEL BIT(2) 1141#define PWR_ST BIT(6) 1142#define PWRBIT_OW_EN BIT(7) 1143#define ACRC BIT(8) 1144#define CFENDFORM BIT(9) 1145#define ICV BIT(10) 1146 1147#define AAP BIT(0) 1148#define APM BIT(1) 1149#define AM BIT(2) 1150#define AB BIT(3) 1151#define ADD3 BIT(4) 1152#define APWRMGT BIT(5) 1153#define CBSSID BIT(6) 1154#define CBSSID_DATA BIT(6) 1155#define CBSSID_BCN BIT(7) 1156#define ACRC32 BIT(8) 1157#define AICV BIT(9) 1158#define ADF BIT(11) 1159#define ACF BIT(12) 1160#define AMF BIT(13) 1161#define HTC_LOC_CTRL BIT(14) 1162#define UC_DATA_EN BIT(16) 1163#define BM_DATA_EN BIT(17) 1164#define MFBEN BIT(22) 1165#define LSIGEN BIT(23) 1166#define ENMBID BIT(24) 1167#define APP_BASSN BIT(27) 1168#define APP_PHYSTS BIT(28) 1169#define APP_ICV BIT(29) 1170#define APP_MIC BIT(30) 1171#define APP_FCS BIT(31) 1172 1173#define _MIN_SPACE(x) ((x) & 0x7) 1174#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1175 1176#define RXERR_TYPE_OFDM_PPDU 0 1177#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1178#define RXERR_TYPE_OFDM_MPDU_OK 2 1179#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1180#define RXERR_TYPE_CCK_PPDU 4 1181#define RXERR_TYPE_CCK_FALSE_ALARM 5 1182#define RXERR_TYPE_CCK_MPDU_OK 6 1183#define RXERR_TYPE_CCK_MPDU_FAIL 7 1184#define RXERR_TYPE_HT_PPDU 8 1185#define RXERR_TYPE_HT_FALSE_ALARM 9 1186#define RXERR_TYPE_HT_MPDU_TOTAL 10 1187#define RXERR_TYPE_HT_MPDU_OK 11 1188#define RXERR_TYPE_HT_MPDU_FAIL 12 1189#define RXERR_TYPE_RX_FULL_DROP 15 1190 1191#define RXERR_COUNTER_MASK 0xFFFFF 1192#define RXERR_RPT_RST BIT(27) 1193#define _RXERR_RPT_SEL(type) ((type) << 28) 1194 1195#define SCR_TXUSEDK BIT(0) 1196#define SCR_RXUSEDK BIT(1) 1197#define SCR_TXENCENABLE BIT(2) 1198#define SCR_RXDECENABLE BIT(3) 1199#define SCR_SKBYA2 BIT(4) 1200#define SCR_NOSKMC BIT(5) 1201#define SCR_TXBCUSEDK BIT(6) 1202#define SCR_RXBCUSEDK BIT(7) 1203 1204#define USB_IS_HIGH_SPEED 0 1205#define USB_IS_FULL_SPEED 1 1206#define USB_SPEED_MASK BIT(5) 1207 1208#define USB_NORMAL_SIE_EP_MASK 0xF 1209#define USB_NORMAL_SIE_EP_SHIFT 4 1210 1211#define USB_TEST_EP_MASK 0x30 1212#define USB_TEST_EP_SHIFT 4 1213 1214#define USB_AGG_EN BIT(3) 1215 1216#define MAC_ADDR_LEN 6 1217#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 1218 1219#define POLLING_LLT_THRESHOLD 20 1220#define POLLING_READY_TIMEOUT_COUNT 1000 1221 1222#define MAX_MSS_DENSITY_2T 0x13 1223#define MAX_MSS_DENSITY_1T 0x0A 1224 1225#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1226#define EPROM_CMD_CONFIG 0x3 1227#define EPROM_CMD_LOAD 1 1228 1229#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1230 1231#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1232 1233#define RPMAC_RESET 0x100 1234#define RPMAC_TXSTART 0x104 1235#define RPMAC_TXLEGACYSIG 0x108 1236#define RPMAC_TXHTSIG1 0x10c 1237#define RPMAC_TXHTSIG2 0x110 1238#define RPMAC_PHYDEBUG 0x114 1239#define RPMAC_TXPACKETNUM 0x118 1240#define RPMAC_TXIDLE 0x11c 1241#define RPMAC_TXMACHEADER0 0x120 1242#define RPMAC_TXMACHEADER1 0x124 1243#define RPMAC_TXMACHEADER2 0x128 1244#define RPMAC_TXMACHEADER3 0x12c 1245#define RPMAC_TXMACHEADER4 0x130 1246#define RPMAC_TXMACHEADER5 0x134 1247#define RPMAC_TXDADATYPE 0x138 1248#define RPMAC_TXRANDOMSEED 0x13c 1249#define RPMAC_CCKPLCPPREAMBLE 0x140 1250#define RPMAC_CCKPLCPHEADER 0x144 1251#define RPMAC_CCKCRC16 0x148 1252#define RPMAC_OFDMRXCRC32OK 0x170 1253#define RPMAC_OFDMRXCRC32ER 0x174 1254#define RPMAC_OFDMRXPARITYER 0x178 1255#define RPMAC_OFDMRXCRC8ER 0x17c 1256#define RPMAC_CCKCRXRC16ER 0x180 1257#define RPMAC_CCKCRXRC32ER 0x184 1258#define RPMAC_CCKCRXRC32OK 0x188 1259#define RPMAC_TXSTATUS 0x18c 1260 1261#define RFPGA0_RFMOD 0x800 1262 1263#define RFPGA0_TXINFO 0x804 1264#define RFPGA0_PSDFUNCTION 0x808 1265 1266#define RFPGA0_TXGAINSTAGE 0x80c 1267 1268#define RFPGA0_RFTIMING1 0x810 1269#define RFPGA0_RFTIMING2 0x814 1270 1271#define RFPGA0_XA_HSSIPARAMETER1 0x820 1272#define RFPGA0_XA_HSSIPARAMETER2 0x824 1273#define RFPGA0_XB_HSSIPARAMETER1 0x828 1274#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1275 1276#define RFPGA0_XA_LSSIPARAMETER 0x840 1277#define RFPGA0_XB_LSSIPARAMETER 0x844 1278 1279#define RFPGA0_RFWAKEUPPARAMETER 0x850 1280#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1281 1282#define RFPGA0_XAB_SWITCHCONTROL 0x858 1283#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1284 1285#define RFPGA0_XA_RFINTERFACEOE 0x860 1286#define RFPGA0_XB_RFINTERFACEOE 0x864 1287 1288#define RFPGA0_XAB_RFINTERFACESW 0x870 1289#define RFPGA0_XCD_RFINTERFACESW 0x874 1290 1291#define RFPGA0_XAB_RFPARAMETER 0x878 1292#define RFPGA0_XCD_RFPARAMETER 0x87c 1293 1294#define RFPGA0_ANALOGPARAMETER1 0x880 1295#define RFPGA0_ANALOGPARAMETER2 0x884 1296#define RFPGA0_ANALOGPARAMETER3 0x888 1297#define RFPGA0_ANALOGPARAMETER4 0x88c 1298 1299#define RFPGA0_XA_LSSIREADBACK 0x8a0 1300#define RFPGA0_XB_LSSIREADBACK 0x8a4 1301#define RFPGA0_XC_LSSIREADBACK 0x8a8 1302#define RFPGA0_XD_LSSIREADBACK 0x8ac 1303 1304#define RFPGA0_PSDREPORT 0x8b4 1305#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1306#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1307#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1308#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1309 1310#define RFPGA1_RFMOD 0x900 1311 1312#define RFPGA1_TXBLOCK 0x904 1313#define RFPGA1_DEBUGSELECT 0x908 1314#define RFPGA1_TXINFO 0x90c 1315 1316#define RCCK0_SYSTEM 0xa00 1317 1318#define RCCK0_AFESETTING 0xa04 1319#define RCCK0_CCA 0xa08 1320 1321#define RCCK0_RXAGC1 0xa0c 1322#define RCCK0_RXAGC2 0xa10 1323 1324#define RCCK0_RXHP 0xa14 1325 1326#define RCCK0_DSPPARAMETER1 0xa18 1327#define RCCK0_DSPPARAMETER2 0xa1c 1328 1329#define RCCK0_TXFILTER1 0xa20 1330#define RCCK0_TXFILTER2 0xa24 1331#define RCCK0_DEBUGPORT 0xa28 1332#define RCCK0_FALSEALARMREPORT 0xa2c 1333#define RCCK0_TRSSIREPORT 0xa50 1334#define RCCK0_RXREPORT 0xa54 1335#define RCCK0_FACOUNTERLOWER 0xa5c 1336#define RCCK0_FACOUNTERUPPER 0xa58 1337 1338#define ROFDM0_LSTF 0xc00 1339 1340#define ROFDM0_TRXPATHENABLE 0xc04 1341#define ROFDM0_TRMUXPAR 0xc08 1342#define ROFDM0_TRSWISOLATION 0xc0c 1343 1344#define ROFDM0_XARXAFE 0xc10 1345#define ROFDM0_XARXIQIMBALANCE 0xc14 1346#define ROFDM0_XBRXAFE 0xc18 1347#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1348#define ROFDM0_XCRXAFE 0xc20 1349#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1350#define ROFDM0_XDRXAFE 0xc28 1351#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1352 1353#define ROFDM0_RXDETECTOR1 0xc30 1354#define ROFDM0_RXDETECTOR2 0xc34 1355#define ROFDM0_RXDETECTOR3 0xc38 1356#define ROFDM0_RXDETECTOR4 0xc3c 1357 1358#define ROFDM0_RXDSP 0xc40 1359#define ROFDM0_CFOANDDAGC 0xc44 1360#define ROFDM0_CCADROPTHRESHOLD 0xc48 1361#define ROFDM0_ECCATHRESHOLD 0xc4c 1362 1363#define ROFDM0_XAAGCCORE1 0xc50 1364#define ROFDM0_XAAGCCORE2 0xc54 1365#define ROFDM0_XBAGCCORE1 0xc58 1366#define ROFDM0_XBAGCCORE2 0xc5c 1367#define ROFDM0_XCAGCCORE1 0xc60 1368#define ROFDM0_XCAGCCORE2 0xc64 1369#define ROFDM0_XDAGCCORE1 0xc68 1370#define ROFDM0_XDAGCCORE2 0xc6c 1371 1372#define ROFDM0_AGCPARAMETER1 0xc70 1373#define ROFDM0_AGCPARAMETER2 0xc74 1374#define ROFDM0_AGCRSSITABLE 0xc78 1375#define ROFDM0_HTSTFAGC 0xc7c 1376 1377#define ROFDM0_XATXIQIMBALANCE 0xc80 1378#define ROFDM0_XATXAFE 0xc84 1379#define ROFDM0_XBTXIQIMBALANCE 0xc88 1380#define ROFDM0_XBTXAFE 0xc8c 1381#define ROFDM0_XCTXIQIMBALANCE 0xc90 1382#define ROFDM0_XCTXAFE 0xc94 1383#define ROFDM0_XDTXIQIMBALANCE 0xc98 1384#define ROFDM0_XDTXAFE 0xc9c 1385 1386#define ROFDM0_RXIQEXTANTA 0xca0 1387 1388#define ROFDM0_RXHPPARAMETER 0xce0 1389#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1390#define ROFDM0_FRAMESYNC 0xcf0 1391#define ROFDM0_DFSREPORT 0xcf4 1392#define ROFDM0_TXCOEFF1 0xca4 1393#define ROFDM0_TXCOEFF2 0xca8 1394#define ROFDM0_TXCOEFF3 0xcac 1395#define ROFDM0_TXCOEFF4 0xcb0 1396#define ROFDM0_TXCOEFF5 0xcb4 1397#define ROFDM0_TXCOEFF6 0xcb8 1398 1399#define ROFDM1_LSTF 0xd00 1400#define ROFDM1_TRXPATHENABLE 0xd04 1401 1402#define ROFDM1_CF0 0xd08 1403#define ROFDM1_CSI1 0xd10 1404#define ROFDM1_SBD 0xd14 1405#define ROFDM1_CSI2 0xd18 1406#define ROFDM1_CFOTRACKING 0xd2c 1407#define ROFDM1_TRXMESAURE1 0xd34 1408#define ROFDM1_INTFDET 0xd3c 1409#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1410#define ROFDM1_PSEUDONOISESTATECD 0xd54 1411#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1412 1413#define ROFDM_PHYCOUNTER1 0xda0 1414#define ROFDM_PHYCOUNTER2 0xda4 1415#define ROFDM_PHYCOUNTER3 0xda8 1416 1417#define ROFDM_SHORTCFOAB 0xdac 1418#define ROFDM_SHORTCFOCD 0xdb0 1419#define ROFDM_LONGCFOAB 0xdb4 1420#define ROFDM_LONGCFOCD 0xdb8 1421#define ROFDM_TAILCF0AB 0xdbc 1422#define ROFDM_TAILCF0CD 0xdc0 1423#define ROFDM_PWMEASURE1 0xdc4 1424#define ROFDM_PWMEASURE2 0xdc8 1425#define ROFDM_BWREPORT 0xdcc 1426#define ROFDM_AGCREPORT 0xdd0 1427#define ROFDM_RXSNR 0xdd4 1428#define ROFDM_RXEVMCSI 0xdd8 1429#define ROFDM_SIGREPORT 0xddc 1430 1431#define RTXAGC_A_RATE18_06 0xe00 1432#define RTXAGC_A_RATE54_24 0xe04 1433#define RTXAGC_A_CCK1_MCS32 0xe08 1434#define RTXAGC_A_MCS03_MCS00 0xe10 1435#define RTXAGC_A_MCS07_MCS04 0xe14 1436#define RTXAGC_A_MCS11_MCS08 0xe18 1437#define RTXAGC_A_MCS15_MCS12 0xe1c 1438 1439#define RTXAGC_B_RATE18_06 0x830 1440#define RTXAGC_B_RATE54_24 0x834 1441#define RTXAGC_B_CCK1_55_MCS32 0x838 1442#define RTXAGC_B_MCS03_MCS00 0x83c 1443#define RTXAGC_B_MCS07_MCS04 0x848 1444#define RTXAGC_B_MCS11_MCS08 0x84c 1445#define RTXAGC_B_MCS15_MCS12 0x868 1446#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1447 1448#define RZEBRA1_HSSIENABLE 0x0 1449#define RZEBRA1_TRXENABLE1 0x1 1450#define RZEBRA1_TRXENABLE2 0x2 1451#define RZEBRA1_AGC 0x4 1452#define RZEBRA1_CHARGEPUMP 0x5 1453#define RZEBRA1_CHANNEL 0x7 1454 1455#define RZEBRA1_TXGAIN 0x8 1456#define RZEBRA1_TXLPF 0x9 1457#define RZEBRA1_RXLPF 0xb 1458#define RZEBRA1_RXHPFCORNER 0xc 1459 1460#define RGLOBALCTRL 0 1461#define RRTL8256_TXLPF 19 1462#define RRTL8256_RXLPF 11 1463#define RRTL8258_TXLPF 0x11 1464#define RRTL8258_RXLPF 0x13 1465#define RRTL8258_RSSILPF 0xa 1466 1467#define RF_AC 0x00 1468 1469#define RF_IQADJ_G1 0x01 1470#define RF_IQADJ_G2 0x02 1471#define RF_POW_TRSW 0x05 1472 1473#define RF_GAIN_RX 0x06 1474#define RF_GAIN_TX 0x07 1475 1476#define RF_TXM_IDAC 0x08 1477#define RF_BS_IQGEN 0x0F 1478 1479#define RF_MODE1 0x10 1480#define RF_MODE2 0x11 1481 1482#define RF_RX_AGC_HP 0x12 1483#define RF_TX_AGC 0x13 1484#define RF_BIAS 0x14 1485#define RF_IPA 0x15 1486#define RF_POW_ABILITY 0x17 1487#define RF_MODE_AG 0x18 1488#define RRFCHANNEL 0x18 1489#define RF_CHNLBW 0x18 1490#define RF_TOP 0x19 1491 1492#define RF_RX_G1 0x1A 1493#define RF_RX_G2 0x1B 1494 1495#define RF_RX_BB2 0x1C 1496#define RF_RX_BB1 0x1D 1497 1498#define RF_RCK1 0x1E 1499#define RF_RCK2 0x1F 1500 1501#define RF_TX_G1 0x20 1502#define RF_TX_G2 0x21 1503#define RF_TX_G3 0x22 1504 1505#define RF_TX_BB1 0x23 1506#define RF_T_METER 0x24 1507 1508#define RF_SYN_G1 0x25 1509#define RF_SYN_G2 0x26 1510#define RF_SYN_G3 0x27 1511#define RF_SYN_G4 0x28 1512#define RF_SYN_G5 0x29 1513#define RF_SYN_G6 0x2A 1514#define RF_SYN_G7 0x2B 1515#define RF_SYN_G8 0x2C 1516 1517#define RF_RCK_OS 0x30 1518#define RF_TXPA_G1 0x31 1519#define RF_TXPA_G2 0x32 1520#define RF_TXPA_G3 0x33 1521 1522#define BBBRESETB 0x100 1523#define BGLOBALRESETB 0x200 1524#define BOFDMTXSTART 0x4 1525#define BCCKTXSTART 0x8 1526#define BCRC32DEBUG 0x100 1527#define BPMACLOOPBACK 0x10 1528#define BTXLSIG 0xffffff 1529#define BOFDMTXRATE 0xf 1530#define BOFDMTXRESERVED 0x10 1531#define BOFDMTXLENGTH 0x1ffe0 1532#define BOFDMTXPARITY 0x20000 1533#define BTXHTSIG1 0xffffff 1534#define BTXHTMCSRATE 0x7f 1535#define BTXHTBW 0x80 1536#define BTXHTLENGTH 0xffff00 1537#define BTXHTSIG2 0xffffff 1538#define BTXHTSMOOTHING 0x1 1539#define BTXHTSOUNDING 0x2 1540#define BTXHTRESERVED 0x4 1541#define BTXHTAGGREATION 0x8 1542#define BTXHTSTBC 0x30 1543#define BTXHTADVANCECODING 0x40 1544#define BTXHTSHORTGI 0x80 1545#define BTXHTNUMBERHT_LTF 0x300 1546#define BTXHTCRC8 0x3fc00 1547#define BCOUNTERRESET 0x10000 1548#define BNUMOFOFDMTX 0xffff 1549#define BNUMOFCCKTX 0xffff0000 1550#define BTXIDLEINTERVAL 0xffff 1551#define BOFDMSERVICE 0xffff0000 1552#define BTXMACHEADER 0xffffffff 1553#define BTXDATAINIT 0xff 1554#define BTXHTMODE 0x100 1555#define BTXDATATYPE 0x30000 1556#define BTXRANDOMSEED 0xffffffff 1557#define BCCKTXPREAMBLE 0x1 1558#define BCCKTXSFD 0xffff0000 1559#define BCCKTXSIG 0xff 1560#define BCCKTXSERVICE 0xff00 1561#define BCCKLENGTHEXT 0x8000 1562#define BCCKTXLENGHT 0xffff0000 1563#define BCCKTXCRC16 0xffff 1564#define BCCKTXSTATUS 0x1 1565#define BOFDMTXSTATUS 0x2 1566#define IS_BB_REG_OFFSET_92S(_offset) \ 1567 ((_offset >= 0x800) && (_offset <= 0xfff)) 1568 1569#define BRFMOD 0x1 1570#define BJAPANMODE 0x2 1571#define BCCKTXSC 0x30 1572#define BCCKEN 0x1000000 1573#define BOFDMEN 0x2000000 1574 1575#define BOFDMRXADCPHASE 0x10000 1576#define BOFDMTXDACPHASE 0x40000 1577#define BXATXAGC 0x3f 1578 1579#define BXBTXAGC 0xf00 1580#define BXCTXAGC 0xf000 1581#define BXDTXAGC 0xf0000 1582 1583#define BPASTART 0xf0000000 1584#define BTRSTART 0x00f00000 1585#define BRFSTART 0x0000f000 1586#define BBBSTART 0x000000f0 1587#define BBBCCKSTART 0x0000000f 1588#define BPAEND 0xf 1589#define BTREND 0x0f000000 1590#define BRFEND 0x000f0000 1591#define BCCAMASK 0x000000f0 1592#define BR2RCCAMASK 0x00000f00 1593#define BHSSI_R2TDELAY 0xf8000000 1594#define BHSSI_T2RDELAY 0xf80000 1595#define BCONTXHSSI 0x400 1596#define BIGFROMCCK 0x200 1597#define BAGCADDRESS 0x3f 1598#define BRXHPTX 0x7000 1599#define BRXHP2RX 0x38000 1600#define BRXHPCCKINI 0xc0000 1601#define BAGCTXCODE 0xc00000 1602#define BAGCRXCODE 0x300000 1603 1604#define B3WIREDATALENGTH 0x800 1605#define B3WIREADDREAALENGTH 0x400 1606 1607#define B3WIRERFPOWERDOWN 0x1 1608#define B5GPAPEPOLARITY 0x40000000 1609#define B2GPAPEPOLARITY 0x80000000 1610#define BRFSW_TXDEFAULTANT 0x3 1611#define BRFSW_TXOPTIONANT 0x30 1612#define BRFSW_RXDEFAULTANT 0x300 1613#define BRFSW_RXOPTIONANT 0x3000 1614#define BRFSI_3WIREDATA 0x1 1615#define BRFSI_3WIRECLOCK 0x2 1616#define BRFSI_3WIRELOAD 0x4 1617#define BRFSI_3WIRERW 0x8 1618#define BRFSI_3WIRE 0xf 1619 1620#define BRFSI_RFENV 0x10 1621 1622#define BRFSI_TRSW 0x20 1623#define BRFSI_TRSWB 0x40 1624#define BRFSI_ANTSW 0x100 1625#define BRFSI_ANTSWB 0x200 1626#define BRFSI_PAPE 0x400 1627#define BRFSI_PAPE5G 0x800 1628#define BBANDSELECT 0x1 1629#define BHTSIG2_GI 0x80 1630#define BHTSIG2_SMOOTHING 0x01 1631#define BHTSIG2_SOUNDING 0x02 1632#define BHTSIG2_AGGREATON 0x08 1633#define BHTSIG2_STBC 0x30 1634#define BHTSIG2_ADVCODING 0x40 1635#define BHTSIG2_NUMOFHTLTF 0x300 1636#define BHTSIG2_CRC8 0x3fc 1637#define BHTSIG1_MCS 0x7f 1638#define BHTSIG1_BANDWIDTH 0x80 1639#define BHTSIG1_HTLENGTH 0xffff 1640#define BLSIG_RATE 0xf 1641#define BLSIG_RESERVED 0x10 1642#define BLSIG_LENGTH 0x1fffe 1643#define BLSIG_PARITY 0x20 1644#define BCCKRXPHASE 0x4 1645 1646#define BLSSIREADADDRESS 0x7f800000 1647#define BLSSIREADEDGE 0x80000000 1648 1649#define BLSSIREADBACKDATA 0xfffff 1650 1651#define BLSSIREADOKFLAG 0x1000 1652#define BCCKSAMPLERATE 0x8 1653#define BREGULATOR0STANDBY 0x1 1654#define BREGULATORPLLSTANDBY 0x2 1655#define BREGULATOR1STANDBY 0x4 1656#define BPLLPOWERUP 0x8 1657#define BDPLLPOWERUP 0x10 1658#define BDA10POWERUP 0x20 1659#define BAD7POWERUP 0x200 1660#define BDA6POWERUP 0x2000 1661#define BXTALPOWERUP 0x4000 1662#define B40MDCLKPOWERUP 0x8000 1663#define BDA6DEBUGMODE 0x20000 1664#define BDA6SWING 0x380000 1665 1666#define BADCLKPHASE 0x4000000 1667#define B80MCLKDELAY 0x18000000 1668#define BAFEWATCHDOGENABLE 0x20000000 1669 1670#define BXTALCAP01 0xc0000000 1671#define BXTALCAP23 0x3 1672#define BXTALCAP92X 0x0f000000 1673#define BXTALCAP 0x0f000000 1674 1675#define BINTDIFCLKENABLE 0x400 1676#define BEXTSIGCLKENABLE 0x800 1677#define BBANDGAP_MBIAS_POWERUP 0x10000 1678#define BAD11SH_GAIN 0xc0000 1679#define BAD11NPUT_RANGE 0x700000 1680#define BAD110P_CURRENT 0x3800000 1681#define BLPATH_LOOPBACK 0x4000000 1682#define BQPATH_LOOPBACK 0x8000000 1683#define BAFE_LOOPBACK 0x10000000 1684#define BDA10_SWING 0x7e0 1685#define BDA10_REVERSE 0x800 1686#define BDA_CLK_SOURCE 0x1000 1687#define BDA7INPUT_RANGE 0x6000 1688#define BDA7_GAIN 0x38000 1689#define BDA7OUTPUT_CM_MODE 0x40000 1690#define BDA7INPUT_CM_MODE 0x380000 1691#define BDA7CURRENT 0xc00000 1692#define BREGULATOR_ADJUST 0x7000000 1693#define BAD11POWERUP_ATTX 0x1 1694#define BDA10PS_ATTX 0x10 1695#define BAD11POWERUP_ATRX 0x100 1696#define BDA10PS_ATRX 0x1000 1697#define BCCKRX_AGC_FORMAT 0x200 1698#define BPSDFFT_SAMPLE_POINT 0xc000 1699#define BPSD_AVERAGE_NUM 0x3000 1700#define BIQPATH_CONTROL 0xc00 1701#define BPSD_FREQ 0x3ff 1702#define BPSD_ANTENNA_PATH 0x30 1703#define BPSD_IQ_SWITCH 0x40 1704#define BPSD_RX_TRIGGER 0x400000 1705#define BPSD_TX_TRIGGER 0x80000000 1706#define BPSD_SINE_TONE_SCALE 0x7f000000 1707#define BPSD_REPORT 0xffff 1708 1709#define BOFDM_TXSC 0x30000000 1710#define BCCK_TXON 0x1 1711#define BOFDM_TXON 0x2 1712#define BDEBUG_PAGE 0xfff 1713#define BDEBUG_ITEM 0xff 1714#define BANTL 0x10 1715#define BANT_NONHT 0x100 1716#define BANT_HT1 0x1000 1717#define BANT_HT2 0x10000 1718#define BANT_HT1S1 0x100000 1719#define BANT_NONHTS1 0x1000000 1720 1721#define BCCK_BBMODE 0x3 1722#define BCCK_TXPOWERSAVING 0x80 1723#define BCCK_RXPOWERSAVING 0x40 1724 1725#define BCCK_SIDEBAND 0x10 1726 1727#define BCCK_SCRAMBLE 0x8 1728#define BCCK_ANTDIVERSITY 0x8000 1729#define BCCK_CARRIER_RECOVERY 0x4000 1730#define BCCK_TXRATE 0x3000 1731#define BCCK_DCCANCEL 0x0800 1732#define BCCK_ISICANCEL 0x0400 1733#define BCCK_MATCH_FILTER 0x0200 1734#define BCCK_EQUALIZER 0x0100 1735#define BCCK_PREAMBLE_DETECT 0x800000 1736#define BCCK_FAST_FALSECCA 0x400000 1737#define BCCK_CH_ESTSTART 0x300000 1738#define BCCK_CCA_COUNT 0x080000 1739#define BCCK_CS_LIM 0x070000 1740#define BCCK_BIST_MODE 0x80000000 1741#define BCCK_CCAMASK 0x40000000 1742#define BCCK_TX_DAC_PHASE 0x4 1743#define BCCK_RX_ADC_PHASE 0x20000000 1744#define BCCKR_CP_MODE 0x0100 1745#define BCCK_TXDC_OFFSET 0xf0 1746#define BCCK_RXDC_OFFSET 0xf 1747#define BCCK_CCA_MODE 0xc000 1748#define BCCK_FALSECS_LIM 0x3f00 1749#define BCCK_CS_RATIO 0xc00000 1750#define BCCK_CORGBIT_SEL 0x300000 1751#define BCCK_PD_LIM 0x0f0000 1752#define BCCK_NEWCCA 0x80000000 1753#define BCCK_RXHP_OF_IG 0x8000 1754#define BCCK_RXIG 0x7f00 1755#define BCCK_LNA_POLARITY 0x800000 1756#define BCCK_RX1ST_BAIN 0x7f0000 1757#define BCCK_RF_EXTEND 0x20000000 1758#define BCCK_RXAGC_SATLEVEL 0x1f000000 1759#define BCCK_RXAGC_SATCOUNT 0xe0 1760#define BCCKRXRFSETTLE 0x1f 1761#define BCCK_FIXED_RXAGC 0x8000 1762#define BCCK_ANTENNA_POLARITY 0x2000 1763#define BCCK_TXFILTER_TYPE 0x0c00 1764#define BCCK_RXAGC_REPORTTYPE 0x0300 1765#define BCCK_RXDAGC_EN 0x80000000 1766#define BCCK_RXDAGC_PERIOD 0x20000000 1767#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1768#define BCCK_TIMING_RECOVERY 0x800000 1769#define BCCK_TXC0 0x3f0000 1770#define BCCK_TXC1 0x3f000000 1771#define BCCK_TXC2 0x3f 1772#define BCCK_TXC3 0x3f00 1773#define BCCK_TXC4 0x3f0000 1774#define BCCK_TXC5 0x3f000000 1775#define BCCK_TXC6 0x3f 1776#define BCCK_TXC7 0x3f00 1777#define BCCK_DEBUGPORT 0xff0000 1778#define BCCK_DAC_DEBUG 0x0f000000 1779#define BCCK_FALSEALARM_ENABLE 0x8000 1780#define BCCK_FALSEALARM_READ 0x4000 1781#define BCCK_TRSSI 0x7f 1782#define BCCK_RXAGC_REPORT 0xfe 1783#define BCCK_RXREPORT_ANTSEL 0x80000000 1784#define BCCK_RXREPORT_MFOFF 0x40000000 1785#define BCCK_RXREPORT_SQLOSS 0x20000000 1786#define BCCK_RXREPORT_PKTLOSS 0x10000000 1787#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1788#define BCCK_RXREPORT_RATEERROR 0x04000000 1789#define BCCK_RXREPORT_RXRATE 0x03000000 1790#define BCCK_RXFA_COUNTER_LOWER 0xff 1791#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1792#define BCCK_RXHPAGC_START 0xe000 1793#define BCCK_RXHPAGC_FINAL 0x1c00 1794#define BCCK_RXFALSEALARM_ENABLE 0x8000 1795#define BCCK_FACOUNTER_FREEZE 0x4000 1796#define BCCK_TXPATH_SEL 0x10000000 1797#define BCCK_DEFAULT_RXPATH 0xc000000 1798#define BCCK_OPTION_RXPATH 0x3000000 1799 1800#define BNUM_OFSTF 0x3 1801#define BSHIFT_L 0xc0 1802#define BGI_TH 0xc 1803#define BRXPATH_A 0x1 1804#define BRXPATH_B 0x2 1805#define BRXPATH_C 0x4 1806#define BRXPATH_D 0x8 1807#define BTXPATH_A 0x1 1808#define BTXPATH_B 0x2 1809#define BTXPATH_C 0x4 1810#define BTXPATH_D 0x8 1811#define BTRSSI_FREQ 0x200 1812#define BADC_BACKOFF 0x3000 1813#define BDFIR_BACKOFF 0xc000 1814#define BTRSSI_LATCH_PHASE 0x10000 1815#define BRX_LDC_OFFSET 0xff 1816#define BRX_QDC_OFFSET 0xff00 1817#define BRX_DFIR_MODE 0x1800000 1818#define BRX_DCNF_TYPE 0xe000000 1819#define BRXIQIMB_A 0x3ff 1820#define BRXIQIMB_B 0xfc00 1821#define BRXIQIMB_C 0x3f0000 1822#define BRXIQIMB_D 0xffc00000 1823#define BDC_DC_NOTCH 0x60000 1824#define BRXNB_NOTCH 0x1f000000 1825#define BPD_TH 0xf 1826#define BPD_TH_OPT2 0xc000 1827#define BPWED_TH 0x700 1828#define BIFMF_WIN_L 0x800 1829#define BPD_OPTION 0x1000 1830#define BMF_WIN_L 0xe000 1831#define BBW_SEARCH_L 0x30000 1832#define BWIN_ENH_L 0xc0000 1833#define BBW_TH 0x700000 1834#define BED_TH2 0x3800000 1835#define BBW_OPTION 0x4000000 1836#define BRADIO_TH 0x18000000 1837#define BWINDOW_L 0xe0000000 1838#define BSBD_OPTION 0x1 1839#define BFRAME_TH 0x1c 1840#define BFS_OPTION 0x60 1841#define BDC_SLOPE_CHECK 0x80 1842#define BFGUARD_COUNTER_DC_L 0xe00 1843#define BFRAME_WEIGHT_SHORT 0x7000 1844#define BSUB_TUNE 0xe00000 1845#define BFRAME_DC_LENGTH 0xe000000 1846#define BSBD_START_OFFSET 0x30000000 1847#define BFRAME_TH_2 0x7 1848#define BFRAME_GI2_TH 0x38 1849#define BGI2_SYNC_EN 0x40 1850#define BSARCH_SHORT_EARLY 0x300 1851#define BSARCH_SHORT_LATE 0xc00 1852#define BSARCH_GI2_LATE 0x70000 1853#define BCFOANTSUM 0x1 1854#define BCFOACC 0x2 1855#define BCFOSTARTOFFSET 0xc 1856#define BCFOLOOPBACK 0x70 1857#define BCFOSUMWEIGHT 0x80 1858#define BDAGCENABLE 0x10000 1859#define BTXIQIMB_A 0x3ff 1860#define BTXIQIMB_b 0xfc00 1861#define BTXIQIMB_C 0x3f0000 1862#define BTXIQIMB_D 0xffc00000 1863#define BTXIDCOFFSET 0xff 1864#define BTXIQDCOFFSET 0xff00 1865#define BTXDFIRMODE 0x10000 1866#define BTXPESUDO_NOISEON 0x4000000 1867#define BTXPESUDO_NOISE_A 0xff 1868#define BTXPESUDO_NOISE_B 0xff00 1869#define BTXPESUDO_NOISE_C 0xff0000 1870#define BTXPESUDO_NOISE_D 0xff000000 1871#define BCCA_DROPOPTION 0x20000 1872#define BCCA_DROPTHRES 0xfff00000 1873#define BEDCCA_H 0xf 1874#define BEDCCA_L 0xf0 1875#define BLAMBDA_ED 0x300 1876#define BRX_INITIALGAIN 0x7f 1877#define BRX_ANTDIV_EN 0x80 1878#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 1879#define BRX_HIGHPOWER_FLOW 0x8000 1880#define BRX_AGC_FREEZE_THRES 0xc0000 1881#define BRX_FREEZESTEP_AGC1 0x300000 1882#define BRX_FREEZESTEP_AGC2 0xc00000 1883#define BRX_FREEZESTEP_AGC3 0x3000000 1884#define BRX_FREEZESTEP_AGC0 0xc000000 1885#define BRXRSSI_CMP_EN 0x10000000 1886#define BRXQUICK_AGCEN 0x20000000 1887#define BRXAGC_FREEZE_THRES_MODE 0x40000000 1888#define BRX_OVERFLOW_CHECKTYPE 0x80000000 1889#define BRX_AGCSHIFT 0x7f 1890#define BTRSW_TRI_ONLY 0x80 1891#define BPOWER_THRES 0x300 1892#define BRXAGC_EN 0x1 1893#define BRXAGC_TOGETHER_EN 0x2 1894#define BRXAGC_MIN 0x4 1895#define BRXHP_INI 0x7 1896#define BRXHP_TRLNA 0x70 1897#define BRXHP_RSSI 0x700 1898#define BRXHP_BBP1 0x7000 1899#define BRXHP_BBP2 0x70000 1900#define BRXHP_BBP3 0x700000 1901#define BRSSI_H 0x7f0000 1902#define BRSSI_GEN 0x7f000000 1903#define BRXSETTLE_TRSW 0x7 1904#define BRXSETTLE_LNA 0x38 1905#define BRXSETTLE_RSSI 0x1c0 1906#define BRXSETTLE_BBP 0xe00 1907#define BRXSETTLE_RXHP 0x7000 1908#define BRXSETTLE_ANTSW_RSSI 0x38000 1909#define BRXSETTLE_ANTSW 0xc0000 1910#define BRXPROCESS_TIME_DAGC 0x300000 1911#define BRXSETTLE_HSSI 0x400000 1912#define BRXPROCESS_TIME_BBPPW 0x800000 1913#define BRXANTENNA_POWER_SHIFT 0x3000000 1914#define BRSSI_TABLE_SELECT 0xc000000 1915#define BRXHP_FINAL 0x7000000 1916#define BRXHPSETTLE_BBP 0x7 1917#define BRXHTSETTLE_HSSI 0x8 1918#define BRXHTSETTLE_RXHP 0x70 1919#define BRXHTSETTLE_BBPPW 0x80 1920#define BRXHTSETTLE_IDLE 0x300 1921#define BRXHTSETTLE_RESERVED 0x1c00 1922#define BRXHT_RXHP_EN 0x8000 1923#define BRXAGC_FREEZE_THRES 0x30000 1924#define BRXAGC_TOGETHEREN 0x40000 1925#define BRXHTAGC_MIN 0x80000 1926#define BRXHTAGC_EN 0x100000 1927#define BRXHTDAGC_EN 0x200000 1928#define BRXHT_RXHP_BBP 0x1c00000 1929#define BRXHT_RXHP_FINAL 0xe0000000 1930#define BRXPW_RADIO_TH 0x3 1931#define BRXPW_RADIO_EN 0x4 1932#define BRXMF_HOLD 0x3800 1933#define BRXPD_DELAY_TH1 0x38 1934#define BRXPD_DELAY_TH2 0x1c0 1935#define BRXPD_DC_COUNT_MAX 0x600 1936#define BRXPD_DELAY_TH 0x8000 1937#define BRXPROCESS_DELAY 0xf0000 1938#define BRXSEARCHRANGE_GI2_EARLY 0x700000 1939#define BRXFRAME_FUARD_COUNTER_L 0x3800000 1940#define BRXSGI_GUARD_L 0xc000000 1941#define BRXSGI_SEARCH_L 0x30000000 1942#define BRXSGI_TH 0xc0000000 1943#define BDFSCNT0 0xff 1944#define BDFSCNT1 0xff00 1945#define BDFSFLAG 0xf0000 1946#define BMF_WEIGHT_SUM 0x300000 1947#define BMINIDX_TH 0x7f000000 1948#define BDAFORMAT 0x40000 1949#define BTXCH_EMU_ENABLE 0x01000000 1950#define BTRSW_ISOLATION_A 0x7f 1951#define BTRSW_ISOLATION_B 0x7f00 1952#define BTRSW_ISOLATION_C 0x7f0000 1953#define BTRSW_ISOLATION_D 0x7f000000 1954#define BEXT_LNA_GAIN 0x7c00 1955 1956#define BSTBC_EN 0x4 1957#define BANTENNA_MAPPING 0x10 1958#define BNSS 0x20 1959#define BCFO_ANTSUM_ID 0x200 1960#define BPHY_COUNTER_RESET 0x8000000 1961#define BCFO_REPORT_GET 0x4000000 1962#define BOFDM_CONTINUE_TX 0x10000000 1963#define BOFDM_SINGLE_CARRIER 0x20000000 1964#define BOFDM_SINGLE_TONE 0x40000000 1965#define BHT_DETECT 0x100 1966#define BCFOEN 0x10000 1967#define BCFOVALUE 0xfff00000 1968#define BSIGTONE_RE 0x3f 1969#define BSIGTONE_IM 0x7f00 1970#define BCOUNTER_CCA 0xffff 1971#define BCOUNTER_PARITYFAIL 0xffff0000 1972#define BCOUNTER_RATEILLEGAL 0xffff 1973#define BCOUNTER_CRC8FAIL 0xffff0000 1974#define BCOUNTER_MCSNOSUPPORT 0xffff 1975#define BCOUNTER_FASTSYNC 0xffff 1976#define BSHORTCFO 0xfff 1977#define BSHORTCFOT_LENGTH 12 1978#define BSHORTCFOF_LENGTH 11 1979#define BLONGCFO 0x7ff 1980#define BLONGCFOT_LENGTH 11 1981#define BLONGCFOF_LENGTH 11 1982#define BTAILCFO 0x1fff 1983#define BTAILCFOT_LENGTH 13 1984#define BTAILCFOF_LENGTH 12 1985#define BNOISE_EN_PWDB 0xffff 1986#define BCC_POWER_DB 0xffff0000 1987#define BMOISE_PWDB 0xffff 1988#define BPOWERMEAST_LENGTH 10 1989#define BPOWERMEASF_LENGTH 3 1990#define BRX_HT_BW 0x1 1991#define BRXSC 0x6 1992#define BRX_HT 0x8 1993#define BNB_INTF_DET_ON 0x1 1994#define BINTF_WIN_LEN_CFG 0x30 1995#define BNB_INTF_TH_CFG 0x1c0 1996#define BRFGAIN 0x3f 1997#define BTABLESEL 0x40 1998#define BTRSW 0x80 1999#define BRXSNR_A 0xff 2000#define BRXSNR_B 0xff00
2001#define BRXSNR_C 0xff0000 2002#define BRXSNR_D 0xff000000 2003#define BSNR_EVMT_LENGTH 8 2004#define BSNR_EVMF_LENGTH 1 2005#define BCSI1ST 0xff 2006#define BCSI2ND 0xff00 2007#define BRXEVM1ST 0xff0000 2008#define BRXEVM2ND 0xff000000 2009#define BSIGEVM 0xff 2010#define BPWDB 0xff00 2011#define BSGIEN 0x10000 2012 2013#define BSFACTOR_QMA1 0xf 2014#define BSFACTOR_QMA2 0xf0 2015#define BSFACTOR_QMA3 0xf00 2016#define BSFACTOR_QMA4 0xf000 2017#define BSFACTOR_QMA5 0xf0000 2018#define BSFACTOR_QMA6 0xf0000 2019#define BSFACTOR_QMA7 0xf00000 2020#define BSFACTOR_QMA8 0xf000000 2021#define BSFACTOR_QMA9 0xf0000000 2022#define BCSI_SCHEME 0x100000 2023 2024#define BNOISE_LVL_TOP_SET 0x3 2025#define BCHSMOOTH 0x4 2026#define BCHSMOOTH_CFG1 0x38 2027#define BCHSMOOTH_CFG2 0x1c0 2028#define BCHSMOOTH_CFG3 0xe00 2029#define BCHSMOOTH_CFG4 0x7000 2030#define BMRCMODE 0x800000 2031#define BTHEVMCFG 0x7000000 2032 2033#define BLOOP_FIT_TYPE 0x1 2034#define BUPD_CFO 0x40 2035#define BUPD_CFO_OFFDATA 0x80 2036#define BADV_UPD_CFO 0x100 2037#define BADV_TIME_CTRL 0x800 2038#define BUPD_CLKO 0x1000 2039#define BFC 0x6000 2040#define BTRACKING_MODE 0x8000 2041#define BPHCMP_ENABLE 0x10000 2042#define BUPD_CLKO_LTF 0x20000 2043#define BCOM_CH_CFO 0x40000 2044#define BCSI_ESTI_MODE 0x80000 2045#define BADV_UPD_EQZ 0x100000 2046#define BUCHCFG 0x7000000 2047#define BUPDEQZ 0x8000000 2048 2049#define BRX_PESUDO_NOISE_ON 0x20000000 2050#define BRX_PESUDO_NOISE_A 0xff 2051#define BRX_PESUDO_NOISE_B 0xff00 2052#define BRX_PESUDO_NOISE_C 0xff0000 2053#define BRX_PESUDO_NOISE_D 0xff000000 2054#define BRX_PESUDO_NOISESTATE_A 0xffff 2055#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2056#define BRX_PESUDO_NOISESTATE_C 0xffff 2057#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2058 2059#define BZEBRA1_HSSIENABLE 0x8 2060#define BZEBRA1_TRXCONTROL 0xc00 2061#define BZEBRA1_TRXGAINSETTING 0x07f 2062#define BZEBRA1_RXCOUNTER 0xc00 2063#define BZEBRA1_TXCHANGEPUMP 0x38 2064#define BZEBRA1_RXCHANGEPUMP 0x7 2065#define BZEBRA1_CHANNEL_NUM 0xf80 2066#define BZEBRA1_TXLPFBW 0x400 2067#define BZEBRA1_RXLPFBW 0x600 2068 2069#define BRTL8256REG_MODE_CTRL1 0x100 2070#define BRTL8256REG_MODE_CTRL0 0x40 2071#define BRTL8256REG_TXLPFBW 0x18 2072#define BRTL8256REG_RXLPFBW 0x600 2073 2074#define BRTL8258_TXLPFBW 0xc 2075#define BRTL8258_RXLPFBW 0xc00 2076#define BRTL8258_RSSILPFBW 0xc0 2077 2078#define BBYTE0 0x1 2079#define BBYTE1 0x2 2080#define BBYTE2 0x4 2081#define BBYTE3 0x8 2082#define BWORD0 0x3 2083#define BWORD1 0xc 2084#define BWORD 0xf 2085 2086#define MASKBYTE0 0xff 2087#define MASKBYTE1 0xff00 2088#define MASKBYTE2 0xff0000 2089#define MASKBYTE3 0xff000000 2090#define MASKHWORD 0xffff0000 2091#define MASKLWORD 0x0000ffff 2092#define MASKDWORD 0xffffffff 2093#define MASK12BITS 0xfff 2094#define MASKH4BITS 0xf0000000 2095#define MASKOFDM_D 0xffc00000 2096#define MASKCCK 0x3f3f3f3f 2097 2098#define MASK4BITS 0x0f 2099#define MASK20BITS 0xfffff 2100#define RFREG_OFFSET_MASK 0xfffff 2101 2102#define BENABLE 0x1 2103#define BDISABLE 0x0 2104 2105#define LEFT_ANTENNA 0x0 2106#define RIGHT_ANTENNA 0x1 2107 2108#define TCHECK_TXSTATUS 500 2109#define TUPDATE_RXCOUNTER 100 2110 2111/* 2 EFUSE_TEST (For RTL8723 partially) */ 2112#define EFUSE_SEL(x) (((x) & 0x3) << 8) 2113#define EFUSE_SEL_MASK 0x300 2114#define EFUSE_WIFI_SEL_0 0x0 2115/* Enable GPIO[9] as WiFi HW PDn source*/ 2116#define WL_HWPDN_EN BIT(0) 2117/* WiFi HW PDn polarity control*/ 2118#define WL_HWPDN_SL BIT(1) 2119 2120#endif 2121