linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c
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   1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2014  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * The full GNU General Public License is included in this distribution in the
  15 * file called LICENSE.
  16 *
  17 * Contact Information:
  18 * wlanfae <wlanfae@realtek.com>
  19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20 * Hsinchu 300, Taiwan.
  21 *
  22 * Larry Finger <Larry.Finger@lwfinger.net>
  23 *
  24 *****************************************************************************/
  25
  26#include "../wifi.h"
  27#include "../core.h"
  28#include "../pci.h"
  29#include "reg.h"
  30#include "def.h"
  31#include "phy.h"
  32#include "../rtl8723com/phy_common.h"
  33#include "dm.h"
  34#include "../rtl8723com/dm_common.h"
  35#include "hw.h"
  36#include "fw.h"
  37#include "../rtl8723com/fw_common.h"
  38#include "sw.h"
  39#include "trx.h"
  40#include "led.h"
  41#include "table.h"
  42#include "../btcoexist/rtl_btc.h"
  43
  44#include <linux/vmalloc.h>
  45#include <linux/module.h>
  46
  47static void rtl8723be_init_aspm_vars(struct ieee80211_hw *hw)
  48{
  49        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50
  51        /*close ASPM for AMD defaultly */
  52        rtlpci->const_amdpci_aspm = 0;
  53
  54        /* ASPM PS mode.
  55         * 0 - Disable ASPM,
  56         * 1 - Enable ASPM without Clock Req,
  57         * 2 - Enable ASPM with Clock Req,
  58         * 3 - Alwyas Enable ASPM with Clock Req,
  59         * 4 - Always Enable ASPM without Clock Req.
  60         * set defult to RTL8192CE:3 RTL8192E:2
  61         */
  62        rtlpci->const_pci_aspm = 3;
  63
  64        /*Setting for PCI-E device */
  65        rtlpci->const_devicepci_aspm_setting = 0x03;
  66
  67        /*Setting for PCI-E bridge */
  68        rtlpci->const_hostpci_aspm_setting = 0x02;
  69
  70        /* In Hw/Sw Radio Off situation.
  71         * 0 - Default,
  72         * 1 - From ASPM setting without low Mac Pwr,
  73         * 2 - From ASPM setting with low Mac Pwr,
  74         * 3 - Bus D3
  75         * set default to RTL8192CE:0 RTL8192SE:2
  76         */
  77        rtlpci->const_hwsw_rfoff_d3 = 0;
  78
  79        /* This setting works for those device with
  80         * backdoor ASPM setting such as EPHY setting.
  81         * 0 - Not support ASPM,
  82         * 1 - Support ASPM,
  83         * 2 - According to chipset.
  84         */
  85        rtlpci->const_support_pciaspm = 1;
  86}
  87
  88int rtl8723be_init_sw_vars(struct ieee80211_hw *hw)
  89{
  90        int err = 0;
  91        struct rtl_priv *rtlpriv = rtl_priv(hw);
  92        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  93        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  94
  95        rtl8723be_bt_reg_init(hw);
  96        rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
  97
  98        rtlpriv->dm.dm_initialgain_enable = 1;
  99        rtlpriv->dm.dm_flag = 0;
 100        rtlpriv->dm.disable_framebursting = 0;
 101        rtlpriv->dm.thermalvalue = 0;
 102        rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25);
 103
 104        rtlpriv->phy.lck_inprogress = false;
 105
 106        mac->ht_enable = true;
 107
 108        /* compatible 5G band 88ce just 2.4G band & smsp */
 109        rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 110        rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 111        rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 112
 113        rtlpci->receive_config = (RCR_APPFCS            |
 114                                  RCR_APP_MIC           |
 115                                  RCR_APP_ICV           |
 116                                  RCR_APP_PHYST_RXFF    |
 117                                  RCR_HTC_LOC_CTRL      |
 118                                  RCR_AMF               |
 119                                  RCR_ACF               |
 120                                  RCR_ADF               |
 121                                  RCR_AICV              |
 122                                  RCR_AB                |
 123                                  RCR_AM                |
 124                                  RCR_APM               |
 125                                  0);
 126
 127        rtlpci->irq_mask[0] = (u32) (IMR_PSTIMEOUT      |
 128                                     IMR_HSISR_IND_ON_INT       |
 129                                     IMR_C2HCMD         |
 130                                     IMR_HIGHDOK        |
 131                                     IMR_MGNTDOK        |
 132                                     IMR_BKDOK          |
 133                                     IMR_BEDOK          |
 134                                     IMR_VIDOK          |
 135                                     IMR_VODOK          |
 136                                     IMR_RDU            |
 137                                     IMR_ROK            |
 138                                     0);
 139
 140        rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
 141
 142        rtlpci->sys_irq_mask = (u32)(HSIMR_PDN_INT_EN   |
 143                                     HSIMR_RON_INT_EN   |
 144                                     0);
 145
 146        /* for debug level */
 147        rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
 148        /* for LPS & IPS */
 149        rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 150        rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 151        rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 152        rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
 153        rtlpriv->cfg->mod_params->sw_crypto =
 154                 rtlpriv->cfg->mod_params->sw_crypto;
 155        rtlpriv->cfg->mod_params->disable_watchdog =
 156                 rtlpriv->cfg->mod_params->disable_watchdog;
 157        if (rtlpriv->cfg->mod_params->disable_watchdog)
 158                pr_info("watchdog disabled\n");
 159        rtlpriv->psc.reg_fwctrl_lps = 3;
 160        rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 161        /* for ASPM, you can close aspm through
 162         * set const_support_pciaspm = 0
 163         */
 164        rtl8723be_init_aspm_vars(hw);
 165
 166        if (rtlpriv->psc.reg_fwctrl_lps == 1)
 167                rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 168        else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 169                rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 170        else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 171                rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 172
 173        /*low power: Disable 32k */
 174        rtlpriv->psc.low_power_enable = false;
 175
 176        rtlpriv->rtlhal.earlymode_enable = false;
 177
 178        /* for firmware buf */
 179        rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
 180        if (!rtlpriv->rtlhal.pfirmware) {
 181                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 182                         "Can't alloc buffer for fw.\n");
 183                return 1;
 184        }
 185
 186        rtlpriv->max_fw_size = 0x8000;
 187        pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
 188        err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
 189                                      rtlpriv->io.dev, GFP_KERNEL, hw,
 190                                      rtl_fw_cb);
 191        if (err) {
 192                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 193                         "Failed to request firmware!\n");
 194                return 1;
 195        }
 196        return 0;
 197}
 198
 199void rtl8723be_deinit_sw_vars(struct ieee80211_hw *hw)
 200{
 201        struct rtl_priv *rtlpriv = rtl_priv(hw);
 202
 203        if (rtlpriv->rtlhal.pfirmware) {
 204                vfree(rtlpriv->rtlhal.pfirmware);
 205                rtlpriv->rtlhal.pfirmware = NULL;
 206        }
 207}
 208
 209/* get bt coexist status */
 210bool rtl8723be_get_btc_status(void)
 211{
 212        return true;
 213}
 214
 215static bool is_fw_header(struct rtlwifi_firmware_header *hdr)
 216{
 217        return (le16_to_cpu(hdr->signature) & 0xfff0) == 0x5300;
 218}
 219
 220static struct rtl_hal_ops rtl8723be_hal_ops = {
 221        .init_sw_vars = rtl8723be_init_sw_vars,
 222        .deinit_sw_vars = rtl8723be_deinit_sw_vars,
 223        .read_eeprom_info = rtl8723be_read_eeprom_info,
 224        .interrupt_recognized = rtl8723be_interrupt_recognized,
 225        .hw_init = rtl8723be_hw_init,
 226        .hw_disable = rtl8723be_card_disable,
 227        .hw_suspend = rtl8723be_suspend,
 228        .hw_resume = rtl8723be_resume,
 229        .enable_interrupt = rtl8723be_enable_interrupt,
 230        .disable_interrupt = rtl8723be_disable_interrupt,
 231        .set_network_type = rtl8723be_set_network_type,
 232        .set_chk_bssid = rtl8723be_set_check_bssid,
 233        .set_qos = rtl8723be_set_qos,
 234        .set_bcn_reg = rtl8723be_set_beacon_related_registers,
 235        .set_bcn_intv = rtl8723be_set_beacon_interval,
 236        .update_interrupt_mask = rtl8723be_update_interrupt_mask,
 237        .get_hw_reg = rtl8723be_get_hw_reg,
 238        .set_hw_reg = rtl8723be_set_hw_reg,
 239        .update_rate_tbl = rtl8723be_update_hal_rate_tbl,
 240        .fill_tx_desc = rtl8723be_tx_fill_desc,
 241        .fill_tx_cmddesc = rtl8723be_tx_fill_cmddesc,
 242        .query_rx_desc = rtl8723be_rx_query_desc,
 243        .set_channel_access = rtl8723be_update_channel_access_setting,
 244        .radio_onoff_checking = rtl8723be_gpio_radio_on_off_checking,
 245        .set_bw_mode = rtl8723be_phy_set_bw_mode,
 246        .switch_channel = rtl8723be_phy_sw_chnl,
 247        .dm_watchdog = rtl8723be_dm_watchdog,
 248        .scan_operation_backup = rtl8723be_phy_scan_operation_backup,
 249        .set_rf_power_state = rtl8723be_phy_set_rf_power_state,
 250        .led_control = rtl8723be_led_control,
 251        .set_desc = rtl8723be_set_desc,
 252        .get_desc = rtl8723be_get_desc,
 253        .is_tx_desc_closed = rtl8723be_is_tx_desc_closed,
 254        .tx_polling = rtl8723be_tx_polling,
 255        .enable_hw_sec = rtl8723be_enable_hw_security_config,
 256        .set_key = rtl8723be_set_key,
 257        .init_sw_leds = rtl8723be_init_sw_leds,
 258        .get_bbreg = rtl8723_phy_query_bb_reg,
 259        .set_bbreg = rtl8723_phy_set_bb_reg,
 260        .get_rfreg = rtl8723be_phy_query_rf_reg,
 261        .set_rfreg = rtl8723be_phy_set_rf_reg,
 262        .fill_h2c_cmd = rtl8723be_fill_h2c_cmd,
 263        .get_btc_status = rtl8723be_get_btc_status,
 264        .rx_command_packet = rtl8723be_rx_command_packet,
 265        .is_fw_header = is_fw_header,
 266};
 267
 268static struct rtl_mod_params rtl8723be_mod_params = {
 269        .sw_crypto = false,
 270        .inactiveps = true,
 271        .swctrl_lps = false,
 272        .fwctrl_lps = true,
 273        .msi_support = false,
 274        .disable_watchdog = false,
 275        .debug = DBG_EMERG,
 276        .ant_sel = 0,
 277};
 278
 279static struct rtl_hal_cfg rtl8723be_hal_cfg = {
 280        .bar_id = 2,
 281        .write_readback = true,
 282        .name = "rtl8723be_pci",
 283        .fw_name = "rtlwifi/rtl8723befw.bin",
 284        .ops = &rtl8723be_hal_ops,
 285        .mod_params = &rtl8723be_mod_params,
 286        .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 287        .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 288        .maps[SYS_CLK] = REG_SYS_CLKR,
 289        .maps[MAC_RCR_AM] = AM,
 290        .maps[MAC_RCR_AB] = AB,
 291        .maps[MAC_RCR_ACRC32] = ACRC32,
 292        .maps[MAC_RCR_ACF] = ACF,
 293        .maps[MAC_RCR_AAP] = AAP,
 294        .maps[MAC_HIMR] = REG_HIMR,
 295        .maps[MAC_HIMRE] = REG_HIMRE,
 296        .maps[MAC_HSISR] = REG_HSISR,
 297
 298        .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
 299
 300        .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 301        .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 302        .maps[EFUSE_CLK] = 0,
 303        .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 304        .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 305        .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 306        .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 307        .maps[EFUSE_ANA8M] = ANA8M,
 308        .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 309        .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 310        .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 311        .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 312
 313        .maps[RWCAM] = REG_CAMCMD,
 314        .maps[WCAMI] = REG_CAMWRITE,
 315        .maps[RCAMO] = REG_CAMREAD,
 316        .maps[CAMDBG] = REG_CAMDBG,
 317        .maps[SECR] = REG_SECCFG,
 318        .maps[SEC_CAM_NONE] = CAM_NONE,
 319        .maps[SEC_CAM_WEP40] = CAM_WEP40,
 320        .maps[SEC_CAM_TKIP] = CAM_TKIP,
 321        .maps[SEC_CAM_AES] = CAM_AES,
 322        .maps[SEC_CAM_WEP104] = CAM_WEP104,
 323
 324        .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 325        .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 326        .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 327        .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 328        .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 329        .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 330/*      .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,     */   /*need check*/
 331        .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 332        .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 333        .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 334        .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 335        .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 336        .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 337        .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 338/*      .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
 339/*      .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
 340
 341        .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 342        .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 343        .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
 344        .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 345        .maps[RTL_IMR_RDU] = IMR_RDU,
 346        .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 347        .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
 348        .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 349        .maps[RTL_IMR_TBDER] = IMR_TBDER,
 350        .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 351        .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 352        .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 353        .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 354        .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 355        .maps[RTL_IMR_VODOK] = IMR_VODOK,
 356        .maps[RTL_IMR_ROK] = IMR_ROK,
 357        .maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
 358        .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
 359
 360        .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
 361        .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
 362        .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
 363        .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
 364        .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
 365        .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
 366        .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
 367        .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
 368        .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
 369        .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
 370        .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
 371        .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
 372
 373        .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
 374        .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
 375};
 376
 377static struct pci_device_id rtl8723be_pci_ids[] = {
 378        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0xB723, rtl8723be_hal_cfg)},
 379        {},
 380};
 381
 382MODULE_DEVICE_TABLE(pci, rtl8723be_pci_ids);
 383
 384MODULE_AUTHOR("PageHe   <page_he@realsil.com.cn>");
 385MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 386MODULE_LICENSE("GPL");
 387MODULE_DESCRIPTION("Realtek 8723BE 802.11n PCI wireless");
 388MODULE_FIRMWARE("rtlwifi/rtl8723befw.bin");
 389
 390module_param_named(swenc, rtl8723be_mod_params.sw_crypto, bool, 0444);
 391module_param_named(debug, rtl8723be_mod_params.debug, int, 0444);
 392module_param_named(ips, rtl8723be_mod_params.inactiveps, bool, 0444);
 393module_param_named(swlps, rtl8723be_mod_params.swctrl_lps, bool, 0444);
 394module_param_named(fwlps, rtl8723be_mod_params.fwctrl_lps, bool, 0444);
 395module_param_named(msi, rtl8723be_mod_params.msi_support, bool, 0444);
 396module_param_named(disable_watchdog, rtl8723be_mod_params.disable_watchdog,
 397                   bool, 0444);
 398module_param_named(ant_sel, rtl8723be_mod_params.ant_sel, int, 0444);
 399MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 400MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 401MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 402MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 403MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
 404MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
 405MODULE_PARM_DESC(disable_watchdog,
 406                 "Set to 1 to disable the watchdog (default 0)\n");
 407MODULE_PARM_DESC(ant_sel, "Set to 1 or 2 to force antenna number (default 0)\n");
 408
 409static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 410
 411static struct pci_driver rtl8723be_driver = {
 412        .name = KBUILD_MODNAME,
 413        .id_table = rtl8723be_pci_ids,
 414        .probe = rtl_pci_probe,
 415        .remove = rtl_pci_disconnect,
 416        .driver.pm = &rtlwifi_pm_ops,
 417};
 418
 419module_pci_driver(rtl8723be_driver);
 420