1#ifndef __IBMPHP_H
2#define __IBMPHP_H
3
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33#include <linux/pci_hotplug.h>
34
35extern int ibmphp_debug;
36
37#if !defined(MODULE)
38 #define MY_NAME "ibmphpd"
39#else
40 #define MY_NAME THIS_MODULE->name
41#endif
42#define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
43#define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
44#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
45#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
46#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
47
48
49
50
51
52
53
54
55#define EBDA_SLOT_133_MAX 0x20
56#define EBDA_SLOT_100_MAX 0x10
57#define EBDA_SLOT_66_MAX 0x02
58#define EBDA_SLOT_PCIX_CAP 0x08
59
60
61
62
63
64
65#define EBDA_RSRC_TYPE_MASK 0x03
66#define EBDA_IO_RSRC_TYPE 0x00
67#define EBDA_MEM_RSRC_TYPE 0x01
68#define EBDA_PFM_RSRC_TYPE 0x03
69#define EBDA_RES_RSRC_TYPE 0x02
70
71
72
73
74
75
76#define EBDA_IO_RESTRI_MASK 0x0c
77#define EBDA_NO_RESTRI 0x00
78#define EBDA_AVO_VGA_ADDR 0x04
79#define EBDA_AVO_VGA_ADDR_AND_ALIA 0x08
80#define EBDA_AVO_ISA_ADDR 0x0c
81
82
83
84
85
86
87#define EBDA_DEV_TYPE_MASK 0x10
88#define EBDA_PCI_DEV 0x10
89#define EBDA_NON_PCI_DEV 0x00
90
91
92
93
94
95
96#define EBDA_PRI_DEF_MASK 0x20
97#define EBDA_PRI_PCI_BUS_INFO 0x20
98#define EBDA_NORM_DEV_RSRC_INFO 0x00
99
100
101
102
103
104
105struct rio_table_hdr {
106 u8 ver_num;
107 u8 scal_count;
108 u8 riodev_count;
109 u16 offset;
110};
111
112
113
114
115
116struct scal_detail {
117 u8 node_id;
118 u32 cbar;
119 u8 port0_node_connect;
120 u8 port0_port_connect;
121 u8 port1_node_connect;
122 u8 port1_port_connect;
123 u8 port2_node_connect;
124 u8 port2_port_connect;
125 u8 chassis_num;
126
127};
128
129
130
131
132
133struct rio_detail {
134 u8 rio_node_id;
135 u32 bbar;
136 u8 rio_type;
137 u8 owner_id;
138 u8 port0_node_connect;
139 u8 port0_port_connect;
140 u8 port1_node_connect;
141 u8 port1_port_connect;
142 u8 first_slot_num;
143 u8 status;
144 u8 wpindex;
145 u8 chassis_num;
146 struct list_head rio_detail_list;
147};
148
149struct opt_rio {
150 u8 rio_type;
151 u8 chassis_num;
152 u8 first_slot_num;
153 u8 middle_num;
154 struct list_head opt_rio_list;
155};
156
157struct opt_rio_lo {
158 u8 rio_type;
159 u8 chassis_num;
160 u8 first_slot_num;
161 u8 middle_num;
162 u8 pack_count;
163 struct list_head opt_rio_lo_list;
164};
165
166
167
168
169
170struct ebda_hpc_list {
171 u8 format;
172 u16 num_ctlrs;
173 short phys_addr;
174
175};
176
177
178
179
180
181struct ebda_hpc_slot {
182 u8 slot_num;
183 u32 slot_bus_num;
184 u8 ctl_index;
185 u8 slot_cap;
186};
187
188struct ebda_hpc_bus {
189 u32 bus_num;
190 u8 slots_at_33_conv;
191 u8 slots_at_66_conv;
192 u8 slots_at_66_pcix;
193 u8 slots_at_100_pcix;
194 u8 slots_at_133_pcix;
195};
196
197
198
199
200
201
202struct isa_ctlr_access {
203 u16 io_start;
204 u16 io_end;
205};
206
207struct pci_ctlr_access {
208 u8 bus;
209 u8 dev_fun;
210};
211
212struct wpeg_i2c_ctlr_access {
213 ulong wpegbbar;
214 u8 i2c_addr;
215};
216
217#define HPC_DEVICE_ID 0x0246
218#define HPC_SUBSYSTEM_ID 0x0247
219#define HPC_PCI_OFFSET 0x40
220
221
222
223
224struct ebda_rsrc_list {
225 u8 format;
226 u16 num_entries;
227 u16 phys_addr;
228 struct ebda_rsrc_list *next;
229};
230
231
232
233
234
235
236struct ebda_pci_rsrc {
237 u8 rsrc_type;
238 u8 bus_num;
239 u8 dev_fun;
240 u32 start_addr;
241 u32 end_addr;
242 u8 marked;
243 struct list_head ebda_pci_rsrc_list;
244};
245
246
247
248
249
250
251struct bus_info {
252 u8 slot_min;
253 u8 slot_max;
254 u8 slot_count;
255 u8 busno;
256 u8 controller_id;
257 u8 current_speed;
258 u8 current_bus_mode;
259 u8 index;
260 u8 slots_at_33_conv;
261 u8 slots_at_66_conv;
262 u8 slots_at_66_pcix;
263 u8 slots_at_100_pcix;
264 u8 slots_at_133_pcix;
265 struct list_head bus_info_list;
266};
267
268
269
270
271
272extern struct list_head ibmphp_ebda_pci_rsrc_head;
273extern struct list_head ibmphp_slot_head;
274
275
276
277
278void ibmphp_free_ebda_hpc_queue(void);
279int ibmphp_access_ebda(void);
280struct slot *ibmphp_get_slot_from_physical_num(u8);
281int ibmphp_get_total_hp_slots(void);
282void ibmphp_free_ibm_slot(struct slot *);
283void ibmphp_free_bus_info_queue(void);
284void ibmphp_free_ebda_pci_rsrc_queue(void);
285struct bus_info *ibmphp_find_same_bus_num(u32);
286int ibmphp_get_bus_index(u8);
287u16 ibmphp_get_total_controllers(void);
288int ibmphp_register_pci(void);
289
290
291#define MEM 0
292#define IO 1
293#define PFMEM 2
294
295
296#define RESTYPE 0x03
297#define IOMASK 0x00
298#define MMASK 0x01
299#define PFMASK 0x03
300#define PCIDEVMASK 0x10
301#define PRIMARYBUSMASK 0x20
302
303
304#define PCI_VENDOR_ID_NOTVALID 0xFFFF
305#define PCI_HEADER_TYPE_MULTIDEVICE 0x80
306#define PCI_HEADER_TYPE_MULTIBRIDGE 0x81
307
308#define LATENCY 0x64
309#define CACHE 64
310#define DEVICEENABLE 0x015F
311
312#define IOBRIDGE 0x1000
313#define MEMBRIDGE 0x100000
314
315
316#define SCSI_IRQ 0x09
317#define LAN_IRQ 0x0A
318#define OTHER_IRQ 0x0B
319
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332
333
334
335struct range_node {
336 int rangeno;
337 u32 start;
338 u32 end;
339 struct range_node *next;
340};
341
342struct bus_node {
343 u8 busno;
344 int noIORanges;
345 struct range_node *rangeIO;
346 int noMemRanges;
347 struct range_node *rangeMem;
348 int noPFMemRanges;
349 struct range_node *rangePFMem;
350 int needIOUpdate;
351 int needMemUpdate;
352 int needPFMemUpdate;
353 struct resource_node *firstIO;
354 struct resource_node *firstMem;
355 struct resource_node *firstPFMem;
356 struct resource_node *firstPFMemFromMem;
357 struct list_head bus_list;
358};
359
360struct resource_node {
361 int rangeno;
362 u8 busno;
363 u8 devfunc;
364 u32 start;
365 u32 end;
366 u32 len;
367 int type;
368 u8 fromMem;
369
370 struct resource_node *next;
371 struct resource_node *nextRange;
372};
373
374struct res_needed {
375 u32 mem;
376 u32 pfmem;
377 u32 io;
378 u8 not_correct;
379 int devices[32];
380};
381
382
383
384int ibmphp_rsrc_init(void);
385int ibmphp_add_resource(struct resource_node *);
386int ibmphp_remove_resource(struct resource_node *);
387int ibmphp_find_resource(struct bus_node *, u32, struct resource_node **, int);
388int ibmphp_check_resource(struct resource_node *, u8);
389int ibmphp_remove_bus(struct bus_node *, u8);
390void ibmphp_free_resources(void);
391int ibmphp_add_pfmem_from_mem(struct resource_node *);
392struct bus_node *ibmphp_find_res_bus(u8);
393void ibmphp_print_test(void);
394
395void ibmphp_hpc_initvars(void);
396int ibmphp_hpc_readslot(struct slot *, u8, u8 *);
397int ibmphp_hpc_writeslot(struct slot *, u8);
398void ibmphp_lock_operations(void);
399void ibmphp_unlock_operations(void);
400int ibmphp_hpc_start_poll_thread(void);
401void ibmphp_hpc_stop_poll_thread(void);
402
403
404
405
406
407
408
409#define HPC_ERROR 0xFF
410
411
412
413
414#define BUS_SPEED 0x30
415#define BUS_MODE 0x40
416#define BUS_MODE_PCIX 0x01
417#define BUS_MODE_PCI 0x00
418#define BUS_SPEED_2 0x20
419#define BUS_SPEED_1 0x10
420#define BUS_SPEED_33 0x00
421#define BUS_SPEED_66 0x01
422#define BUS_SPEED_100 0x02
423#define BUS_SPEED_133 0x03
424#define BUS_SPEED_66PCIX 0x04
425#define BUS_SPEED_66UNKNOWN 0x05
426#define BUS_STATUS_AVAILABLE 0x01
427#define BUS_CONTROL_AVAILABLE 0x02
428#define SLOT_LATCH_REGS_SUPPORTED 0x10
429
430#define PRGM_MODEL_REV_LEVEL 0xF0
431#define MAX_ADAPTER_NONE 0x09
432
433
434
435
436
437
438
439#define HPC_CTLR_ENABLEIRQ 0x00
440#define HPC_CTLR_DISABLEIRQ 0x01
441#define HPC_SLOT_OFF 0x02
442#define HPC_SLOT_ON 0x03
443#define HPC_SLOT_ATTNOFF 0x04
444#define HPC_SLOT_ATTNON 0x05
445#define HPC_CTLR_CLEARIRQ 0x06
446#define HPC_CTLR_RESET 0x07
447#define HPC_CTLR_IRQSTEER 0x08
448#define HPC_BUS_33CONVMODE 0x09
449#define HPC_BUS_66CONVMODE 0x0A
450#define HPC_BUS_66PCIXMODE 0x0B
451#define HPC_BUS_100PCIXMODE 0x0C
452#define HPC_BUS_133PCIXMODE 0x0D
453#define HPC_ALLSLOT_OFF 0x11
454#define HPC_ALLSLOT_ON 0x12
455#define HPC_SLOT_BLINKLED 0x13
456
457
458
459
460#define READ_SLOTSTATUS 0x01
461#define READ_EXTSLOTSTATUS 0x02
462#define READ_BUSSTATUS 0x03
463#define READ_CTLRSTATUS 0x04
464#define READ_ALLSTAT 0x05
465#define READ_ALLSLOT 0x06
466#define READ_SLOTLATCHLOWREG 0x07
467#define READ_REVLEVEL 0x08
468#define READ_HPCOPTIONS 0x09
469
470
471
472#define HPC_SLOT_POWER 0x01
473#define HPC_SLOT_CONNECT 0x02
474#define HPC_SLOT_ATTN 0x04
475#define HPC_SLOT_PRSNT2 0x08
476#define HPC_SLOT_PRSNT1 0x10
477#define HPC_SLOT_PWRGD 0x20
478#define HPC_SLOT_BUS_SPEED 0x40
479#define HPC_SLOT_LATCH 0x80
480
481
482
483
484#define HPC_SLOT_POWER_OFF 0x00
485#define HPC_SLOT_POWER_ON 0x01
486
487
488
489
490#define HPC_SLOT_CONNECTED 0x00
491#define HPC_SLOT_DISCONNECTED 0x01
492
493
494
495
496#define HPC_SLOT_ATTN_OFF 0x00
497#define HPC_SLOT_ATTN_ON 0x01
498#define HPC_SLOT_ATTN_BLINK 0x02
499
500
501
502
503#define HPC_SLOT_EMPTY 0x00
504#define HPC_SLOT_PRSNT_7 0x01
505#define HPC_SLOT_PRSNT_15 0x02
506#define HPC_SLOT_PRSNT_25 0x03
507
508
509
510
511#define HPC_SLOT_PWRGD_FAULT_NONE 0x00
512#define HPC_SLOT_PWRGD_GOOD 0x01
513
514
515
516
517#define HPC_SLOT_BUS_SPEED_OK 0x00
518#define HPC_SLOT_BUS_SPEED_MISM 0x01
519
520
521
522
523#define HPC_SLOT_LATCH_OPEN 0x01
524#define HPC_SLOT_LATCH_CLOSED 0x00
525
526
527
528
529
530#define HPC_SLOT_PCIX 0x01
531#define HPC_SLOT_SPEED1 0x02
532#define HPC_SLOT_SPEED2 0x04
533#define HPC_SLOT_BLINK_ATTN 0x08
534#define HPC_SLOT_RSRVD1 0x10
535#define HPC_SLOT_RSRVD2 0x20
536#define HPC_SLOT_BUS_MODE 0x40
537#define HPC_SLOT_RSRVD3 0x80
538
539
540
541
542#define HPC_SLOT_PCIX_NO 0x00
543#define HPC_SLOT_PCIX_YES 0x01
544
545
546
547
548#define HPC_SLOT_SPEED_33 0x00
549#define HPC_SLOT_SPEED_66 0x01
550#define HPC_SLOT_SPEED_133 0x02
551
552
553
554
555#define HPC_SLOT_ATTN_BLINK_OFF 0x00
556#define HPC_SLOT_ATTN_BLINK_ON 0x01
557
558
559
560
561#define HPC_SLOT_BUS_MODE_OK 0x00
562#define HPC_SLOT_BUS_MODE_MISM 0x01
563
564
565
566
567#define HPC_CTLR_WORKING 0x01
568#define HPC_CTLR_FINISHED 0x02
569#define HPC_CTLR_RESULT0 0x04
570#define HPC_CTLR_RESULT1 0x08
571#define HPC_CTLR_RESULE2 0x10
572#define HPC_CTLR_RESULT3 0x20
573#define HPC_CTLR_IRQ_ROUTG 0x40
574#define HPC_CTLR_IRQ_PENDG 0x80
575
576
577
578
579#define HPC_CTLR_WORKING_NO 0x00
580#define HPC_CTLR_WORKING_YES 0x01
581
582
583
584
585#define HPC_CTLR_FINISHED_NO 0x00
586#define HPC_CTLR_FINISHED_YES 0x01
587
588
589
590
591#define HPC_CTLR_RESULT_SUCCESS 0x00
592#define HPC_CTLR_RESULT_FAILED 0x01
593#define HPC_CTLR_RESULT_RSVD 0x02
594#define HPC_CTLR_RESULT_NORESP 0x03
595
596
597
598
599
600#define SLOT_POWER(s) ((u8) ((s & HPC_SLOT_POWER) \
601 ? HPC_SLOT_POWER_ON : HPC_SLOT_POWER_OFF))
602
603#define SLOT_CONNECT(s) ((u8) ((s & HPC_SLOT_CONNECT) \
604 ? HPC_SLOT_DISCONNECTED : HPC_SLOT_CONNECTED))
605
606#define SLOT_ATTN(s, es) ((u8) ((es & HPC_SLOT_BLINK_ATTN) \
607 ? HPC_SLOT_ATTN_BLINK \
608 : ((s & HPC_SLOT_ATTN) ? HPC_SLOT_ATTN_ON : HPC_SLOT_ATTN_OFF)))
609
610#define SLOT_PRESENT(s) ((u8) ((s & HPC_SLOT_PRSNT1) \
611 ? ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_EMPTY : HPC_SLOT_PRSNT_15) \
612 : ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_PRSNT_25 : HPC_SLOT_PRSNT_7)))
613
614#define SLOT_PWRGD(s) ((u8) ((s & HPC_SLOT_PWRGD) \
615 ? HPC_SLOT_PWRGD_GOOD : HPC_SLOT_PWRGD_FAULT_NONE))
616
617#define SLOT_BUS_SPEED(s) ((u8) ((s & HPC_SLOT_BUS_SPEED) \
618 ? HPC_SLOT_BUS_SPEED_MISM : HPC_SLOT_BUS_SPEED_OK))
619
620#define SLOT_LATCH(s) ((u8) ((s & HPC_SLOT_LATCH) \
621 ? HPC_SLOT_LATCH_CLOSED : HPC_SLOT_LATCH_OPEN))
622
623#define SLOT_PCIX(es) ((u8) ((es & HPC_SLOT_PCIX) \
624 ? HPC_SLOT_PCIX_YES : HPC_SLOT_PCIX_NO))
625
626#define SLOT_SPEED(es) ((u8) ((es & HPC_SLOT_SPEED2) \
627 ? ((es & HPC_SLOT_SPEED1) ? HPC_SLOT_SPEED_133 \
628 : HPC_SLOT_SPEED_66) \
629 : HPC_SLOT_SPEED_33))
630
631#define SLOT_BUS_MODE(es) ((u8) ((es & HPC_SLOT_BUS_MODE) \
632 ? HPC_SLOT_BUS_MODE_MISM : HPC_SLOT_BUS_MODE_OK))
633
634
635
636
637#define CURRENT_BUS_SPEED(s) ((u8) (s & BUS_SPEED_2) \
638 ? ((s & BUS_SPEED_1) ? BUS_SPEED_133 : BUS_SPEED_100) \
639 : ((s & BUS_SPEED_1) ? BUS_SPEED_66 : BUS_SPEED_33))
640
641#define CURRENT_BUS_MODE(s) ((u8) (s & BUS_MODE) ? BUS_MODE_PCIX : BUS_MODE_PCI)
642
643#define READ_BUS_STATUS(s) ((u8) (s->options & BUS_STATUS_AVAILABLE))
644
645#define READ_BUS_MODE(s) ((s->revision & PRGM_MODEL_REV_LEVEL) >= 0x20)
646
647#define SET_BUS_STATUS(s) ((u8) (s->options & BUS_CONTROL_AVAILABLE))
648
649#define READ_SLOT_LATCH(s) ((u8) (s->options & SLOT_LATCH_REGS_SUPPORTED))
650
651
652
653
654#define CTLR_WORKING(c) ((u8) ((c & HPC_CTLR_WORKING) \
655 ? HPC_CTLR_WORKING_YES : HPC_CTLR_WORKING_NO))
656#define CTLR_FINISHED(c) ((u8) ((c & HPC_CTLR_FINISHED) \
657 ? HPC_CTLR_FINISHED_YES : HPC_CTLR_FINISHED_NO))
658#define CTLR_RESULT(c) ((u8) ((c & HPC_CTLR_RESULT1) \
659 ? ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_NORESP \
660 : HPC_CTLR_RESULT_RSVD) \
661 : ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_FAILED \
662 : HPC_CTLR_RESULT_SUCCESS)))
663
664
665#define NEEDTOCHECK_CMDSTATUS(c) ((c == HPC_SLOT_OFF) || \
666 (c == HPC_SLOT_ON) || \
667 (c == HPC_CTLR_RESET) || \
668 (c == HPC_BUS_33CONVMODE) || \
669 (c == HPC_BUS_66CONVMODE) || \
670 (c == HPC_BUS_66PCIXMODE) || \
671 (c == HPC_BUS_100PCIXMODE) || \
672 (c == HPC_BUS_133PCIXMODE) || \
673 (c == HPC_ALLSLOT_OFF) || \
674 (c == HPC_ALLSLOT_ON))
675
676
677
678
679#define ENABLE 1
680#define DISABLE 0
681
682#define CARD_INFO 0x07
683#define PCIX133 0x07
684#define PCIX66 0x05
685#define PCI66 0x04
686
687extern struct pci_bus *ibmphp_pci_bus;
688
689
690
691struct pci_func {
692 struct pci_dev *dev;
693 u8 busno;
694 u8 device;
695 u8 function;
696 struct resource_node *io[6];
697 struct resource_node *mem[6];
698 struct resource_node *pfmem[6];
699 struct pci_func *next;
700 int devices[32];
701 u8 irq[4];
702 u8 bus;
703};
704
705struct slot {
706 u8 bus;
707 u8 device;
708 u8 number;
709 u8 real_physical_slot_num;
710 u32 capabilities;
711 u8 supported_speed;
712 u8 supported_bus_mode;
713 u8 flag;
714 u8 ctlr_index;
715 struct hotplug_slot *hotplug_slot;
716 struct controller *ctrl;
717 struct pci_func *func;
718 u8 irq[4];
719 int bit_mode;
720 struct bus_info *bus_on;
721 struct list_head ibm_slot_list;
722 u8 status;
723 u8 ext_status;
724 u8 busstatus;
725};
726
727struct controller {
728 struct ebda_hpc_slot *slots;
729 struct ebda_hpc_bus *buses;
730 struct pci_dev *ctrl_dev;
731 u8 starting_slot_num;
732 u8 ending_slot_num;
733 u8 revision;
734 u8 options;
735 u8 status;
736 u8 ctlr_id;
737 u8 slot_count;
738 u8 bus_count;
739 u8 ctlr_relative_id;
740 u32 irq;
741 union {
742 struct isa_ctlr_access isa_ctlr;
743 struct pci_ctlr_access pci_ctlr;
744 struct wpeg_i2c_ctlr_access wpeg_ctlr;
745 } u;
746 u8 ctlr_type;
747 struct list_head ebda_hpc_list;
748};
749
750
751
752int ibmphp_init_devno(struct slot **);
753int ibmphp_do_disable_slot(struct slot *slot_cur);
754int ibmphp_update_slot_info(struct slot *);
755int ibmphp_configure_card(struct pci_func *, u8);
756int ibmphp_unconfigure_card(struct slot **, int);
757extern struct hotplug_slot_ops ibmphp_hotplug_slot_ops;
758
759#endif
760
761
