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21#define EXYNOS_GPIO_ECON_OFFSET 0x700
22#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
23#define EXYNOS_GPIO_EMASK_OFFSET 0x900
24#define EXYNOS_GPIO_EPEND_OFFSET 0xA00
25#define EXYNOS_WKUP_ECON_OFFSET 0xE00
26#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
27#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
28#define EXYNOS_SVC_OFFSET 0xB08
29#define EXYNOS_EINT_FUNC 0xF
30
31
32#define EXYNOS_SVC_GROUP_SHIFT 3
33#define EXYNOS_SVC_GROUP_MASK 0x1f
34#define EXYNOS_SVC_NUM_MASK 7
35#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
36 EXYNOS_SVC_GROUP_MASK)
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38
39#define EXYNOS_EINT_LEVEL_LOW 0
40#define EXYNOS_EINT_LEVEL_HIGH 1
41#define EXYNOS_EINT_EDGE_FALLING 2
42#define EXYNOS_EINT_EDGE_RISING 3
43#define EXYNOS_EINT_EDGE_BOTH 4
44#define EXYNOS_EINT_CON_MASK 0xF
45#define EXYNOS_EINT_CON_LEN 4
46
47#define EXYNOS_EINT_MAX_PER_BANK 8
48#define EXYNOS_EINT_NR_WKUP_EINT
49
50#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
51 { \
52 .type = &bank_type_off, \
53 .pctl_offset = reg, \
54 .nr_pins = pins, \
55 .eint_type = EINT_TYPE_NONE, \
56 .name = id \
57 }
58
59#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \
60 { \
61 .type = &bank_type_off, \
62 .pctl_offset = reg, \
63 .nr_pins = pins, \
64 .eint_type = EINT_TYPE_GPIO, \
65 .eint_offset = offs, \
66 .name = id \
67 }
68
69#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \
70 { \
71 .type = &bank_type_alive, \
72 .pctl_offset = reg, \
73 .nr_pins = pins, \
74 .eint_type = EINT_TYPE_WKUP, \
75 .eint_offset = offs, \
76 .name = id \
77 }
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85struct exynos_weint_data {
86 unsigned int irq;
87 struct samsung_pin_bank *bank;
88};
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96struct exynos_muxed_weint_data {
97 unsigned int nr_banks;
98 struct samsung_pin_bank *banks[];
99};
100