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33#ifndef _AACRAID_H_
34#define _AACRAID_H_
35#ifndef dprintk
36# define dprintk(x)
37#endif
38
39#define _nblank(x) #x
40#define nblank(x) _nblank(x)[0]
41
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44
45
46
47
48
49#define AAC_MAX_MSIX 32
50#define AAC_PCI_MSI_ENABLE 0x8000
51
52enum {
53 AAC_ENABLE_INTERRUPT = 0x0,
54 AAC_DISABLE_INTERRUPT,
55 AAC_ENABLE_MSIX,
56 AAC_DISABLE_MSIX,
57 AAC_CLEAR_AIF_BIT,
58 AAC_CLEAR_SYNC_BIT,
59 AAC_ENABLE_INTX
60};
61
62#define AAC_INT_MODE_INTX (1<<0)
63#define AAC_INT_MODE_MSI (1<<1)
64#define AAC_INT_MODE_AIF (1<<2)
65#define AAC_INT_MODE_SYNC (1<<3)
66#define AAC_INT_MODE_MSIX (1<<16)
67
68#define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
69#define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
70#define AAC_INT_DISABLE_ALL 0xffffffff
71
72
73#define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
74#define PMC_IOARCB_TRANSFER_FAILED (1<<28)
75#define PMC_IOA_UNIT_CHECK (1<<27)
76#define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
77#define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
78#define PMC_IOARRIN_LOST (1<<4)
79#define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
80#define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
81#define PMC_HOST_RRQ_VALID (1<<1)
82#define PMC_OPERATIONAL_STATUS (1<<31)
83#define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
84
85#define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
86 PMC_IOA_UNIT_CHECK | \
87 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
88 PMC_IOARRIN_LOST | \
89 PMC_SYSTEM_BUS_MMIO_ERROR | \
90 PMC_IOA_PROCESSOR_IN_ERROR_STATE)
91
92#define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
93 PMC_HOST_RRQ_VALID | \
94 PMC_TRANSITION_TO_OPERATIONAL | \
95 PMC_ALLOW_MSIX_VECTOR0)
96#define PMC_GLOBAL_INT_BIT2 0x00000004
97#define PMC_GLOBAL_INT_BIT0 0x00000001
98
99#ifndef AAC_DRIVER_BUILD
100# define AAC_DRIVER_BUILD 50792
101# define AAC_DRIVER_BRANCH "-custom"
102#endif
103#define MAXIMUM_NUM_CONTAINERS 32
104
105#define AAC_NUM_MGT_FIB 8
106#define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
107#define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
108
109#define AAC_MAX_LUN 256
110
111#define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
112#define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
113
114#define AAC_DEBUG_INSTRUMENT_AIF_DELETE
115
116#define AAC_MAX_NATIVE_TARGETS 1024
117
118#define AAC_MAX_BUSES 5
119#define AAC_MAX_TARGETS 256
120#define AAC_MAX_NATIVE_SIZE 2048
121#define FW_ERROR_BUFFER_SIZE 512
122
123
124#define SA_AIF_HOTPLUG (1<<1)
125#define SA_AIF_HARDWARE (1<<2)
126#define SA_AIF_PDEV_CHANGE (1<<4)
127#define SA_AIF_LDEV_CHANGE (1<<5)
128#define SA_AIF_BPSTAT_CHANGE (1<<30)
129#define SA_AIF_BPCFG_CHANGE (1<<31)
130
131#define HBA_MAX_SG_EMBEDDED 28
132#define HBA_MAX_SG_SEPARATE 90
133#define HBA_SENSE_DATA_LEN_MAX 32
134#define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002
135#define HBA_SGL_FLAGS_EXT 0x80000000UL
136
137struct aac_hba_sgl {
138 u32 addr_lo;
139 u32 addr_hi;
140 u32 len;
141 u32 flags;
142};
143
144enum {
145 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40,
146 HBA_IU_TYPE_SCSI_TM_REQ = 0x41,
147 HBA_IU_TYPE_SATA_REQ = 0x42,
148 HBA_IU_TYPE_RESP = 0x60,
149 HBA_IU_TYPE_COALESCED_RESP = 0x61,
150 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70
151};
152
153enum {
154 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1,
155 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2,
156 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4,
157 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8
158};
159
160enum {
161 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0,
162 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT,
163 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR,
164 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
165};
166
167enum {
168 HBA_RESP_DATAPRES_NO_DATA = 0x0,
169 HBA_RESP_DATAPRES_RESPONSE_DATA,
170 HBA_RESP_DATAPRES_SENSE_DATA
171};
172
173enum {
174 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0,
175 HBA_RESP_SVCRES_FAILURE,
176 HBA_RESP_SVCRES_TMF_COMPLETE,
177 HBA_RESP_SVCRES_TMF_SUCCEEDED,
178 HBA_RESP_SVCRES_TMF_REJECTED,
179 HBA_RESP_SVCRES_TMF_LUN_INVALID
180};
181
182enum {
183 HBA_RESP_STAT_IO_ERROR = 0x1,
184 HBA_RESP_STAT_IO_ABORTED,
185 HBA_RESP_STAT_NO_PATH_TO_DEVICE,
186 HBA_RESP_STAT_INVALID_DEVICE,
187 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE,
188 HBA_RESP_STAT_UNDERRUN = 0x51,
189 HBA_RESP_STAT_OVERRUN = 0x75
190};
191
192struct aac_hba_cmd_req {
193 u8 iu_type;
194
195
196
197
198
199
200 u8 byte1;
201 u8 reply_qid;
202 u8 reserved1;
203 __le32 it_nexus;
204 __le32 request_id;
205
206 __le32 tweak_value_lo;
207 u8 cdb[16];
208 u8 lun[8];
209
210
211 __le32 data_length;
212
213
214 u8 attr_prio;
215
216
217 u8 emb_data_desc_count;
218
219 __le16 dek_index;
220
221
222 __le32 error_ptr_lo;
223
224
225 __le32 error_ptr_hi;
226
227
228 __le32 error_length;
229
230
231 __le32 tweak_value_hi;
232
233 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2];
234
235
236
237
238
239};
240
241
242#define HBA_TMF_ABORT_TASK 0x01
243#define HBA_TMF_LUN_RESET 0x08
244
245struct aac_hba_tm_req {
246 u8 iu_type;
247 u8 reply_qid;
248 u8 tmf;
249 u8 reserved1;
250
251 __le32 it_nexus;
252
253 u8 lun[8];
254
255
256 __le32 request_id;
257 __le32 reserved2;
258
259
260 __le32 managed_request_id;
261 __le32 reserved3;
262
263
264 __le32 error_ptr_lo;
265
266 __le32 error_ptr_hi;
267
268 __le32 error_length;
269};
270
271struct aac_hba_reset_req {
272 u8 iu_type;
273
274 u8 reset_type;
275 u8 reply_qid;
276 u8 reserved1;
277
278 __le32 it_nexus;
279 __le32 request_id;
280
281 __le32 error_ptr_lo;
282
283 __le32 error_ptr_hi;
284
285 __le32 error_length;
286};
287
288struct aac_hba_resp {
289 u8 iu_type;
290 u8 reserved1[3];
291 __le32 request_identifier;
292 __le32 reserved2;
293 u8 service_response;
294 u8 status;
295 u8 datapres;
296 u8 sense_response_data_len;
297 __le32 residual_count;
298
299 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX];
300};
301
302struct aac_native_hba {
303 union {
304 struct aac_hba_cmd_req cmd;
305 struct aac_hba_tm_req tmr;
306 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
307 } cmd;
308 union {
309 struct aac_hba_resp err;
310 u8 resp_bytes[FW_ERROR_BUFFER_SIZE];
311 } resp;
312};
313
314#define CISS_REPORT_PHYSICAL_LUNS 0xc3
315#define WRITE_HOST_WELLNESS 0xa5
316#define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15
317#define BMIC_IN 0x26
318#define BMIC_OUT 0x27
319
320struct aac_ciss_phys_luns_resp {
321 u8 list_length[4];
322 u8 resp_flag;
323 u8 reserved[3];
324 struct _ciss_lun {
325 u8 tid[3];
326 u8 bus;
327 u8 level3[2];
328 u8 level2[2];
329 u8 node_ident[16];
330 } lun[1];
331};
332
333
334
335
336#define AAC_MAX_HRRQ 64
337
338struct aac_ciss_identify_pd {
339 u8 scsi_bus;
340 u8 scsi_id;
341 u16 block_size;
342 u32 total_blocks;
343 u32 reserved_blocks;
344 u8 model[40];
345 u8 serial_number[40];
346 u8 firmware_revision[8];
347 u8 scsi_inquiry_bits;
348 u8 compaq_drive_stamp;
349 u8 last_failure_reason;
350
351 u8 flags;
352 u8 more_flags;
353 u8 scsi_lun;
354 u8 yet_more_flags;
355 u8 even_more_flags;
356 u32 spi_speed_rules;
357 u8 phys_connector[2];
358 u8 phys_box_on_bus;
359 u8 phys_bay_in_box;
360 u32 rpm;
361 u8 device_type;
362 u8 sata_version;
363 u64 big_total_block_count;
364 u64 ris_starting_lba;
365 u32 ris_size;
366 u8 wwid[20];
367 u8 controller_phy_map[32];
368 u16 phy_count;
369 u8 phy_connected_dev_type[256];
370 u8 phy_to_drive_bay_num[256];
371 u16 phy_to_attached_dev_index[256];
372 u8 box_index;
373 u8 spitfire_support;
374 u16 extra_physical_drive_flags;
375 u8 negotiated_link_rate[256];
376 u8 phy_to_phy_map[256];
377 u8 redundant_path_present_map;
378 u8 redundant_path_failure_map;
379 u8 active_path_number;
380 u16 alternate_paths_phys_connector[8];
381 u8 alternate_paths_phys_box_on_port[8];
382 u8 multi_lun_device_lun_count;
383 u8 minimum_good_fw_revision[8];
384 u8 unique_inquiry_bytes[20];
385 u8 current_temperature_degreesC;
386 u8 temperature_threshold_degreesC;
387 u8 max_temperature_degreesC;
388 u8 logical_blocks_per_phys_block_exp;
389 u16 current_queue_depth_limit;
390 u8 switch_name[10];
391 u16 switch_port;
392 u8 alternate_paths_switch_name[40];
393 u8 alternate_paths_switch_port[8];
394 u16 power_on_hours;
395 u16 percent_endurance_used;
396 u8 drive_authentication;
397 u8 smart_carrier_authentication;
398 u8 smart_carrier_app_fw_version;
399 u8 smart_carrier_bootloader_fw_version;
400 u8 SanitizeSecureEraseSupport;
401 u8 DriveKeyFlags;
402 u8 encryption_key_name[64];
403 u32 misc_drive_flags;
404 u16 dek_index;
405 u16 drive_encryption_flags;
406 u8 sanitize_maximum_time[6];
407 u8 connector_info_mode;
408 u8 connector_info_number[4];
409 u8 long_connector_name[64];
410 u8 device_unique_identifier[16];
411 u8 padto_2K[17];
412} __packed;
413
414
415
416
417#define CONTAINER_CHANNEL (0)
418#define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
419#define CONTAINER_TO_ID(cont) (cont)
420#define CONTAINER_TO_LUN(cont) (0)
421#define ENCLOSURE_CHANNEL (3)
422
423#define PMC_DEVICE_S6 0x28b
424#define PMC_DEVICE_S7 0x28c
425#define PMC_DEVICE_S8 0x28d
426#define PMC_DEVICE_S9 0x28f
427
428#define aac_phys_to_logical(x) ((x)+1)
429#define aac_logical_to_phys(x) ((x)?(x)-1:0)
430
431
432
433
434
435#define AAC_CHARDEV_UNREGISTERED (-1)
436#define AAC_CHARDEV_NEEDS_REINIT (-2)
437
438
439
440struct diskparm
441{
442 int heads;
443 int sectors;
444 int cylinders;
445};
446
447
448
449
450
451
452#define CT_NONE 0
453#define CT_OK 218
454#define FT_FILESYS 8
455#define FT_DRIVE 9
456
457
458
459
460
461
462
463struct sgentry {
464 __le32 addr;
465 __le32 count;
466};
467
468struct user_sgentry {
469 u32 addr;
470 u32 count;
471};
472
473struct sgentry64 {
474 __le32 addr[2];
475 __le32 count;
476};
477
478struct user_sgentry64 {
479 u32 addr[2];
480 u32 count;
481};
482
483struct sgentryraw {
484 __le32 next;
485 __le32 prev;
486 __le32 addr[2];
487 __le32 count;
488 __le32 flags;
489};
490
491struct user_sgentryraw {
492 u32 next;
493 u32 prev;
494 u32 addr[2];
495 u32 count;
496 u32 flags;
497};
498
499struct sge_ieee1212 {
500 u32 addrLow;
501 u32 addrHigh;
502 u32 length;
503 u32 flags;
504};
505
506
507
508
509
510
511
512
513struct sgmap {
514 __le32 count;
515 struct sgentry sg[1];
516};
517
518struct user_sgmap {
519 u32 count;
520 struct user_sgentry sg[1];
521};
522
523struct sgmap64 {
524 __le32 count;
525 struct sgentry64 sg[1];
526};
527
528struct user_sgmap64 {
529 u32 count;
530 struct user_sgentry64 sg[1];
531};
532
533struct sgmapraw {
534 __le32 count;
535 struct sgentryraw sg[1];
536};
537
538struct user_sgmapraw {
539 u32 count;
540 struct user_sgentryraw sg[1];
541};
542
543struct creation_info
544{
545 u8 buildnum;
546 u8 usec;
547 u8 via;
548
549
550 u8 year;
551 __le32 date;
552
553
554
555
556
557
558 __le32 serial[2];
559};
560
561
562
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564
565
566
567
568
569
570
571
572
573
574#define NUMBER_OF_COMM_QUEUES 8
575#define HOST_HIGH_CMD_ENTRIES 4
576#define HOST_NORM_CMD_ENTRIES 8
577#define ADAP_HIGH_CMD_ENTRIES 4
578#define ADAP_NORM_CMD_ENTRIES 512
579#define HOST_HIGH_RESP_ENTRIES 4
580#define HOST_NORM_RESP_ENTRIES 512
581#define ADAP_HIGH_RESP_ENTRIES 4
582#define ADAP_NORM_RESP_ENTRIES 8
583
584#define TOTAL_QUEUE_ENTRIES \
585 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
586 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
587
588
589
590
591
592
593#define QUEUE_ALIGNMENT 16
594
595
596
597
598
599
600
601
602struct aac_entry {
603 __le32 size;
604 __le32 addr;
605};
606
607
608
609
610
611
612struct aac_qhdr {
613 __le64 header_addr;
614
615 __le32 *producer;
616 __le32 *consumer;
617};
618
619
620
621
622
623
624#define HostNormCmdQue 1
625#define HostHighCmdQue 2
626#define HostNormRespQue 3
627#define HostHighRespQue 4
628#define AdapNormRespNotFull 5
629#define AdapHighRespNotFull 6
630#define AdapNormCmdNotFull 7
631#define AdapHighCmdNotFull 8
632#define SynchCommandComplete 9
633#define AdapInternalError 0xfe
634
635
636
637
638
639
640
641#define AdapNormCmdQue 2
642#define AdapHighCmdQue 3
643#define AdapNormRespQue 6
644#define AdapHighRespQue 7
645#define HostShutdown 8
646#define HostPowerFail 9
647#define FatalCommError 10
648#define HostNormRespNotFull 11
649#define HostHighRespNotFull 12
650#define HostNormCmdNotFull 13
651#define HostHighCmdNotFull 14
652#define FastIo 15
653#define AdapPrintfDone 16
654
655
656
657
658
659
660enum aac_queue_types {
661 HostNormCmdQueue = 0,
662 HostHighCmdQueue,
663 AdapNormCmdQueue,
664 AdapHighCmdQueue,
665 HostNormRespQueue,
666 HostHighRespQueue,
667 AdapNormRespQueue,
668 AdapHighRespQueue
669};
670
671
672
673
674
675#define FIB_MAGIC 0x0001
676#define FIB_MAGIC2 0x0004
677#define FIB_MAGIC2_64 0x0005
678
679
680
681
682
683#define FsaNormal 1
684
685
686struct aac_fib_xporthdr {
687 __le64 HostAddress;
688 __le32 Size;
689 __le32 Handle;
690 __le64 Reserved[2];
691};
692
693#define ALIGN32 32
694
695
696
697
698
699
700struct aac_fibhdr {
701 __le32 XferState;
702 __le16 Command;
703 u8 StructType;
704 u8 Unused;
705 __le16 Size;
706 __le16 SenderSize;
707
708 __le32 SenderFibAddress;
709 union {
710 __le32 ReceiverFibAddress;
711
712 __le32 SenderFibAddressHigh;
713 __le32 TimeStamp;
714 } u;
715 __le32 Handle;
716 u32 Previous;
717 u32 Next;
718};
719
720struct hw_fib {
721 struct aac_fibhdr header;
722 u8 data[512-sizeof(struct aac_fibhdr)];
723};
724
725
726
727
728
729#define TestCommandResponse 1
730#define TestAdapterCommand 2
731
732
733
734#define LastTestCommand 100
735#define ReinitHostNormCommandQueue 101
736#define ReinitHostHighCommandQueue 102
737#define ReinitHostHighRespQueue 103
738#define ReinitHostNormRespQueue 104
739#define ReinitAdapNormCommandQueue 105
740#define ReinitAdapHighCommandQueue 107
741#define ReinitAdapHighRespQueue 108
742#define ReinitAdapNormRespQueue 109
743#define InterfaceShutdown 110
744#define DmaCommandFib 120
745#define StartProfile 121
746#define TermProfile 122
747#define SpeedTest 123
748#define TakeABreakPt 124
749#define RequestPerfData 125
750#define SetInterruptDefTimer 126
751#define SetInterruptDefCount 127
752#define GetInterruptDefStatus 128
753#define LastCommCommand 129
754
755
756
757#define NuFileSystem 300
758#define UFS 301
759#define HostFileSystem 302
760#define LastFileSystemCommand 303
761
762
763
764#define ContainerCommand 500
765#define ContainerCommand64 501
766#define ContainerRawIo 502
767#define ContainerRawIo2 503
768
769
770
771#define ScsiPortCommand 600
772#define ScsiPortCommand64 601
773
774
775
776#define AifRequest 700
777#define CheckRevision 701
778#define FsaHostShutdown 702
779#define RequestAdapterInfo 703
780#define IsAdapterPaused 704
781#define SendHostTime 705
782#define RequestSupplementAdapterInfo 706
783#define LastMiscCommand 707
784
785
786
787
788
789enum fib_xfer_state {
790 HostOwned = (1<<0),
791 AdapterOwned = (1<<1),
792 FibInitialized = (1<<2),
793 FibEmpty = (1<<3),
794 AllocatedFromPool = (1<<4),
795 SentFromHost = (1<<5),
796 SentFromAdapter = (1<<6),
797 ResponseExpected = (1<<7),
798 NoResponseExpected = (1<<8),
799 AdapterProcessed = (1<<9),
800 HostProcessed = (1<<10),
801 HighPriority = (1<<11),
802 NormalPriority = (1<<12),
803 Async = (1<<13),
804 AsyncIo = (1<<13),
805 PageFileIo = (1<<14),
806 ShutdownRequest = (1<<15),
807 LazyWrite = (1<<16),
808 AdapterMicroFib = (1<<17),
809 BIOSFibPath = (1<<18),
810 FastResponseCapable = (1<<19),
811 ApiFib = (1<<20),
812
813 NoMoreAifDataAvailable = (1<<21)
814};
815
816
817
818
819
820
821#define ADAPTER_INIT_STRUCT_REVISION 3
822#define ADAPTER_INIT_STRUCT_REVISION_4 4
823#define ADAPTER_INIT_STRUCT_REVISION_6 6
824#define ADAPTER_INIT_STRUCT_REVISION_7 7
825#define ADAPTER_INIT_STRUCT_REVISION_8 8
826
827union aac_init
828{
829 struct _r7 {
830 __le32 init_struct_revision;
831 __le32 no_of_msix_vectors;
832 __le32 fsrev;
833 __le32 comm_header_address;
834 __le32 fast_io_comm_area_address;
835 __le32 adapter_fibs_physical_address;
836 __le32 adapter_fibs_virtual_address;
837 __le32 adapter_fibs_size;
838 __le32 adapter_fib_align;
839 __le32 printfbuf;
840 __le32 printfbufsiz;
841
842 __le32 host_phys_mem_pages;
843
844 __le32 host_elapsed_seconds;
845
846 __le32 init_flags;
847#define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
848#define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
849#define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
850#define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
851#define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
852#define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
853#define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400
854 __le32 max_io_commands;
855 __le32 max_io_size;
856 __le32 max_fib_size;
857
858 __le32 max_num_aif;
859
860
861 __le32 host_rrq_addr_low;
862 __le32 host_rrq_addr_high;
863 } r7;
864 struct _r8 {
865
866 __le32 init_struct_revision;
867 __le32 rr_queue_count;
868 __le32 host_elapsed_seconds;
869 __le32 init_flags;
870 __le32 max_io_size;
871 __le32 max_num_aif;
872 __le32 reserved1;
873 __le32 reserved2;
874 struct _rrq {
875 __le32 host_addr_low;
876 __le32 host_addr_high;
877 __le16 msix_id;
878 __le16 element_count;
879 __le16 comp_thresh;
880 __le16 unused;
881 } rrq[1];
882 } r8;
883};
884
885enum aac_log_level {
886 LOG_AAC_INIT = 10,
887 LOG_AAC_INFORMATIONAL = 20,
888 LOG_AAC_WARNING = 30,
889 LOG_AAC_LOW_ERROR = 40,
890 LOG_AAC_MEDIUM_ERROR = 50,
891 LOG_AAC_HIGH_ERROR = 60,
892 LOG_AAC_PANIC = 70,
893 LOG_AAC_DEBUG = 80,
894 LOG_AAC_WINDBG_PRINT = 90
895};
896
897#define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
898#define FSAFS_NTC_FIB_CONTEXT 0x030c
899
900struct aac_dev;
901struct fib;
902struct scsi_cmnd;
903
904struct adapter_ops
905{
906
907 void (*adapter_interrupt)(struct aac_dev *dev);
908 void (*adapter_notify)(struct aac_dev *dev, u32 event);
909 void (*adapter_disable_int)(struct aac_dev *dev);
910 void (*adapter_enable_int)(struct aac_dev *dev);
911 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
912 int (*adapter_check_health)(struct aac_dev *dev);
913 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type);
914 void (*adapter_start)(struct aac_dev *dev);
915
916 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
917 irq_handler_t adapter_intr;
918
919 int (*adapter_deliver)(struct fib * fib);
920 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
921 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
922 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
923 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
924
925 int (*adapter_comm)(struct aac_dev * dev, int comm);
926};
927
928
929
930
931
932struct aac_driver_ident
933{
934 int (*init)(struct aac_dev *dev);
935 char * name;
936 char * vname;
937 char * model;
938 u16 channels;
939 int quirks;
940};
941
942
943
944
945
946
947#define AAC_QUIRK_31BIT 0x0001
948
949
950
951
952
953
954#define AAC_QUIRK_34SG 0x0002
955
956
957
958
959#define AAC_QUIRK_SLAVE 0x0004
960
961
962
963
964#define AAC_QUIRK_MASTER 0x0008
965
966
967
968
969
970
971#define AAC_QUIRK_17SG 0x0010
972
973
974
975
976
977#define AAC_QUIRK_SCSI_32 0x0020
978
979
980
981
982#define AAC_QUIRK_SRC 0x0040
983
984
985
986
987
988
989
990
991
992
993
994struct aac_queue {
995 u64 logical;
996 struct aac_entry *base;
997 struct aac_qhdr headers;
998 u32 entries;
999 wait_queue_head_t qfull;
1000 wait_queue_head_t cmdready;
1001
1002 spinlock_t *lock;
1003 spinlock_t lockdata;
1004 struct list_head cmdq;
1005
1006
1007 atomic_t numpending;
1008 struct aac_dev * dev;
1009};
1010
1011
1012
1013
1014
1015
1016struct aac_queue_block
1017{
1018 struct aac_queue queue[8];
1019};
1020
1021
1022
1023
1024
1025struct sa_drawbridge_CSR {
1026
1027 __le32 reserved[10];
1028 u8 LUT_Offset;
1029 u8 reserved1[3];
1030 __le32 LUT_Data;
1031 __le32 reserved2[26];
1032 __le16 PRICLEARIRQ;
1033 __le16 SECCLEARIRQ;
1034 __le16 PRISETIRQ;
1035 __le16 SECSETIRQ;
1036 __le16 PRICLEARIRQMASK;
1037 __le16 SECCLEARIRQMASK;
1038 __le16 PRISETIRQMASK;
1039 __le16 SECSETIRQMASK;
1040 __le32 MAILBOX0;
1041 __le32 MAILBOX1;
1042 __le32 MAILBOX2;
1043 __le32 MAILBOX3;
1044 __le32 MAILBOX4;
1045 __le32 MAILBOX5;
1046 __le32 MAILBOX6;
1047 __le32 MAILBOX7;
1048 __le32 ROM_Setup_Data;
1049 __le32 ROM_Control_Addr;
1050 __le32 reserved3[12];
1051 __le32 LUT[64];
1052};
1053
1054#define Mailbox0 SaDbCSR.MAILBOX0
1055#define Mailbox1 SaDbCSR.MAILBOX1
1056#define Mailbox2 SaDbCSR.MAILBOX2
1057#define Mailbox3 SaDbCSR.MAILBOX3
1058#define Mailbox4 SaDbCSR.MAILBOX4
1059#define Mailbox5 SaDbCSR.MAILBOX5
1060#define Mailbox6 SaDbCSR.MAILBOX6
1061#define Mailbox7 SaDbCSR.MAILBOX7
1062
1063#define DoorbellReg_p SaDbCSR.PRISETIRQ
1064#define DoorbellReg_s SaDbCSR.SECSETIRQ
1065#define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
1066
1067
1068#define DOORBELL_0 0x0001
1069#define DOORBELL_1 0x0002
1070#define DOORBELL_2 0x0004
1071#define DOORBELL_3 0x0008
1072#define DOORBELL_4 0x0010
1073#define DOORBELL_5 0x0020
1074#define DOORBELL_6 0x0040
1075
1076
1077#define PrintfReady DOORBELL_5
1078#define PrintfDone DOORBELL_5
1079
1080struct sa_registers {
1081 struct sa_drawbridge_CSR SaDbCSR;
1082};
1083
1084
1085#define SA_INIT_NUM_MSIXVECTORS 1
1086#define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS
1087
1088#define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1089#define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1090#define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
1091#define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
1092
1093
1094
1095
1096
1097struct rx_mu_registers {
1098
1099 __le32 ARSR;
1100 __le32 reserved0;
1101 __le32 AWR;
1102 __le32 reserved1;
1103 __le32 IMRx[2];
1104 __le32 OMRx[2];
1105 __le32 IDR;
1106 __le32 IISR;
1107
1108 __le32 IIMR;
1109
1110 __le32 ODR;
1111 __le32 OISR;
1112
1113 __le32 OIMR;
1114
1115 __le32 reserved2;
1116 __le32 reserved3;
1117 __le32 InboundQueue;
1118 __le32 OutboundQueue;
1119
1120
1121};
1122
1123struct rx_inbound {
1124 __le32 Mailbox[8];
1125};
1126
1127#define INBOUNDDOORBELL_0 0x00000001
1128#define INBOUNDDOORBELL_1 0x00000002
1129#define INBOUNDDOORBELL_2 0x00000004
1130#define INBOUNDDOORBELL_3 0x00000008
1131#define INBOUNDDOORBELL_4 0x00000010
1132#define INBOUNDDOORBELL_5 0x00000020
1133#define INBOUNDDOORBELL_6 0x00000040
1134
1135#define OUTBOUNDDOORBELL_0 0x00000001
1136#define OUTBOUNDDOORBELL_1 0x00000002
1137#define OUTBOUNDDOORBELL_2 0x00000004
1138#define OUTBOUNDDOORBELL_3 0x00000008
1139#define OUTBOUNDDOORBELL_4 0x00000010
1140
1141#define InboundDoorbellReg MUnit.IDR
1142#define OutboundDoorbellReg MUnit.ODR
1143
1144struct rx_registers {
1145 struct rx_mu_registers MUnit;
1146 __le32 reserved1[2];
1147 struct rx_inbound IndexRegs;
1148};
1149
1150#define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
1151#define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
1152#define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
1153#define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
1154
1155
1156
1157
1158
1159#define rkt_mu_registers rx_mu_registers
1160#define rkt_inbound rx_inbound
1161
1162struct rkt_registers {
1163 struct rkt_mu_registers MUnit;
1164 __le32 reserved1[1006];
1165 struct rkt_inbound IndexRegs;
1166};
1167
1168#define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
1169#define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
1170#define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
1171#define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
1172
1173
1174
1175
1176
1177#define src_inbound rx_inbound
1178
1179struct src_mu_registers {
1180
1181 __le32 reserved0[6];
1182 __le32 IOAR[2];
1183 __le32 IDR;
1184 __le32 IISR;
1185 __le32 reserved1[3];
1186 __le32 OIMR;
1187 __le32 reserved2[25];
1188 __le32 ODR_R;
1189 __le32 ODR_C;
1190 __le32 reserved3[3];
1191 __le32 SCR0;
1192 __le32 reserved4[2];
1193 __le32 OMR;
1194 __le32 IQ_L;
1195 __le32 IQ_H;
1196 __le32 ODR_MSI;
1197 __le32 reserved5;
1198 __le32 IQN_L;
1199 __le32 IQN_H;
1200};
1201
1202struct src_registers {
1203 struct src_mu_registers MUnit;
1204 union {
1205 struct {
1206 __le32 reserved1[130786];
1207 struct src_inbound IndexRegs;
1208 } tupelo;
1209 struct {
1210 __le32 reserved1[970];
1211 struct src_inbound IndexRegs;
1212 } denali;
1213 } u;
1214};
1215
1216#define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
1217#define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
1218#define src_writeb(AEP, CSR, value) writeb(value, \
1219 &((AEP)->regs.src.bar0->CSR))
1220#define src_writel(AEP, CSR, value) writel(value, \
1221 &((AEP)->regs.src.bar0->CSR))
1222#if defined(writeq)
1223#define src_writeq(AEP, CSR, value) writeq(value, \
1224 &((AEP)->regs.src.bar0->CSR))
1225#endif
1226
1227#define SRC_ODR_SHIFT 12
1228#define SRC_IDR_SHIFT 9
1229
1230typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
1231
1232struct aac_fib_context {
1233 s16 type;
1234 s16 size;
1235 u32 unique;
1236 ulong jiffies;
1237 struct list_head next;
1238 struct semaphore wait_sem;
1239 int wait;
1240 unsigned long count;
1241 struct list_head fib_list;
1242};
1243
1244struct sense_data {
1245 u8 error_code;
1246 u8 valid:1;
1247
1248
1249
1250 u8 segment_number;
1251 u8 sense_key:4;
1252 u8 reserved:1;
1253 u8 ILI:1;
1254 u8 EOM:1;
1255 u8 filemark:1;
1256
1257 u8 information[4];
1258
1259
1260
1261 u8 add_sense_len;
1262 u8 cmnd_info[4];
1263 u8 ASC;
1264 u8 ASCQ;
1265 u8 FRUC;
1266 u8 bit_ptr:3;
1267
1268
1269 u8 BPV:1;
1270
1271
1272 u8 reserved2:2;
1273 u8 CD:1;
1274
1275
1276 u8 SKSV:1;
1277 u8 field_ptr[2];
1278};
1279
1280struct fsa_dev_info {
1281 u64 last;
1282 u64 size;
1283 u32 type;
1284 u32 config_waiting_on;
1285 unsigned long config_waiting_stamp;
1286 u16 queue_depth;
1287 u8 config_needed;
1288 u8 valid;
1289 u8 ro;
1290 u8 locked;
1291 u8 deleted;
1292 char devname[8];
1293 struct sense_data sense_data;
1294 u32 block_size;
1295 u8 identifier[16];
1296};
1297
1298struct fib {
1299 void *next;
1300 s16 type;
1301 s16 size;
1302
1303
1304
1305 struct aac_dev *dev;
1306
1307
1308
1309
1310 struct semaphore event_wait;
1311 spinlock_t event_lock;
1312
1313 u32 done;
1314 fib_callback callback;
1315 void *callback_data;
1316 u32 flags;
1317
1318
1319
1320
1321 struct list_head fiblink;
1322 void *data;
1323 u32 vector_no;
1324 struct hw_fib *hw_fib_va;
1325 dma_addr_t hw_fib_pa;
1326 dma_addr_t hw_sgl_pa;
1327 dma_addr_t hw_error_pa;
1328 u32 hbacmd_size;
1329};
1330
1331#define AAC_INIT 0
1332#define AAC_RESCAN 1
1333
1334#define AAC_DEVTYPE_RAID_MEMBER 1
1335#define AAC_DEVTYPE_ARC_RAW 2
1336#define AAC_DEVTYPE_NATIVE_RAW 3
1337#define AAC_EXPOSE_DISK 0
1338#define AAC_HIDE_DISK 3
1339
1340struct aac_hba_map_info {
1341 __le32 rmw_nexus;
1342 u8 devtype;
1343 u8 new_devtype;
1344 u8 reset_state;
1345
1346 u16 qd_limit;
1347 u8 expose;
1348};
1349
1350
1351
1352
1353
1354
1355
1356struct aac_adapter_info
1357{
1358 __le32 platform;
1359 __le32 cpu;
1360 __le32 subcpu;
1361 __le32 clock;
1362 __le32 execmem;
1363 __le32 buffermem;
1364 __le32 totalmem;
1365 __le32 kernelrev;
1366 __le32 kernelbuild;
1367 __le32 monitorrev;
1368 __le32 monitorbuild;
1369 __le32 hwrev;
1370 __le32 hwbuild;
1371 __le32 biosrev;
1372 __le32 biosbuild;
1373 __le32 cluster;
1374 __le32 clusterchannelmask;
1375 __le32 serial[2];
1376 __le32 battery;
1377 __le32 options;
1378 __le32 OEM;
1379};
1380
1381struct aac_supplement_adapter_info
1382{
1383 u8 adapter_type_text[17+1];
1384 u8 pad[2];
1385 __le32 flash_memory_byte_size;
1386 __le32 flash_image_id;
1387 __le32 max_number_ports;
1388 __le32 version;
1389 __le32 feature_bits;
1390 u8 slot_number;
1391 u8 reserved_pad0[3];
1392 u8 build_date[12];
1393 __le32 current_number_ports;
1394 struct {
1395 u8 assembly_pn[8];
1396 u8 fru_pn[8];
1397 u8 battery_fru_pn[8];
1398 u8 ec_version_string[8];
1399 u8 tsid[12];
1400 } vpd_info;
1401 __le32 flash_firmware_revision;
1402 __le32 flash_firmware_build;
1403 __le32 raid_type_morph_options;
1404 __le32 flash_firmware_boot_revision;
1405 __le32 flash_firmware_boot_build;
1406 u8 mfg_pcba_serial_no[12];
1407 u8 mfg_wwn_name[8];
1408 __le32 supported_options2;
1409 __le32 struct_expansion;
1410
1411 __le32 feature_bits3;
1412 __le32 supported_performance_modes;
1413 u8 host_bus_type;
1414 u8 host_bus_width;
1415 u16 host_bus_speed;
1416 u8 max_rrc_drives;
1417 u8 max_disk_xtasks;
1418
1419 u8 cpld_ver_loaded;
1420 u8 cpld_ver_in_flash;
1421
1422 __le64 max_rrc_capacity;
1423 __le32 compiled_max_hist_log_level;
1424 u8 custom_board_name[12];
1425 u16 supported_cntlr_mode;
1426 u16 reserved_for_future16;
1427 __le32 supported_options3;
1428
1429 __le16 virt_device_bus;
1430 __le16 virt_device_target;
1431 __le16 virt_device_lun;
1432 __le16 unused;
1433 __le32 reserved_for_future_growth[68];
1434
1435};
1436#define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
1437#define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
1438
1439#define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
1440#define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
1441#define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
1442#define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
1443
1444#define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
1445
1446#define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1447
1448
1449
1450#define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000)
1451#define AAC_SIS_VERSION_V3 3
1452#define AAC_SIS_SLOT_UNKNOWN 0xFF
1453
1454#define GetBusInfo 0x00000009
1455struct aac_bus_info {
1456 __le32 Command;
1457 __le32 ObjType;
1458 __le32 MethodId;
1459 __le32 ObjectId;
1460 __le32 CtlCmd;
1461};
1462
1463struct aac_bus_info_response {
1464 __le32 Status;
1465 __le32 ObjType;
1466 __le32 MethodId;
1467 __le32 ObjectId;
1468 __le32 CtlCmd;
1469 __le32 ProbeComplete;
1470 __le32 BusCount;
1471 __le32 TargetsPerBus;
1472 u8 InitiatorBusId[10];
1473 u8 BusValid[10];
1474};
1475
1476
1477
1478
1479#define AAC_BAT_REQ_PRESENT (1)
1480#define AAC_BAT_REQ_NOTPRESENT (2)
1481#define AAC_BAT_OPT_PRESENT (3)
1482#define AAC_BAT_OPT_NOTPRESENT (4)
1483#define AAC_BAT_NOT_SUPPORTED (5)
1484
1485
1486
1487#define AAC_CPU_SIMULATOR (1)
1488#define AAC_CPU_I960 (2)
1489#define AAC_CPU_STRONGARM (3)
1490
1491
1492
1493
1494#define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1495#define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1496#define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1497#define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1498#define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1499#define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1500#define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1501#define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1502#define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1503#define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1504#define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1505#define AAC_OPT_ALARM cpu_to_le32(1<<11)
1506#define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1507#define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1508#define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1509#define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1510#define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1511#define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1512#define AAC_OPT_EXTENDED cpu_to_le32(1<<23)
1513#define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25)
1514#define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1515#define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1516#define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1517#define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1518
1519#define AAC_COMM_PRODUCER 0
1520#define AAC_COMM_MESSAGE 1
1521#define AAC_COMM_MESSAGE_TYPE1 3
1522#define AAC_COMM_MESSAGE_TYPE2 4
1523#define AAC_COMM_MESSAGE_TYPE3 5
1524
1525#define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1)
1526
1527
1528struct aac_msix_ctx {
1529 int vector_no;
1530 struct aac_dev *dev;
1531};
1532
1533struct aac_dev
1534{
1535 struct list_head entry;
1536 const char *name;
1537 int id;
1538
1539
1540
1541
1542 unsigned int max_fib_size;
1543 unsigned int sg_tablesize;
1544 unsigned int max_num_aif;
1545
1546 unsigned int max_cmd_size;
1547
1548
1549
1550
1551 dma_addr_t hw_fib_pa;
1552 struct hw_fib *hw_fib_va;
1553 struct hw_fib *aif_base_va;
1554
1555
1556
1557 struct fib *fibs;
1558
1559 struct fib *free_fib;
1560 spinlock_t fib_lock;
1561
1562 struct mutex ioctl_mutex;
1563 struct aac_queue_block *queues;
1564
1565
1566
1567
1568
1569
1570
1571 struct list_head fib_list;
1572
1573 struct adapter_ops a_ops;
1574 unsigned long fsrev;
1575
1576 resource_size_t base_start;
1577 resource_size_t dbg_base;
1578
1579
1580 resource_size_t base_size, dbg_size;
1581
1582
1583
1584
1585
1586 union aac_init *init;
1587 dma_addr_t init_pa;
1588
1589 __le32 *host_rrq;
1590 dma_addr_t host_rrq_pa;
1591
1592 u32 host_rrq_idx[AAC_MAX_MSIX];
1593 atomic_t rrq_outstanding[AAC_MAX_MSIX];
1594 u32 fibs_pushed_no;
1595 struct pci_dev *pdev;
1596
1597 void *printfbuf;
1598 void *comm_addr;
1599 dma_addr_t comm_phys;
1600 size_t comm_size;
1601
1602 struct Scsi_Host *scsi_host_ptr;
1603 int maximum_num_containers;
1604 int maximum_num_physicals;
1605 int maximum_num_channels;
1606 struct fsa_dev_info *fsa_dev;
1607 struct task_struct *thread;
1608 int cardtype;
1609
1610
1611
1612
1613 spinlock_t iq_lock;
1614
1615
1616
1617
1618#ifndef AAC_MIN_FOOTPRINT_SIZE
1619# define AAC_MIN_FOOTPRINT_SIZE 8192
1620# define AAC_MIN_SRC_BAR0_SIZE 0x400000
1621# define AAC_MIN_SRC_BAR1_SIZE 0x800
1622# define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1623# define AAC_MIN_SRCV_BAR1_SIZE 0x400
1624#endif
1625 union
1626 {
1627 struct sa_registers __iomem *sa;
1628 struct rx_registers __iomem *rx;
1629 struct rkt_registers __iomem *rkt;
1630 struct {
1631 struct src_registers __iomem *bar0;
1632 char __iomem *bar1;
1633 } src;
1634 } regs;
1635 volatile void __iomem *base, *dbg_base_mapped;
1636 volatile struct rx_inbound __iomem *IndexRegs;
1637 u32 OIMR;
1638
1639
1640
1641 u32 aif_thread;
1642 struct aac_adapter_info adapter_info;
1643 struct aac_supplement_adapter_info supplement_adapter_info;
1644
1645
1646
1647 u8 nondasd_support;
1648 u8 jbod;
1649 u8 cache_protected;
1650 u8 dac_support;
1651 u8 needs_dac;
1652 u8 raid_scsi_mode;
1653 u8 comm_interface;
1654 u8 raw_io_interface;
1655 u8 raw_io_64;
1656 u8 printf_enabled;
1657 u8 in_reset;
1658 u8 msi;
1659 u8 sa_firmware;
1660 int management_fib_count;
1661 spinlock_t manage_lock;
1662 spinlock_t sync_lock;
1663 int sync_mode;
1664 struct fib *sync_fib;
1665 struct list_head sync_fib_list;
1666 u32 doorbell_mask;
1667 u32 max_msix;
1668 u32 vector_cap;
1669 int msi_enabled;
1670 atomic_t msix_counter;
1671 struct msix_entry msixentry[AAC_MAX_MSIX];
1672 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX];
1673 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
1674 u8 adapter_shutdown;
1675 u32 handle_pci_error;
1676};
1677
1678#define aac_adapter_interrupt(dev) \
1679 (dev)->a_ops.adapter_interrupt(dev)
1680
1681#define aac_adapter_notify(dev, event) \
1682 (dev)->a_ops.adapter_notify(dev, event)
1683
1684#define aac_adapter_disable_int(dev) \
1685 (dev)->a_ops.adapter_disable_int(dev)
1686
1687#define aac_adapter_enable_int(dev) \
1688 (dev)->a_ops.adapter_enable_int(dev)
1689
1690#define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1691 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1692
1693#define aac_adapter_check_health(dev) \
1694 (dev)->a_ops.adapter_check_health(dev)
1695
1696#define aac_adapter_restart(dev, bled, reset_type) \
1697 ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
1698
1699#define aac_adapter_start(dev) \
1700 ((dev)->a_ops.adapter_start(dev))
1701
1702#define aac_adapter_ioremap(dev, size) \
1703 (dev)->a_ops.adapter_ioremap(dev, size)
1704
1705#define aac_adapter_deliver(fib) \
1706 ((fib)->dev)->a_ops.adapter_deliver(fib)
1707
1708#define aac_adapter_bounds(dev,cmd,lba) \
1709 dev->a_ops.adapter_bounds(dev,cmd,lba)
1710
1711#define aac_adapter_read(fib,cmd,lba,count) \
1712 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1713
1714#define aac_adapter_write(fib,cmd,lba,count,fua) \
1715 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1716
1717#define aac_adapter_scsi(fib,cmd) \
1718 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1719
1720#define aac_adapter_comm(dev,comm) \
1721 (dev)->a_ops.adapter_comm(dev, comm)
1722
1723#define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1724#define FIB_CONTEXT_FLAG (0x00000002)
1725#define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1726#define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1727#define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010)
1728#define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020)
1729
1730
1731
1732
1733
1734#define Null 0
1735#define GetAttributes 1
1736#define SetAttributes 2
1737#define Lookup 3
1738#define ReadLink 4
1739#define Read 5
1740#define Write 6
1741#define Create 7
1742#define MakeDirectory 8
1743#define SymbolicLink 9
1744#define MakeNode 10
1745#define Removex 11
1746#define RemoveDirectoryx 12
1747#define Rename 13
1748#define Link 14
1749#define ReadDirectory 15
1750#define ReadDirectoryPlus 16
1751#define FileSystemStatus 17
1752#define FileSystemInfo 18
1753#define PathConfigure 19
1754#define Commit 20
1755#define Mount 21
1756#define UnMount 22
1757#define Newfs 23
1758#define FsCheck 24
1759#define FsSync 25
1760#define SimReadWrite 26
1761#define SetFileSystemStatus 27
1762#define BlockRead 28
1763#define BlockWrite 29
1764#define NvramIoctl 30
1765#define FsSyncWait 31
1766#define ClearArchiveBit 32
1767#define SetAcl 33
1768#define GetAcl 34
1769#define AssignAcl 35
1770#define FaultInsertion 36
1771#define CrazyCache 37
1772
1773#define MAX_FSACOMMAND_NUM 38
1774
1775
1776
1777
1778
1779
1780
1781#define ST_OK 0
1782#define ST_PERM 1
1783#define ST_NOENT 2
1784#define ST_IO 5
1785#define ST_NXIO 6
1786#define ST_E2BIG 7
1787#define ST_MEDERR 8
1788#define ST_ACCES 13
1789#define ST_EXIST 17
1790#define ST_XDEV 18
1791#define ST_NODEV 19
1792#define ST_NOTDIR 20
1793#define ST_ISDIR 21
1794#define ST_INVAL 22
1795#define ST_FBIG 27
1796#define ST_NOSPC 28
1797#define ST_ROFS 30
1798#define ST_MLINK 31
1799#define ST_WOULDBLOCK 35
1800#define ST_NAMETOOLONG 63
1801#define ST_NOTEMPTY 66
1802#define ST_DQUOT 69
1803#define ST_STALE 70
1804#define ST_REMOTE 71
1805#define ST_NOT_READY 72
1806#define ST_BADHANDLE 10001
1807#define ST_NOT_SYNC 10002
1808#define ST_BAD_COOKIE 10003
1809#define ST_NOTSUPP 10004
1810#define ST_TOOSMALL 10005
1811#define ST_SERVERFAULT 10006
1812#define ST_BADTYPE 10007
1813#define ST_JUKEBOX 10008
1814#define ST_NOTMOUNTED 10009
1815#define ST_MAINTMODE 10010
1816#define ST_STALEACL 10011
1817
1818
1819
1820
1821
1822#define CACHE_CSTABLE 1
1823#define CACHE_UNSTABLE 2
1824
1825
1826
1827
1828
1829
1830#define CMFILE_SYNCH_NVRAM 1
1831#define CMDATA_SYNCH_NVRAM 2
1832#define CMFILE_SYNCH 3
1833#define CMDATA_SYNCH 4
1834#define CMUNSTABLE 5
1835
1836#define RIO_TYPE_WRITE 0x0000
1837#define RIO_TYPE_READ 0x0001
1838#define RIO_SUREWRITE 0x0008
1839
1840#define RIO2_IO_TYPE 0x0003
1841#define RIO2_IO_TYPE_WRITE 0x0000
1842#define RIO2_IO_TYPE_READ 0x0001
1843#define RIO2_IO_TYPE_VERIFY 0x0002
1844#define RIO2_IO_ERROR 0x0004
1845#define RIO2_IO_SUREWRITE 0x0008
1846#define RIO2_SGL_CONFORMANT 0x0010
1847#define RIO2_SG_FORMAT 0xF000
1848#define RIO2_SG_FORMAT_ARC 0x0000
1849#define RIO2_SG_FORMAT_SRL 0x1000
1850#define RIO2_SG_FORMAT_IEEE1212 0x2000
1851
1852struct aac_read
1853{
1854 __le32 command;
1855 __le32 cid;
1856 __le32 block;
1857 __le32 count;
1858 struct sgmap sg;
1859};
1860
1861struct aac_read64
1862{
1863 __le32 command;
1864 __le16 cid;
1865 __le16 sector_count;
1866 __le32 block;
1867 __le16 pad;
1868 __le16 flags;
1869 struct sgmap64 sg;
1870};
1871
1872struct aac_read_reply
1873{
1874 __le32 status;
1875 __le32 count;
1876};
1877
1878struct aac_write
1879{
1880 __le32 command;
1881 __le32 cid;
1882 __le32 block;
1883 __le32 count;
1884 __le32 stable;
1885 struct sgmap sg;
1886};
1887
1888struct aac_write64
1889{
1890 __le32 command;
1891 __le16 cid;
1892 __le16 sector_count;
1893 __le32 block;
1894 __le16 pad;
1895 __le16 flags;
1896 struct sgmap64 sg;
1897};
1898struct aac_write_reply
1899{
1900 __le32 status;
1901 __le32 count;
1902 __le32 committed;
1903};
1904
1905struct aac_raw_io
1906{
1907 __le32 block[2];
1908 __le32 count;
1909 __le16 cid;
1910 __le16 flags;
1911 __le16 bpTotal;
1912 __le16 bpComplete;
1913 struct sgmapraw sg;
1914};
1915
1916struct aac_raw_io2 {
1917 __le32 blockLow;
1918 __le32 blockHigh;
1919 __le32 byteCount;
1920 __le16 cid;
1921 __le16 flags;
1922 __le32 sgeFirstSize;
1923 __le32 sgeNominalSize;
1924 u8 sgeCnt;
1925 u8 bpTotal;
1926 u8 bpComplete;
1927 u8 sgeFirstIndex;
1928 u8 unused[4];
1929 struct sge_ieee1212 sge[1];
1930};
1931
1932#define CT_FLUSH_CACHE 129
1933struct aac_synchronize {
1934 __le32 command;
1935 __le32 type;
1936 __le32 cid;
1937 __le32 parm1;
1938 __le32 parm2;
1939 __le32 parm3;
1940 __le32 parm4;
1941 __le32 count;
1942};
1943
1944struct aac_synchronize_reply {
1945 __le32 dummy0;
1946 __le32 dummy1;
1947 __le32 status;
1948 __le32 parm1;
1949 __le32 parm2;
1950 __le32 parm3;
1951 __le32 parm4;
1952 __le32 parm5;
1953 u8 data[16];
1954};
1955
1956#define CT_POWER_MANAGEMENT 245
1957#define CT_PM_START_UNIT 2
1958#define CT_PM_STOP_UNIT 3
1959#define CT_PM_UNIT_IMMEDIATE 1
1960struct aac_power_management {
1961 __le32 command;
1962 __le32 type;
1963 __le32 sub;
1964 __le32 cid;
1965 __le32 parm;
1966};
1967
1968#define CT_PAUSE_IO 65
1969#define CT_RELEASE_IO 66
1970struct aac_pause {
1971 __le32 command;
1972 __le32 type;
1973 __le32 timeout;
1974 __le32 min;
1975 __le32 noRescan;
1976 __le32 parm3;
1977 __le32 parm4;
1978 __le32 count;
1979};
1980
1981struct aac_srb
1982{
1983 __le32 function;
1984 __le32 channel;
1985 __le32 id;
1986 __le32 lun;
1987 __le32 timeout;
1988 __le32 flags;
1989 __le32 count;
1990 __le32 retry_limit;
1991 __le32 cdb_size;
1992 u8 cdb[16];
1993 struct sgmap sg;
1994};
1995
1996
1997
1998
1999
2000struct user_aac_srb
2001{
2002 u32 function;
2003 u32 channel;
2004 u32 id;
2005 u32 lun;
2006 u32 timeout;
2007 u32 flags;
2008 u32 count;
2009 u32 retry_limit;
2010 u32 cdb_size;
2011 u8 cdb[16];
2012 struct user_sgmap sg;
2013};
2014
2015#define AAC_SENSE_BUFFERSIZE 30
2016
2017struct aac_srb_reply
2018{
2019 __le32 status;
2020 __le32 srb_status;
2021 __le32 scsi_status;
2022 __le32 data_xfer_length;
2023 __le32 sense_data_size;
2024 u8 sense_data[AAC_SENSE_BUFFERSIZE];
2025};
2026
2027
2028
2029#define SRB_NoDataXfer 0x0000
2030#define SRB_DisableDisconnect 0x0004
2031#define SRB_DisableSynchTransfer 0x0008
2032#define SRB_BypassFrozenQueue 0x0010
2033#define SRB_DisableAutosense 0x0020
2034#define SRB_DataIn 0x0040
2035#define SRB_DataOut 0x0080
2036
2037
2038
2039
2040#define SRBF_ExecuteScsi 0x0000
2041#define SRBF_ClaimDevice 0x0001
2042#define SRBF_IO_Control 0x0002
2043#define SRBF_ReceiveEvent 0x0003
2044#define SRBF_ReleaseQueue 0x0004
2045#define SRBF_AttachDevice 0x0005
2046#define SRBF_ReleaseDevice 0x0006
2047#define SRBF_Shutdown 0x0007
2048#define SRBF_Flush 0x0008
2049#define SRBF_AbortCommand 0x0010
2050#define SRBF_ReleaseRecovery 0x0011
2051#define SRBF_ResetBus 0x0012
2052#define SRBF_ResetDevice 0x0013
2053#define SRBF_TerminateIO 0x0014
2054#define SRBF_FlushQueue 0x0015
2055#define SRBF_RemoveDevice 0x0016
2056#define SRBF_DomainValidation 0x0017
2057
2058
2059
2060
2061#define SRB_STATUS_PENDING 0x00
2062#define SRB_STATUS_SUCCESS 0x01
2063#define SRB_STATUS_ABORTED 0x02
2064#define SRB_STATUS_ABORT_FAILED 0x03
2065#define SRB_STATUS_ERROR 0x04
2066#define SRB_STATUS_BUSY 0x05
2067#define SRB_STATUS_INVALID_REQUEST 0x06
2068#define SRB_STATUS_INVALID_PATH_ID 0x07
2069#define SRB_STATUS_NO_DEVICE 0x08
2070#define SRB_STATUS_TIMEOUT 0x09
2071#define SRB_STATUS_SELECTION_TIMEOUT 0x0A
2072#define SRB_STATUS_COMMAND_TIMEOUT 0x0B
2073#define SRB_STATUS_MESSAGE_REJECTED 0x0D
2074#define SRB_STATUS_BUS_RESET 0x0E
2075#define SRB_STATUS_PARITY_ERROR 0x0F
2076#define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
2077#define SRB_STATUS_NO_HBA 0x11
2078#define SRB_STATUS_DATA_OVERRUN 0x12
2079#define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
2080#define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
2081#define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
2082#define SRB_STATUS_REQUEST_FLUSHED 0x16
2083#define SRB_STATUS_DELAYED_RETRY 0x17
2084#define SRB_STATUS_INVALID_LUN 0x20
2085#define SRB_STATUS_INVALID_TARGET_ID 0x21
2086#define SRB_STATUS_BAD_FUNCTION 0x22
2087#define SRB_STATUS_ERROR_RECOVERY 0x23
2088#define SRB_STATUS_NOT_STARTED 0x24
2089#define SRB_STATUS_NOT_IN_USE 0x30
2090#define SRB_STATUS_FORCE_ABORT 0x31
2091#define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
2092
2093
2094
2095
2096
2097#define VM_Null 0
2098#define VM_NameServe 1
2099#define VM_ContainerConfig 2
2100#define VM_Ioctl 3
2101#define VM_FilesystemIoctl 4
2102#define VM_CloseAll 5
2103#define VM_CtBlockRead 6
2104#define VM_CtBlockWrite 7
2105#define VM_SliceBlockRead 8
2106#define VM_SliceBlockWrite 9
2107#define VM_DriveBlockRead 10
2108#define VM_DriveBlockWrite 11
2109#define VM_EnclosureMgt 12
2110#define VM_Unused 13
2111#define VM_CtBlockVerify 14
2112#define VM_CtPerf 15
2113#define VM_CtBlockRead64 16
2114#define VM_CtBlockWrite64 17
2115#define VM_CtBlockVerify64 18
2116#define VM_CtHostRead64 19
2117#define VM_CtHostWrite64 20
2118#define VM_DrvErrTblLog 21
2119#define VM_NameServe64 22
2120#define VM_NameServeAllBlk 30
2121
2122#define MAX_VMCOMMAND_NUM 23
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132struct aac_fsinfo {
2133 __le32 fsTotalSize;
2134 __le32 fsBlockSize;
2135 __le32 fsFragSize;
2136 __le32 fsMaxExtendSize;
2137 __le32 fsSpaceUnits;
2138 __le32 fsMaxNumFiles;
2139 __le32 fsNumFreeFiles;
2140 __le32 fsInodeDensity;
2141};
2142
2143struct aac_blockdevinfo {
2144 __le32 block_size;
2145 __le32 logical_phys_map;
2146 u8 identifier[16];
2147};
2148
2149union aac_contentinfo {
2150 struct aac_fsinfo filesys;
2151 struct aac_blockdevinfo bdevinfo;
2152};
2153
2154
2155
2156
2157
2158#define CT_GET_CONFIG_STATUS 147
2159struct aac_get_config_status {
2160 __le32 command;
2161 __le32 type;
2162 __le32 parm1;
2163 __le32 parm2;
2164 __le32 parm3;
2165 __le32 parm4;
2166 __le32 parm5;
2167 __le32 count;
2168};
2169
2170#define CFACT_CONTINUE 0
2171#define CFACT_PAUSE 1
2172#define CFACT_ABORT 2
2173struct aac_get_config_status_resp {
2174 __le32 response;
2175 __le32 dummy0;
2176 __le32 status;
2177 __le32 parm1;
2178 __le32 parm2;
2179 __le32 parm3;
2180 __le32 parm4;
2181 __le32 parm5;
2182 struct {
2183 __le32 action;
2184 __le16 flags;
2185 __le16 count;
2186 } data;
2187};
2188
2189
2190
2191
2192
2193#define CT_COMMIT_CONFIG 152
2194
2195struct aac_commit_config {
2196 __le32 command;
2197 __le32 type;
2198};
2199
2200
2201
2202
2203
2204#define CT_GET_CONTAINER_COUNT 4
2205struct aac_get_container_count {
2206 __le32 command;
2207 __le32 type;
2208};
2209
2210struct aac_get_container_count_resp {
2211 __le32 response;
2212 __le32 dummy0;
2213 __le32 MaxContainers;
2214 __le32 ContainerSwitchEntries;
2215 __le32 MaxPartitions;
2216 __le32 MaxSimpleVolumes;
2217};
2218
2219
2220
2221
2222
2223
2224
2225struct aac_mntent {
2226 __le32 oid;
2227 u8 name[16];
2228 struct creation_info create_info;
2229 __le32 capacity;
2230 __le32 vol;
2231 __le32 obj;
2232 __le32 state;
2233
2234 union aac_contentinfo fileinfo;
2235
2236 __le32 altoid;
2237
2238 __le32 capacityhigh;
2239};
2240
2241#define FSCS_NOTCLEAN 0x0001
2242#define FSCS_READONLY 0x0002
2243#define FSCS_HIDDEN 0x0004
2244#define FSCS_NOT_READY 0x0008
2245
2246struct aac_query_mount {
2247 __le32 command;
2248 __le32 type;
2249 __le32 count;
2250};
2251
2252struct aac_mount {
2253 __le32 status;
2254 __le32 type;
2255 __le32 count;
2256 struct aac_mntent mnt[1];
2257};
2258
2259#define CT_READ_NAME 130
2260struct aac_get_name {
2261 __le32 command;
2262 __le32 type;
2263 __le32 cid;
2264 __le32 parm1;
2265 __le32 parm2;
2266 __le32 parm3;
2267 __le32 parm4;
2268 __le32 count;
2269};
2270
2271struct aac_get_name_resp {
2272 __le32 dummy0;
2273 __le32 dummy1;
2274 __le32 status;
2275 __le32 parm1;
2276 __le32 parm2;
2277 __le32 parm3;
2278 __le32 parm4;
2279 __le32 parm5;
2280 u8 data[16];
2281};
2282
2283#define CT_CID_TO_32BITS_UID 165
2284struct aac_get_serial {
2285 __le32 command;
2286 __le32 type;
2287 __le32 cid;
2288};
2289
2290struct aac_get_serial_resp {
2291 __le32 dummy0;
2292 __le32 dummy1;
2293 __le32 status;
2294 __le32 uid;
2295};
2296
2297
2298
2299
2300
2301struct aac_close {
2302 __le32 command;
2303 __le32 cid;
2304};
2305
2306struct aac_query_disk
2307{
2308 s32 cnum;
2309 s32 bus;
2310 s32 id;
2311 s32 lun;
2312 u32 valid;
2313 u32 locked;
2314 u32 deleted;
2315 s32 instance;
2316 s8 name[10];
2317 u32 unmapped;
2318};
2319
2320struct aac_delete_disk {
2321 u32 disknum;
2322 u32 cnum;
2323};
2324
2325struct fib_ioctl
2326{
2327 u32 fibctx;
2328 s32 wait;
2329 char __user *fib;
2330};
2331
2332struct revision
2333{
2334 u32 compat;
2335 __le32 version;
2336 __le32 build;
2337};
2338
2339
2340
2341
2342
2343
2344#define CTL_CODE(function, method) ( \
2345 (4<< 16) | ((function) << 2) | (method) \
2346)
2347
2348
2349
2350
2351
2352
2353#define METHOD_BUFFERED 0
2354#define METHOD_NEITHER 3
2355
2356
2357
2358
2359
2360#define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
2361#define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
2362#define FSACTL_DELETE_DISK 0x163
2363#define FSACTL_QUERY_DISK 0x173
2364#define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
2365#define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
2366#define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
2367#define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
2368#define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
2369#define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
2370#define FSACTL_GET_CONTAINERS 2131
2371#define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
2372#define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED)
2373#define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED)
2374
2375#define HW_IOP_RESET 0x01
2376#define HW_SOFT_RESET 0x02
2377#define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET)
2378
2379#define IBW_SWR_OFFSET 0x4000
2380#define SOFT_RESET_TIME 60
2381
2382
2383struct aac_common
2384{
2385
2386
2387
2388
2389 u32 irq_mod;
2390 u32 peak_fibs;
2391 u32 zero_fibs;
2392 u32 fib_timeouts;
2393
2394
2395
2396#ifdef DBG
2397 u32 FibsSent;
2398 u32 FibRecved;
2399 u32 NativeSent;
2400 u32 NativeRecved;
2401 u32 NoResponseSent;
2402 u32 NoResponseRecved;
2403 u32 AsyncSent;
2404 u32 AsyncRecved;
2405 u32 NormalSent;
2406 u32 NormalRecved;
2407#endif
2408};
2409
2410extern struct aac_common aac_config;
2411
2412
2413
2414
2415struct aac_hba_info {
2416
2417 u8 driver_name[50];
2418 u8 adapter_number;
2419 u8 system_io_bus_number;
2420 u8 device_number;
2421 u32 function_number;
2422 u32 vendor_id;
2423 u32 device_id;
2424 u32 sub_vendor_id;
2425 u32 sub_system_id;
2426 u32 mapped_base_address_size;
2427 u32 base_physical_address_high_part;
2428 u32 base_physical_address_low_part;
2429
2430 u32 max_command_size;
2431 u32 max_fib_size;
2432 u32 max_scatter_gather_from_os;
2433 u32 max_scatter_gather_to_fw;
2434 u32 max_outstanding_fibs;
2435
2436 u32 queue_start_threshold;
2437 u32 queue_dump_threshold;
2438 u32 max_io_size_queued;
2439 u32 outstanding_io;
2440
2441 u32 firmware_build_number;
2442 u32 bios_build_number;
2443 u32 driver_build_number;
2444 u32 serial_number_high_part;
2445 u32 serial_number_low_part;
2446 u32 supported_options;
2447 u32 feature_bits;
2448 u32 currentnumber_ports;
2449
2450 u8 new_comm_interface:1;
2451 u8 new_commands_supported:1;
2452 u8 disable_passthrough:1;
2453 u8 expose_non_dasd:1;
2454 u8 queue_allowed:1;
2455 u8 bled_check_enabled:1;
2456 u8 reserved1:1;
2457 u8 reserted2:1;
2458
2459 u32 reserved3[10];
2460
2461};
2462
2463
2464
2465
2466
2467
2468#ifdef DBG
2469#define FIB_COUNTER_INCREMENT(counter) (counter)++
2470#else
2471#define FIB_COUNTER_INCREMENT(counter)
2472#endif
2473
2474
2475
2476
2477
2478
2479#define BREAKPOINT_REQUEST 0x00000004
2480#define INIT_STRUCT_BASE_ADDRESS 0x00000005
2481#define READ_PERMANENT_PARAMETERS 0x0000000a
2482#define WRITE_PERMANENT_PARAMETERS 0x0000000b
2483#define HOST_CRASHING 0x0000000d
2484#define SEND_SYNCHRONOUS_FIB 0x0000000c
2485#define COMMAND_POST_RESULTS 0x00000014
2486#define GET_ADAPTER_PROPERTIES 0x00000019
2487#define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
2488#define RCV_TEMP_READINGS 0x00000025
2489#define GET_COMM_PREFERRED_SETTINGS 0x00000026
2490#define IOP_RESET_FW_FIB_DUMP 0x00000034
2491#define IOP_RESET 0x00001000
2492#define IOP_RESET_ALWAYS 0x00001001
2493#define RE_INIT_ADAPTER 0x000000ee
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516#define SELF_TEST_FAILED 0x00000004
2517#define MONITOR_PANIC 0x00000020
2518#define KERNEL_UP_AND_RUNNING 0x00000080
2519#define KERNEL_PANIC 0x00000100
2520#define FLASH_UPD_PENDING 0x00002000
2521#define FLASH_UPD_SUCCESS 0x00004000
2522#define FLASH_UPD_FAILED 0x00008000
2523#define FWUPD_TIMEOUT (5 * 60)
2524
2525
2526
2527
2528
2529#define DoorBellSyncCmdAvailable (1<<0)
2530#define DoorBellPrintfDone (1<<5)
2531#define DoorBellAdapterNormCmdReady (1<<1)
2532#define DoorBellAdapterNormRespReady (1<<2)
2533#define DoorBellAdapterNormCmdNotFull (1<<3)
2534#define DoorBellAdapterNormRespNotFull (1<<4)
2535#define DoorBellPrintfReady (1<<5)
2536#define DoorBellAifPending (1<<6)
2537
2538
2539#define PmDoorBellResponseSent (1<<1)
2540
2541
2542
2543
2544
2545
2546#define AifCmdEventNotify 1
2547#define AifEnConfigChange 3
2548#define AifEnContainerChange 4
2549#define AifEnDeviceFailure 5
2550#define AifEnEnclosureManagement 13
2551#define EM_DRIVE_INSERTION 31
2552#define EM_DRIVE_REMOVAL 32
2553#define EM_SES_DRIVE_INSERTION 33
2554#define EM_SES_DRIVE_REMOVAL 26
2555#define AifEnBatteryEvent 14
2556#define AifEnAddContainer 15
2557#define AifEnDeleteContainer 16
2558#define AifEnExpEvent 23
2559#define AifExeFirmwarePanic 3
2560#define AifHighPriority 3
2561#define AifEnAddJBOD 30
2562#define AifEnDeleteJBOD 31
2563
2564#define AifBuManagerEvent 42
2565#define AifBuCacheDataLoss 10
2566#define AifBuCacheDataRecover 11
2567
2568#define AifCmdJobProgress 2
2569#define AifJobCtrZero 101
2570#define AifJobStsSuccess 1
2571#define AifJobStsRunning 102
2572#define AifCmdAPIReport 3
2573#define AifCmdDriverNotify 4
2574#define AifDenMorphComplete 200
2575#define AifDenVolumeExtendComplete 201
2576#define AifReqJobList 100
2577#define AifReqJobsForCtr 101
2578#define AifReqJobsForScsi 102
2579#define AifReqJobReport 103
2580#define AifReqTerminateJob 104
2581#define AifReqSuspendJob 105
2582#define AifReqResumeJob 106
2583#define AifReqSendAPIReport 107
2584#define AifReqAPIJobStart 108
2585#define AifReqAPIJobUpdate 109
2586#define AifReqAPIJobFinish 110
2587
2588
2589#define AifReqEvent 200
2590#define AifRawDeviceRemove 203
2591#define AifNativeDeviceAdd 204
2592#define AifNativeDeviceRemove 205
2593
2594
2595
2596
2597
2598
2599
2600
2601struct aac_aifcmd {
2602 __le32 command;
2603 __le32 seqnum;
2604 u8 data[1];
2605};
2606
2607
2608
2609
2610
2611
2612static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2613{
2614 sector_div(capacity, divisor);
2615 return capacity;
2616}
2617
2618
2619#define AAC_OWNER_MIDLEVEL 0x101
2620#define AAC_OWNER_LOWLEVEL 0x102
2621#define AAC_OWNER_ERROR_HANDLER 0x103
2622#define AAC_OWNER_FIRMWARE 0x106
2623
2624int aac_acquire_irq(struct aac_dev *dev);
2625void aac_free_irq(struct aac_dev *dev);
2626int aac_report_phys_luns(struct aac_dev *dev, struct fib *fibptr, int rescan);
2627int aac_issue_bmic_identify(struct aac_dev *dev, u32 bus, u32 target);
2628const char *aac_driverinfo(struct Scsi_Host *);
2629void aac_fib_vector_assign(struct aac_dev *dev);
2630struct fib *aac_fib_alloc(struct aac_dev *dev);
2631struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2632int aac_fib_setup(struct aac_dev *dev);
2633void aac_fib_map_free(struct aac_dev *dev);
2634void aac_fib_free(struct fib * context);
2635void aac_fib_init(struct fib * context);
2636void aac_printf(struct aac_dev *dev, u32 val);
2637int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2638int aac_hba_send(u8 command, struct fib *context,
2639 fib_callback callback, void *ctxt);
2640int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2641void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2642int aac_fib_complete(struct fib * context);
2643void aac_hba_callback(void *context, struct fib *fibptr);
2644#define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2645struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2646void aac_src_access_devreg(struct aac_dev *dev, int mode);
2647void aac_set_intx_mode(struct aac_dev *dev);
2648int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2649int aac_get_containers(struct aac_dev *dev);
2650int aac_scsi_cmd(struct scsi_cmnd *cmd);
2651int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg);
2652#ifndef shost_to_class
2653#define shost_to_class(shost) &shost->shost_dev
2654#endif
2655ssize_t aac_get_serial_number(struct device *dev, char *buf);
2656int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg);
2657int aac_rx_init(struct aac_dev *dev);
2658int aac_rkt_init(struct aac_dev *dev);
2659int aac_nark_init(struct aac_dev *dev);
2660int aac_sa_init(struct aac_dev *dev);
2661int aac_src_init(struct aac_dev *dev);
2662int aac_srcv_init(struct aac_dev *dev);
2663int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2664void aac_define_int_mode(struct aac_dev *dev);
2665unsigned int aac_response_normal(struct aac_queue * q);
2666unsigned int aac_command_normal(struct aac_queue * q);
2667unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2668 int isAif, int isFastResponse,
2669 struct hw_fib *aif_fib);
2670int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type);
2671int aac_check_health(struct aac_dev * dev);
2672int aac_command_thread(void *data);
2673int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2674int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2675struct aac_driver_ident* aac_get_driver_ident(int devtype);
2676int aac_get_adapter_info(struct aac_dev* dev);
2677int aac_send_shutdown(struct aac_dev *dev);
2678int aac_probe_container(struct aac_dev *dev, int cid);
2679int _aac_rx_init(struct aac_dev *dev);
2680int aac_rx_select_comm(struct aac_dev *dev, int comm);
2681int aac_rx_deliver_producer(struct fib * fib);
2682char * get_container_type(unsigned type);
2683extern int numacb;
2684extern char aac_driver_version[];
2685extern int startup_timeout;
2686extern int aif_timeout;
2687extern int expose_physicals;
2688extern int aac_reset_devices;
2689extern int aac_msi;
2690extern int aac_commit;
2691extern int update_interval;
2692extern int check_interval;
2693extern int aac_check_reset;
2694extern int aac_fib_dump;
2695#endif
2696