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8#ifndef __QL4_DEF_H
9#define __QL4_DEF_H
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/dmapool.h>
21#include <linux/mempool.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/mutex.h>
27#include <linux/aer.h>
28#include <linux/bsg-lib.h>
29
30#include <net/tcp.h>
31#include <scsi/scsi.h>
32#include <scsi/scsi_host.h>
33#include <scsi/scsi_device.h>
34#include <scsi/scsi_cmnd.h>
35#include <scsi/scsi_transport.h>
36#include <scsi/scsi_transport_iscsi.h>
37#include <scsi/scsi_bsg_iscsi.h>
38#include <scsi/scsi_netlink.h>
39#include <scsi/libiscsi.h>
40
41#include "ql4_dbg.h"
42#include "ql4_nx.h"
43#include "ql4_fw.h"
44#include "ql4_nvram.h"
45#include "ql4_83xx.h"
46
47#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
48#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
49#endif
50
51#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
52#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
53#endif
54
55#ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
56#define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
57#endif
58
59#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
60#define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
61#endif
62
63#ifndef PCI_DEVICE_ID_QLOGIC_ISP8324
64#define PCI_DEVICE_ID_QLOGIC_ISP8324 0x8032
65#endif
66
67#ifndef PCI_DEVICE_ID_QLOGIC_ISP8042
68#define PCI_DEVICE_ID_QLOGIC_ISP8042 0x8042
69#endif
70
71#define ISP4XXX_PCI_FN_1 0x1
72#define ISP4XXX_PCI_FN_2 0x3
73
74#define QLA_SUCCESS 0
75#define QLA_ERROR 1
76#define STATUS(status) status == QLA_ERROR ? "FAILED" : "SUCCEEDED"
77
78
79
80
81#define BIT_0 0x1
82#define BIT_1 0x2
83#define BIT_2 0x4
84#define BIT_3 0x8
85#define BIT_4 0x10
86#define BIT_5 0x20
87#define BIT_6 0x40
88#define BIT_7 0x80
89#define BIT_8 0x100
90#define BIT_9 0x200
91#define BIT_10 0x400
92#define BIT_11 0x800
93#define BIT_12 0x1000
94#define BIT_13 0x2000
95#define BIT_14 0x4000
96#define BIT_15 0x8000
97#define BIT_16 0x10000
98#define BIT_17 0x20000
99#define BIT_18 0x40000
100#define BIT_19 0x80000
101#define BIT_20 0x100000
102#define BIT_21 0x200000
103#define BIT_22 0x400000
104#define BIT_23 0x800000
105#define BIT_24 0x1000000
106#define BIT_25 0x2000000
107#define BIT_26 0x4000000
108#define BIT_27 0x8000000
109#define BIT_28 0x10000000
110#define BIT_29 0x20000000
111#define BIT_30 0x40000000
112#define BIT_31 0x80000000
113
114
115
116
117#define ql4_printk(level, ha, format, arg...) \
118 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
119
120
121
122
123
124#define MAX_HBAS 16
125#define MAX_BUSES 1
126#define MAX_TARGETS MAX_DEV_DB_ENTRIES
127#define MAX_LUNS 0xffff
128#define MAX_AEN_ENTRIES MAX_DEV_DB_ENTRIES
129#define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
130#define MAX_PDU_ENTRIES 32
131#define INVALID_ENTRY 0xFFFF
132#define MAX_CMDS_TO_RISC 1024
133#define MAX_SRBS MAX_CMDS_TO_RISC
134#define MBOX_AEN_REG_COUNT 8
135#define MAX_INIT_RETRIES 5
136
137
138
139
140#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
141#define RESPONSE_QUEUE_DEPTH 64
142#define QUEUE_SIZE 64
143#define DMA_BUFFER_SIZE 512
144#define IOCB_HIWAT_CUSHION 4
145
146
147
148
149#define MAC_ADDR_LEN 6
150#define IP_ADDR_LEN 4
151#define IPv6_ADDR_LEN 16
152#define DRIVER_NAME "qla4xxx"
153
154#define MAX_LINKED_CMDS_PER_LUN 3
155#define MAX_REQS_SERVICED_PER_INTR 1
156
157#define ISCSI_IPADDR_SIZE 4
158#define ISCSI_ALIAS_SIZE 32
159#define ISCSI_NAME_SIZE 0xE0
160
161#define QL4_SESS_RECOVERY_TMO 120
162
163
164#define LSDW(x) ((u32)((u64)(x)))
165#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
166
167#define DEV_DB_NON_PERSISTENT 0
168#define DEV_DB_PERSISTENT 1
169
170#define COPY_ISID(dst_isid, src_isid) { \
171 int i, j; \
172 for (i = 0, j = ISID_SIZE - 1; i < ISID_SIZE;) \
173 dst_isid[i++] = src_isid[j--]; \
174}
175
176#define SET_BITVAL(o, n, v) { \
177 if (o) \
178 n |= v; \
179 else \
180 n &= ~v; \
181}
182
183#define OP_STATE(o, f, p) { \
184 p = (o & f) ? "enable" : "disable"; \
185}
186
187
188
189
190#define MBOX_TOV 60
191#define SOFT_RESET_TOV 30
192#define RESET_INTR_TOV 3
193#define SEMAPHORE_TOV 10
194#define ADAPTER_INIT_TOV 30
195#define ADAPTER_RESET_TOV 180
196#define EXTEND_CMD_TOV 60
197#define WAIT_CMD_TOV 5
198#define EH_WAIT_CMD_TOV 120
199#define FIRMWARE_UP_TOV 60
200#define RESET_FIRMWARE_TOV 30
201#define LOGOUT_TOV 10
202#define IOCB_TOV_MARGIN 10
203#define RELOGIN_TOV 18
204#define ISNS_DEREG_TOV 5
205#define HBA_ONLINE_TOV 30
206#define DISABLE_ACB_TOV 30
207#define IP_CONFIG_TOV 30
208#define LOGIN_TOV 12
209#define BOOT_LOGIN_RESP_TOV 60
210
211#define MAX_RESET_HA_RETRIES 2
212#define FW_ALIVE_WAIT_TOV 3
213#define IDC_EXTEND_TOV 8
214#define IDC_COMP_TOV 5
215#define LINK_UP_COMP_TOV 30
216
217#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
218
219
220
221
222
223struct srb {
224 struct list_head list;
225 struct scsi_qla_host *ha;
226 struct ddb_entry *ddb;
227 uint16_t flags;
228
229#define SRB_DMA_VALID BIT_3
230#define SRB_GOT_SENSE BIT_4
231 uint8_t state;
232
233#define SRB_NO_QUEUE_STATE 0
234#define SRB_FREE_STATE 1
235#define SRB_ACTIVE_STATE 3
236#define SRB_ACTIVE_TIMEOUT_STATE 4
237#define SRB_SUSPENDED_STATE 7
238
239 struct scsi_cmnd *cmd;
240 dma_addr_t dma_handle;
241 struct kref srb_ref;
242 uint8_t err_id;
243#define SRB_ERR_PORT 1
244#define SRB_ERR_LOOP 2
245#define SRB_ERR_DEVICE 3
246#define SRB_ERR_OTHER 4
247
248 uint16_t reserved;
249 uint16_t iocb_tov;
250 uint16_t iocb_cnt;
251 uint16_t cc_stat;
252
253
254 uint8_t *req_sense_ptr;
255 uint16_t req_sense_len;
256 uint16_t reserved2;
257};
258
259
260struct mrb {
261 struct scsi_qla_host *ha;
262 struct mbox_cmd_iocb *mbox;
263 uint32_t mbox_cmd;
264 uint16_t iocb_cnt;
265 uint32_t pid;
266};
267
268
269
270
271struct aen {
272 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
273};
274
275struct ql4_aen_log {
276 int count;
277 struct aen entry[MAX_AEN_ENTRIES];
278};
279
280
281
282
283struct ddb_entry {
284 struct scsi_qla_host *ha;
285 struct iscsi_cls_session *sess;
286 struct iscsi_cls_conn *conn;
287
288 uint16_t fw_ddb_index;
289 uint32_t fw_ddb_device_state;
290 uint16_t ddb_type;
291#define FLASH_DDB 0x01
292
293 struct dev_db_entry fw_ddb_entry;
294 int (*unblock_sess)(struct iscsi_cls_session *cls_session);
295 int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
296 struct ddb_entry *ddb_entry, uint32_t state);
297
298
299 unsigned long flags;
300#define DDB_CONN_CLOSE_FAILURE 0
301
302 uint16_t default_relogin_timeout;
303
304 atomic_t retry_relogin_timer;
305
306 atomic_t relogin_timer;
307
308 atomic_t relogin_retry_count;
309
310 uint32_t default_time2wait;
311
312 uint16_t chap_tbl_idx;
313};
314
315struct qla_ddb_index {
316 struct list_head list;
317 uint16_t fw_ddb_idx;
318 uint16_t flash_ddb_idx;
319 struct dev_db_entry fw_ddb;
320 uint8_t flash_isid[6];
321};
322
323#define DDB_IPADDR_LEN 64
324
325struct ql4_tuple_ddb {
326 int port;
327 int tpgt;
328 char ip_addr[DDB_IPADDR_LEN];
329 char iscsi_name[ISCSI_NAME_SIZE];
330 uint16_t options;
331#define DDB_OPT_IPV6 0x0e0e
332#define DDB_OPT_IPV4 0x0f0f
333 uint8_t isid[6];
334};
335
336
337
338
339#define DDB_STATE_DEAD 0
340
341#define DDB_STATE_ONLINE 1
342
343#define DDB_STATE_MISSING 2
344
345
346
347
348
349#define DF_RELOGIN 0
350#define DF_BOOT_TGT 1
351#define DF_ISNS_DISCOVERED 2
352#define DF_FO_MASKED 3
353#define DF_DISABLE_RELOGIN 4
354
355enum qla4_work_type {
356 QLA4_EVENT_AEN,
357 QLA4_EVENT_PING_STATUS,
358};
359
360struct qla4_work_evt {
361 struct list_head list;
362 enum qla4_work_type type;
363 union {
364 struct {
365 enum iscsi_host_event_code code;
366 uint32_t data_size;
367 uint8_t data[0];
368 } aen;
369 struct {
370 uint32_t status;
371 uint32_t pid;
372 uint32_t data_size;
373 uint8_t data[0];
374 } ping;
375 } u;
376};
377
378struct ql82xx_hw_data {
379
380 uint32_t flash_conf_off;
381 uint32_t flash_data_off;
382
383 uint32_t fdt_wrt_disable;
384 uint32_t fdt_erase_cmd;
385 uint32_t fdt_block_size;
386 uint32_t fdt_unprotect_sec_cmd;
387 uint32_t fdt_protect_sec_cmd;
388
389 uint32_t flt_region_flt;
390 uint32_t flt_region_fdt;
391 uint32_t flt_region_boot;
392 uint32_t flt_region_bootload;
393 uint32_t flt_region_fw;
394
395 uint32_t flt_iscsi_param;
396 uint32_t flt_region_chap;
397 uint32_t flt_chap_size;
398 uint32_t flt_region_ddb;
399 uint32_t flt_ddb_size;
400};
401
402struct qla4_8xxx_legacy_intr_set {
403 uint32_t int_vec_bit;
404 uint32_t tgt_status_reg;
405 uint32_t tgt_mask_reg;
406 uint32_t pci_int_reg;
407};
408
409
410
411#define QLA_MSIX_DEFAULT 0x00
412#define QLA_MSIX_RSP_Q 0x01
413
414#define QLA_MSIX_ENTRIES 2
415#define QLA_MIDX_DEFAULT 0
416#define QLA_MIDX_RSP_Q 1
417
418struct ql4_msix_entry {
419 int have_irq;
420 uint16_t msix_vector;
421 uint16_t msix_entry;
422};
423
424
425
426
427struct isp_operations {
428 int (*iospace_config) (struct scsi_qla_host *ha);
429 void (*pci_config) (struct scsi_qla_host *);
430 void (*disable_intrs) (struct scsi_qla_host *);
431 void (*enable_intrs) (struct scsi_qla_host *);
432 int (*start_firmware) (struct scsi_qla_host *);
433 int (*restart_firmware) (struct scsi_qla_host *);
434 irqreturn_t (*intr_handler) (int , void *);
435 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
436 int (*need_reset) (struct scsi_qla_host *);
437 int (*reset_chip) (struct scsi_qla_host *);
438 int (*reset_firmware) (struct scsi_qla_host *);
439 void (*queue_iocb) (struct scsi_qla_host *);
440 void (*complete_iocb) (struct scsi_qla_host *);
441 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
442 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
443 int (*get_sys_info) (struct scsi_qla_host *);
444 uint32_t (*rd_reg_direct) (struct scsi_qla_host *, ulong);
445 void (*wr_reg_direct) (struct scsi_qla_host *, ulong, uint32_t);
446 int (*rd_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t *);
447 int (*wr_reg_indirect) (struct scsi_qla_host *, uint32_t, uint32_t);
448 int (*idc_lock) (struct scsi_qla_host *);
449 void (*idc_unlock) (struct scsi_qla_host *);
450 void (*rom_lock_recovery) (struct scsi_qla_host *);
451 void (*queue_mailbox_command) (struct scsi_qla_host *, uint32_t *, int);
452 void (*process_mailbox_interrupt) (struct scsi_qla_host *, int);
453};
454
455struct ql4_mdump_size_table {
456 uint32_t size;
457 uint32_t size_cmask_02;
458 uint32_t size_cmask_04;
459 uint32_t size_cmask_08;
460 uint32_t size_cmask_10;
461 uint32_t size_cmask_FF;
462 uint32_t version;
463};
464
465
466struct ipaddress_config {
467 uint16_t ipv4_options;
468 uint16_t tcp_options;
469 uint16_t ipv4_vlan_tag;
470 uint8_t ipv4_addr_state;
471 uint8_t ip_address[IP_ADDR_LEN];
472 uint8_t subnet_mask[IP_ADDR_LEN];
473 uint8_t gateway[IP_ADDR_LEN];
474 uint32_t ipv6_options;
475 uint32_t ipv6_addl_options;
476 uint8_t ipv6_link_local_state;
477 uint8_t ipv6_addr0_state;
478 uint8_t ipv6_addr1_state;
479 uint8_t ipv6_default_router_state;
480 uint16_t ipv6_vlan_tag;
481 struct in6_addr ipv6_link_local_addr;
482 struct in6_addr ipv6_addr0;
483 struct in6_addr ipv6_addr1;
484 struct in6_addr ipv6_default_router_addr;
485 uint16_t eth_mtu_size;
486 uint16_t ipv4_port;
487 uint16_t ipv6_port;
488 uint8_t control;
489 uint16_t ipv6_tcp_options;
490 uint8_t tcp_wsf;
491 uint8_t ipv6_tcp_wsf;
492 uint8_t ipv4_tos;
493 uint8_t ipv4_cache_id;
494 uint8_t ipv6_cache_id;
495 uint8_t ipv4_alt_cid_len;
496 uint8_t ipv4_alt_cid[11];
497 uint8_t ipv4_vid_len;
498 uint8_t ipv4_vid[11];
499 uint8_t ipv4_ttl;
500 uint16_t ipv6_flow_lbl;
501 uint8_t ipv6_traffic_class;
502 uint8_t ipv6_hop_limit;
503 uint32_t ipv6_nd_reach_time;
504 uint32_t ipv6_nd_rexmit_timer;
505 uint32_t ipv6_nd_stale_timeout;
506 uint8_t ipv6_dup_addr_detect_count;
507 uint32_t ipv6_gw_advrt_mtu;
508 uint16_t def_timeout;
509 uint8_t abort_timer;
510 uint16_t iscsi_options;
511 uint16_t iscsi_max_pdu_size;
512 uint16_t iscsi_first_burst_len;
513 uint16_t iscsi_max_outstnd_r2t;
514 uint16_t iscsi_max_burst_len;
515 uint8_t iscsi_name[224];
516};
517
518#define QL4_CHAP_MAX_NAME_LEN 256
519#define QL4_CHAP_MAX_SECRET_LEN 100
520#define LOCAL_CHAP 0
521#define BIDI_CHAP 1
522
523struct ql4_chap_format {
524 u8 intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
525 u8 intr_secret[QL4_CHAP_MAX_SECRET_LEN];
526 u8 target_chap_name[QL4_CHAP_MAX_NAME_LEN];
527 u8 target_secret[QL4_CHAP_MAX_SECRET_LEN];
528 u16 intr_chap_name_length;
529 u16 intr_secret_length;
530 u16 target_chap_name_length;
531 u16 target_secret_length;
532};
533
534struct ip_address_format {
535 u8 ip_type;
536 u8 ip_address[16];
537};
538
539struct ql4_conn_info {
540 u16 dest_port;
541 struct ip_address_format dest_ipaddr;
542 struct ql4_chap_format chap;
543};
544
545struct ql4_boot_session_info {
546 u8 target_name[224];
547 struct ql4_conn_info conn_list[1];
548};
549
550struct ql4_boot_tgt_info {
551 struct ql4_boot_session_info boot_pri_sess;
552 struct ql4_boot_session_info boot_sec_sess;
553};
554
555
556
557
558struct scsi_qla_host {
559
560 unsigned long flags;
561
562#define AF_ONLINE 0
563#define AF_INIT_DONE 1
564#define AF_MBOX_COMMAND 2
565#define AF_MBOX_COMMAND_DONE 3
566#define AF_ST_DISCOVERY_IN_PROGRESS 4
567#define AF_INTERRUPTS_ON 6
568#define AF_GET_CRASH_RECORD 7
569#define AF_LINK_UP 8
570#define AF_LOOPBACK 9
571#define AF_IRQ_ATTACHED 10
572#define AF_DISABLE_ACB_COMPLETE 11
573#define AF_HA_REMOVAL 12
574#define AF_INTx_ENABLED 15
575#define AF_MSI_ENABLED 16
576#define AF_MSIX_ENABLED 17
577#define AF_MBOX_COMMAND_NOPOLL 18
578#define AF_FW_RECOVERY 19
579#define AF_EEH_BUSY 20
580#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21
581#define AF_BUILD_DDB_LIST 22
582#define AF_82XX_FW_DUMPED 24
583#define AF_8XXX_RST_OWNER 25
584#define AF_82XX_DUMP_READING 26
585#define AF_83XX_IOCB_INTR_ON 28
586#define AF_83XX_MBOX_INTR_ON 29
587
588 unsigned long dpc_flags;
589
590#define DPC_RESET_HA 1
591#define DPC_RETRY_RESET_HA 2
592#define DPC_RELOGIN_DEVICE 3
593#define DPC_RESET_HA_FW_CONTEXT 4
594#define DPC_RESET_HA_INTR 5
595#define DPC_ISNS_RESTART 7
596#define DPC_AEN 9
597#define DPC_GET_DHCP_IP_ADDR 15
598#define DPC_LINK_CHANGED 18
599#define DPC_RESET_ACTIVE 20
600#define DPC_HA_UNRECOVERABLE 21
601#define DPC_HA_NEED_QUIESCENT 22
602#define DPC_POST_IDC_ACK 23
603#define DPC_RESTORE_ACB 24
604#define DPC_SYSFS_DDB_EXPORT 25
605
606 struct Scsi_Host *host;
607 uint32_t tot_ddbs;
608
609 uint16_t iocb_cnt;
610 uint16_t iocb_hiwat;
611
612
613#define SRB_MIN_REQ 128
614 mempool_t *srb_mempool;
615
616
617 struct pci_dev *pdev;
618
619 struct isp_reg __iomem *reg;
620 unsigned long pio_address;
621 unsigned long pio_length;
622#define MIN_IOBASE_LEN 0x100
623
624 uint16_t req_q_count;
625
626 unsigned long host_no;
627
628
629 struct eeprom_data *nvram;
630 spinlock_t hardware_lock ____cacheline_aligned;
631 uint32_t eeprom_cmd_data;
632
633
634 uint64_t isr_count;
635 uint64_t adapter_error_count;
636 uint64_t device_error_count;
637 uint64_t total_io_count;
638 uint64_t total_mbytes_xferred;
639 uint64_t link_failure_count;
640 uint64_t invalid_crc_count;
641 uint32_t bytes_xfered;
642 uint32_t spurious_int_count;
643 uint32_t aborted_io_count;
644 uint32_t io_timeout_count;
645 uint32_t mailbox_timeout_count;
646 uint32_t seconds_since_last_intr;
647 uint32_t seconds_since_last_heartbeat;
648 uint32_t mac_index;
649
650
651
652 uint32_t firmware_version[2];
653 uint32_t patch_number;
654 uint32_t build_number;
655 uint32_t board_id;
656
657
658
659 uint16_t firmware_options;
660 uint8_t alias[32];
661 uint8_t name_string[256];
662 uint8_t heartbeat_interval;
663
664
665 uint8_t my_mac[MAC_ADDR_LEN];
666 uint8_t serial_number[16];
667 uint16_t port_num;
668
669 uint32_t firmware_state;
670 uint32_t addl_fw_state;
671
672
673 struct workqueue_struct *dpc_thread;
674 struct work_struct dpc_work;
675
676
677 struct timer_list timer;
678 uint32_t timer_active;
679
680
681 atomic_t check_relogin_timeouts;
682 uint32_t retry_reset_ha_cnt;
683 uint32_t isp_reset_timer;
684 uint32_t nic_reset_timer;
685 int eh_start;
686 struct list_head free_srb_q;
687 uint16_t free_srb_q_count;
688 uint16_t num_srbs_allocated;
689
690
691 void *queues;
692 dma_addr_t queues_dma;
693 unsigned long queues_len;
694
695#define MEM_ALIGN_VALUE \
696 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
697 sizeof(struct queue_entry))
698
699 dma_addr_t request_dma;
700 struct queue_entry *request_ring;
701 struct queue_entry *request_ptr;
702 dma_addr_t response_dma;
703 struct queue_entry *response_ring;
704 struct queue_entry *response_ptr;
705 dma_addr_t shadow_regs_dma;
706 struct shadow_regs *shadow_regs;
707 uint16_t request_in;
708 uint16_t request_out;
709 uint16_t response_in;
710 uint16_t response_out;
711
712
713 uint16_t aen_q_count;
714 uint16_t aen_in;
715 uint16_t aen_out;
716 struct aen aen_q[MAX_AEN_ENTRIES];
717
718 struct ql4_aen_log aen_log;
719
720
721
722
723 struct mutex mbox_sem;
724
725
726 volatile uint8_t mbox_status_count;
727 volatile uint32_t mbox_status[MBOX_REG_COUNT];
728
729
730 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
731
732
733 struct srb *status_srb;
734
735 uint8_t acb_version;
736
737
738 struct device_reg_82xx __iomem *qla4_82xx_reg;
739 unsigned long nx_pcibase;
740 uint8_t *nx_db_rd_ptr;
741 unsigned long nx_db_wr_ptr;
742 unsigned long first_page_group_start;
743 unsigned long first_page_group_end;
744
745 uint32_t crb_win;
746 uint32_t curr_window;
747 uint32_t ddr_mn_window;
748 unsigned long mn_win_crb;
749 unsigned long ms_win_crb;
750 int qdr_sn_window;
751 rwlock_t hw_lock;
752 uint16_t func_num;
753 int link_width;
754
755 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
756 u32 nx_crb_mask;
757
758 uint8_t revision_id;
759 uint32_t fw_heartbeat_counter;
760
761 struct isp_operations *isp_ops;
762 struct ql82xx_hw_data hw;
763
764 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
765
766 uint32_t nx_dev_init_timeout;
767 uint32_t nx_reset_timeout;
768 void *fw_dump;
769 uint32_t fw_dump_size;
770 uint32_t fw_dump_capture_mask;
771 void *fw_dump_tmplt_hdr;
772 uint32_t fw_dump_tmplt_size;
773 uint32_t fw_dump_skip_size;
774
775 struct completion mbx_intr_comp;
776
777 struct ipaddress_config ip_config;
778 struct iscsi_iface *iface_ipv4;
779 struct iscsi_iface *iface_ipv6_0;
780 struct iscsi_iface *iface_ipv6_1;
781
782
783 struct about_fw_info fw_info;
784 uint32_t fw_uptime_secs;
785 uint32_t fw_uptime_msecs;
786 uint16_t def_timeout;
787
788 uint32_t flash_state;
789#define QLFLASH_WAITING 0
790#define QLFLASH_READING 1
791#define QLFLASH_WRITING 2
792 struct dma_pool *chap_dma_pool;
793 uint8_t *chap_list;
794 struct mutex chap_sem;
795
796#define CHAP_DMA_BLOCK_SIZE 512
797 struct workqueue_struct *task_wq;
798 unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
799#define SYSFS_FLAG_FW_SEL_BOOT 2
800 struct iscsi_boot_kset *boot_kset;
801 struct ql4_boot_tgt_info boot_tgt;
802 uint16_t phy_port_num;
803 uint16_t phy_port_cnt;
804 uint16_t iscsi_pci_func_cnt;
805 uint8_t model_name[16];
806 struct completion disable_acb_comp;
807 struct dma_pool *fw_ddb_dma_pool;
808#define DDB_DMA_BLOCK_SIZE 512
809 uint16_t pri_ddb_idx;
810 uint16_t sec_ddb_idx;
811 int is_reset;
812 uint16_t temperature;
813
814
815 struct list_head work_list;
816 spinlock_t work_lock;
817
818
819#define MAX_MRB 128
820 struct mrb *active_mrb_array[MAX_MRB];
821 uint32_t mrb_index;
822
823 uint32_t *reg_tbl;
824 struct qla4_83xx_reset_template reset_tmplt;
825 struct device_reg_83xx __iomem *qla4_83xx_reg;
826
827
828 uint32_t pf_bit;
829 struct qla4_83xx_idc_information idc_info;
830 struct addr_ctrl_blk *saved_acb;
831 int notify_idc_comp;
832 int notify_link_up_comp;
833 int idc_extend_tmo;
834 struct completion idc_comp;
835 struct completion link_up_comp;
836};
837
838struct ql4_task_data {
839 struct scsi_qla_host *ha;
840 uint8_t iocb_req_cnt;
841 dma_addr_t data_dma;
842 void *req_buffer;
843 dma_addr_t req_dma;
844 uint32_t req_len;
845 void *resp_buffer;
846 dma_addr_t resp_dma;
847 uint32_t resp_len;
848 struct iscsi_task *task;
849 struct passthru_status sts;
850 struct work_struct task_work;
851};
852
853struct qla_endpoint {
854 struct Scsi_Host *host;
855 struct sockaddr_storage dst_addr;
856};
857
858struct qla_conn {
859 struct qla_endpoint *qla_ep;
860};
861
862static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
863{
864 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
865}
866
867static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
868{
869 return ((ha->ip_config.ipv6_options &
870 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
871}
872
873static inline int is_qla4010(struct scsi_qla_host *ha)
874{
875 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
876}
877
878static inline int is_qla4022(struct scsi_qla_host *ha)
879{
880 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
881}
882
883static inline int is_qla4032(struct scsi_qla_host *ha)
884{
885 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
886}
887
888static inline int is_qla40XX(struct scsi_qla_host *ha)
889{
890 return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
891}
892
893static inline int is_qla8022(struct scsi_qla_host *ha)
894{
895 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
896}
897
898static inline int is_qla8032(struct scsi_qla_host *ha)
899{
900 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324;
901}
902
903static inline int is_qla8042(struct scsi_qla_host *ha)
904{
905 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042;
906}
907
908static inline int is_qla80XX(struct scsi_qla_host *ha)
909{
910 return is_qla8022(ha) || is_qla8032(ha) || is_qla8042(ha);
911}
912
913static inline int is_aer_supported(struct scsi_qla_host *ha)
914{
915 return ((ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022) ||
916 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8324) ||
917 (ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8042));
918}
919
920static inline int adapter_up(struct scsi_qla_host *ha)
921{
922 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
923 (test_bit(AF_LINK_UP, &ha->flags) != 0) &&
924 (!test_bit(AF_LOOPBACK, &ha->flags));
925}
926
927static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
928{
929 return (struct scsi_qla_host *)iscsi_host_priv(shost);
930}
931
932static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
933{
934 return (is_qla4010(ha) ?
935 &ha->reg->u1.isp4010.nvram :
936 &ha->reg->u1.isp4022.semaphore);
937}
938
939static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
940{
941 return (is_qla4010(ha) ?
942 &ha->reg->u1.isp4010.nvram :
943 &ha->reg->u1.isp4022.nvram);
944}
945
946static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
947{
948 return (is_qla4010(ha) ?
949 &ha->reg->u2.isp4010.ext_hw_conf :
950 &ha->reg->u2.isp4022.p0.ext_hw_conf);
951}
952
953static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
954{
955 return (is_qla4010(ha) ?
956 &ha->reg->u2.isp4010.port_status :
957 &ha->reg->u2.isp4022.p0.port_status);
958}
959
960static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
961{
962 return (is_qla4010(ha) ?
963 &ha->reg->u2.isp4010.port_ctrl :
964 &ha->reg->u2.isp4022.p0.port_ctrl);
965}
966
967static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
968{
969 return (is_qla4010(ha) ?
970 &ha->reg->u2.isp4010.port_err_status :
971 &ha->reg->u2.isp4022.p0.port_err_status);
972}
973
974static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
975{
976 return (is_qla4010(ha) ?
977 &ha->reg->u2.isp4010.gp_out :
978 &ha->reg->u2.isp4022.p0.gp_out);
979}
980
981static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
982{
983 return (is_qla4010(ha) ?
984 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
985 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
986}
987
988int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
989void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
990int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
991
992static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
993{
994 if (is_qla4010(a))
995 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
996 QL4010_FLASH_SEM_BITS);
997 else
998 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
999 (QL4022_RESOURCE_BITS_BASE_CODE |
1000 (a->mac_index)) << 13);
1001}
1002
1003static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
1004{
1005 if (is_qla4010(a))
1006 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
1007 else
1008 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
1009}
1010
1011static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
1012{
1013 if (is_qla4010(a))
1014 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
1015 QL4010_NVRAM_SEM_BITS);
1016 else
1017 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
1018 (QL4022_RESOURCE_BITS_BASE_CODE |
1019 (a->mac_index)) << 10);
1020}
1021
1022static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
1023{
1024 if (is_qla4010(a))
1025 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
1026 else
1027 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
1028}
1029
1030static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
1031{
1032 if (is_qla4010(a))
1033 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
1034 QL4010_DRVR_SEM_BITS);
1035 else
1036 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
1037 (QL4022_RESOURCE_BITS_BASE_CODE |
1038 (a->mac_index)) << 1);
1039}
1040
1041static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
1042{
1043 if (is_qla4010(a))
1044 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
1045 else
1046 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
1047}
1048
1049static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
1050{
1051 return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
1052 test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
1053 test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
1054 test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
1055 test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
1056 test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
1057
1058}
1059
1060static inline int qla4_8xxx_rd_direct(struct scsi_qla_host *ha,
1061 const uint32_t crb_reg)
1062{
1063 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]);
1064}
1065
1066static inline void qla4_8xxx_wr_direct(struct scsi_qla_host *ha,
1067 const uint32_t crb_reg,
1068 const uint32_t value)
1069{
1070 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value);
1071}
1072
1073
1074
1075
1076
1077#define INIT_ADAPTER 0
1078#define RESET_ADAPTER 1
1079
1080#define PRESERVE_DDB_LIST 0
1081#define REBUILD_DDB_LIST 1
1082
1083
1084#define PROCESS_ALL_AENS 0
1085#define FLUSH_DDB_CHANGED_AENS 1
1086
1087
1088#define QL4_UEVENT_CODE_FW_DUMP 0
1089
1090#endif
1091
