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14#include <linux/platform_device.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/console.h>
20#include <linux/clk.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23#include <linux/of.h>
24#include <linux/module.h>
25
26#define XUARTPS_TTY_NAME "ttyPS"
27#define XUARTPS_NAME "xuartps"
28#define XUARTPS_MAJOR 0
29#define XUARTPS_MINOR 0
30#define XUARTPS_NR_PORTS 2
31#define XUARTPS_FIFO_SIZE 16
32#define XUARTPS_REGISTER_SPACE 0xFFF
33
34#define xuartps_readl(offset) ioread32(port->membase + offset)
35#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
36
37
38
39
40
41
42
43#define XUARTPS_CR_OFFSET 0x00
44#define XUARTPS_MR_OFFSET 0x04
45#define XUARTPS_IER_OFFSET 0x08
46#define XUARTPS_IDR_OFFSET 0x0C
47#define XUARTPS_IMR_OFFSET 0x10
48#define XUARTPS_ISR_OFFSET 0x14
49#define XUARTPS_BAUDGEN_OFFSET 0x18
50#define XUARTPS_RXTOUT_OFFSET 0x1C
51#define XUARTPS_RXWM_OFFSET 0x20
52#define XUARTPS_MODEMCR_OFFSET 0x24
53#define XUARTPS_MODEMSR_OFFSET 0x28
54#define XUARTPS_SR_OFFSET 0x2C
55#define XUARTPS_FIFO_OFFSET 0x30
56#define XUARTPS_BAUDDIV_OFFSET 0x34
57#define XUARTPS_FLOWDEL_OFFSET 0x38
58#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C
59
60#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40
61
62#define XUARTPS_TXWM_OFFSET 0x44
63
64
65
66
67
68
69
70#define XUARTPS_CR_STOPBRK 0x00000100
71#define XUARTPS_CR_STARTBRK 0x00000080
72#define XUARTPS_CR_TX_DIS 0x00000020
73#define XUARTPS_CR_TX_EN 0x00000010
74#define XUARTPS_CR_RX_DIS 0x00000008
75#define XUARTPS_CR_RX_EN 0x00000004
76#define XUARTPS_CR_TXRST 0x00000002
77#define XUARTPS_CR_RXRST 0x00000001
78#define XUARTPS_CR_RST_TO 0x00000040
79
80
81
82
83
84
85
86
87
88
89#define XUARTPS_MR_CLKSEL 0x00000001
90#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200
91#define XUARTPS_MR_CHMODE_NORM 0x00000000
92
93#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080
94#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000
95
96#define XUARTPS_MR_PARITY_NONE 0x00000020
97#define XUARTPS_MR_PARITY_MARK 0x00000018
98#define XUARTPS_MR_PARITY_SPACE 0x00000010
99#define XUARTPS_MR_PARITY_ODD 0x00000008
100#define XUARTPS_MR_PARITY_EVEN 0x00000000
101
102#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006
103#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004
104#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000
105
106
107
108
109
110
111
112
113
114
115
116
117
118#define XUARTPS_IXR_TOUT 0x00000100
119#define XUARTPS_IXR_PARITY 0x00000080
120#define XUARTPS_IXR_FRAMING 0x00000040
121#define XUARTPS_IXR_OVERRUN 0x00000020
122#define XUARTPS_IXR_TXFULL 0x00000010
123#define XUARTPS_IXR_TXEMPTY 0x00000008
124#define XUARTPS_ISR_RXEMPTY 0x00000002
125#define XUARTPS_IXR_RXTRIG 0x00000001
126#define XUARTPS_IXR_RXFULL 0x00000004
127#define XUARTPS_IXR_RXEMPTY 0x00000002
128#define XUARTPS_IXR_MASK 0x00001FFF
129
130
131
132
133
134
135
136#define XUARTPS_SR_RXEMPTY 0x00000002
137#define XUARTPS_SR_TXEMPTY 0x00000008
138#define XUARTPS_SR_TXFULL 0x00000010
139#define XUARTPS_SR_RXTRIG 0x00000001
140
141
142
143
144
145
146
147
148static irqreturn_t xuartps_isr(int irq, void *dev_id)
149{
150 struct uart_port *port = (struct uart_port *)dev_id;
151 unsigned long flags;
152 unsigned int isrstatus, numbytes;
153 unsigned int data;
154 char status = TTY_NORMAL;
155
156 spin_lock_irqsave(&port->lock, flags);
157
158
159
160
161 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
162
163
164 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
165 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
166
167 isrstatus &= port->read_status_mask;
168 isrstatus &= ~port->ignore_status_mask;
169
170 if ((isrstatus & XUARTPS_IXR_TOUT) ||
171 (isrstatus & XUARTPS_IXR_RXTRIG)) {
172
173 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
174 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
175 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
176 port->icount.rx++;
177
178 if (isrstatus & XUARTPS_IXR_PARITY) {
179 port->icount.parity++;
180 status = TTY_PARITY;
181 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
182 port->icount.frame++;
183 status = TTY_FRAME;
184 } else if (isrstatus & XUARTPS_IXR_OVERRUN)
185 port->icount.overrun++;
186
187 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN,
188 data, status);
189 }
190 spin_unlock(&port->lock);
191 tty_flip_buffer_push(&port->state->port);
192 spin_lock(&port->lock);
193 }
194
195
196 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
197 if (uart_circ_empty(&port->state->xmit)) {
198 xuartps_writel(XUARTPS_IXR_TXEMPTY,
199 XUARTPS_IDR_OFFSET);
200 } else {
201 numbytes = port->fifosize;
202
203 while (numbytes--) {
204 if (uart_circ_empty(&port->state->xmit))
205 break;
206
207
208
209
210 xuartps_writel(
211 port->state->xmit.buf[port->state->xmit.
212 tail], XUARTPS_FIFO_OFFSET);
213
214 port->icount.tx++;
215
216
217
218
219 port->state->xmit.tail =
220 (port->state->xmit.tail + 1) & \
221 (UART_XMIT_SIZE - 1);
222 }
223
224 if (uart_circ_chars_pending(
225 &port->state->xmit) < WAKEUP_CHARS)
226 uart_write_wakeup(port);
227 }
228 }
229
230 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
231
232
233 spin_unlock_irqrestore(&port->lock, flags);
234
235 return IRQ_HANDLED;
236}
237
238
239
240
241
242
243
244
245
246static unsigned int xuartps_set_baud_rate(struct uart_port *port,
247 unsigned int baud)
248{
249 unsigned int sel_clk;
250 unsigned int calc_baud = 0;
251 unsigned int brgr_val, brdiv_val;
252 unsigned int bauderror;
253
254
255
256
257
258
259
260
261
262
263
264 sel_clk = port->uartclk;
265 if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL)
266 sel_clk = sel_clk / 8;
267
268
269 for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) {
270
271 brgr_val = sel_clk / (baud * (brdiv_val + 1));
272 if (brgr_val < 2 || brgr_val > 65535)
273 continue;
274
275 calc_baud = sel_clk / (brgr_val * (brdiv_val + 1));
276
277 if (baud > calc_baud)
278 bauderror = baud - calc_baud;
279 else
280 bauderror = calc_baud - baud;
281
282
283 if (((bauderror * 100) / baud) < 3) {
284 calc_baud = baud;
285 break;
286 }
287 }
288
289
290 xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET);
291 xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET);
292
293 return calc_baud;
294}
295
296
297
298
299
300
301
302
303static void xuartps_start_tx(struct uart_port *port)
304{
305 unsigned int status, numbytes = port->fifosize;
306
307 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
308 return;
309
310 status = xuartps_readl(XUARTPS_CR_OFFSET);
311
312
313
314 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
315 XUARTPS_CR_OFFSET);
316
317 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
318 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
319
320
321 if (uart_circ_empty(&port->state->xmit))
322 break;
323
324
325
326
327 xuartps_writel(
328 port->state->xmit.buf[port->state->xmit.tail],
329 XUARTPS_FIFO_OFFSET);
330 port->icount.tx++;
331
332
333
334
335 port->state->xmit.tail = (port->state->xmit.tail + 1) &
336 (UART_XMIT_SIZE - 1);
337 }
338
339
340 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
341
342 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(port);
344}
345
346
347
348
349
350
351static void xuartps_stop_tx(struct uart_port *port)
352{
353 unsigned int regval;
354
355 regval = xuartps_readl(XUARTPS_CR_OFFSET);
356 regval |= XUARTPS_CR_TX_DIS;
357
358 xuartps_writel(regval, XUARTPS_CR_OFFSET);
359}
360
361
362
363
364
365
366static void xuartps_stop_rx(struct uart_port *port)
367{
368 unsigned int regval;
369
370 regval = xuartps_readl(XUARTPS_CR_OFFSET);
371 regval |= XUARTPS_CR_RX_DIS;
372
373 xuartps_writel(regval, XUARTPS_CR_OFFSET);
374}
375
376
377
378
379
380
381
382static unsigned int xuartps_tx_empty(struct uart_port *port)
383{
384 unsigned int status;
385
386 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
387 return status ? TIOCSER_TEMT : 0;
388}
389
390
391
392
393
394
395
396
397static void xuartps_break_ctl(struct uart_port *port, int ctl)
398{
399 unsigned int status;
400 unsigned long flags;
401
402 spin_lock_irqsave(&port->lock, flags);
403
404 status = xuartps_readl(XUARTPS_CR_OFFSET);
405
406 if (ctl == -1)
407 xuartps_writel(XUARTPS_CR_STARTBRK | status,
408 XUARTPS_CR_OFFSET);
409 else {
410 if ((status & XUARTPS_CR_STOPBRK) == 0)
411 xuartps_writel(XUARTPS_CR_STOPBRK | status,
412 XUARTPS_CR_OFFSET);
413 }
414 spin_unlock_irqrestore(&port->lock, flags);
415}
416
417
418
419
420
421
422
423
424
425static void xuartps_set_termios(struct uart_port *port,
426 struct ktermios *termios, struct ktermios *old)
427{
428 unsigned int cval = 0;
429 unsigned int baud;
430 unsigned long flags;
431 unsigned int ctrl_reg, mode_reg;
432
433 spin_lock_irqsave(&port->lock, flags);
434
435
436 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
437 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
438 xuartps_readl(XUARTPS_FIFO_OFFSET);
439 }
440
441
442 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
443 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
444 XUARTPS_CR_OFFSET);
445
446
447 baud = uart_get_baud_rate(port, termios, old, 0, 10000000);
448 baud = xuartps_set_baud_rate(port, baud);
449 if (tty_termios_baud_rate(termios))
450 tty_termios_encode_baud_rate(termios, baud, baud);
451
452
453
454
455 uart_update_timeout(port, termios->c_cflag, baud);
456
457
458 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
459 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
460 XUARTPS_CR_OFFSET);
461
462 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
463
464
465
466
467 xuartps_writel(
468 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
469 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
470 XUARTPS_CR_OFFSET);
471
472 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
473
474 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
475 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
476 port->ignore_status_mask = 0;
477
478 if (termios->c_iflag & INPCK)
479 port->read_status_mask |= XUARTPS_IXR_PARITY |
480 XUARTPS_IXR_FRAMING;
481
482 if (termios->c_iflag & IGNPAR)
483 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
484 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
485
486
487 if ((termios->c_cflag & CREAD) == 0)
488 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
489 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
490 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
491
492 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
493
494
495 switch (termios->c_cflag & CSIZE) {
496 case CS6:
497 cval |= XUARTPS_MR_CHARLEN_6_BIT;
498 break;
499 case CS7:
500 cval |= XUARTPS_MR_CHARLEN_7_BIT;
501 break;
502 default:
503 case CS8:
504 cval |= XUARTPS_MR_CHARLEN_8_BIT;
505 termios->c_cflag &= ~CSIZE;
506 termios->c_cflag |= CS8;
507 break;
508 }
509
510
511 if (termios->c_cflag & CSTOPB)
512 cval |= XUARTPS_MR_STOPMODE_2_BIT;
513 else
514 cval |= XUARTPS_MR_STOPMODE_1_BIT;
515
516 if (termios->c_cflag & PARENB) {
517
518 if (termios->c_cflag & CMSPAR) {
519 if (termios->c_cflag & PARODD)
520 cval |= XUARTPS_MR_PARITY_MARK;
521 else
522 cval |= XUARTPS_MR_PARITY_SPACE;
523 } else if (termios->c_cflag & PARODD)
524 cval |= XUARTPS_MR_PARITY_ODD;
525 else
526 cval |= XUARTPS_MR_PARITY_EVEN;
527 } else
528 cval |= XUARTPS_MR_PARITY_NONE;
529 xuartps_writel(cval , XUARTPS_MR_OFFSET);
530
531 spin_unlock_irqrestore(&port->lock, flags);
532}
533
534
535
536
537
538
539
540static int xuartps_startup(struct uart_port *port)
541{
542 unsigned int retval = 0, status = 0;
543
544 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
545 (void *)port);
546 if (retval)
547 return retval;
548
549
550 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
551 XUARTPS_CR_OFFSET);
552
553
554
555
556 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
557 XUARTPS_CR_OFFSET);
558
559 status = xuartps_readl(XUARTPS_CR_OFFSET);
560
561
562
563
564 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
565 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
566 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
567
568
569
570
571 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
572 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
573 XUARTPS_MR_OFFSET);
574
575
576 xuartps_writel(14, XUARTPS_RXWM_OFFSET);
577
578
579 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
580
581
582 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET);
583
584
585 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
586 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
587 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
588
589 return retval;
590}
591
592
593
594
595
596
597static void xuartps_shutdown(struct uart_port *port)
598{
599 int status;
600
601
602 status = xuartps_readl(XUARTPS_IMR_OFFSET);
603 xuartps_writel(status, XUARTPS_IDR_OFFSET);
604
605
606 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
607 XUARTPS_CR_OFFSET);
608 free_irq(port->irq, port);
609}
610
611
612
613
614
615
616
617static const char *xuartps_type(struct uart_port *port)
618{
619 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
620}
621
622
623
624
625
626
627
628
629static int xuartps_verify_port(struct uart_port *port,
630 struct serial_struct *ser)
631{
632 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
633 return -EINVAL;
634 if (port->irq != ser->irq)
635 return -EINVAL;
636 if (ser->io_type != UPIO_MEM)
637 return -EINVAL;
638 if (port->iobase != ser->port)
639 return -EINVAL;
640 if (ser->hub6 != 0)
641 return -EINVAL;
642 return 0;
643}
644
645
646
647
648
649
650
651
652
653static int xuartps_request_port(struct uart_port *port)
654{
655 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
656 XUARTPS_NAME)) {
657 return -ENOMEM;
658 }
659
660 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
661 if (!port->membase) {
662 dev_err(port->dev, "Unable to map registers\n");
663 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
664 return -ENOMEM;
665 }
666 return 0;
667}
668
669
670
671
672
673
674
675
676static void xuartps_release_port(struct uart_port *port)
677{
678 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
679 iounmap(port->membase);
680 port->membase = NULL;
681}
682
683
684
685
686
687
688
689
690static void xuartps_config_port(struct uart_port *port, int flags)
691{
692 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
693 port->type = PORT_XUARTPS;
694}
695
696
697
698
699
700
701
702
703
704static unsigned int xuartps_get_mctrl(struct uart_port *port)
705{
706 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
707}
708
709static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
710{
711
712}
713
714static void xuartps_enable_ms(struct uart_port *port)
715{
716
717}
718
719
720
721static struct uart_ops xuartps_ops = {
722 .set_mctrl = xuartps_set_mctrl,
723 .get_mctrl = xuartps_get_mctrl,
724 .enable_ms = xuartps_enable_ms,
725
726 .start_tx = xuartps_start_tx,
727 .stop_tx = xuartps_stop_tx,
728 .stop_rx = xuartps_stop_rx,
729 .tx_empty = xuartps_tx_empty,
730 .break_ctl = xuartps_break_ctl,
731
732
733 .set_termios = xuartps_set_termios,
734 .startup = xuartps_startup,
735 .shutdown = xuartps_shutdown,
736 .type = xuartps_type,
737 .verify_port = xuartps_verify_port,
738
739
740 .request_port = xuartps_request_port,
741
742
743
744 .release_port = xuartps_release_port,
745
746
747
748 .config_port = xuartps_config_port,
749
750
751};
752
753static struct uart_port xuartps_port[2];
754
755
756
757
758
759
760
761static struct uart_port *xuartps_get_port(void)
762{
763 struct uart_port *port;
764 int id;
765
766
767 for (id = 0; id < XUARTPS_NR_PORTS; id++)
768 if (xuartps_port[id].mapbase == 0)
769 break;
770
771 if (id >= XUARTPS_NR_PORTS)
772 return NULL;
773
774 port = &xuartps_port[id];
775
776
777 spin_lock_init(&port->lock);
778 port->membase = NULL;
779 port->iobase = 1;
780 port->irq = 0;
781 port->type = PORT_UNKNOWN;
782 port->iotype = UPIO_MEM32;
783 port->flags = UPF_BOOT_AUTOCONF;
784 port->ops = &xuartps_ops;
785 port->fifosize = XUARTPS_FIFO_SIZE;
786 port->line = id;
787 port->dev = NULL;
788 return port;
789}
790
791
792
793#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
794
795
796
797
798
799static void xuartps_console_wait_tx(struct uart_port *port)
800{
801 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
802 != XUARTPS_SR_TXEMPTY)
803 barrier();
804}
805
806
807
808
809
810
811
812static void xuartps_console_putchar(struct uart_port *port, int ch)
813{
814 xuartps_console_wait_tx(port);
815 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
816}
817
818
819
820
821
822
823
824static void xuartps_console_write(struct console *co, const char *s,
825 unsigned int count)
826{
827 struct uart_port *port = &xuartps_port[co->index];
828 unsigned long flags;
829 unsigned int imr;
830 int locked = 1;
831
832 if (oops_in_progress)
833 locked = spin_trylock_irqsave(&port->lock, flags);
834 else
835 spin_lock_irqsave(&port->lock, flags);
836
837
838 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
839 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
840
841 uart_console_write(port, s, count, xuartps_console_putchar);
842 xuartps_console_wait_tx(port);
843
844
845
846
847
848 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
849 xuartps_writel(imr, XUARTPS_IER_OFFSET);
850
851 if (locked)
852 spin_unlock_irqrestore(&port->lock, flags);
853}
854
855
856
857
858
859
860
861
862static int __init xuartps_console_setup(struct console *co, char *options)
863{
864 struct uart_port *port = &xuartps_port[co->index];
865 int baud = 9600;
866 int bits = 8;
867 int parity = 'n';
868 int flow = 'n';
869
870 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
871 return -EINVAL;
872
873 if (!port->mapbase) {
874 pr_debug("console on ttyPS%i not present\n", co->index);
875 return -ENODEV;
876 }
877
878 if (options)
879 uart_parse_options(options, &baud, &parity, &bits, &flow);
880
881 return uart_set_options(port, co, baud, parity, bits, flow);
882}
883
884static struct uart_driver xuartps_uart_driver;
885
886static struct console xuartps_console = {
887 .name = XUARTPS_TTY_NAME,
888 .write = xuartps_console_write,
889 .device = uart_console_device,
890 .setup = xuartps_console_setup,
891 .flags = CON_PRINTBUFFER,
892 .index = -1,
893 .data = &xuartps_uart_driver,
894};
895
896
897
898
899
900
901static int __init xuartps_console_init(void)
902{
903 register_console(&xuartps_console);
904 return 0;
905}
906
907console_initcall(xuartps_console_init);
908
909#endif
910
911
912
913static struct uart_driver xuartps_uart_driver = {
914 .owner = THIS_MODULE,
915 .driver_name = XUARTPS_NAME,
916 .dev_name = XUARTPS_TTY_NAME,
917 .major = XUARTPS_MAJOR,
918 .minor = XUARTPS_MINOR,
919 .nr = XUARTPS_NR_PORTS,
920#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
921 .cons = &xuartps_console,
922#endif
923};
924
925
926
927
928
929
930
931
932
933
934static int xuartps_probe(struct platform_device *pdev)
935{
936 int rc;
937 struct uart_port *port;
938 struct resource *res, *res2;
939 struct clk *clk;
940
941 clk = of_clk_get(pdev->dev.of_node, 0);
942 if (IS_ERR(clk)) {
943 dev_err(&pdev->dev, "no clock specified\n");
944 return PTR_ERR(clk);
945 }
946
947 rc = clk_prepare_enable(clk);
948 if (rc) {
949 dev_err(&pdev->dev, "could not enable clock\n");
950 return -EBUSY;
951 }
952
953 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
954 if (!res)
955 return -ENODEV;
956
957 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
958 if (!res2)
959 return -ENODEV;
960
961
962 port = xuartps_get_port();
963
964 if (!port) {
965 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
966 return -ENODEV;
967 } else {
968
969
970
971
972 port->mapbase = res->start;
973 port->irq = res2->start;
974 port->dev = &pdev->dev;
975 port->uartclk = clk_get_rate(clk);
976 port->private_data = clk;
977 dev_set_drvdata(&pdev->dev, port);
978 rc = uart_add_one_port(&xuartps_uart_driver, port);
979 if (rc) {
980 dev_err(&pdev->dev,
981 "uart_add_one_port() failed; err=%i\n", rc);
982 dev_set_drvdata(&pdev->dev, NULL);
983 return rc;
984 }
985 return 0;
986 }
987}
988
989
990
991
992
993
994
995static int xuartps_remove(struct platform_device *pdev)
996{
997 struct uart_port *port = dev_get_drvdata(&pdev->dev);
998 struct clk *clk = port->private_data;
999 int rc;
1000
1001
1002 rc = uart_remove_one_port(&xuartps_uart_driver, port);
1003 dev_set_drvdata(&pdev->dev, NULL);
1004 port->mapbase = 0;
1005 clk_disable_unprepare(clk);
1006 return rc;
1007}
1008
1009
1010
1011
1012
1013
1014
1015
1016static int xuartps_suspend(struct platform_device *pdev, pm_message_t state)
1017{
1018
1019
1020
1021 uart_suspend_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
1022 return 0;
1023}
1024
1025
1026
1027
1028
1029
1030
1031static int xuartps_resume(struct platform_device *pdev)
1032{
1033 uart_resume_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
1034 return 0;
1035}
1036
1037
1038static struct of_device_id xuartps_of_match[] = {
1039 { .compatible = "xlnx,xuartps", },
1040 {}
1041};
1042MODULE_DEVICE_TABLE(of, xuartps_of_match);
1043
1044static struct platform_driver xuartps_platform_driver = {
1045 .probe = xuartps_probe,
1046 .remove = xuartps_remove,
1047 .suspend = xuartps_suspend,
1048 .resume = xuartps_resume,
1049 .driver = {
1050 .owner = THIS_MODULE,
1051 .name = XUARTPS_NAME,
1052 .of_match_table = xuartps_of_match,
1053 },
1054};
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064static int __init xuartps_init(void)
1065{
1066 int retval = 0;
1067
1068
1069 retval = uart_register_driver(&xuartps_uart_driver);
1070 if (retval)
1071 return retval;
1072
1073
1074 retval = platform_driver_register(&xuartps_platform_driver);
1075 if (retval)
1076 uart_unregister_driver(&xuartps_uart_driver);
1077
1078 return retval;
1079}
1080
1081
1082
1083
1084static void __exit xuartps_exit(void)
1085{
1086
1087
1088
1089
1090
1091 platform_driver_unregister(&xuartps_platform_driver);
1092
1093
1094 uart_unregister_driver(&xuartps_uart_driver);
1095}
1096
1097module_init(xuartps_init);
1098module_exit(xuartps_exit);
1099
1100MODULE_DESCRIPTION("Driver for PS UART");
1101MODULE_AUTHOR("Xilinx Inc.");
1102MODULE_LICENSE("GPL");
1103