LXR linux/drivers/tty/synclink

   1/*
   2 * Device driver for Microgate SyncLink GT serial adapters.
   3 *
   4 * written by Paul Fulghum for Microgate Corporation
   5 * paulkf@microgate.com
   6 *
   7 * Microgate and SyncLink are trademarks of Microgate Corporation
   8 *
   9 * This code is released under the GNU General Public License (GPL)
  10 *
  11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21 * OF THE POSSIBILITY OF SUCH DAMAGE.
  22 */
  23
  24/*
  25 * DEBUG OUTPUT DEFINITIONS
  26 *
  27 * uncomment lines below to enable specific types of debug output
  28 *
  29 * DBGINFO   information - most verbose output
  30 * DBGERR    serious errors
  31 * DBGBH     bottom half service routine debugging
  32 * DBGISR    interrupt service routine debugging
  33 * DBGDATA   output receive and transmit data
  34 * DBGTBUF   output transmit DMA buffers and registers
  35 * DBGRBUF   output receive DMA buffers and registers
  36 */
  37
  38#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43/*#define DBGTBUF(info) dump_tbufs(info)*/
  44/*#define DBGRBUF(info) dump_rbufs(info)*/
  45
  46
  47#include <linux/module.h>
  48#include <linux/errno.h>
  49#include <linux/signal.h>
  50#include <linux/sched.h>
  51#include <linux/timer.h>
  52#include <linux/interrupt.h>
  53#include <linux/pci.h>
  54#include <linux/tty.h>
  55#include <linux/tty_flip.h>
  56#include <linux/serial.h>
  57#include <linux/major.h>
  58#include <linux/string.h>
  59#include <linux/fcntl.h>
  60#include <linux/ptrace.h>
  61#include <linux/ioport.h>
  62#include <linux/mm.h>
  63#include <linux/seq_file.h>
  64#include <linux/slab.h>
  65#include <linux/netdevice.h>
  66#include <linux/vmalloc.h>
  67#include <linux/init.h>
  68#include <linux/delay.h>
  69#include <linux/ioctl.h>
  70#include <linux/termios.h>
  71#include <linux/bitops.h>
  72#include <linux/workqueue.h>
  73#include <linux/hdlc.h>
  74#include <linux/synclink.h>
  75
  76#include <asm/io.h>
  77#include <asm/irq.h>
  78#include <asm/dma.h>
  79#include <asm/types.h>
  80#include <asm/uaccess.h>
  81
  82#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  83#define SYNCLINK_GENERIC_HDLC 1
  84#else
  85#define SYNCLINK_GENERIC_HDLC 0
  86#endif
  87
  88/*
  89 * module identification
  90 */
  91static char *driver_name     = "SyncLink GT";
  92static char *tty_driver_name = "synclink_gt";
  93static char *tty_dev_prefix  = "ttySLG";
  94MODULE_LICENSE("GPL");
  95#define MGSL_MAGIC 0x5401
  96#define MAX_DEVICES 32
  97
  98static struct pci_device_id pci_table[] = {
  99        {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100        {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101        {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102        {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103        {0,}, /* terminate list */
 104};
 105MODULE_DEVICE_TABLE(pci, pci_table);
 106
 107static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 108static void remove_one(struct pci_dev *dev);
 109static struct pci_driver pci_driver = {
 110        .name           = "synclink_gt",
 111        .id_table       = pci_table,
 112        .probe          = init_one,
 113        .remove         = remove_one,
 114};
 115
 116static bool pci_registered;
 117
 118/*
 119 * module configuration and status
 120 */
 121static struct slgt_info *slgt_device_list;
 122static int slgt_device_count;
 123
 124static int ttymajor;
 125static int debug_level;
 126static int maxframe[MAX_DEVICES];
 127
 128module_param(ttymajor, int, 0);
 129module_param(debug_level, int, 0);
 130module_param_array(maxframe, int, NULL, 0);
 131
 132MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 133MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 134MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 135
 136/*
 137 * tty support and callbacks
 138 */
 139static struct tty_driver *serial_driver;
 140
 141static int  open(struct tty_struct *tty, struct file * filp);
 142static void close(struct tty_struct *tty, struct file * filp);
 143static void hangup(struct tty_struct *tty);
 144static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 145
 146static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 147static int put_char(struct tty_struct *tty, unsigned char ch);
 148static void send_xchar(struct tty_struct *tty, char ch);
 149static void wait_until_sent(struct tty_struct *tty, int timeout);
 150static int  write_room(struct tty_struct *tty);
 151static void flush_chars(struct tty_struct *tty);
 152static void flush_buffer(struct tty_struct *tty);
 153static void tx_hold(struct tty_struct *tty);
 154static void tx_release(struct tty_struct *tty);
 155
 156static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
 157static int  chars_in_buffer(struct tty_struct *tty);
 158static void throttle(struct tty_struct * tty);
 159static void unthrottle(struct tty_struct * tty);
 160static int set_break(struct tty_struct *tty, int break_state);
 161
 162/*
 163 * generic HDLC support and callbacks
 164 */
 165#if SYNCLINK_GENERIC_HDLC
 166#define dev_to_port(D) (dev_to_hdlc(D)->priv)
 167static void hdlcdev_tx_done(struct slgt_info *info);
 168static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 169static int  hdlcdev_init(struct slgt_info *info);
 170static void hdlcdev_exit(struct slgt_info *info);
 171#endif
 172
 173
 174/*
 175 * device specific structures, macros and functions
 176 */
 177
 178#define SLGT_MAX_PORTS 4
 179#define SLGT_REG_SIZE  256
 180
 181/*
 182 * conditional wait facility
 183 */
 184struct cond_wait {
 185        struct cond_wait *next;
 186        wait_queue_head_t q;
 187        wait_queue_t wait;
 188        unsigned int data;
 189};
 190static void init_cond_wait(struct cond_wait *w, unsigned int data);
 191static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 192static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 193static void flush_cond_wait(struct cond_wait **head);
 194
 195/*
 196 * DMA buffer descriptor and access macros
 197 */
 198struct slgt_desc
 199{
 200        __le16 count;
 201        __le16 status;
 202        __le32 pbuf;  /* physical address of data buffer */
 203        __le32 next;  /* physical address of next descriptor */
 204
 205        /* driver book keeping */
 206        char *buf;          /* virtual  address of data buffer */
 207        unsigned int pdesc; /* physical address of this descriptor */
 208        dma_addr_t buf_dma_addr;
 209        unsigned short buf_count;
 210};
 211
 212#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 213#define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 214#define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 215#define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 216#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 217#define desc_count(a)      (le16_to_cpu((a).count))
 218#define desc_status(a)     (le16_to_cpu((a).status))
 219#define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 220#define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 221#define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 222#define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 223#define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 224
 225struct _input_signal_events {
 226        int ri_up;
 227        int ri_down;
 228        int dsr_up;
 229        int dsr_down;
 230        int dcd_up;
 231        int dcd_down;
 232        int cts_up;
 233        int cts_down;
 234};
 235
 236/*
 237 * device instance data structure
 238 */
 239struct slgt_info {
 240        void *if_ptr;           /* General purpose pointer (used by SPPP) */
 241        struct tty_port port;
 242
 243        struct slgt_info *next_device;  /* device list link */
 244
 245        int magic;
 246
 247        char device_name[25];
 248        struct pci_dev *pdev;
 249
 250        int port_count;  /* count of ports on adapter */
 251        int adapter_num; /* adapter instance number */
 252        int port_num;    /* port instance number */
 253
 254        /* array of pointers to port contexts on this adapter */
 255        struct slgt_info *port_array[SLGT_MAX_PORTS];
 256
 257        int                     line;           /* tty line instance number */
 258
 259        struct mgsl_icount      icount;
 260
 261        int                     timeout;
 262        int                     x_char;         /* xon/xoff character */
 263        unsigned int            read_status_mask;
 264        unsigned int            ignore_status_mask;
 265
 266        wait_queue_head_t       status_event_wait_q;
 267        wait_queue_head_t       event_wait_q;
 268        struct timer_list       tx_timer;
 269        struct timer_list       rx_timer;
 270
 271        unsigned int            gpio_present;
 272        struct cond_wait        *gpio_wait_q;
 273
 274        spinlock_t lock;        /* spinlock for synchronizing with ISR */
 275
 276        struct work_struct task;
 277        u32 pending_bh;
 278        bool bh_requested;
 279        bool bh_running;
 280
 281        int isr_overflow;
 282        bool irq_requested;     /* true if IRQ requested */
 283        bool irq_occurred;      /* for diagnostics use */
 284
 285        /* device configuration */
 286
 287        unsigned int bus_type;
 288        unsigned int irq_level;
 289        unsigned long irq_flags;
 290
 291        unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 292        u32 phys_reg_addr;
 293        bool reg_addr_requested;
 294
 295        MGSL_PARAMS params;       /* communications parameters */
 296        u32 idle_mode;
 297        u32 max_frame_size;       /* as set by device config */
 298
 299        unsigned int rbuf_fill_level;
 300        unsigned int rx_pio;
 301        unsigned int if_mode;
 302        unsigned int base_clock;
 303        unsigned int xsync;
 304        unsigned int xctrl;
 305
 306        /* device status */
 307
 308        bool rx_enabled;
 309        bool rx_restart;
 310
 311        bool tx_enabled;
 312        bool tx_active;
 313
 314        unsigned char signals;    /* serial signal states */
 315        int init_error;  /* initialization error */
 316
 317        unsigned char *tx_buf;
 318        int tx_count;
 319
 320        char *flag_buf;
 321        bool drop_rts_on_tx_done;
 322        struct  _input_signal_events    input_signal_events;
 323
 324        int dcd_chkcount;       /* check counts to prevent */
 325        int cts_chkcount;       /* too many IRQs if a signal */
 326        int dsr_chkcount;       /* is floating */
 327        int ri_chkcount;
 328
 329        char *bufs;             /* virtual address of DMA buffer lists */
 330        dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332        unsigned int rbuf_count;
 333        struct slgt_desc *rbufs;
 334        unsigned int rbuf_current;
 335        unsigned int rbuf_index;
 336        unsigned int rbuf_fill_index;
 337        unsigned short rbuf_fill_count;
 338
 339        unsigned int tbuf_count;
 340        struct slgt_desc *tbufs;
 341        unsigned int tbuf_current;
 342        unsigned int tbuf_start;
 343
 344        unsigned char *tmp_rbuf;
 345        unsigned int tmp_rbuf_count;
 346
 347        /* SPPP/Cisco HDLC device parts */
 348
 349        int netcount;
 350        spinlock_t netlock;
 351#if SYNCLINK_GENERIC_HDLC
 352        struct net_device *netdev;
 353#endif
 354
 355};
 356
 357static MGSL_PARAMS default_params = {
 358        .mode            = MGSL_MODE_HDLC,
 359        .loopback        = 0,
 360        .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 361        .encoding        = HDLC_ENCODING_NRZI_SPACE,
 362        .clock_speed     = 0,
 363        .addr_filter     = 0xff,
 364        .crc_type        = HDLC_CRC_16_CCITT,
 365        .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 366        .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 367        .data_rate       = 9600,
 368        .data_bits       = 8,
 369        .stop_bits       = 1,
 370        .parity          = ASYNC_PARITY_NONE
 371};
 372
 373
 374#define BH_RECEIVE  1
 375#define BH_TRANSMIT 2
 376#define BH_STATUS   4
 377#define IO_PIN_SHUTDOWN_LIMIT 100
 378
 379#define DMABUFSIZE 256
 380#define DESC_LIST_SIZE 4096
 381
 382#define MASK_PARITY  BIT1
 383#define MASK_FRAMING BIT0
 384#define MASK_BREAK   BIT14
 385#define MASK_OVERRUN BIT4
 386
 387#define GSR   0x00 /* global status */
 388#define JCR   0x04 /* JTAG control */
 389#define IODR  0x08 /* GPIO direction */
 390#define IOER  0x0c /* GPIO interrupt enable */
 391#define IOVR  0x10 /* GPIO value */
 392#define IOSR  0x14 /* GPIO interrupt status */
 393#define TDR   0x80 /* tx data */
 394#define RDR   0x80 /* rx data */
 395#define TCR   0x82 /* tx control */
 396#define TIR   0x84 /* tx idle */
 397#define TPR   0x85 /* tx preamble */
 398#define RCR   0x86 /* rx control */
 399#define VCR   0x88 /* V.24 control */
 400#define CCR   0x89 /* clock control */
 401#define BDR   0x8a /* baud divisor */
 402#define SCR   0x8c /* serial control */
 403#define SSR   0x8e /* serial status */
 404#define RDCSR 0x90 /* rx DMA control/status */
 405#define TDCSR 0x94 /* tx DMA control/status */
 406#define RDDAR 0x98 /* rx DMA descriptor address */
 407#define TDDAR 0x9c /* tx DMA descriptor address */
 408#define XSR   0x40 /* extended sync pattern */
 409#define XCR   0x44 /* extended control */
 410
 411#define RXIDLE      BIT14
 412#define RXBREAK     BIT14
 413#define IRQ_TXDATA  BIT13
 414#define IRQ_TXIDLE  BIT12
 415#define IRQ_TXUNDER BIT11 /* HDLC */
 416#define IRQ_RXDATA  BIT10
 417#define IRQ_RXIDLE  BIT9  /* HDLC */
 418#define IRQ_RXBREAK BIT9  /* async */
 419#define IRQ_RXOVER  BIT8
 420#define IRQ_DSR     BIT7
 421#define IRQ_CTS     BIT6
 422#define IRQ_DCD     BIT5
 423#define IRQ_RI      BIT4
 424#define IRQ_ALL     0x3ff0
 425#define IRQ_MASTER  BIT0
 426
 427#define slgt_irq_on(info, mask) \
 428        wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 429#define slgt_irq_off(info, mask) \
 430        wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 431
 432static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 433static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 434static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 435static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 436static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 437static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 438
 439static void  msc_set_vcr(struct slgt_info *info);
 440
 441static int  startup(struct slgt_info *info);
 442static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 443static void shutdown(struct slgt_info *info);
 444static void program_hw(struct slgt_info *info);
 445static void change_params(struct slgt_info *info);
 446
 447static int  register_test(struct slgt_info *info);
 448static int  irq_test(struct slgt_info *info);
 449static int  loopback_test(struct slgt_info *info);
 450static int  adapter_test(struct slgt_info *info);
 451
 452static void reset_adapter(struct slgt_info *info);
 453static void reset_port(struct slgt_info *info);
 454static void async_mode(struct slgt_info *info);
 455static void sync_mode(struct slgt_info *info);
 456
 457static void rx_stop(struct slgt_info *info);
 458static void rx_start(struct slgt_info *info);
 459static void reset_rbufs(struct slgt_info *info);
 460static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 461static void rdma_reset(struct slgt_info *info);
 462static bool rx_get_frame(struct slgt_info *info);
 463static bool rx_get_buf(struct slgt_info *info);
 464
 465static void tx_start(struct slgt_info *info);
 466static void tx_stop(struct slgt_info *info);
 467static void tx_set_idle(struct slgt_info *info);
 468static unsigned int free_tbuf_count(struct slgt_info *info);
 469static unsigned int tbuf_bytes(struct slgt_info *info);
 470static void reset_tbufs(struct slgt_info *info);
 471static void tdma_reset(struct slgt_info *info);
 472static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 473
 474static void get_signals(struct slgt_info *info);
 475static void set_signals(struct slgt_info *info);
 476static void enable_loopback(struct slgt_info *info);
 477static void set_rate(struct slgt_info *info, u32 data_rate);
 478
 479static int  bh_action(struct slgt_info *info);
 480static void bh_handler(struct work_struct *work);
 481static void bh_transmit(struct slgt_info *info);
 482static void isr_serial(struct slgt_info *info);
 483static void isr_rdma(struct slgt_info *info);
 484static void isr_txeom(struct slgt_info *info, unsigned short status);
 485static void isr_tdma(struct slgt_info *info);
 486
 487static int  alloc_dma_bufs(struct slgt_info *info);
 488static void free_dma_bufs(struct slgt_info *info);
 489static int  alloc_desc(struct slgt_info *info);
 490static void free_desc(struct slgt_info *info);
 491static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 493
 494static int  alloc_tmp_rbuf(struct slgt_info *info);
 495static void free_tmp_rbuf(struct slgt_info *info);
 496
 497static void tx_timeout(unsigned long context);
 498static void rx_timeout(unsigned long context);
 499
 500/*
 501 * ioctl handlers
 502 */
 503static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 504static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 506static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 507static int  set_txidle(struct slgt_info *info, int idle_mode);
 508static int  tx_enable(struct slgt_info *info, int enable);
 509static int  tx_abort(struct slgt_info *info);
 510static int  rx_enable(struct slgt_info *info, int enable);
 511static int  modem_input_wait(struct slgt_info *info,int arg);
 512static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 513static int  tiocmget(struct tty_struct *tty);
 514static int  tiocmset(struct tty_struct *tty,
 515                                unsigned int set, unsigned int clear);
 516static int set_break(struct tty_struct *tty, int break_state);
 517static int  get_interface(struct slgt_info *info, int __user *if_mode);
 518static int  set_interface(struct slgt_info *info, int if_mode);
 519static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 523static int  set_xsync(struct slgt_info *info, int if_mode);
 524static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 525static int  set_xctrl(struct slgt_info *info, int if_mode);
 526
 527/*
 528 * driver functions
 529 */
 530static void add_device(struct slgt_info *info);
 531static void device_init(int adapter_num, struct pci_dev *pdev);
 532static int  claim_resources(struct slgt_info *info);
 533static void release_resources(struct slgt_info *info);
 534
 535/*
 536 * DEBUG OUTPUT CODE
 537 */
 538#ifndef DBGINFO
 539#define DBGINFO(fmt)
 540#endif
 541#ifndef DBGERR
 542#define DBGERR(fmt)
 543#endif
 544#ifndef DBGBH
 545#define DBGBH(fmt)
 546#endif
 547#ifndef DBGISR
 548#define DBGISR(fmt)
 549#endif
 550
 551#ifdef DBGDATA
 552static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 553{
 554        int i;
 555        int linecount;
 556        printk("%s %s data:\n",info->device_name, label);
 557        while(count) {
 558                linecount = (count > 16) ? 16 : count;
 559                for(i=0; i < linecount; i++)
 560                        printk("%02X ",(unsigned char)data[i]);
 561                for(;i<17;i++)
 562                        printk("   ");
 563                for(i=0;i<linecount;i++) {
 564                        if (data[i]>=040 && data[i]<=0176)
 565                                printk("%c",data[i]);
 566                        else
 567                                printk(".");
 568                }
 569                printk("\n");
 570                data  += linecount;
 571                count -= linecount;
 572        }
 573}
 574#else
 575#define DBGDATA(info, buf, size, label)
 576#endif
 577
 578#ifdef DBGTBUF
 579static void dump_tbufs(struct slgt_info *info)
 580{
 581        int i;
 582        printk("tbuf_current=%d\n", info->tbuf_current);
 583        for (i=0 ; i < info->tbuf_count ; i++) {
 584                printk("%d: count=%04X status=%04X\n",
 585                        i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 586        }
 587}
 588#else
 589#define DBGTBUF(info)
 590#endif
 591
 592#ifdef DBGRBUF
 593static void dump_rbufs(struct slgt_info *info)
 594{
 595        int i;
 596        printk("rbuf_current=%d\n", info->rbuf_current);
 597        for (i=0 ; i < info->rbuf_count ; i++) {
 598                printk("%d: count=%04X status=%04X\n",
 599                        i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 600        }
 601}
 602#else
 603#define DBGRBUF(info)
 604#endif
 605
 606static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 607{
 608#ifdef SANITY_CHECK
 609        if (!info) {
 610                printk("null struct slgt_info for (%s) in %s\n", devname, name);
 611                return 1;
 612        }
 613        if (info->magic != MGSL_MAGIC) {
 614                printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 615                return 1;
 616        }
 617#else
 618        if (!info)
 619                return 1;
 620#endif
 621        return 0;
 622}
 623
 624/**
 625 * line discipline callback wrappers
 626 *
 627 * The wrappers maintain line discipline references
 628 * while calling into the line discipline.
 629 *
 630 * ldisc_receive_buf  - pass receive data to line discipline
 631 */
 632static void ldisc_receive_buf(struct tty_struct *tty,
 633                              const __u8 *data, char *flags, int count)
 634{
 635        struct tty_ldisc *ld;
 636        if (!tty)
 637                return;
 638        ld = tty_ldisc_ref(tty);
 639        if (ld) {
 640                if (ld->ops->receive_buf)
 641                        ld->ops->receive_buf(tty, data, flags, count);
 642                tty_ldisc_deref(ld);
 643        }
 644}
 645
 646/* tty callbacks */
 647
 648static int open(struct tty_struct *tty, struct file *filp)
 649{
 650        struct slgt_info *info;
 651        int retval, line;
 652        unsigned long flags;
 653
 654        line = tty->index;
 655        if (line >= slgt_device_count) {
 656                DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 657                return -ENODEV;
 658        }
 659
 660        info = slgt_device_list;
 661        while(info && info->line != line)
 662                info = info->next_device;
 663        if (sanity_check(info, tty->name, "open"))
 664                return -ENODEV;
 665        if (info->init_error) {
 666                DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 667                return -ENODEV;
 668        }
 669
 670        tty->driver_data = info;
 671        info->port.tty = tty;
 672
 673        DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 674
 675        mutex_lock(&info->port.mutex);
 676        info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 677
 678        spin_lock_irqsave(&info->netlock, flags);
 679        if (info->netcount) {
 680                retval = -EBUSY;
 681                spin_unlock_irqrestore(&info->netlock, flags);
 682                mutex_unlock(&info->port.mutex);
 683                goto cleanup;
 684        }
 685        info->port.count++;
 686        spin_unlock_irqrestore(&info->netlock, flags);
 687
 688        if (info->port.count == 1) {
 689                /* 1st open on this device, init hardware */
 690                retval = startup(info);
 691                if (retval < 0) {
 692                        mutex_unlock(&info->port.mutex);
 693                        goto cleanup;
 694                }
 695        }
 696        mutex_unlock(&info->port.mutex);
 697        retval = block_til_ready(tty, filp, info);
 698        if (retval) {
 699                DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 700                goto cleanup;
 701        }
 702
 703        retval = 0;
 704
 705cleanup:
 706        if (retval) {
 707                if (tty->count == 1)
 708                        info->port.tty = NULL; /* tty layer will release tty struct */
 709                if(info->port.count)
 710                        info->port.count--;
 711        }
 712
 713        DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 714        return retval;
 715}
 716
 717static void close(struct tty_struct *tty, struct file *filp)
 718{
 719        struct slgt_info *info = tty->driver_data;
 720
 721        if (sanity_check(info, tty->name, "close"))
 722                return;
 723        DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 724
 725        if (tty_port_close_start(&info->port, tty, filp) == 0)
 726                goto cleanup;
 727
 728        mutex_lock(&info->port.mutex);
 729        if (info->port.flags & ASYNC_INITIALIZED)
 730                wait_until_sent(tty, info->timeout);
 731        flush_buffer(tty);
 732        tty_ldisc_flush(tty);
 733
 734        shutdown(info);
 735        mutex_unlock(&info->port.mutex);
 736
 737        tty_port_close_end(&info->port, tty);
 738        info->port.tty = NULL;
 739cleanup:
 740        DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 741}
 742
 743static void hangup(struct tty_struct *tty)
 744{
 745        struct slgt_info *info = tty->driver_data;
 746        unsigned long flags;
 747
 748        if (sanity_check(info, tty->name, "hangup"))
 749                return;
 750        DBGINFO(("%s hangup\n", info->device_name));
 751
 752        flush_buffer(tty);
 753
 754        mutex_lock(&info->port.mutex);
 755        shutdown(info);
 756
 757        spin_lock_irqsave(&info->port.lock, flags);
 758        info->port.count = 0;
 759        info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 760        info->port.tty = NULL;
 761        spin_unlock_irqrestore(&info->port.lock, flags);
 762        mutex_unlock(&info->port.mutex);
 763
 764        wake_up_interruptible(&info->port.open_wait);
 765}
 766
 767static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 768{
 769        struct slgt_info *info = tty->driver_data;
 770        unsigned long flags;
 771
 772        DBGINFO(("%s set_termios\n", tty->driver->name));
 773
 774        change_params(info);
 775
 776        /* Handle transition to B0 status */
 777        if (old_termios->c_cflag & CBAUD &&
 778            !(tty->termios.c_cflag & CBAUD)) {
 779                info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 780                spin_lock_irqsave(&info->lock,flags);
 781                set_signals(info);
 782                spin_unlock_irqrestore(&info->lock,flags);
 783        }
 784
 785        /* Handle transition away from B0 status */
 786        if (!(old_termios->c_cflag & CBAUD) &&
 787            tty->termios.c_cflag & CBAUD) {
 788                info->signals |= SerialSignal_DTR;
 789                if (!(tty->termios.c_cflag & CRTSCTS) ||
 790                    !tty_throttled(tty)) {
 791                        info->signals |= SerialSignal_RTS;
 792                }
 793                spin_lock_irqsave(&info->lock,flags);
 794                set_signals(info);
 795                spin_unlock_irqrestore(&info->lock,flags);
 796        }
 797
 798        /* Handle turning off CRTSCTS */
 799        if (old_termios->c_cflag & CRTSCTS &&
 800            !(tty->termios.c_cflag & CRTSCTS)) {
 801                tty->hw_stopped = 0;
 802                tx_release(tty);
 803        }
 804}
 805
 806static void update_tx_timer(struct slgt_info *info)
 807{
 808        /*
 809         * use worst case speed of 1200bps to calculate transmit timeout
 810         * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 811         */
 812        if (info->params.mode == MGSL_MODE_HDLC) {
 813                int timeout  = (tbuf_bytes(info) * 7) + 1000;
 814                mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 815        }
 816}
 817
 818static int write(struct tty_struct *tty,
 819                 const unsigned char *buf, int count)
 820{
 821        int ret = 0;
 822        struct slgt_info *info = tty->driver_data;
 823        unsigned long flags;
 824
 825        if (sanity_check(info, tty->name, "write"))
 826                return -EIO;
 827
 828        DBGINFO(("%s write count=%d\n", info->device_name, count));
 829
 830        if (!info->tx_buf || (count > info->max_frame_size))
 831                return -EIO;
 832
 833        if (!count || tty->stopped || tty->hw_stopped)
 834                return 0;
 835
 836        spin_lock_irqsave(&info->lock, flags);
 837
 838        if (info->tx_count) {
 839                /* send accumulated data from send_char() */
 840                if (!tx_load(info, info->tx_buf, info->tx_count))
 841                        goto cleanup;
 842                info->tx_count = 0;
 843        }
 844
 845        if (tx_load(info, buf, count))
 846                ret = count;
 847
 848cleanup:
 849        spin_unlock_irqrestore(&info->lock, flags);
 850        DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 851        return ret;
 852}
 853
 854static int put_char(struct tty_struct *tty, unsigned char ch)
 855{
 856        struct slgt_info *info = tty->driver_data;
 857        unsigned long flags;
 858        int ret = 0;
 859
 860        if (sanity_check(info, tty->name, "put_char"))
 861                return 0;
 862        DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 863        if (!info->tx_buf)
 864                return 0;
 865        spin_lock_irqsave(&info->lock,flags);
 866        if (info->tx_count < info->max_frame_size) {
 867                info->tx_buf[info->tx_count++] = ch;
 868                ret = 1;
 869        }
 870        spin_unlock_irqrestore(&info->lock,flags);
 871        return ret;
 872}
 873
 874static void send_xchar(struct tty_struct *tty, char ch)
 875{
 876        struct slgt_info *info = tty->driver_data;
 877        unsigned long flags;
 878
 879        if (sanity_check(info, tty->name, "send_xchar"))
 880                return;
 881        DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 882        info->x_char = ch;
 883        if (ch) {
 884                spin_lock_irqsave(&info->lock,flags);
 885                if (!info->tx_enabled)
 886                        tx_start(info);
 887                spin_unlock_irqrestore(&info->lock,flags);
 888        }
 889}
 890
 891static void wait_until_sent(struct tty_struct *tty, int timeout)
 892{
 893        struct slgt_info *info = tty->driver_data;
 894        unsigned long orig_jiffies, char_time;
 895
 896        if (!info )
 897                return;
 898        if (sanity_check(info, tty->name, "wait_until_sent"))
 899                return;
 900        DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 901        if (!(info->port.flags & ASYNC_INITIALIZED))
 902                goto exit;
 903
 904        orig_jiffies = jiffies;
 905
 906        /* Set check interval to 1/5 of estimated time to
 907         * send a character, and make it at least 1. The check
 908         * interval should also be less than the timeout.
 909         * Note: use tight timings here to satisfy the NIST-PCTS.
 910         */
 911
 912        if (info->params.data_rate) {
 913                char_time = info->timeout/(32 * 5);
 914                if (!char_time)
 915                        char_time++;
 916        } else
 917                char_time = 1;
 918
 919        if (timeout)
 920                char_time = min_t(unsigned long, char_time, timeout);
 921
 922        while (info->tx_active) {
 923                msleep_interruptible(jiffies_to_msecs(char_time));
 924                if (signal_pending(current))
 925                        break;
 926                if (timeout && time_after(jiffies, orig_jiffies + timeout))
 927                        break;
 928        }
 929exit:
 930        DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 931}
 932
 933static int write_room(struct tty_struct *tty)
 934{
 935        struct slgt_info *info = tty->driver_data;
 936        int ret;
 937
 938        if (sanity_check(info, tty->name, "write_room"))
 939                return 0;
 940        ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 941        DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 942        return ret;
 943}
 944
 945static void flush_chars(struct tty_struct *tty)
 946{
 947        struct slgt_info *info = tty->driver_data;
 948        unsigned long flags;
 949
 950        if (sanity_check(info, tty->name, "flush_chars"))
 951                return;
 952        DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 953
 954        if (info->tx_count <= 0 || tty->stopped ||
 955            tty->hw_stopped || !info->tx_buf)
 956                return;
 957
 958        DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 959
 960        spin_lock_irqsave(&info->lock,flags);
 961        if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 962                info->tx_count = 0;
 963        spin_unlock_irqrestore(&info->lock,flags);
 964}
 965
 966static void flush_buffer(struct tty_struct *tty)
 967{
 968        struct slgt_info *info = tty->driver_data;
 969        unsigned long flags;
 970
 971        if (sanity_check(info, tty->name, "flush_buffer"))
 972                return;
 973        DBGINFO(("%s flush_buffer\n", info->device_name));
 974
 975        spin_lock_irqsave(&info->lock, flags);
 976        info->tx_count = 0;
 977        spin_unlock_irqrestore(&info->lock, flags);
 978
 979        tty_wakeup(tty);
 980}
 981
 982/*
 983 * throttle (stop) transmitter
 984 */
 985static void tx_hold(struct tty_struct *tty)
 986{
 987        struct slgt_info *info = tty->driver_data;
 988        unsigned long flags;
 989
 990        if (sanity_check(info, tty->name, "tx_hold"))
 991                return;
 992        DBGINFO(("%s tx_hold\n", info->device_name));
 993        spin_lock_irqsave(&info->lock,flags);
 994        if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 995                tx_stop(info);
 996        spin_unlock_irqrestore(&info->lock,flags);
 997}
 998
 999/*
1000 * release (start) transmitter

1001 */
1002static void tx_release(struct tty_struct *tty)
1003{
1004        struct slgt_info *info = tty->driver_data;
1005        unsigned long flags;
1006
1007        if (sanity_check(info, tty->name, "tx_release"))
1008                return;
1009        DBGINFO(("%s tx_release\n", info->device_name));
1010        spin_lock_irqsave(&info->lock, flags);
1011        if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1012                info->tx_count = 0;
1013        spin_unlock_irqrestore(&info->lock, flags);
1014}
1015
1016/*
1017 * Service an IOCTL request
1018 *
1019 * Arguments
1020 *
1021 *      tty     pointer to tty instance data
1022 *      cmd     IOCTL command code
1023 *      arg     command argument/context
1024 *
1025 * Return 0 if success, otherwise error code
1026 */
1027static int ioctl(struct tty_struct *tty,
1028                 unsigned int cmd, unsigned long arg)
1029{
1030        struct slgt_info *info = tty->driver_data;
1031        void __user *argp = (void __user *)arg;
1032        int ret;
1033
1034        if (sanity_check(info, tty->name, "ioctl"))
1035                return -ENODEV;
1036        DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1037
1038        if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1039            (cmd != TIOCMIWAIT)) {
1040                if (tty->flags & (1 << TTY_IO_ERROR))
1041                    return -EIO;
1042        }
1043
1044        switch (cmd) {
1045        case MGSL_IOCWAITEVENT:
1046                return wait_mgsl_event(info, argp);
1047        case TIOCMIWAIT:
1048                return modem_input_wait(info,(int)arg);
1049        case MGSL_IOCSGPIO:
1050                return set_gpio(info, argp);
1051        case MGSL_IOCGGPIO:
1052                return get_gpio(info, argp);
1053        case MGSL_IOCWAITGPIO:
1054                return wait_gpio(info, argp);
1055        case MGSL_IOCGXSYNC:
1056                return get_xsync(info, argp);
1057        case MGSL_IOCSXSYNC:
1058                return set_xsync(info, (int)arg);
1059        case MGSL_IOCGXCTRL:
1060                return get_xctrl(info, argp);
1061        case MGSL_IOCSXCTRL:
1062                return set_xctrl(info, (int)arg);
1063        }
1064        mutex_lock(&info->port.mutex);
1065        switch (cmd) {
1066        case MGSL_IOCGPARAMS:
1067                ret = get_params(info, argp);
1068                break;
1069        case MGSL_IOCSPARAMS:
1070                ret = set_params(info, argp);
1071                break;
1072        case MGSL_IOCGTXIDLE:
1073                ret = get_txidle(info, argp);
1074                break;
1075        case MGSL_IOCSTXIDLE:
1076                ret = set_txidle(info, (int)arg);
1077                break;
1078        case MGSL_IOCTXENABLE:
1079                ret = tx_enable(info, (int)arg);
1080                break;
1081        case MGSL_IOCRXENABLE:
1082                ret = rx_enable(info, (int)arg);
1083                break;
1084        case MGSL_IOCTXABORT:
1085                ret = tx_abort(info);
1086                break;
1087        case MGSL_IOCGSTATS:
1088                ret = get_stats(info, argp);
1089                break;
1090        case MGSL_IOCGIF:
1091                ret = get_interface(info, argp);
1092                break;
1093        case MGSL_IOCSIF:
1094                ret = set_interface(info,(int)arg);
1095                break;
1096        default:
1097                ret = -ENOIOCTLCMD;
1098        }
1099        mutex_unlock(&info->port.mutex);
1100        return ret;
1101}
1102
1103static int get_icount(struct tty_struct *tty,
1104                                struct serial_icounter_struct *icount)
1105
1106{
1107        struct slgt_info *info = tty->driver_data;
1108        struct mgsl_icount cnow;        /* kernel counter temps */
1109        unsigned long flags;
1110
1111        spin_lock_irqsave(&info->lock,flags);
1112        cnow = info->icount;
1113        spin_unlock_irqrestore(&info->lock,flags);
1114
1115        icount->cts = cnow.cts;
1116        icount->dsr = cnow.dsr;
1117        icount->rng = cnow.rng;
1118        icount->dcd = cnow.dcd;
1119        icount->rx = cnow.rx;
1120        icount->tx = cnow.tx;
1121        icount->frame = cnow.frame;
1122        icount->overrun = cnow.overrun;
1123        icount->parity = cnow.parity;
1124        icount->brk = cnow.brk;
1125        icount->buf_overrun = cnow.buf_overrun;
1126
1127        return 0;
1128}
1129
1130/*
1131 * support for 32 bit ioctl calls on 64 bit systems
1132 */
1133#ifdef CONFIG_COMPAT
1134static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1135{
1136        struct MGSL_PARAMS32 tmp_params;
1137
1138        DBGINFO(("%s get_params32\n", info->device_name));
1139        memset(&tmp_params, 0, sizeof(tmp_params));
1140        tmp_params.mode            = (compat_ulong_t)info->params.mode;
1141        tmp_params.loopback        = info->params.loopback;
1142        tmp_params.flags           = info->params.flags;
1143        tmp_params.encoding        = info->params.encoding;
1144        tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1145        tmp_params.addr_filter     = info->params.addr_filter;
1146        tmp_params.crc_type        = info->params.crc_type;
1147        tmp_params.preamble_length = info->params.preamble_length;
1148        tmp_params.preamble        = info->params.preamble;
1149        tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1150        tmp_params.data_bits       = info->params.data_bits;
1151        tmp_params.stop_bits       = info->params.stop_bits;
1152        tmp_params.parity          = info->params.parity;
1153        if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1154                return -EFAULT;
1155        return 0;
1156}
1157
1158static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1159{
1160        struct MGSL_PARAMS32 tmp_params;
1161
1162        DBGINFO(("%s set_params32\n", info->device_name));
1163        if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1164                return -EFAULT;
1165
1166        spin_lock(&info->lock);
1167        if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1168                info->base_clock = tmp_params.clock_speed;
1169        } else {
1170                info->params.mode            = tmp_params.mode;
1171                info->params.loopback        = tmp_params.loopback;
1172                info->params.flags           = tmp_params.flags;
1173                info->params.encoding        = tmp_params.encoding;
1174                info->params.clock_speed     = tmp_params.clock_speed;
1175                info->params.addr_filter     = tmp_params.addr_filter;
1176                info->params.crc_type        = tmp_params.crc_type;
1177                info->params.preamble_length = tmp_params.preamble_length;
1178                info->params.preamble        = tmp_params.preamble;
1179                info->params.data_rate       = tmp_params.data_rate;
1180                info->params.data_bits       = tmp_params.data_bits;
1181                info->params.stop_bits       = tmp_params.stop_bits;
1182                info->params.parity          = tmp_params.parity;
1183        }
1184        spin_unlock(&info->lock);
1185
1186        program_hw(info);
1187
1188        return 0;
1189}
1190
1191static long slgt_compat_ioctl(struct tty_struct *tty,
1192                         unsigned int cmd, unsigned long arg)
1193{
1194        struct slgt_info *info = tty->driver_data;
1195        int rc = -ENOIOCTLCMD;
1196
1197        if (sanity_check(info, tty->name, "compat_ioctl"))
1198                return -ENODEV;
1199        DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1200
1201        switch (cmd) {
1202
1203        case MGSL_IOCSPARAMS32:
1204                rc = set_params32(info, compat_ptr(arg));
1205                break;
1206
1207        case MGSL_IOCGPARAMS32:
1208                rc = get_params32(info, compat_ptr(arg));
1209                break;
1210
1211        case MGSL_IOCGPARAMS:
1212        case MGSL_IOCSPARAMS:
1213        case MGSL_IOCGTXIDLE:
1214        case MGSL_IOCGSTATS:
1215        case MGSL_IOCWAITEVENT:
1216        case MGSL_IOCGIF:
1217        case MGSL_IOCSGPIO:
1218        case MGSL_IOCGGPIO:
1219        case MGSL_IOCWAITGPIO:
1220        case MGSL_IOCGXSYNC:
1221        case MGSL_IOCGXCTRL:
1222        case MGSL_IOCSTXIDLE:
1223        case MGSL_IOCTXENABLE:
1224        case MGSL_IOCRXENABLE:
1225        case MGSL_IOCTXABORT:
1226        case TIOCMIWAIT:
1227        case MGSL_IOCSIF:
1228        case MGSL_IOCSXSYNC:
1229        case MGSL_IOCSXCTRL:
1230                rc = ioctl(tty, cmd, arg);
1231                break;
1232        }
1233
1234        DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1235        return rc;
1236}
1237#else
1238#define slgt_compat_ioctl NULL
1239#endif /* ifdef CONFIG_COMPAT */
1240
1241/*
1242 * proc fs support
1243 */
1244static inline void line_info(struct seq_file *m, struct slgt_info *info)
1245{
1246        char stat_buf[30];
1247        unsigned long flags;
1248
1249        seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1250                      info->device_name, info->phys_reg_addr,
1251                      info->irq_level, info->max_frame_size);
1252
1253        /* output current serial signal states */
1254        spin_lock_irqsave(&info->lock,flags);
1255        get_signals(info);
1256        spin_unlock_irqrestore(&info->lock,flags);
1257
1258        stat_buf[0] = 0;
1259        stat_buf[1] = 0;
1260        if (info->signals & SerialSignal_RTS)
1261                strcat(stat_buf, "|RTS");
1262        if (info->signals & SerialSignal_CTS)
1263                strcat(stat_buf, "|CTS");
1264        if (info->signals & SerialSignal_DTR)
1265                strcat(stat_buf, "|DTR");
1266        if (info->signals & SerialSignal_DSR)
1267                strcat(stat_buf, "|DSR");
1268        if (info->signals & SerialSignal_DCD)
1269                strcat(stat_buf, "|CD");
1270        if (info->signals & SerialSignal_RI)
1271                strcat(stat_buf, "|RI");
1272
1273        if (info->params.mode != MGSL_MODE_ASYNC) {
1274                seq_printf(m, "\tHDLC txok:%d rxok:%d",
1275                               info->icount.txok, info->icount.rxok);
1276                if (info->icount.txunder)
1277                        seq_printf(m, " txunder:%d", info->icount.txunder);
1278                if (info->icount.txabort)
1279                        seq_printf(m, " txabort:%d", info->icount.txabort);
1280                if (info->icount.rxshort)
1281                        seq_printf(m, " rxshort:%d", info->icount.rxshort);
1282                if (info->icount.rxlong)
1283                        seq_printf(m, " rxlong:%d", info->icount.rxlong);
1284                if (info->icount.rxover)
1285                        seq_printf(m, " rxover:%d", info->icount.rxover);
1286                if (info->icount.rxcrc)
1287                        seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1288        } else {
1289                seq_printf(m, "\tASYNC tx:%d rx:%d",
1290                               info->icount.tx, info->icount.rx);
1291                if (info->icount.frame)
1292                        seq_printf(m, " fe:%d", info->icount.frame);
1293                if (info->icount.parity)
1294                        seq_printf(m, " pe:%d", info->icount.parity);
1295                if (info->icount.brk)
1296                        seq_printf(m, " brk:%d", info->icount.brk);
1297                if (info->icount.overrun)
1298                        seq_printf(m, " oe:%d", info->icount.overrun);
1299        }
1300
1301        /* Append serial signal status to end */
1302        seq_printf(m, " %s\n", stat_buf+1);
1303
1304        seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1305                       info->tx_active,info->bh_requested,info->bh_running,
1306                       info->pending_bh);
1307}
1308
1309/* Called to print information about devices
1310 */
1311static int synclink_gt_proc_show(struct seq_file *m, void *v)
1312{
1313        struct slgt_info *info;
1314
1315        seq_puts(m, "synclink_gt driver\n");
1316
1317        info = slgt_device_list;
1318        while( info ) {
1319                line_info(m, info);
1320                info = info->next_device;
1321        }
1322        return 0;
1323}
1324
1325static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1326{
1327        return single_open(file, synclink_gt_proc_show, NULL);
1328}
1329
1330static const struct file_operations synclink_gt_proc_fops = {
1331        .owner          = THIS_MODULE,
1332        .open           = synclink_gt_proc_open,
1333        .read           = seq_read,
1334        .llseek         = seq_lseek,
1335        .release        = single_release,
1336};
1337
1338/*
1339 * return count of bytes in transmit buffer
1340 */
1341static int chars_in_buffer(struct tty_struct *tty)
1342{
1343        struct slgt_info *info = tty->driver_data;
1344        int count;
1345        if (sanity_check(info, tty->name, "chars_in_buffer"))
1346                return 0;
1347        count = tbuf_bytes(info);
1348        DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1349        return count;
1350}
1351
1352/*
1353 * signal remote device to throttle send data (our receive data)
1354 */
1355static void throttle(struct tty_struct * tty)
1356{
1357        struct slgt_info *info = tty->driver_data;
1358        unsigned long flags;
1359
1360        if (sanity_check(info, tty->name, "throttle"))
1361                return;
1362        DBGINFO(("%s throttle\n", info->device_name));
1363        if (I_IXOFF(tty))
1364                send_xchar(tty, STOP_CHAR(tty));
1365        if (tty->termios.c_cflag & CRTSCTS) {
1366                spin_lock_irqsave(&info->lock,flags);
1367                info->signals &= ~SerialSignal_RTS;
1368                set_signals(info);
1369                spin_unlock_irqrestore(&info->lock,flags);
1370        }
1371}
1372
1373/*
1374 * signal remote device to stop throttling send data (our receive data)
1375 */
1376static void unthrottle(struct tty_struct * tty)
1377{
1378        struct slgt_info *info = tty->driver_data;
1379        unsigned long flags;
1380
1381        if (sanity_check(info, tty->name, "unthrottle"))
1382                return;
1383        DBGINFO(("%s unthrottle\n", info->device_name));
1384        if (I_IXOFF(tty)) {
1385                if (info->x_char)
1386                        info->x_char = 0;
1387                else
1388                        send_xchar(tty, START_CHAR(tty));
1389        }
1390        if (tty->termios.c_cflag & CRTSCTS) {
1391                spin_lock_irqsave(&info->lock,flags);
1392                info->signals |= SerialSignal_RTS;
1393                set_signals(info);
1394                spin_unlock_irqrestore(&info->lock,flags);
1395        }
1396}
1397
1398/*
1399 * set or clear transmit break condition
1400 * break_state  -1=set break condition, 0=clear
1401 */
1402static int set_break(struct tty_struct *tty, int break_state)
1403{
1404        struct slgt_info *info = tty->driver_data;
1405        unsigned short value;
1406        unsigned long flags;
1407
1408        if (sanity_check(info, tty->name, "set_break"))
1409                return -EINVAL;
1410        DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1411
1412        spin_lock_irqsave(&info->lock,flags);
1413        value = rd_reg16(info, TCR);
1414        if (break_state == -1)
1415                value |= BIT6;
1416        else
1417                value &= ~BIT6;
1418        wr_reg16(info, TCR, value);
1419        spin_unlock_irqrestore(&info->lock,flags);
1420        return 0;
1421}
1422
1423#if SYNCLINK_GENERIC_HDLC
1424
1425/**
1426 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1427 * set encoding and frame check sequence (FCS) options
1428 *
1429 * dev       pointer to network device structure
1430 * encoding  serial encoding setting
1431 * parity    FCS setting
1432 *
1433 * returns 0 if success, otherwise error code
1434 */
1435static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1436                          unsigned short parity)
1437{
1438        struct slgt_info *info = dev_to_port(dev);
1439        unsigned char  new_encoding;
1440        unsigned short new_crctype;
1441
1442        /* return error if TTY interface open */
1443        if (info->port.count)
1444                return -EBUSY;
1445
1446        DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1447
1448        switch (encoding)
1449        {
1450        case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1451        case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1452        case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1453        case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1454        case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1455        default: return -EINVAL;
1456        }
1457
1458        switch (parity)
1459        {
1460        case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1461        case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1462        case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1463        default: return -EINVAL;
1464        }
1465
1466        info->params.encoding = new_encoding;
1467        info->params.crc_type = new_crctype;
1468
1469        /* if network interface up, reprogram hardware */
1470        if (info->netcount)
1471                program_hw(info);
1472
1473        return 0;
1474}
1475
1476/**
1477 * called by generic HDLC layer to send frame
1478 *
1479 * skb  socket buffer containing HDLC frame
1480 * dev  pointer to network device structure
1481 */
1482static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1483                                      struct net_device *dev)
1484{
1485        struct slgt_info *info = dev_to_port(dev);
1486        unsigned long flags;
1487
1488        DBGINFO(("%s hdlc_xmit\n", dev->name));
1489
1490        if (!skb->len)
1491                return NETDEV_TX_OK;
1492
1493        /* stop sending until this frame completes */
1494        netif_stop_queue(dev);
1495
1496        /* update network statistics */
1497        dev->stats.tx_packets++;
1498        dev->stats.tx_bytes += skb->len;
1499
1500        /* save start time for transmit timeout detection */
1501        netif_trans_update(dev);
1502
1503        spin_lock_irqsave(&info->lock, flags);
1504        tx_load(info, skb->data, skb->len);
1505        spin_unlock_irqrestore(&info->lock, flags);
1506
1507        /* done with socket buffer, so free it */
1508        dev_kfree_skb(skb);
1509
1510        return NETDEV_TX_OK;
1511}
1512
1513/**
1514 * called by network layer when interface enabled
1515 * claim resources and initialize hardware
1516 *
1517 * dev  pointer to network device structure
1518 *
1519 * returns 0 if success, otherwise error code
1520 */
1521static int hdlcdev_open(struct net_device *dev)
1522{
1523        struct slgt_info *info = dev_to_port(dev);
1524        int rc;
1525        unsigned long flags;
1526
1527        if (!try_module_get(THIS_MODULE))
1528                return -EBUSY;
1529
1530        DBGINFO(("%s hdlcdev_open\n", dev->name));
1531
1532        /* generic HDLC layer open processing */
1533        if ((rc = hdlc_open(dev)))
1534                return rc;
1535
1536        /* arbitrate between network and tty opens */
1537        spin_lock_irqsave(&info->netlock, flags);
1538        if (info->port.count != 0 || info->netcount != 0) {
1539                DBGINFO(("%s hdlc_open busy\n", dev->name));
1540                spin_unlock_irqrestore(&info->netlock, flags);
1541                return -EBUSY;
1542        }
1543        info->netcount=1;
1544        spin_unlock_irqrestore(&info->netlock, flags);
1545
1546        /* claim resources and init adapter */
1547        if ((rc = startup(info)) != 0) {
1548                spin_lock_irqsave(&info->netlock, flags);
1549                info->netcount=0;
1550                spin_unlock_irqrestore(&info->netlock, flags);
1551                return rc;
1552        }
1553
1554        /* assert RTS and DTR, apply hardware settings */
1555        info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1556        program_hw(info);
1557
1558        /* enable network layer transmit */
1559        netif_trans_update(dev);
1560        netif_start_queue(dev);
1561
1562        /* inform generic HDLC layer of current DCD status */
1563        spin_lock_irqsave(&info->lock, flags);
1564        get_signals(info);
1565        spin_unlock_irqrestore(&info->lock, flags);
1566        if (info->signals & SerialSignal_DCD)
1567                netif_carrier_on(dev);
1568        else
1569                netif_carrier_off(dev);
1570        return 0;
1571}
1572
1573/**
1574 * called by network layer when interface is disabled
1575 * shutdown hardware and release resources
1576 *
1577 * dev  pointer to network device structure
1578 *
1579 * returns 0 if success, otherwise error code
1580 */
1581static int hdlcdev_close(struct net_device *dev)
1582{
1583        struct slgt_info *info = dev_to_port(dev);
1584        unsigned long flags;
1585
1586        DBGINFO(("%s hdlcdev_close\n", dev->name));
1587
1588        netif_stop_queue(dev);
1589
1590        /* shutdown adapter and release resources */
1591        shutdown(info);
1592
1593        hdlc_close(dev);
1594
1595        spin_lock_irqsave(&info->netlock, flags);
1596        info->netcount=0;
1597        spin_unlock_irqrestore(&info->netlock, flags);
1598
1599        module_put(THIS_MODULE);
1600        return 0;
1601}
1602
1603/**
1604 * called by network layer to process IOCTL call to network device
1605 *
1606 * dev  pointer to network device structure
1607 * ifr  pointer to network interface request structure
1608 * cmd  IOCTL command code
1609 *
1610 * returns 0 if success, otherwise error code
1611 */
1612static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1613{
1614        const size_t size = sizeof(sync_serial_settings);
1615        sync_serial_settings new_line;
1616        sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1617        struct slgt_info *info = dev_to_port(dev);
1618        unsigned int flags;
1619
1620        DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1621
1622        /* return error if TTY interface open */
1623        if (info->port.count)
1624                return -EBUSY;
1625
1626        if (cmd != SIOCWANDEV)
1627                return hdlc_ioctl(dev, ifr, cmd);
1628
1629        memset(&new_line, 0, sizeof(new_line));
1630
1631        switch(ifr->ifr_settings.type) {
1632        case IF_GET_IFACE: /* return current sync_serial_settings */
1633
1634                ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1635                if (ifr->ifr_settings.size < size) {
1636                        ifr->ifr_settings.size = size; /* data size wanted */
1637                        return -ENOBUFS;
1638                }
1639
1640                flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1641                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1642                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1643                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1644
1645                switch (flags){
1646                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1647                case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1648                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1649                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1650                default: new_line.clock_type = CLOCK_DEFAULT;
1651                }
1652
1653                new_line.clock_rate = info->params.clock_speed;
1654                new_line.loopback   = info->params.loopback ? 1:0;
1655
1656                if (copy_to_user(line, &new_line, size))
1657                        return -EFAULT;
1658                return 0;
1659
1660        case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1661
1662                if(!capable(CAP_NET_ADMIN))
1663                        return -EPERM;
1664                if (copy_from_user(&new_line, line, size))
1665                        return -EFAULT;
1666
1667                switch (new_line.clock_type)
1668                {
1669                case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1670                case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1671                case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1672                case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1673                case CLOCK_DEFAULT:  flags = info->params.flags &
1674                                             (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1675                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1676                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1677                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1678                default: return -EINVAL;
1679                }
1680
1681                if (new_line.loopback != 0 && new_line.loopback != 1)
1682                        return -EINVAL;
1683
1684                info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1685                                        HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1686                                        HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1687                                        HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1688                info->params.flags |= flags;
1689
1690                info->params.loopback = new_line.loopback;
1691
1692                if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1693                        info->params.clock_speed = new_line.clock_rate;
1694                else
1695                        info->params.clock_speed = 0;
1696
1697                /* if network interface up, reprogram hardware */
1698                if (info->netcount)
1699                        program_hw(info);
1700                return 0;
1701
1702        default:
1703                return hdlc_ioctl(dev, ifr, cmd);
1704        }
1705}
1706
1707/**
1708 * called by network layer when transmit timeout is detected
1709 *
1710 * dev  pointer to network device structure
1711 */
1712static void hdlcdev_tx_timeout(struct net_device *dev)
1713{
1714        struct slgt_info *info = dev_to_port(dev);
1715        unsigned long flags;
1716
1717        DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1718
1719        dev->stats.tx_errors++;
1720        dev->stats.tx_aborted_errors++;
1721
1722        spin_lock_irqsave(&info->lock,flags);
1723        tx_stop(info);
1724        spin_unlock_irqrestore(&info->lock,flags);
1725
1726        netif_wake_queue(dev);
1727}
1728
1729/**
1730 * called by device driver when transmit completes
1731 * reenable network layer transmit if stopped
1732 *
1733 * info  pointer to device instance information
1734 */
1735static void hdlcdev_tx_done(struct slgt_info *info)
1736{
1737        if (netif_queue_stopped(info->netdev))
1738                netif_wake_queue(info->netdev);
1739}
1740
1741/**
1742 * called by device driver when frame received
1743 * pass frame to network layer
1744 *
1745 * info  pointer to device instance information
1746 * buf   pointer to buffer contianing frame data
1747 * size  count of data bytes in buf
1748 */
1749static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1750{
1751        struct sk_buff *skb = dev_alloc_skb(size);
1752        struct net_device *dev = info->netdev;
1753
1754        DBGINFO(("%s hdlcdev_rx\n", dev->name));
1755
1756        if (skb == NULL) {
1757                DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1758                dev->stats.rx_dropped++;
1759                return;
1760        }
1761
1762        memcpy(skb_put(skb, size), buf, size);
1763
1764        skb->protocol = hdlc_type_trans(skb, dev);
1765
1766        dev->stats.rx_packets++;
1767        dev->stats.rx_bytes += size;
1768
1769        netif_rx(skb);
1770}
1771
1772static const struct net_device_ops hdlcdev_ops = {
1773        .ndo_open       = hdlcdev_open,
1774        .ndo_stop       = hdlcdev_close,
1775        .ndo_change_mtu = hdlc_change_mtu,
1776        .ndo_start_xmit = hdlc_start_xmit,
1777        .ndo_do_ioctl   = hdlcdev_ioctl,
1778        .ndo_tx_timeout = hdlcdev_tx_timeout,
1779};
1780
1781/**
1782 * called by device driver when adding device instance
1783 * do generic HDLC initialization
1784 *
1785 * info  pointer to device instance information
1786 *
1787 * returns 0 if success, otherwise error code
1788 */
1789static int hdlcdev_init(struct slgt_info *info)
1790{
1791        int rc;
1792        struct net_device *dev;
1793        hdlc_device *hdlc;
1794
1795        /* allocate and initialize network and HDLC layer objects */
1796
1797        if (!(dev = alloc_hdlcdev(info))) {
1798                printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1799                return -ENOMEM;
1800        }
1801
1802        /* for network layer reporting purposes only */
1803        dev->mem_start = info->phys_reg_addr;
1804        dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1805        dev->irq       = info->irq_level;
1806
1807        /* network layer callbacks and settings */
1808        dev->netdev_ops     = &hdlcdev_ops;
1809        dev->watchdog_timeo = 10 * HZ;
1810        dev->tx_queue_len   = 50;
1811
1812        /* generic HDLC layer callbacks and settings */
1813        hdlc         = dev_to_hdlc(dev);
1814        hdlc->attach = hdlcdev_attach;
1815        hdlc->xmit   = hdlcdev_xmit;
1816
1817        /* register objects with HDLC layer */
1818        if ((rc = register_hdlc_device(dev))) {
1819                printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1820                free_netdev(dev);
1821                return rc;
1822        }
1823
1824        info->netdev = dev;
1825        return 0;
1826}
1827
1828/**
1829 * called by device driver when removing device instance
1830 * do generic HDLC cleanup
1831 *
1832 * info  pointer to device instance information
1833 */
1834static void hdlcdev_exit(struct slgt_info *info)
1835{
1836        unregister_hdlc_device(info->netdev);
1837        free_netdev(info->netdev);
1838        info->netdev = NULL;
1839}
1840
1841#endif /* ifdef CONFIG_HDLC */
1842
1843/*
1844 * get async data from rx DMA buffers
1845 */
1846static void rx_async(struct slgt_info *info)
1847{
1848        struct mgsl_icount *icount = &info->icount;
1849        unsigned int start, end;
1850        unsigned char *p;
1851        unsigned char status;
1852        struct slgt_desc *bufs = info->rbufs;
1853        int i, count;
1854        int chars = 0;
1855        int stat;
1856        unsigned char ch;
1857
1858        start = end = info->rbuf_current;
1859
1860        while(desc_complete(bufs[end])) {
1861                count = desc_count(bufs[end]) - info->rbuf_index;
1862                p     = bufs[end].buf + info->rbuf_index;
1863
1864                DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1865                DBGDATA(info, p, count, "rx");
1866
1867                for(i=0 ; i < count; i+=2, p+=2) {
1868                        ch = *p;
1869                        icount->rx++;
1870
1871                        stat = 0;
1872
1873                        if ((status = *(p+1) & (BIT1 + BIT0))) {
1874                                if (status & BIT1)
1875                                        icount->parity++;
1876                                else if (status & BIT0)
1877                                        icount->frame++;
1878                                /* discard char if tty control flags say so */
1879                                if (status & info->ignore_status_mask)
1880                                        continue;
1881                                if (status & BIT1)
1882                                        stat = TTY_PARITY;
1883                                else if (status & BIT0)
1884                                        stat = TTY_FRAME;
1885                        }
1886                        tty_insert_flip_char(&info->port, ch, stat);
1887                        chars++;
1888                }
1889
1890                if (i < count) {
1891                        /* receive buffer not completed */
1892                        info->rbuf_index += i;
1893                        mod_timer(&info->rx_timer, jiffies + 1);
1894                        break;
1895                }
1896
1897                info->rbuf_index = 0;
1898                free_rbufs(info, end, end);
1899
1900                if (++end == info->rbuf_count)
1901                        end = 0;
1902
1903                /* if entire list searched then no frame available */
1904                if (end == start)
1905                        break;
1906        }
1907
1908        if (chars)
1909                tty_flip_buffer_push(&info->port);
1910}
1911
1912/*
1913 * return next bottom half action to perform
1914 */
1915static int bh_action(struct slgt_info *info)
1916{
1917        unsigned long flags;
1918        int rc;
1919
1920        spin_lock_irqsave(&info->lock,flags);
1921
1922        if (info->pending_bh & BH_RECEIVE) {
1923                info->pending_bh &= ~BH_RECEIVE;
1924                rc = BH_RECEIVE;
1925        } else if (info->pending_bh & BH_TRANSMIT) {
1926                info->pending_bh &= ~BH_TRANSMIT;
1927                rc = BH_TRANSMIT;
1928        } else if (info->pending_bh & BH_STATUS) {
1929                info->pending_bh &= ~BH_STATUS;
1930                rc = BH_STATUS;
1931        } else {
1932                /* Mark BH routine as complete */
1933                info->bh_running = false;
1934                info->bh_requested = false;
1935                rc = 0;
1936        }
1937
1938        spin_unlock_irqrestore(&info->lock,flags);
1939
1940        return rc;
1941}
1942
1943/*
1944 * perform bottom half processing
1945 */
1946static void bh_handler(struct work_struct *work)
1947{
1948        struct slgt_info *info = container_of(work, struct slgt_info, task);
1949        int action;
1950
1951        info->bh_running = true;
1952
1953        while((action = bh_action(info))) {
1954                switch (action) {
1955                case BH_RECEIVE:
1956                        DBGBH(("%s bh receive\n", info->device_name));
1957                        switch(info->params.mode) {
1958                        case MGSL_MODE_ASYNC:
1959                                rx_async(info);
1960                                break;
1961                        case MGSL_MODE_HDLC:
1962                                while(rx_get_frame(info));
1963                                break;
1964                        case MGSL_MODE_RAW:
1965                        case MGSL_MODE_MONOSYNC:
1966                        case MGSL_MODE_BISYNC:
1967                        case MGSL_MODE_XSYNC:
1968                                while(rx_get_buf(info));
1969                                break;
1970                        }
1971                        /* restart receiver if rx DMA buffers exhausted */
1972                        if (info->rx_restart)
1973                                rx_start(info);
1974                        break;
1975                case BH_TRANSMIT:
1976                        bh_transmit(info);
1977                        break;
1978                case BH_STATUS:
1979                        DBGBH(("%s bh status\n", info->device_name));
1980                        info->ri_chkcount = 0;
1981                        info->dsr_chkcount = 0;
1982                        info->dcd_chkcount = 0;
1983                        info->cts_chkcount = 0;
1984                        break;
1985                default:
1986                        DBGBH(("%s unknown action\n", info->device_name));
1987                        break;
1988                }
1989        }
1990        DBGBH(("%s bh_handler exit\n", info->device_name));
1991}
1992
1993static void bh_transmit(struct slgt_info *info)
1994{
1995        struct tty_struct *tty = info->port.tty;
1996
1997        DBGBH(("%s bh_transmit\n", info->device_name));
1998        if (tty)
1999                tty_wakeup(tty);
2000}

2001
2002static void dsr_change(struct slgt_info *info, unsigned short status)
2003{
2004        if (status & BIT3) {
2005                info->signals |= SerialSignal_DSR;
2006                info->input_signal_events.dsr_up++;
2007        } else {
2008                info->signals &= ~SerialSignal_DSR;
2009                info->input_signal_events.dsr_down++;
2010        }
2011        DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2012        if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2013                slgt_irq_off(info, IRQ_DSR);
2014                return;
2015        }
2016        info->icount.dsr++;
2017        wake_up_interruptible(&info->status_event_wait_q);
2018        wake_up_interruptible(&info->event_wait_q);
2019        info->pending_bh |= BH_STATUS;
2020}
2021
2022static void cts_change(struct slgt_info *info, unsigned short status)
2023{
2024        if (status & BIT2) {
2025                info->signals |= SerialSignal_CTS;
2026                info->input_signal_events.cts_up++;
2027        } else {
2028                info->signals &= ~SerialSignal_CTS;
2029                info->input_signal_events.cts_down++;
2030        }
2031        DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2032        if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2033                slgt_irq_off(info, IRQ_CTS);
2034                return;
2035        }
2036        info->icount.cts++;
2037        wake_up_interruptible(&info->status_event_wait_q);
2038        wake_up_interruptible(&info->event_wait_q);
2039        info->pending_bh |= BH_STATUS;
2040
2041        if (tty_port_cts_enabled(&info->port)) {
2042                if (info->port.tty) {
2043                        if (info->port.tty->hw_stopped) {
2044                                if (info->signals & SerialSignal_CTS) {
2045                                        info->port.tty->hw_stopped = 0;
2046                                        info->pending_bh |= BH_TRANSMIT;
2047                                        return;
2048                                }
2049                        } else {
2050                                if (!(info->signals & SerialSignal_CTS))
2051                                        info->port.tty->hw_stopped = 1;
2052                        }
2053                }
2054        }
2055}
2056
2057static void dcd_change(struct slgt_info *info, unsigned short status)
2058{
2059        if (status & BIT1) {
2060                info->signals |= SerialSignal_DCD;
2061                info->input_signal_events.dcd_up++;
2062        } else {
2063                info->signals &= ~SerialSignal_DCD;
2064                info->input_signal_events.dcd_down++;
2065        }
2066        DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2067        if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2068                slgt_irq_off(info, IRQ_DCD);
2069                return;
2070        }
2071        info->icount.dcd++;
2072#if SYNCLINK_GENERIC_HDLC
2073        if (info->netcount) {
2074                if (info->signals & SerialSignal_DCD)
2075                        netif_carrier_on(info->netdev);
2076                else
2077                        netif_carrier_off(info->netdev);
2078        }
2079#endif
2080        wake_up_interruptible(&info->status_event_wait_q);
2081        wake_up_interruptible(&info->event_wait_q);
2082        info->pending_bh |= BH_STATUS;
2083
2084        if (info->port.flags & ASYNC_CHECK_CD) {
2085                if (info->signals & SerialSignal_DCD)
2086                        wake_up_interruptible(&info->port.open_wait);
2087                else {
2088                        if (info->port.tty)
2089                                tty_hangup(info->port.tty);
2090                }
2091        }
2092}
2093
2094static void ri_change(struct slgt_info *info, unsigned short status)
2095{
2096        if (status & BIT0) {
2097                info->signals |= SerialSignal_RI;
2098                info->input_signal_events.ri_up++;
2099        } else {
2100                info->signals &= ~SerialSignal_RI;
2101                info->input_signal_events.ri_down++;
2102        }
2103        DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2104        if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2105                slgt_irq_off(info, IRQ_RI);
2106                return;
2107        }
2108        info->icount.rng++;
2109        wake_up_interruptible(&info->status_event_wait_q);
2110        wake_up_interruptible(&info->event_wait_q);
2111        info->pending_bh |= BH_STATUS;
2112}
2113
2114static void isr_rxdata(struct slgt_info *info)
2115{
2116        unsigned int count = info->rbuf_fill_count;
2117        unsigned int i = info->rbuf_fill_index;
2118        unsigned short reg;
2119
2120        while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2121                reg = rd_reg16(info, RDR);
2122                DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2123                if (desc_complete(info->rbufs[i])) {
2124                        /* all buffers full */
2125                        rx_stop(info);
2126                        info->rx_restart = 1;
2127                        continue;
2128                }
2129                info->rbufs[i].buf[count++] = (unsigned char)reg;
2130                /* async mode saves status byte to buffer for each data byte */
2131                if (info->params.mode == MGSL_MODE_ASYNC)
2132                        info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2133                if (count == info->rbuf_fill_level || (reg & BIT10)) {
2134                        /* buffer full or end of frame */
2135                        set_desc_count(info->rbufs[i], count);
2136                        set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2137                        info->rbuf_fill_count = count = 0;
2138                        if (++i == info->rbuf_count)
2139                                i = 0;
2140                        info->pending_bh |= BH_RECEIVE;
2141                }
2142        }
2143
2144        info->rbuf_fill_index = i;
2145        info->rbuf_fill_count = count;
2146}
2147
2148static void isr_serial(struct slgt_info *info)
2149{
2150        unsigned short status = rd_reg16(info, SSR);
2151
2152        DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2153
2154        wr_reg16(info, SSR, status); /* clear pending */
2155
2156        info->irq_occurred = true;
2157
2158        if (info->params.mode == MGSL_MODE_ASYNC) {
2159                if (status & IRQ_TXIDLE) {
2160                        if (info->tx_active)
2161                                isr_txeom(info, status);
2162                }
2163                if (info->rx_pio && (status & IRQ_RXDATA))
2164                        isr_rxdata(info);
2165                if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2166                        info->icount.brk++;
2167                        /* process break detection if tty control allows */
2168                        if (info->port.tty) {
2169                                if (!(status & info->ignore_status_mask)) {
2170                                        if (info->read_status_mask & MASK_BREAK) {
2171                                                tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2172                                                if (info->port.flags & ASYNC_SAK)
2173                                                        do_SAK(info->port.tty);
2174                                        }
2175                                }
2176                        }
2177                }
2178        } else {
2179                if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2180                        isr_txeom(info, status);
2181                if (info->rx_pio && (status & IRQ_RXDATA))
2182                        isr_rxdata(info);
2183                if (status & IRQ_RXIDLE) {
2184                        if (status & RXIDLE)
2185                                info->icount.rxidle++;
2186                        else
2187                                info->icount.exithunt++;
2188                        wake_up_interruptible(&info->event_wait_q);
2189                }
2190
2191                if (status & IRQ_RXOVER)
2192                        rx_start(info);
2193        }
2194
2195        if (status & IRQ_DSR)
2196                dsr_change(info, status);
2197        if (status & IRQ_CTS)
2198                cts_change(info, status);
2199        if (status & IRQ_DCD)
2200                dcd_change(info, status);
2201        if (status & IRQ_RI)
2202                ri_change(info, status);
2203}
2204
2205static void isr_rdma(struct slgt_info *info)
2206{
2207        unsigned int status = rd_reg32(info, RDCSR);
2208
2209        DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2210
2211        /* RDCSR (rx DMA control/status)
2212         *
2213         * 31..07  reserved
2214         * 06      save status byte to DMA buffer
2215         * 05      error
2216         * 04      eol (end of list)
2217         * 03      eob (end of buffer)
2218         * 02      IRQ enable
2219         * 01      reset
2220         * 00      enable
2221         */
2222        wr_reg32(info, RDCSR, status);  /* clear pending */
2223
2224        if (status & (BIT5 + BIT4)) {
2225                DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2226                info->rx_restart = true;
2227        }
2228        info->pending_bh |= BH_RECEIVE;
2229}
2230
2231static void isr_tdma(struct slgt_info *info)
2232{
2233        unsigned int status = rd_reg32(info, TDCSR);
2234
2235        DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2236
2237        /* TDCSR (tx DMA control/status)
2238         *
2239         * 31..06  reserved
2240         * 05      error
2241         * 04      eol (end of list)
2242         * 03      eob (end of buffer)
2243         * 02      IRQ enable
2244         * 01      reset
2245         * 00      enable
2246         */
2247        wr_reg32(info, TDCSR, status);  /* clear pending */
2248
2249        if (status & (BIT5 + BIT4 + BIT3)) {
2250                // another transmit buffer has completed
2251                // run bottom half to get more send data from user
2252                info->pending_bh |= BH_TRANSMIT;
2253        }
2254}
2255
2256/*
2257 * return true if there are unsent tx DMA buffers, otherwise false
2258 *
2259 * if there are unsent buffers then info->tbuf_start
2260 * is set to index of first unsent buffer
2261 */
2262static bool unsent_tbufs(struct slgt_info *info)
2263{
2264        unsigned int i = info->tbuf_current;
2265        bool rc = false;
2266
2267        /*
2268         * search backwards from last loaded buffer (precedes tbuf_current)
2269         * for first unsent buffer (desc_count > 0)
2270         */
2271
2272        do {
2273                if (i)
2274                        i--;
2275                else
2276                        i = info->tbuf_count - 1;
2277                if (!desc_count(info->tbufs[i]))
2278                        break;
2279                info->tbuf_start = i;
2280                rc = true;
2281        } while (i != info->tbuf_current);
2282
2283        return rc;
2284}
2285
2286static void isr_txeom(struct slgt_info *info, unsigned short status)
2287{
2288        DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2289
2290        slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2291        tdma_reset(info);
2292        if (status & IRQ_TXUNDER) {
2293                unsigned short val = rd_reg16(info, TCR);
2294                wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2295                wr_reg16(info, TCR, val); /* clear reset bit */
2296        }
2297
2298        if (info->tx_active) {
2299                if (info->params.mode != MGSL_MODE_ASYNC) {
2300                        if (status & IRQ_TXUNDER)
2301                                info->icount.txunder++;
2302                        else if (status & IRQ_TXIDLE)
2303                                info->icount.txok++;
2304                }
2305
2306                if (unsent_tbufs(info)) {
2307                        tx_start(info);
2308                        update_tx_timer(info);
2309                        return;
2310                }
2311                info->tx_active = false;
2312
2313                del_timer(&info->tx_timer);
2314
2315                if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2316                        info->signals &= ~SerialSignal_RTS;
2317                        info->drop_rts_on_tx_done = false;
2318                        set_signals(info);
2319                }
2320
2321#if SYNCLINK_GENERIC_HDLC
2322                if (info->netcount)
2323                        hdlcdev_tx_done(info);
2324                else
2325#endif
2326                {
2327                        if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2328                                tx_stop(info);
2329                                return;
2330                        }
2331                        info->pending_bh |= BH_TRANSMIT;
2332                }
2333        }
2334}
2335
2336static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2337{
2338        struct cond_wait *w, *prev;
2339
2340        /* wake processes waiting for specific transitions */
2341        for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2342                if (w->data & changed) {
2343                        w->data = state;
2344                        wake_up_interruptible(&w->q);
2345                        if (prev != NULL)
2346                                prev->next = w->next;
2347                        else
2348                                info->gpio_wait_q = w->next;
2349                } else
2350                        prev = w;
2351        }
2352}
2353
2354/* interrupt service routine
2355 *
2356 *      irq     interrupt number
2357 *      dev_id  device ID supplied during interrupt registration
2358 */
2359static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2360{
2361        struct slgt_info *info = dev_id;
2362        unsigned int gsr;
2363        unsigned int i;
2364
2365        DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2366
2367        while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2368                DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2369                info->irq_occurred = true;
2370                for(i=0; i < info->port_count ; i++) {
2371                        if (info->port_array[i] == NULL)
2372                                continue;
2373                        spin_lock(&info->port_array[i]->lock);
2374                        if (gsr & (BIT8 << i))
2375                                isr_serial(info->port_array[i]);
2376                        if (gsr & (BIT16 << (i*2)))
2377                                isr_rdma(info->port_array[i]);
2378                        if (gsr & (BIT17 << (i*2)))
2379                                isr_tdma(info->port_array[i]);
2380                        spin_unlock(&info->port_array[i]->lock);
2381                }
2382        }
2383
2384        if (info->gpio_present) {
2385                unsigned int state;
2386                unsigned int changed;
2387                spin_lock(&info->lock);
2388                while ((changed = rd_reg32(info, IOSR)) != 0) {
2389                        DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2390                        /* read latched state of GPIO signals */
2391                        state = rd_reg32(info, IOVR);
2392                        /* clear pending GPIO interrupt bits */
2393                        wr_reg32(info, IOSR, changed);
2394                        for (i=0 ; i < info->port_count ; i++) {
2395                                if (info->port_array[i] != NULL)
2396                                        isr_gpio(info->port_array[i], changed, state);
2397                        }
2398                }
2399                spin_unlock(&info->lock);
2400        }
2401
2402        for(i=0; i < info->port_count ; i++) {
2403                struct slgt_info *port = info->port_array[i];
2404                if (port == NULL)
2405                        continue;
2406                spin_lock(&port->lock);
2407                if ((port->port.count || port->netcount) &&
2408                    port->pending_bh && !port->bh_running &&
2409                    !port->bh_requested) {
2410                        DBGISR(("%s bh queued\n", port->device_name));
2411                        schedule_work(&port->task);
2412                        port->bh_requested = true;
2413                }
2414                spin_unlock(&port->lock);
2415        }
2416
2417        DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2418        return IRQ_HANDLED;
2419}
2420
2421static int startup(struct slgt_info *info)
2422{
2423        DBGINFO(("%s startup\n", info->device_name));
2424
2425        if (info->port.flags & ASYNC_INITIALIZED)
2426                return 0;
2427
2428        if (!info->tx_buf) {
2429                info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2430                if (!info->tx_buf) {
2431                        DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2432                        return -ENOMEM;
2433                }
2434        }
2435
2436        info->pending_bh = 0;
2437
2438        memset(&info->icount, 0, sizeof(info->icount));
2439
2440        /* program hardware for current parameters */
2441        change_params(info);
2442
2443        if (info->port.tty)
2444                clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2445
2446        info->port.flags |= ASYNC_INITIALIZED;
2447
2448        return 0;
2449}
2450
2451/*
2452 *  called by close() and hangup() to shutdown hardware
2453 */
2454static void shutdown(struct slgt_info *info)
2455{
2456        unsigned long flags;
2457
2458        if (!(info->port.flags & ASYNC_INITIALIZED))
2459                return;
2460
2461        DBGINFO(("%s shutdown\n", info->device_name));
2462
2463        /* clear status wait queue because status changes */
2464        /* can't happen after shutting down the hardware */
2465        wake_up_interruptible(&info->status_event_wait_q);
2466        wake_up_interruptible(&info->event_wait_q);
2467
2468        del_timer_sync(&info->tx_timer);
2469        del_timer_sync(&info->rx_timer);
2470
2471        kfree(info->tx_buf);
2472        info->tx_buf = NULL;
2473
2474        spin_lock_irqsave(&info->lock,flags);
2475
2476        tx_stop(info);
2477        rx_stop(info);
2478
2479        slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2480
2481        if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2482                info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2483                set_signals(info);
2484        }
2485
2486        flush_cond_wait(&info->gpio_wait_q);
2487
2488        spin_unlock_irqrestore(&info->lock,flags);
2489
2490        if (info->port.tty)
2491                set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2492
2493        info->port.flags &= ~ASYNC_INITIALIZED;
2494}
2495
2496static void program_hw(struct slgt_info *info)
2497{
2498        unsigned long flags;
2499
2500        spin_lock_irqsave(&info->lock,flags);
2501
2502        rx_stop(info);
2503        tx_stop(info);
2504
2505        if (info->params.mode != MGSL_MODE_ASYNC ||
2506            info->netcount)
2507                sync_mode(info);
2508        else
2509                async_mode(info);
2510
2511        set_signals(info);
2512
2513        info->dcd_chkcount = 0;
2514        info->cts_chkcount = 0;
2515        info->ri_chkcount = 0;
2516        info->dsr_chkcount = 0;
2517
2518        slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2519        get_signals(info);
2520
2521        if (info->netcount ||
2522            (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2523                rx_start(info);
2524
2525        spin_unlock_irqrestore(&info->lock,flags);
2526}
2527
2528/*
2529 * reconfigure adapter based on new parameters
2530 */
2531static void change_params(struct slgt_info *info)
2532{
2533        unsigned cflag;
2534        int bits_per_char;
2535
2536        if (!info->port.tty)
2537                return;
2538        DBGINFO(("%s change_params\n", info->device_name));
2539
2540        cflag = info->port.tty->termios.c_cflag;
2541
2542        /* if B0 rate (hangup) specified then negate RTS and DTR */
2543        /* otherwise assert RTS and DTR */
2544        if (cflag & CBAUD)
2545                info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2546        else
2547                info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2548
2549        /* byte size and parity */
2550
2551        switch (cflag & CSIZE) {
2552        case CS5: info->params.data_bits = 5; break;
2553        case CS6: info->params.data_bits = 6; break;
2554        case CS7: info->params.data_bits = 7; break;
2555        case CS8: info->params.data_bits = 8; break;
2556        default:  info->params.data_bits = 7; break;
2557        }
2558
2559        info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2560
2561        if (cflag & PARENB)
2562                info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2563        else
2564                info->params.parity = ASYNC_PARITY_NONE;
2565
2566        /* calculate number of jiffies to transmit a full
2567         * FIFO (32 bytes) at specified data rate
2568         */
2569        bits_per_char = info->params.data_bits +
2570                        info->params.stop_bits + 1;
2571
2572        info->params.data_rate = tty_get_baud_rate(info->port.tty);
2573
2574        if (info->params.data_rate) {
2575                info->timeout = (32*HZ*bits_per_char) /
2576                                info->params.data_rate;
2577        }
2578        info->timeout += HZ/50;         /* Add .02 seconds of slop */
2579
2580        if (cflag & CRTSCTS)
2581                info->port.flags |= ASYNC_CTS_FLOW;
2582        else
2583                info->port.flags &= ~ASYNC_CTS_FLOW;
2584
2585        if (cflag & CLOCAL)
2586                info->port.flags &= ~ASYNC_CHECK_CD;
2587        else
2588                info->port.flags |= ASYNC_CHECK_CD;
2589
2590        /* process tty input control flags */
2591
2592        info->read_status_mask = IRQ_RXOVER;
2593        if (I_INPCK(info->port.tty))
2594                info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2595        if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2596                info->read_status_mask |= MASK_BREAK;
2597        if (I_IGNPAR(info->port.tty))
2598                info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2599        if (I_IGNBRK(info->port.tty)) {
2600                info->ignore_status_mask |= MASK_BREAK;
2601                /* If ignoring parity and break indicators, ignore
2602                 * overruns too.  (For real raw support).
2603                 */
2604                if (I_IGNPAR(info->port.tty))
2605                        info->ignore_status_mask |= MASK_OVERRUN;
2606        }
2607
2608        program_hw(info);
2609}
2610
2611static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2612{
2613        DBGINFO(("%s get_stats\n",  info->device_name));
2614        if (!user_icount) {
2615                memset(&info->icount, 0, sizeof(info->icount));
2616        } else {
2617                if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2618                        return -EFAULT;
2619        }
2620        return 0;
2621}
2622
2623static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2624{
2625        DBGINFO(("%s get_params\n", info->device_name));
2626        if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2627                return -EFAULT;
2628        return 0;
2629}
2630
2631static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2632{
2633        unsigned long flags;
2634        MGSL_PARAMS tmp_params;
2635
2636        DBGINFO(("%s set_params\n", info->device_name));
2637        if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2638                return -EFAULT;
2639
2640        spin_lock_irqsave(&info->lock, flags);
2641        if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2642                info->base_clock = tmp_params.clock_speed;
2643        else
2644                memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2645        spin_unlock_irqrestore(&info->lock, flags);
2646
2647        program_hw(info);
2648
2649        return 0;
2650}
2651
2652static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2653{
2654        DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2655        if (put_user(info->idle_mode, idle_mode))
2656                return -EFAULT;
2657        return 0;
2658}
2659
2660static int set_txidle(struct slgt_info *info, int idle_mode)
2661{
2662        unsigned long flags;
2663        DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2664        spin_lock_irqsave(&info->lock,flags);
2665        info->idle_mode = idle_mode;
2666        if (info->params.mode != MGSL_MODE_ASYNC)
2667                tx_set_idle(info);
2668        spin_unlock_irqrestore(&info->lock,flags);
2669        return 0;
2670}
2671
2672static int tx_enable(struct slgt_info *info, int enable)
2673{
2674        unsigned long flags;
2675        DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2676        spin_lock_irqsave(&info->lock,flags);
2677        if (enable) {
2678                if (!info->tx_enabled)
2679                        tx_start(info);
2680        } else {
2681                if (info->tx_enabled)
2682                        tx_stop(info);
2683        }
2684        spin_unlock_irqrestore(&info->lock,flags);
2685        return 0;
2686}
2687
2688/*
2689 * abort transmit HDLC frame
2690 */
2691static int tx_abort(struct slgt_info *info)
2692{
2693        unsigned long flags;
2694        DBGINFO(("%s tx_abort\n", info->device_name));
2695        spin_lock_irqsave(&info->lock,flags);
2696        tdma_reset(info);
2697        spin_unlock_irqrestore(&info->lock,flags);
2698        return 0;
2699}
2700
2701static int rx_enable(struct slgt_info *info, int enable)
2702{
2703        unsigned long flags;
2704        unsigned int rbuf_fill_level;
2705        DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2706        spin_lock_irqsave(&info->lock,flags);
2707        /*
2708         * enable[31..16] = receive DMA buffer fill level
2709         * 0 = noop (leave fill level unchanged)
2710         * fill level must be multiple of 4 and <= buffer size
2711         */
2712        rbuf_fill_level = ((unsigned int)enable) >> 16;
2713        if (rbuf_fill_level) {
2714                if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2715                        spin_unlock_irqrestore(&info->lock, flags);
2716                        return -EINVAL;
2717                }
2718                info->rbuf_fill_level = rbuf_fill_level;
2719                if (rbuf_fill_level < 128)
2720                        info->rx_pio = 1; /* PIO mode */
2721                else
2722                        info->rx_pio = 0; /* DMA mode */
2723                rx_stop(info); /* restart receiver to use new fill level */
2724        }
2725
2726        /*
2727         * enable[1..0] = receiver enable command
2728         * 0 = disable
2729         * 1 = enable
2730         * 2 = enable or force hunt mode if already enabled
2731         */
2732        enable &= 3;
2733        if (enable) {
2734                if (!info->rx_enabled)
2735                        rx_start(info);
2736                else if (enable == 2) {
2737                        /* force hunt mode (write 1 to RCR[3]) */
2738                        wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2739                }
2740        } else {
2741                if (info->rx_enabled)
2742                        rx_stop(info);
2743        }
2744        spin_unlock_irqrestore(&info->lock,flags);
2745        return 0;
2746}
2747
2748/*
2749 *  wait for specified event to occur
2750 */
2751static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2752{
2753        unsigned long flags;
2754        int s;
2755        int rc=0;
2756        struct mgsl_icount cprev, cnow;
2757        int events;
2758        int mask;
2759        struct  _input_signal_events oldsigs, newsigs;
2760        DECLARE_WAITQUEUE(wait, current);
2761
2762        if (get_user(mask, mask_ptr))
2763                return -EFAULT;
2764
2765        DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2766
2767        spin_lock_irqsave(&info->lock,flags);
2768
2769        /* return immediately if state matches requested events */
2770        get_signals(info);
2771        s = info->signals;
2772
2773        events = mask &
2774                ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2775                  ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2776                  ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2777                  ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2778        if (events) {
2779                spin_unlock_irqrestore(&info->lock,flags);
2780                goto exit;
2781        }
2782
2783        /* save current irq counts */
2784        cprev = info->icount;
2785        oldsigs = info->input_signal_events;
2786
2787        /* enable hunt and idle irqs if needed */
2788        if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2789                unsigned short val = rd_reg16(info, SCR);
2790                if (!(val & IRQ_RXIDLE))
2791                        wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2792        }
2793
2794        set_current_state(TASK_INTERRUPTIBLE);
2795        add_wait_queue(&info->event_wait_q, &wait);
2796
2797        spin_unlock_irqrestore(&info->lock,flags);
2798
2799        for(;;) {
2800                schedule();
2801                if (signal_pending(current)) {
2802                        rc = -ERESTARTSYS;
2803                        break;
2804                }
2805
2806                /* get current irq counts */
2807                spin_lock_irqsave(&info->lock,flags);
2808                cnow = info->icount;
2809                newsigs = info->input_signal_events;
2810                set_current_state(TASK_INTERRUPTIBLE);
2811                spin_unlock_irqrestore(&info->lock,flags);
2812
2813                /* if no change, wait aborted for some reason */
2814                if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2815                    newsigs.dsr_down == oldsigs.dsr_down &&
2816                    newsigs.dcd_up   == oldsigs.dcd_up   &&
2817                    newsigs.dcd_down == oldsigs.dcd_down &&
2818                    newsigs.cts_up   == oldsigs.cts_up   &&
2819                    newsigs.cts_down == oldsigs.cts_down &&
2820                    newsigs.ri_up    == oldsigs.ri_up    &&
2821                    newsigs.ri_down  == oldsigs.ri_down  &&
2822                    cnow.exithunt    == cprev.exithunt   &&
2823                    cnow.rxidle      == cprev.rxidle) {
2824                        rc = -EIO;
2825                        break;
2826                }
2827
2828                events = mask &
2829                        ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2830                          (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2831                          (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2832                          (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2833                          (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2834                          (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2835                          (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2836                          (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2837                          (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2838                          (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2839                if (events)
2840                        break;
2841
2842                cprev = cnow;
2843                oldsigs = newsigs;
2844        }
2845
2846        remove_wait_queue(&info->event_wait_q, &wait);
2847        set_current_state(TASK_RUNNING);
2848
2849
2850        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2851                spin_lock_irqsave(&info->lock,flags);
2852                if (!waitqueue_active(&info->event_wait_q)) {
2853                        /* disable enable exit hunt mode/idle rcvd IRQs */
2854                        wr_reg16(info, SCR,
2855                                (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2856                }
2857                spin_unlock_irqrestore(&info->lock,flags);
2858        }
2859exit:
2860        if (rc == 0)
2861                rc = put_user(events, mask_ptr);
2862        return rc;
2863}
2864
2865static int get_interface(struct slgt_info *info, int __user *if_mode)
2866{
2867        DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2868        if (put_user(info->if_mode, if_mode))
2869                return -EFAULT;
2870        return 0;
2871}
2872
2873static int set_interface(struct slgt_info *info, int if_mode)
2874{
2875        unsigned long flags;
2876        unsigned short val;
2877
2878        DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2879        spin_lock_irqsave(&info->lock,flags);
2880        info->if_mode = if_mode;
2881
2882        msc_set_vcr(info);
2883
2884        /* TCR (tx control) 07  1=RTS driver control */
2885        val = rd_reg16(info, TCR);
2886        if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2887                val |= BIT7;
2888        else
2889                val &= ~BIT7;
2890        wr_reg16(info, TCR, val);
2891
2892        spin_unlock_irqrestore(&info->lock,flags);
2893        return 0;
2894}
2895
2896static int get_xsync(struct slgt_info *info, int __user *xsync)
2897{
2898        DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2899        if (put_user(info->xsync, xsync))
2900                return -EFAULT;
2901        return 0;
2902}
2903
2904/*
2905 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2906 *
2907 * sync pattern is contained in least significant bytes of value
2908 * most significant byte of sync pattern is oldest (1st sent/detected)
2909 */
2910static int set_xsync(struct slgt_info *info, int xsync)
2911{
2912        unsigned long flags;
2913
2914        DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2915        spin_lock_irqsave(&info->lock, flags);
2916        info->xsync = xsync;
2917        wr_reg32(info, XSR, xsync);
2918        spin_unlock_irqrestore(&info->lock, flags);
2919        return 0;
2920}
2921
2922static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2923{
2924        DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2925        if (put_user(info->xctrl, xctrl))
2926                return -EFAULT;
2927        return 0;
2928}
2929
2930/*
2931 * set extended control options
2932 *
2933 * xctrl[31:19] reserved, must be zero
2934 * xctrl[18:17] extended sync pattern length in bytes
2935 *              00 = 1 byte  in xsr[7:0]
2936 *              01 = 2 bytes in xsr[15:0]
2937 *              10 = 3 bytes in xsr[23:0]
2938 *              11 = 4 bytes in xsr[31:0]
2939 * xctrl[16]    1 = enable terminal count, 0=disabled
2940 * xctrl[15:0]  receive terminal count for fixed length packets
2941 *              value is count minus one (0 = 1 byte packet)
2942 *              when terminal count is reached, receiver
2943 *              automatically returns to hunt mode and receive
2944 *              FIFO contents are flushed to DMA buffers with
2945 *              end of frame (EOF) status
2946 */
2947static int set_xctrl(struct slgt_info *info, int xctrl)
2948{
2949        unsigned long flags;
2950
2951        DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2952        spin_lock_irqsave(&info->lock, flags);
2953        info->xctrl = xctrl;
2954        wr_reg32(info, XCR, xctrl);
2955        spin_unlock_irqrestore(&info->lock, flags);
2956        return 0;
2957}
2958
2959/*
2960 * set general purpose IO pin state and direction
2961 *
2962 * user_gpio fields:
2963 * state   each bit indicates a pin state
2964 * smask   set bit indicates pin state to set
2965 * dir     each bit indicates a pin direction (0=input, 1=output)
2966 * dmask   set bit indicates pin direction to set
2967 */
2968static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2969{
2970        unsigned long flags;
2971        struct gpio_desc gpio;
2972        __u32 data;
2973
2974        if (!info->gpio_present)
2975                return -EINVAL;
2976        if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2977                return -EFAULT;
2978        DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2979                 info->device_name, gpio.state, gpio.smask,
2980                 gpio.dir, gpio.dmask));
2981
2982        spin_lock_irqsave(&info->port_array[0]->lock, flags);
2983        if (gpio.dmask) {
2984                data = rd_reg32(info, IODR);
2985                data |= gpio.dmask & gpio.dir;
2986                data &= ~(gpio.dmask & ~gpio.dir);
2987                wr_reg32(info, IODR, data);
2988        }
2989        if (gpio.smask) {
2990                data = rd_reg32(info, IOVR);
2991                data |= gpio.smask & gpio.state;
2992                data &= ~(gpio.smask & ~gpio.state);
2993                wr_reg32(info, IOVR, data);
2994        }
2995        spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2996
2997        return 0;
2998}
2999
3000/*

3001 * get general purpose IO pin state and direction
3002 */
3003static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3004{
3005        struct gpio_desc gpio;
3006        if (!info->gpio_present)
3007                return -EINVAL;
3008        gpio.state = rd_reg32(info, IOVR);
3009        gpio.smask = 0xffffffff;
3010        gpio.dir   = rd_reg32(info, IODR);
3011        gpio.dmask = 0xffffffff;
3012        if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3013                return -EFAULT;
3014        DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3015                 info->device_name, gpio.state, gpio.dir));
3016        return 0;
3017}
3018
3019/*
3020 * conditional wait facility
3021 */
3022static void init_cond_wait(struct cond_wait *w, unsigned int data)
3023{
3024        init_waitqueue_head(&w->q);
3025        init_waitqueue_entry(&w->wait, current);
3026        w->data = data;
3027}
3028
3029static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3030{
3031        set_current_state(TASK_INTERRUPTIBLE);
3032        add_wait_queue(&w->q, &w->wait);
3033        w->next = *head;
3034        *head = w;
3035}
3036
3037static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3038{
3039        struct cond_wait *w, *prev;
3040        remove_wait_queue(&cw->q, &cw->wait);
3041        set_current_state(TASK_RUNNING);
3042        for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3043                if (w == cw) {
3044                        if (prev != NULL)
3045                                prev->next = w->next;
3046                        else
3047                                *head = w->next;
3048                        break;
3049                }
3050        }
3051}
3052
3053static void flush_cond_wait(struct cond_wait **head)
3054{
3055        while (*head != NULL) {
3056                wake_up_interruptible(&(*head)->q);
3057                *head = (*head)->next;
3058        }
3059}
3060
3061/*
3062 * wait for general purpose I/O pin(s) to enter specified state
3063 *
3064 * user_gpio fields:
3065 * state - bit indicates target pin state
3066 * smask - set bit indicates watched pin
3067 *
3068 * The wait ends when at least one watched pin enters the specified
3069 * state. When 0 (no error) is returned, user_gpio->state is set to the
3070 * state of all GPIO pins when the wait ends.
3071 *
3072 * Note: Each pin may be a dedicated input, dedicated output, or
3073 * configurable input/output. The number and configuration of pins
3074 * varies with the specific adapter model. Only input pins (dedicated
3075 * or configured) can be monitored with this function.
3076 */
3077static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3078{
3079        unsigned long flags;
3080        int rc = 0;
3081        struct gpio_desc gpio;
3082        struct cond_wait wait;
3083        u32 state;
3084
3085        if (!info->gpio_present)
3086                return -EINVAL;
3087        if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3088                return -EFAULT;
3089        DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3090                 info->device_name, gpio.state, gpio.smask));
3091        /* ignore output pins identified by set IODR bit */
3092        if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3093                return -EINVAL;
3094        init_cond_wait(&wait, gpio.smask);
3095
3096        spin_lock_irqsave(&info->port_array[0]->lock, flags);
3097        /* enable interrupts for watched pins */
3098        wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3099        /* get current pin states */
3100        state = rd_reg32(info, IOVR);
3101
3102        if (gpio.smask & ~(state ^ gpio.state)) {
3103                /* already in target state */
3104                gpio.state = state;
3105        } else {
3106                /* wait for target state */
3107                add_cond_wait(&info->gpio_wait_q, &wait);
3108                spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3109                schedule();
3110                if (signal_pending(current))
3111                        rc = -ERESTARTSYS;
3112                else
3113                        gpio.state = wait.data;
3114                spin_lock_irqsave(&info->port_array[0]->lock, flags);
3115                remove_cond_wait(&info->gpio_wait_q, &wait);
3116        }
3117
3118        /* disable all GPIO interrupts if no waiting processes */
3119        if (info->gpio_wait_q == NULL)
3120                wr_reg32(info, IOER, 0);
3121        spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3122
3123        if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3124                rc = -EFAULT;
3125        return rc;
3126}
3127
3128static int modem_input_wait(struct slgt_info *info,int arg)
3129{
3130        unsigned long flags;
3131        int rc;
3132        struct mgsl_icount cprev, cnow;
3133        DECLARE_WAITQUEUE(wait, current);
3134
3135        /* save current irq counts */
3136        spin_lock_irqsave(&info->lock,flags);
3137        cprev = info->icount;
3138        add_wait_queue(&info->status_event_wait_q, &wait);
3139        set_current_state(TASK_INTERRUPTIBLE);
3140        spin_unlock_irqrestore(&info->lock,flags);
3141
3142        for(;;) {
3143                schedule();
3144                if (signal_pending(current)) {
3145                        rc = -ERESTARTSYS;
3146                        break;
3147                }
3148
3149                /* get new irq counts */
3150                spin_lock_irqsave(&info->lock,flags);
3151                cnow = info->icount;
3152                set_current_state(TASK_INTERRUPTIBLE);
3153                spin_unlock_irqrestore(&info->lock,flags);
3154
3155                /* if no change, wait aborted for some reason */
3156                if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3157                    cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3158                        rc = -EIO;
3159                        break;
3160                }
3161
3162                /* check for change in caller specified modem input */
3163                if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3164                    (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3165                    (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3166                    (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3167                        rc = 0;
3168                        break;
3169                }
3170
3171                cprev = cnow;
3172        }
3173        remove_wait_queue(&info->status_event_wait_q, &wait);
3174        set_current_state(TASK_RUNNING);
3175        return rc;
3176}
3177
3178/*
3179 *  return state of serial control and status signals
3180 */
3181static int tiocmget(struct tty_struct *tty)
3182{
3183        struct slgt_info *info = tty->driver_data;
3184        unsigned int result;
3185        unsigned long flags;
3186
3187        spin_lock_irqsave(&info->lock,flags);
3188        get_signals(info);
3189        spin_unlock_irqrestore(&info->lock,flags);
3190
3191        result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3192                ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3193                ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3194                ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3195                ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3196                ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3197
3198        DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3199        return result;
3200}
3201
3202/*
3203 * set modem control signals (DTR/RTS)
3204 *
3205 *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3206 *              TIOCMSET = set/clear signal values
3207 *      value   bit mask for command
3208 */
3209static int tiocmset(struct tty_struct *tty,
3210                    unsigned int set, unsigned int clear)
3211{
3212        struct slgt_info *info = tty->driver_data;
3213        unsigned long flags;
3214
3215        DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3216
3217        if (set & TIOCM_RTS)
3218                info->signals |= SerialSignal_RTS;
3219        if (set & TIOCM_DTR)
3220                info->signals |= SerialSignal_DTR;
3221        if (clear & TIOCM_RTS)
3222                info->signals &= ~SerialSignal_RTS;
3223        if (clear & TIOCM_DTR)
3224                info->signals &= ~SerialSignal_DTR;
3225
3226        spin_lock_irqsave(&info->lock,flags);
3227        set_signals(info);
3228        spin_unlock_irqrestore(&info->lock,flags);
3229        return 0;
3230}
3231
3232static int carrier_raised(struct tty_port *port)
3233{
3234        unsigned long flags;
3235        struct slgt_info *info = container_of(port, struct slgt_info, port);
3236
3237        spin_lock_irqsave(&info->lock,flags);
3238        get_signals(info);
3239        spin_unlock_irqrestore(&info->lock,flags);
3240        return (info->signals & SerialSignal_DCD) ? 1 : 0;
3241}
3242
3243static void dtr_rts(struct tty_port *port, int on)
3244{
3245        unsigned long flags;
3246        struct slgt_info *info = container_of(port, struct slgt_info, port);
3247
3248        spin_lock_irqsave(&info->lock,flags);
3249        if (on)
3250                info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3251        else
3252                info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3253        set_signals(info);
3254        spin_unlock_irqrestore(&info->lock,flags);
3255}
3256
3257
3258/*
3259 *  block current process until the device is ready to open
3260 */
3261static int block_til_ready(struct tty_struct *tty, struct file *filp,
3262                           struct slgt_info *info)
3263{
3264        DECLARE_WAITQUEUE(wait, current);
3265        int             retval;
3266        bool            do_clocal = false;
3267        unsigned long   flags;
3268        int             cd;
3269        struct tty_port *port = &info->port;
3270
3271        DBGINFO(("%s block_til_ready\n", tty->driver->name));
3272
3273        if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3274                /* nonblock mode is set or port is not enabled */
3275                port->flags |= ASYNC_NORMAL_ACTIVE;
3276                return 0;
3277        }
3278
3279        if (tty->termios.c_cflag & CLOCAL)
3280                do_clocal = true;
3281
3282        /* Wait for carrier detect and the line to become
3283         * free (i.e., not in use by the callout).  While we are in
3284         * this loop, port->count is dropped by one, so that
3285         * close() knows when to free things.  We restore it upon
3286         * exit, either normal or abnormal.
3287         */
3288
3289        retval = 0;
3290        add_wait_queue(&port->open_wait, &wait);
3291
3292        spin_lock_irqsave(&info->lock, flags);
3293        port->count--;
3294        spin_unlock_irqrestore(&info->lock, flags);
3295        port->blocked_open++;
3296
3297        while (1) {
3298                if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3299                        tty_port_raise_dtr_rts(port);
3300
3301                set_current_state(TASK_INTERRUPTIBLE);
3302
3303                if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3304                        retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3305                                        -EAGAIN : -ERESTARTSYS;
3306                        break;
3307                }
3308
3309                cd = tty_port_carrier_raised(port);
3310                if (do_clocal || cd)
3311                        break;
3312
3313                if (signal_pending(current)) {
3314                        retval = -ERESTARTSYS;
3315                        break;
3316                }
3317
3318                DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3319                tty_unlock(tty);
3320                schedule();
3321                tty_lock(tty);
3322        }
3323
3324        set_current_state(TASK_RUNNING);
3325        remove_wait_queue(&port->open_wait, &wait);
3326
3327        if (!tty_hung_up_p(filp))
3328                port->count++;
3329        port->blocked_open--;
3330
3331        if (!retval)
3332                port->flags |= ASYNC_NORMAL_ACTIVE;
3333
3334        DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3335        return retval;
3336}
3337
3338/*
3339 * allocate buffers used for calling line discipline receive_buf
3340 * directly in synchronous mode
3341 * note: add 5 bytes to max frame size to allow appending
3342 * 32-bit CRC and status byte when configured to do so
3343 */
3344static int alloc_tmp_rbuf(struct slgt_info *info)
3345{
3346        info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3347        if (info->tmp_rbuf == NULL)
3348                return -ENOMEM;
3349        /* unused flag buffer to satisfy receive_buf calling interface */
3350        info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3351        if (!info->flag_buf) {
3352                kfree(info->tmp_rbuf);
3353                info->tmp_rbuf = NULL;
3354                return -ENOMEM;
3355        }
3356        return 0;
3357}
3358
3359static void free_tmp_rbuf(struct slgt_info *info)
3360{
3361        kfree(info->tmp_rbuf);
3362        info->tmp_rbuf = NULL;
3363        kfree(info->flag_buf);
3364        info->flag_buf = NULL;
3365}
3366
3367/*
3368 * allocate DMA descriptor lists.
3369 */
3370static int alloc_desc(struct slgt_info *info)
3371{
3372        unsigned int i;
3373        unsigned int pbufs;
3374
3375        /* allocate memory to hold descriptor lists */
3376        info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3377        if (info->bufs == NULL)
3378                return -ENOMEM;
3379
3380        memset(info->bufs, 0, DESC_LIST_SIZE);
3381
3382        info->rbufs = (struct slgt_desc*)info->bufs;
3383        info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3384
3385        pbufs = (unsigned int)info->bufs_dma_addr;
3386
3387        /*
3388         * Build circular lists of descriptors
3389         */
3390
3391        for (i=0; i < info->rbuf_count; i++) {
3392                /* physical address of this descriptor */
3393                info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3394
3395                /* physical address of next descriptor */
3396                if (i == info->rbuf_count - 1)
3397                        info->rbufs[i].next = cpu_to_le32(pbufs);
3398                else
3399                        info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3400                set_desc_count(info->rbufs[i], DMABUFSIZE);
3401        }
3402
3403        for (i=0; i < info->tbuf_count; i++) {
3404                /* physical address of this descriptor */
3405                info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3406
3407                /* physical address of next descriptor */
3408                if (i == info->tbuf_count - 1)
3409                        info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3410                else
3411                        info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3412        }
3413
3414        return 0;
3415}
3416
3417static void free_desc(struct slgt_info *info)
3418{
3419        if (info->bufs != NULL) {
3420                pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3421                info->bufs  = NULL;
3422                info->rbufs = NULL;
3423                info->tbufs = NULL;
3424        }
3425}
3426
3427static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3428{
3429        int i;
3430        for (i=0; i < count; i++) {
3431                if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3432                        return -ENOMEM;
3433                bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3434        }
3435        return 0;
3436}
3437
3438static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3439{
3440        int i;
3441        for (i=0; i < count; i++) {
3442                if (bufs[i].buf == NULL)
3443                        continue;
3444                pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3445                bufs[i].buf = NULL;
3446        }
3447}
3448
3449static int alloc_dma_bufs(struct slgt_info *info)
3450{
3451        info->rbuf_count = 32;
3452        info->tbuf_count = 32;
3453
3454        if (alloc_desc(info) < 0 ||
3455            alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3456            alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3457            alloc_tmp_rbuf(info) < 0) {
3458                DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3459                return -ENOMEM;
3460        }
3461        reset_rbufs(info);
3462        return 0;
3463}
3464
3465static void free_dma_bufs(struct slgt_info *info)
3466{
3467        if (info->bufs) {
3468                free_bufs(info, info->rbufs, info->rbuf_count);
3469                free_bufs(info, info->tbufs, info->tbuf_count);
3470                free_desc(info);
3471        }
3472        free_tmp_rbuf(info);
3473}
3474
3475static int claim_resources(struct slgt_info *info)
3476{
3477        if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3478                DBGERR(("%s reg addr conflict, addr=%08X\n",
3479                        info->device_name, info->phys_reg_addr));
3480                info->init_error = DiagStatus_AddressConflict;
3481                goto errout;
3482        }
3483        else
3484                info->reg_addr_requested = true;
3485
3486        info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3487        if (!info->reg_addr) {
3488                DBGERR(("%s can't map device registers, addr=%08X\n",
3489                        info->device_name, info->phys_reg_addr));
3490                info->init_error = DiagStatus_CantAssignPciResources;
3491                goto errout;
3492        }
3493        return 0;
3494
3495errout:
3496        release_resources(info);
3497        return -ENODEV;
3498}
3499
3500static void release_resources(struct slgt_info *info)
3501{
3502        if (info->irq_requested) {
3503                free_irq(info->irq_level, info);
3504                info->irq_requested = false;
3505        }
3506
3507        if (info->reg_addr_requested) {
3508                release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3509                info->reg_addr_requested = false;
3510        }
3511
3512        if (info->reg_addr) {
3513                iounmap(info->reg_addr);
3514                info->reg_addr = NULL;
3515        }
3516}
3517
3518/* Add the specified device instance data structure to the
3519 * global linked list of devices and increment the device count.
3520 */
3521static void add_device(struct slgt_info *info)
3522{
3523        char *devstr;
3524
3525        info->next_device = NULL;
3526        info->line = slgt_device_count;
3527        sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3528
3529        if (info->line < MAX_DEVICES) {
3530                if (maxframe[info->line])
3531                        info->max_frame_size = maxframe[info->line];
3532        }
3533
3534        slgt_device_count++;
3535
3536        if (!slgt_device_list)
3537                slgt_device_list = info;
3538        else {
3539                struct slgt_info *current_dev = slgt_device_list;
3540                while(current_dev->next_device)
3541                        current_dev = current_dev->next_device;
3542                current_dev->next_device = info;
3543        }
3544
3545        if (info->max_frame_size < 4096)
3546                info->max_frame_size = 4096;
3547        else if (info->max_frame_size > 65535)
3548                info->max_frame_size = 65535;
3549
3550        switch(info->pdev->device) {
3551        case SYNCLINK_GT_DEVICE_ID:
3552                devstr = "GT";
3553                break;
3554        case SYNCLINK_GT2_DEVICE_ID:
3555                devstr = "GT2";
3556                break;
3557        case SYNCLINK_GT4_DEVICE_ID:
3558                devstr = "GT4";
3559                break;
3560        case SYNCLINK_AC_DEVICE_ID:
3561                devstr = "AC";
3562                info->params.mode = MGSL_MODE_ASYNC;
3563                break;
3564        default:
3565                devstr = "(unknown model)";
3566        }
3567        printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3568                devstr, info->device_name, info->phys_reg_addr,
3569                info->irq_level, info->max_frame_size);
3570
3571#if SYNCLINK_GENERIC_HDLC
3572        hdlcdev_init(info);
3573#endif
3574}
3575
3576static const struct tty_port_operations slgt_port_ops = {
3577        .carrier_raised = carrier_raised,
3578        .dtr_rts = dtr_rts,
3579};
3580
3581/*
3582 *  allocate device instance structure, return NULL on failure
3583 */
3584static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3585{
3586        struct slgt_info *info;
3587
3588        info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3589
3590        if (!info) {
3591                DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3592                        driver_name, adapter_num, port_num));
3593        } else {
3594                tty_port_init(&info->port);
3595                info->port.ops = &slgt_port_ops;
3596                info->magic = MGSL_MAGIC;
3597                INIT_WORK(&info->task, bh_handler);
3598                info->max_frame_size = 4096;
3599                info->base_clock = 14745600;
3600                info->rbuf_fill_level = DMABUFSIZE;
3601                info->port.close_delay = 5*HZ/10;
3602                info->port.closing_wait = 30*HZ;
3603                init_waitqueue_head(&info->status_event_wait_q);
3604                init_waitqueue_head(&info->event_wait_q);
3605                spin_lock_init(&info->netlock);
3606                memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3607                info->idle_mode = HDLC_TXIDLE_FLAGS;
3608                info->adapter_num = adapter_num;
3609                info->port_num = port_num;
3610
3611                setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3612                setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3613
3614                /* Copy configuration info to device instance data */
3615                info->pdev = pdev;
3616                info->irq_level = pdev->irq;
3617                info->phys_reg_addr = pci_resource_start(pdev,0);
3618
3619                info->bus_type = MGSL_BUS_TYPE_PCI;
3620                info->irq_flags = IRQF_SHARED;
3621
3622                info->init_error = -1; /* assume error, set to 0 on successful init */
3623        }
3624
3625        return info;
3626}
3627
3628static void device_init(int adapter_num, struct pci_dev *pdev)
3629{
3630        struct slgt_info *port_array[SLGT_MAX_PORTS];
3631        int i;
3632        int port_count = 1;
3633
3634        if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3635                port_count = 2;
3636        else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3637                port_count = 4;
3638
3639        /* allocate device instances for all ports */
3640        for (i=0; i < port_count; ++i) {
3641                port_array[i] = alloc_dev(adapter_num, i, pdev);
3642                if (port_array[i] == NULL) {
3643                        for (--i; i >= 0; --i) {
3644                                tty_port_destroy(&port_array[i]->port);
3645                                kfree(port_array[i]);
3646                        }
3647                        return;
3648                }
3649        }
3650
3651        /* give copy of port_array to all ports and add to device list  */
3652        for (i=0; i < port_count; ++i) {
3653                memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3654                add_device(port_array[i]);
3655                port_array[i]->port_count = port_count;
3656                spin_lock_init(&port_array[i]->lock);
3657        }
3658
3659        /* Allocate and claim adapter resources */
3660        if (!claim_resources(port_array[0])) {
3661
3662                alloc_dma_bufs(port_array[0]);
3663
3664                /* copy resource information from first port to others */
3665                for (i = 1; i < port_count; ++i) {
3666                        port_array[i]->irq_level = port_array[0]->irq_level;
3667                        port_array[i]->reg_addr  = port_array[0]->reg_addr;
3668                        alloc_dma_bufs(port_array[i]);
3669                }
3670
3671                if (request_irq(port_array[0]->irq_level,
3672                                        slgt_interrupt,
3673                                        port_array[0]->irq_flags,
3674                                        port_array[0]->device_name,
3675                                        port_array[0]) < 0) {
3676                        DBGERR(("%s request_irq failed IRQ=%d\n",
3677                                port_array[0]->device_name,
3678                                port_array[0]->irq_level));
3679                } else {
3680                        port_array[0]->irq_requested = true;
3681                        adapter_test(port_array[0]);
3682                        for (i=1 ; i < port_count ; i++) {
3683                                port_array[i]->init_error = port_array[0]->init_error;
3684                                port_array[i]->gpio_present = port_array[0]->gpio_present;
3685                        }
3686                }
3687        }
3688
3689        for (i = 0; i < port_count; ++i) {
3690                struct slgt_info *info = port_array[i];
3691                tty_port_register_device(&info->port, serial_driver, info->line,
3692                                &info->pdev->dev);
3693        }
3694}
3695
3696static int init_one(struct pci_dev *dev,
3697                              const struct pci_device_id *ent)
3698{
3699        if (pci_enable_device(dev)) {
3700                printk("error enabling pci device %p\n", dev);
3701                return -EIO;
3702        }
3703        pci_set_master(dev);
3704        device_init(slgt_device_count, dev);
3705        return 0;
3706}
3707
3708static void remove_one(struct pci_dev *dev)
3709{
3710}
3711
3712static const struct tty_operations ops = {
3713        .open = open,
3714        .close = close,
3715        .write = write,
3716        .put_char = put_char,
3717        .flush_chars = flush_chars,
3718        .write_room = write_room,
3719        .chars_in_buffer = chars_in_buffer,
3720        .flush_buffer = flush_buffer,
3721        .ioctl = ioctl,
3722        .compat_ioctl = slgt_compat_ioctl,
3723        .throttle = throttle,
3724        .unthrottle = unthrottle,
3725        .send_xchar = send_xchar,
3726        .break_ctl = set_break,
3727        .wait_until_sent = wait_until_sent,
3728        .set_termios = set_termios,
3729        .stop = tx_hold,
3730        .start = tx_release,
3731        .hangup = hangup,
3732        .tiocmget = tiocmget,
3733        .tiocmset = tiocmset,
3734        .get_icount = get_icount,
3735        .proc_fops = &synclink_gt_proc_fops,
3736};
3737
3738static void slgt_cleanup(void)
3739{
3740        int rc;
3741        struct slgt_info *info;
3742        struct slgt_info *tmp;
3743
3744        printk(KERN_INFO "unload %s\n", driver_name);
3745
3746        if (serial_driver) {
3747                for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3748                        tty_unregister_device(serial_driver, info->line);
3749                if ((rc = tty_unregister_driver(serial_driver)))
3750                        DBGERR(("tty_unregister_driver error=%d\n", rc));
3751                put_tty_driver(serial_driver);
3752        }
3753
3754        /* reset devices */
3755        info = slgt_device_list;
3756        while(info) {
3757                reset_port(info);
3758                info = info->next_device;
3759        }
3760
3761        /* release devices */
3762        info = slgt_device_list;
3763        while(info) {
3764#if SYNCLINK_GENERIC_HDLC
3765                hdlcdev_exit(info);
3766#endif
3767                free_dma_bufs(info);
3768                free_tmp_rbuf(info);
3769                if (info->port_num == 0)
3770                        release_resources(info);
3771                tmp = info;
3772                info = info->next_device;
3773                tty_port_destroy(&tmp->port);
3774                kfree(tmp);
3775        }
3776
3777        if (pci_registered)
3778                pci_unregister_driver(&pci_driver);
3779}
3780
3781/*
3782 *  Driver initialization entry point.
3783 */
3784static int __init slgt_init(void)
3785{
3786        int rc;
3787
3788        printk(KERN_INFO "%s\n", driver_name);
3789
3790        serial_driver = alloc_tty_driver(MAX_DEVICES);
3791        if (!serial_driver) {
3792                printk("%s can't allocate tty driver\n", driver_name);
3793                return -ENOMEM;
3794        }
3795
3796        /* Initialize the tty_driver structure */
3797
3798        serial_driver->driver_name = tty_driver_name;
3799        serial_driver->name = tty_dev_prefix;
3800        serial_driver->major = ttymajor;
3801        serial_driver->minor_start = 64;
3802        serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3803        serial_driver->subtype = SERIAL_TYPE_NORMAL;
3804        serial_driver->init_termios = tty_std_termios;
3805        serial_driver->init_termios.c_cflag =
3806                B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3807        serial_driver->init_termios.c_ispeed = 9600;
3808        serial_driver->init_termios.c_ospeed = 9600;
3809        serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3810        tty_set_operations(serial_driver, &ops);
3811        if ((rc = tty_register_driver(serial_driver)) < 0) {
3812                DBGERR(("%s can't register serial driver\n", driver_name));
3813                put_tty_driver(serial_driver);
3814                serial_driver = NULL;
3815                goto error;
3816        }
3817
3818        printk(KERN_INFO "%s, tty major#%d\n",
3819               driver_name, serial_driver->major);
3820
3821        slgt_device_count = 0;
3822        if ((rc = pci_register_driver(&pci_driver)) < 0) {
3823                printk("%s pci_register_driver error=%d\n", driver_name, rc);
3824                goto error;
3825        }
3826        pci_registered = true;
3827
3828        if (!slgt_device_list)
3829                printk("%s no devices found\n",driver_name);
3830
3831        return 0;
3832
3833error:
3834        slgt_cleanup();
3835        return rc;
3836}
3837
3838static void __exit slgt_exit(void)
3839{
3840        slgt_cleanup();
3841}
3842
3843module_init(slgt_init);
3844module_exit(slgt_exit);
3845
3846/*
3847 * register access routines
3848 */
3849
3850#define CALC_REGADDR() \
3851        unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3852        if (addr >= 0x80) \
3853                reg_addr += (info->port_num) * 32; \
3854        else if (addr >= 0x40)  \
3855                reg_addr += (info->port_num) * 16;
3856
3857static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3858{
3859        CALC_REGADDR();
3860        return readb((void __iomem *)reg_addr);
3861}
3862
3863static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3864{
3865        CALC_REGADDR();
3866        writeb(value, (void __iomem *)reg_addr);
3867}
3868
3869static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3870{
3871        CALC_REGADDR();
3872        return readw((void __iomem *)reg_addr);
3873}
3874
3875static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3876{
3877        CALC_REGADDR();
3878        writew(value, (void __iomem *)reg_addr);
3879}
3880
3881static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3882{
3883        CALC_REGADDR();
3884        return readl((void __iomem *)reg_addr);
3885}
3886
3887static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3888{
3889        CALC_REGADDR();
3890        writel(value, (void __iomem *)reg_addr);
3891}
3892
3893static void rdma_reset(struct slgt_info *info)
3894{
3895        unsigned int i;
3896
3897        /* set reset bit */
3898        wr_reg32(info, RDCSR, BIT1);
3899
3900        /* wait for enable bit cleared */
3901        for(i=0 ; i < 1000 ; i++)
3902                if (!(rd_reg32(info, RDCSR) & BIT0))
3903                        break;
3904}
3905
3906static void tdma_reset(struct slgt_info *info)
3907{
3908        unsigned int i;
3909
3910        /* set reset bit */
3911        wr_reg32(info, TDCSR, BIT1);
3912
3913        /* wait for enable bit cleared */
3914        for(i=0 ; i < 1000 ; i++)
3915                if (!(rd_reg32(info, TDCSR) & BIT0))
3916                        break;
3917}
3918
3919/*
3920 * enable internal loopback
3921 * TxCLK and RxCLK are generated from BRG
3922 * and TxD is looped back to RxD internally.
3923 */
3924static void enable_loopback(struct slgt_info *info)
3925{
3926        /* SCR (serial control) BIT2=loopback enable */
3927        wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3928
3929        if (info->params.mode != MGSL_MODE_ASYNC) {
3930                /* CCR (clock control)
3931                 * 07..05  tx clock source (010 = BRG)
3932                 * 04..02  rx clock source (010 = BRG)
3933                 * 01      auxclk enable   (0 = disable)
3934                 * 00      BRG enable      (1 = enable)
3935                 *
3936                 * 0100 1001
3937                 */
3938                wr_reg8(info, CCR, 0x49);
3939
3940                /* set speed if available, otherwise use default */
3941                if (info->params.clock_speed)
3942                        set_rate(info, info->params.clock_speed);
3943                else
3944                        set_rate(info, 3686400);
3945        }
3946}
3947
3948/*
3949 *  set baud rate generator to specified rate
3950 */
3951static void set_rate(struct slgt_info *info, u32 rate)
3952{
3953        unsigned int div;
3954        unsigned int osc = info->base_clock;
3955
3956        /* div = osc/rate - 1
3957         *
3958         * Round div up if osc/rate is not integer to
3959         * force to next slowest rate.
3960         */
3961
3962        if (rate) {
3963                div = osc/rate;
3964                if (!(osc % rate) && div)
3965                        div--;
3966                wr_reg16(info, BDR, (unsigned short)div);
3967        }
3968}
3969
3970static void rx_stop(struct slgt_info *info)
3971{
3972        unsigned short val;
3973
3974        /* disable and reset receiver */
3975        val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3976        wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3977        wr_reg16(info, RCR, val);                  /* clear reset bit */
3978
3979        slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3980
3981        /* clear pending rx interrupts */
3982        wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3983
3984        rdma_reset(info);
3985
3986        info->rx_enabled = false;
3987        info->rx_restart = false;
3988}
3989
3990static void rx_start(struct slgt_info *info)
3991{
3992        unsigned short val;
3993
3994        slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3995
3996        /* clear pending rx overrun IRQ */
3997        wr_reg16(info, SSR, IRQ_RXOVER);
3998
3999        /* reset and disable receiver */
4000        val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */

4001        wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4002        wr_reg16(info, RCR, val);                  /* clear reset bit */
4003
4004        rdma_reset(info);
4005        reset_rbufs(info);
4006
4007        if (info->rx_pio) {
4008                /* rx request when rx FIFO not empty */
4009                wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4010                slgt_irq_on(info, IRQ_RXDATA);
4011                if (info->params.mode == MGSL_MODE_ASYNC) {
4012                        /* enable saving of rx status */
4013                        wr_reg32(info, RDCSR, BIT6);
4014                }
4015        } else {
4016                /* rx request when rx FIFO half full */
4017                wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4018                /* set 1st descriptor address */
4019                wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4020
4021                if (info->params.mode != MGSL_MODE_ASYNC) {
4022                        /* enable rx DMA and DMA interrupt */
4023                        wr_reg32(info, RDCSR, (BIT2 + BIT0));
4024                } else {
4025                        /* enable saving of rx status, rx DMA and DMA interrupt */
4026                        wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4027                }
4028        }
4029
4030        slgt_irq_on(info, IRQ_RXOVER);
4031
4032        /* enable receiver */
4033        wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4034
4035        info->rx_restart = false;
4036        info->rx_enabled = true;
4037}
4038
4039static void tx_start(struct slgt_info *info)
4040{
4041        if (!info->tx_enabled) {
4042                wr_reg16(info, TCR,
4043                         (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4044                info->tx_enabled = true;
4045        }
4046
4047        if (desc_count(info->tbufs[info->tbuf_start])) {
4048                info->drop_rts_on_tx_done = false;
4049
4050                if (info->params.mode != MGSL_MODE_ASYNC) {
4051                        if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4052                                get_signals(info);
4053                                if (!(info->signals & SerialSignal_RTS)) {
4054                                        info->signals |= SerialSignal_RTS;
4055                                        set_signals(info);
4056                                        info->drop_rts_on_tx_done = true;
4057                                }
4058                        }
4059
4060                        slgt_irq_off(info, IRQ_TXDATA);
4061                        slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4062                        /* clear tx idle and underrun status bits */
4063                        wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4064                } else {
4065                        slgt_irq_off(info, IRQ_TXDATA);
4066                        slgt_irq_on(info, IRQ_TXIDLE);
4067                        /* clear tx idle status bit */
4068                        wr_reg16(info, SSR, IRQ_TXIDLE);
4069                }
4070                /* set 1st descriptor address and start DMA */
4071                wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4072                wr_reg32(info, TDCSR, BIT2 + BIT0);
4073                info->tx_active = true;
4074        }
4075}
4076
4077static void tx_stop(struct slgt_info *info)
4078{
4079        unsigned short val;
4080
4081        del_timer(&info->tx_timer);
4082
4083        tdma_reset(info);
4084
4085        /* reset and disable transmitter */
4086        val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4087        wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4088
4089        slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4090
4091        /* clear tx idle and underrun status bit */
4092        wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4093
4094        reset_tbufs(info);
4095
4096        info->tx_enabled = false;
4097        info->tx_active = false;
4098}
4099
4100static void reset_port(struct slgt_info *info)
4101{
4102        if (!info->reg_addr)
4103                return;
4104
4105        tx_stop(info);
4106        rx_stop(info);
4107
4108        info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4109        set_signals(info);
4110
4111        slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4112}
4113
4114static void reset_adapter(struct slgt_info *info)
4115{
4116        int i;
4117        for (i=0; i < info->port_count; ++i) {
4118                if (info->port_array[i])
4119                        reset_port(info->port_array[i]);
4120        }
4121}
4122
4123static void async_mode(struct slgt_info *info)
4124{
4125        unsigned short val;
4126
4127        slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4128        tx_stop(info);
4129        rx_stop(info);
4130
4131        /* TCR (tx control)
4132         *
4133         * 15..13  mode, 010=async
4134         * 12..10  encoding, 000=NRZ
4135         * 09      parity enable
4136         * 08      1=odd parity, 0=even parity
4137         * 07      1=RTS driver control
4138         * 06      1=break enable
4139         * 05..04  character length
4140         *         00=5 bits
4141         *         01=6 bits
4142         *         10=7 bits
4143         *         11=8 bits
4144         * 03      0=1 stop bit, 1=2 stop bits
4145         * 02      reset
4146         * 01      enable
4147         * 00      auto-CTS enable
4148         */
4149        val = 0x4000;
4150
4151        if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4152                val |= BIT7;
4153
4154        if (info->params.parity != ASYNC_PARITY_NONE) {
4155                val |= BIT9;
4156                if (info->params.parity == ASYNC_PARITY_ODD)
4157                        val |= BIT8;
4158        }
4159
4160        switch (info->params.data_bits)
4161        {
4162        case 6: val |= BIT4; break;
4163        case 7: val |= BIT5; break;
4164        case 8: val |= BIT5 + BIT4; break;
4165        }
4166
4167        if (info->params.stop_bits != 1)
4168                val |= BIT3;
4169
4170        if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4171                val |= BIT0;
4172
4173        wr_reg16(info, TCR, val);
4174
4175        /* RCR (rx control)
4176         *
4177         * 15..13  mode, 010=async
4178         * 12..10  encoding, 000=NRZ
4179         * 09      parity enable
4180         * 08      1=odd parity, 0=even parity
4181         * 07..06  reserved, must be 0
4182         * 05..04  character length
4183         *         00=5 bits
4184         *         01=6 bits
4185         *         10=7 bits
4186         *         11=8 bits
4187         * 03      reserved, must be zero
4188         * 02      reset
4189         * 01      enable
4190         * 00      auto-DCD enable
4191         */
4192        val = 0x4000;
4193
4194        if (info->params.parity != ASYNC_PARITY_NONE) {
4195                val |= BIT9;
4196                if (info->params.parity == ASYNC_PARITY_ODD)
4197                        val |= BIT8;
4198        }
4199
4200        switch (info->params.data_bits)
4201        {
4202        case 6: val |= BIT4; break;
4203        case 7: val |= BIT5; break;
4204        case 8: val |= BIT5 + BIT4; break;
4205        }
4206
4207        if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4208                val |= BIT0;
4209
4210        wr_reg16(info, RCR, val);
4211
4212        /* CCR (clock control)
4213         *
4214         * 07..05  011 = tx clock source is BRG/16
4215         * 04..02  010 = rx clock source is BRG
4216         * 01      0 = auxclk disabled
4217         * 00      1 = BRG enabled
4218         *
4219         * 0110 1001
4220         */
4221        wr_reg8(info, CCR, 0x69);
4222
4223        msc_set_vcr(info);
4224
4225        /* SCR (serial control)
4226         *
4227         * 15  1=tx req on FIFO half empty
4228         * 14  1=rx req on FIFO half full
4229         * 13  tx data  IRQ enable
4230         * 12  tx idle  IRQ enable
4231         * 11  rx break on IRQ enable
4232         * 10  rx data  IRQ enable
4233         * 09  rx break off IRQ enable
4234         * 08  overrun  IRQ enable
4235         * 07  DSR      IRQ enable
4236         * 06  CTS      IRQ enable
4237         * 05  DCD      IRQ enable
4238         * 04  RI       IRQ enable
4239         * 03  0=16x sampling, 1=8x sampling
4240         * 02  1=txd->rxd internal loopback enable
4241         * 01  reserved, must be zero
4242         * 00  1=master IRQ enable
4243         */
4244        val = BIT15 + BIT14 + BIT0;
4245        /* JCR[8] : 1 = x8 async mode feature available */
4246        if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4247            ((info->base_clock < (info->params.data_rate * 16)) ||
4248             (info->base_clock % (info->params.data_rate * 16)))) {
4249                /* use 8x sampling */
4250                val |= BIT3;
4251                set_rate(info, info->params.data_rate * 8);
4252        } else {
4253                /* use 16x sampling */
4254                set_rate(info, info->params.data_rate * 16);
4255        }
4256        wr_reg16(info, SCR, val);
4257
4258        slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4259
4260        if (info->params.loopback)
4261                enable_loopback(info);
4262}
4263
4264static void sync_mode(struct slgt_info *info)
4265{
4266        unsigned short val;
4267
4268        slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4269        tx_stop(info);
4270        rx_stop(info);
4271
4272        /* TCR (tx control)
4273         *
4274         * 15..13  mode
4275         *         000=HDLC/SDLC
4276         *         001=raw bit synchronous
4277         *         010=asynchronous/isochronous
4278         *         011=monosync byte synchronous
4279         *         100=bisync byte synchronous
4280         *         101=xsync byte synchronous
4281         * 12..10  encoding
4282         * 09      CRC enable
4283         * 08      CRC32
4284         * 07      1=RTS driver control
4285         * 06      preamble enable
4286         * 05..04  preamble length
4287         * 03      share open/close flag
4288         * 02      reset
4289         * 01      enable
4290         * 00      auto-CTS enable
4291         */
4292        val = BIT2;
4293
4294        switch(info->params.mode) {
4295        case MGSL_MODE_XSYNC:
4296                val |= BIT15 + BIT13;
4297                break;
4298        case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4299        case MGSL_MODE_BISYNC:   val |= BIT15; break;
4300        case MGSL_MODE_RAW:      val |= BIT13; break;
4301        }
4302        if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4303                val |= BIT7;
4304
4305        switch(info->params.encoding)
4306        {
4307        case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4308        case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4309        case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4310        case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4311        case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4312        case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4313        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4314        }
4315
4316        switch (info->params.crc_type & HDLC_CRC_MASK)
4317        {
4318        case HDLC_CRC_16_CCITT: val |= BIT9; break;
4319        case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4320        }
4321
4322        if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4323                val |= BIT6;
4324
4325        switch (info->params.preamble_length)
4326        {
4327        case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4328        case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4329        case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4330        }
4331
4332        if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4333                val |= BIT0;
4334
4335        wr_reg16(info, TCR, val);
4336
4337        /* TPR (transmit preamble) */
4338
4339        switch (info->params.preamble)
4340        {
4341        case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4342        case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4343        case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4344        case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4345        case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4346        default:                          val = 0x7e; break;
4347        }
4348        wr_reg8(info, TPR, (unsigned char)val);
4349
4350        /* RCR (rx control)
4351         *
4352         * 15..13  mode
4353         *         000=HDLC/SDLC
4354         *         001=raw bit synchronous
4355         *         010=asynchronous/isochronous
4356         *         011=monosync byte synchronous
4357         *         100=bisync byte synchronous
4358         *         101=xsync byte synchronous
4359         * 12..10  encoding
4360         * 09      CRC enable
4361         * 08      CRC32
4362         * 07..03  reserved, must be 0
4363         * 02      reset
4364         * 01      enable
4365         * 00      auto-DCD enable
4366         */
4367        val = 0;
4368
4369        switch(info->params.mode) {
4370        case MGSL_MODE_XSYNC:
4371                val |= BIT15 + BIT13;
4372                break;
4373        case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4374        case MGSL_MODE_BISYNC:   val |= BIT15; break;
4375        case MGSL_MODE_RAW:      val |= BIT13; break;
4376        }
4377
4378        switch(info->params.encoding)
4379        {
4380        case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4381        case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4382        case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4383        case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4384        case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4385        case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4386        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4387        }
4388
4389        switch (info->params.crc_type & HDLC_CRC_MASK)
4390        {
4391        case HDLC_CRC_16_CCITT: val |= BIT9; break;
4392        case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4393        }
4394
4395        if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4396                val |= BIT0;
4397
4398        wr_reg16(info, RCR, val);
4399
4400        /* CCR (clock control)
4401         *
4402         * 07..05  tx clock source
4403         * 04..02  rx clock source
4404         * 01      auxclk enable
4405         * 00      BRG enable
4406         */
4407        val = 0;
4408
4409        if (info->params.flags & HDLC_FLAG_TXC_BRG)
4410        {
4411                // when RxC source is DPLL, BRG generates 16X DPLL
4412                // reference clock, so take TxC from BRG/16 to get
4413                // transmit clock at actual data rate
4414                if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4415                        val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4416                else
4417                        val |= BIT6;    /* 010, txclk = BRG */
4418        }
4419        else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4420                val |= BIT7;    /* 100, txclk = DPLL Input */
4421        else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4422                val |= BIT5;    /* 001, txclk = RXC Input */
4423
4424        if (info->params.flags & HDLC_FLAG_RXC_BRG)
4425                val |= BIT3;    /* 010, rxclk = BRG */
4426        else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4427                val |= BIT4;    /* 100, rxclk = DPLL */
4428        else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4429                val |= BIT2;    /* 001, rxclk = TXC Input */
4430
4431        if (info->params.clock_speed)
4432                val |= BIT1 + BIT0;
4433
4434        wr_reg8(info, CCR, (unsigned char)val);
4435
4436        if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4437        {
4438                // program DPLL mode
4439                switch(info->params.encoding)
4440                {
4441                case HDLC_ENCODING_BIPHASE_MARK:
4442                case HDLC_ENCODING_BIPHASE_SPACE:
4443                        val = BIT7; break;
4444                case HDLC_ENCODING_BIPHASE_LEVEL:
4445                case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4446                        val = BIT7 + BIT6; break;
4447                default: val = BIT6;    // NRZ encodings
4448                }
4449                wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4450
4451                // DPLL requires a 16X reference clock from BRG
4452                set_rate(info, info->params.clock_speed * 16);
4453        }
4454        else
4455                set_rate(info, info->params.clock_speed);
4456
4457        tx_set_idle(info);
4458
4459        msc_set_vcr(info);
4460
4461        /* SCR (serial control)
4462         *
4463         * 15  1=tx req on FIFO half empty
4464         * 14  1=rx req on FIFO half full
4465         * 13  tx data  IRQ enable
4466         * 12  tx idle  IRQ enable
4467         * 11  underrun IRQ enable
4468         * 10  rx data  IRQ enable
4469         * 09  rx idle  IRQ enable
4470         * 08  overrun  IRQ enable
4471         * 07  DSR      IRQ enable
4472         * 06  CTS      IRQ enable
4473         * 05  DCD      IRQ enable
4474         * 04  RI       IRQ enable
4475         * 03  reserved, must be zero
4476         * 02  1=txd->rxd internal loopback enable
4477         * 01  reserved, must be zero
4478         * 00  1=master IRQ enable
4479         */
4480        wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4481
4482        if (info->params.loopback)
4483                enable_loopback(info);
4484}
4485
4486/*
4487 *  set transmit idle mode
4488 */
4489static void tx_set_idle(struct slgt_info *info)
4490{
4491        unsigned char val;
4492        unsigned short tcr;
4493
4494        /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4495         * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4496         */
4497        tcr = rd_reg16(info, TCR);
4498        if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4499                /* disable preamble, set idle size to 16 bits */
4500                tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4501                /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4502                wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4503        } else if (!(tcr & BIT6)) {
4504                /* preamble is disabled, set idle size to 8 bits */
4505                tcr &= ~(BIT5 + BIT4);
4506        }
4507        wr_reg16(info, TCR, tcr);
4508
4509        if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4510                /* LSB of custom tx idle specified in tx idle register */
4511                val = (unsigned char)(info->idle_mode & 0xff);
4512        } else {
4513                /* standard 8 bit idle patterns */
4514                switch(info->idle_mode)
4515                {
4516                case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4517                case HDLC_TXIDLE_ALT_ZEROS_ONES:
4518                case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4519                case HDLC_TXIDLE_ZEROS:
4520                case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4521                default:                         val = 0xff;
4522                }
4523        }
4524
4525        wr_reg8(info, TIR, val);
4526}
4527
4528/*
4529 * get state of V24 status (input) signals
4530 */
4531static void get_signals(struct slgt_info *info)
4532{
4533        unsigned short status = rd_reg16(info, SSR);
4534
4535        /* clear all serial signals except RTS and DTR */
4536        info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4537
4538        if (status & BIT3)
4539                info->signals |= SerialSignal_DSR;
4540        if (status & BIT2)
4541                info->signals |= SerialSignal_CTS;
4542        if (status & BIT1)
4543                info->signals |= SerialSignal_DCD;
4544        if (status & BIT0)
4545                info->signals |= SerialSignal_RI;
4546}
4547
4548/*
4549 * set V.24 Control Register based on current configuration
4550 */
4551static void msc_set_vcr(struct slgt_info *info)
4552{
4553        unsigned char val = 0;
4554
4555        /* VCR (V.24 control)
4556         *
4557         * 07..04  serial IF select
4558         * 03      DTR
4559         * 02      RTS
4560         * 01      LL
4561         * 00      RL
4562         */
4563
4564        switch(info->if_mode & MGSL_INTERFACE_MASK)
4565        {
4566        case MGSL_INTERFACE_RS232:
4567                val |= BIT5; /* 0010 */
4568                break;
4569        case MGSL_INTERFACE_V35:
4570                val |= BIT7 + BIT6 + BIT5; /* 1110 */
4571                break;
4572        case MGSL_INTERFACE_RS422:
4573                val |= BIT6; /* 0100 */
4574                break;
4575        }
4576
4577        if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4578                val |= BIT4;
4579        if (info->signals & SerialSignal_DTR)
4580                val |= BIT3;
4581        if (info->signals & SerialSignal_RTS)
4582                val |= BIT2;
4583        if (info->if_mode & MGSL_INTERFACE_LL)
4584                val |= BIT1;
4585        if (info->if_mode & MGSL_INTERFACE_RL)
4586                val |= BIT0;
4587        wr_reg8(info, VCR, val);
4588}
4589
4590/*
4591 * set state of V24 control (output) signals
4592 */
4593static void set_signals(struct slgt_info *info)
4594{
4595        unsigned char val = rd_reg8(info, VCR);
4596        if (info->signals & SerialSignal_DTR)
4597                val |= BIT3;
4598        else
4599                val &= ~BIT3;
4600        if (info->signals & SerialSignal_RTS)
4601                val |= BIT2;
4602        else
4603                val &= ~BIT2;
4604        wr_reg8(info, VCR, val);
4605}
4606
4607/*
4608 * free range of receive DMA buffers (i to last)
4609 */
4610static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4611{
4612        int done = 0;
4613
4614        while(!done) {
4615                /* reset current buffer for reuse */
4616                info->rbufs[i].status = 0;
4617                set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4618                if (i == last)
4619                        done = 1;
4620                if (++i == info->rbuf_count)
4621                        i = 0;
4622        }
4623        info->rbuf_current = i;
4624}
4625
4626/*
4627 * mark all receive DMA buffers as free
4628 */
4629static void reset_rbufs(struct slgt_info *info)
4630{
4631        free_rbufs(info, 0, info->rbuf_count - 1);
4632        info->rbuf_fill_index = 0;
4633        info->rbuf_fill_count = 0;
4634}
4635
4636/*
4637 * pass receive HDLC frame to upper layer
4638 *
4639 * return true if frame available, otherwise false
4640 */
4641static bool rx_get_frame(struct slgt_info *info)
4642{
4643        unsigned int start, end;
4644        unsigned short status;
4645        unsigned int framesize = 0;
4646        unsigned long flags;
4647        struct tty_struct *tty = info->port.tty;
4648        unsigned char addr_field = 0xff;
4649        unsigned int crc_size = 0;
4650
4651        switch (info->params.crc_type & HDLC_CRC_MASK) {
4652        case HDLC_CRC_16_CCITT: crc_size = 2; break;
4653        case HDLC_CRC_32_CCITT: crc_size = 4; break;
4654        }
4655
4656check_again:
4657
4658        framesize = 0;
4659        addr_field = 0xff;
4660        start = end = info->rbuf_current;
4661
4662        for (;;) {
4663                if (!desc_complete(info->rbufs[end]))
4664                        goto cleanup;
4665
4666                if (framesize == 0 && info->params.addr_filter != 0xff)
4667                        addr_field = info->rbufs[end].buf[0];
4668
4669                framesize += desc_count(info->rbufs[end]);
4670
4671                if (desc_eof(info->rbufs[end]))
4672                        break;
4673
4674                if (++end == info->rbuf_count)
4675                        end = 0;
4676
4677                if (end == info->rbuf_current) {
4678                        if (info->rx_enabled){
4679                                spin_lock_irqsave(&info->lock,flags);
4680                                rx_start(info);
4681                                spin_unlock_irqrestore(&info->lock,flags);
4682                        }
4683                        goto cleanup;
4684                }
4685        }
4686
4687        /* status
4688         *
4689         * 15      buffer complete
4690         * 14..06  reserved
4691         * 05..04  residue
4692         * 02      eof (end of frame)
4693         * 01      CRC error
4694         * 00      abort
4695         */
4696        status = desc_status(info->rbufs[end]);
4697
4698        /* ignore CRC bit if not using CRC (bit is undefined) */
4699        if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4700                status &= ~BIT1;
4701
4702        if (framesize == 0 ||
4703                 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4704                free_rbufs(info, start, end);
4705                goto check_again;
4706        }
4707
4708        if (framesize < (2 + crc_size) || status & BIT0) {
4709                info->icount.rxshort++;
4710                framesize = 0;
4711        } else if (status & BIT1) {
4712                info->icount.rxcrc++;
4713                if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4714                        framesize = 0;
4715        }
4716
4717#if SYNCLINK_GENERIC_HDLC
4718        if (framesize == 0) {
4719                info->netdev->stats.rx_errors++;
4720                info->netdev->stats.rx_frame_errors++;
4721        }
4722#endif
4723
4724        DBGBH(("%s rx frame status=%04X size=%d\n",
4725                info->device_name, status, framesize));
4726        DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4727
4728        if (framesize) {
4729                if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4730                        framesize -= crc_size;
4731                        crc_size = 0;
4732                }
4733
4734                if (framesize > info->max_frame_size + crc_size)
4735                        info->icount.rxlong++;
4736                else {
4737                        /* copy dma buffer(s) to contiguous temp buffer */
4738                        int copy_count = framesize;
4739                        int i = start;
4740                        unsigned char *p = info->tmp_rbuf;
4741                        info->tmp_rbuf_count = framesize;
4742
4743                        info->icount.rxok++;
4744
4745                        while(copy_count) {
4746                                int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4747                                memcpy(p, info->rbufs[i].buf, partial_count);
4748                                p += partial_count;
4749                                copy_count -= partial_count;
4750                                if (++i == info->rbuf_count)
4751                                        i = 0;
4752                        }
4753
4754                        if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4755                                *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4756                                framesize++;
4757                        }
4758
4759#if SYNCLINK_GENERIC_HDLC
4760                        if (info->netcount)
4761                                hdlcdev_rx(info,info->tmp_rbuf, framesize);
4762                        else
4763#endif
4764                                ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4765                }
4766        }
4767        free_rbufs(info, start, end);
4768        return true;
4769
4770cleanup:
4771        return false;
4772}
4773
4774/*
4775 * pass receive buffer (RAW synchronous mode) to tty layer
4776 * return true if buffer available, otherwise false
4777 */
4778static bool rx_get_buf(struct slgt_info *info)
4779{
4780        unsigned int i = info->rbuf_current;
4781        unsigned int count;
4782
4783        if (!desc_complete(info->rbufs[i]))
4784                return false;
4785        count = desc_count(info->rbufs[i]);
4786        switch(info->params.mode) {
4787        case MGSL_MODE_MONOSYNC:
4788        case MGSL_MODE_BISYNC:
4789        case MGSL_MODE_XSYNC:
4790                /* ignore residue in byte synchronous modes */
4791                if (desc_residue(info->rbufs[i]))
4792                        count--;
4793                break;
4794        }
4795        DBGDATA(info, info->rbufs[i].buf, count, "rx");
4796        DBGINFO(("rx_get_buf size=%d\n", count));
4797        if (count)
4798                ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4799                                  info->flag_buf, count);
4800        free_rbufs(info, i, i);
4801        return true;
4802}
4803
4804static void reset_tbufs(struct slgt_info *info)
4805{
4806        unsigned int i;
4807        info->tbuf_current = 0;
4808        for (i=0 ; i < info->tbuf_count ; i++) {
4809                info->tbufs[i].status = 0;
4810                info->tbufs[i].count  = 0;
4811        }
4812}
4813
4814/*
4815 * return number of free transmit DMA buffers
4816 */
4817static unsigned int free_tbuf_count(struct slgt_info *info)
4818{
4819        unsigned int count = 0;
4820        unsigned int i = info->tbuf_current;
4821
4822        do
4823        {
4824                if (desc_count(info->tbufs[i]))
4825                        break; /* buffer in use */
4826                ++count;
4827                if (++i == info->tbuf_count)
4828                        i=0;
4829        } while (i != info->tbuf_current);
4830
4831        /* if tx DMA active, last zero count buffer is in use */
4832        if (count && (rd_reg32(info, TDCSR) & BIT0))
4833                --count;
4834
4835        return count;
4836}
4837
4838/*
4839 * return number of bytes in unsent transmit DMA buffers
4840 * and the serial controller tx FIFO
4841 */
4842static unsigned int tbuf_bytes(struct slgt_info *info)
4843{
4844        unsigned int total_count = 0;
4845        unsigned int i = info->tbuf_current;
4846        unsigned int reg_value;
4847        unsigned int count;
4848        unsigned int active_buf_count = 0;
4849
4850        /*
4851         * Add descriptor counts for all tx DMA buffers.
4852         * If count is zero (cleared by DMA controller after read),
4853         * the buffer is complete or is actively being read from.
4854         *
4855         * Record buf_count of last buffer with zero count starting
4856         * from current ring position. buf_count is mirror
4857         * copy of count and is not cleared by serial controller.
4858         * If DMA controller is active, that buffer is actively
4859         * being read so add to total.
4860         */
4861        do {
4862                count = desc_count(info->tbufs[i]);
4863                if (count)
4864                        total_count += count;
4865                else if (!total_count)
4866                        active_buf_count = info->tbufs[i].buf_count;
4867                if (++i == info->tbuf_count)
4868                        i = 0;
4869        } while (i != info->tbuf_current);
4870
4871        /* read tx DMA status register */
4872        reg_value = rd_reg32(info, TDCSR);
4873
4874        /* if tx DMA active, last zero count buffer is in use */
4875        if (reg_value & BIT0)
4876                total_count += active_buf_count;
4877
4878        /* add tx FIFO count = reg_value[15..8] */
4879        total_count += (reg_value >> 8) & 0xff;
4880
4881        /* if transmitter active add one byte for shift register */
4882        if (info->tx_active)
4883                total_count++;
4884
4885        return total_count;
4886}
4887
4888/*
4889 * load data into transmit DMA buffer ring and start transmitter if needed
4890 * return true if data accepted, otherwise false (buffers full)
4891 */
4892static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4893{
4894        unsigned short count;
4895        unsigned int i;
4896        struct slgt_desc *d;
4897
4898        /* check required buffer space */
4899        if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4900                return false;
4901
4902        DBGDATA(info, buf, size, "tx");
4903
4904        /*
4905         * copy data to one or more DMA buffers in circular ring
4906         * tbuf_start   = first buffer for this data
4907         * tbuf_current = next free buffer
4908         *
4909         * Copy all data before making data visible to DMA controller by
4910         * setting descriptor count of the first buffer.
4911         * This prevents an active DMA controller from reading the first DMA
4912         * buffers of a frame and stopping before the final buffers are filled.
4913         */
4914
4915        info->tbuf_start = i = info->tbuf_current;
4916
4917        while (size) {
4918                d = &info->tbufs[i];
4919
4920                count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4921                memcpy(d->buf, buf, count);
4922
4923                size -= count;
4924                buf  += count;
4925
4926                /*
4927                 * set EOF bit for last buffer of HDLC frame or
4928                 * for every buffer in raw mode
4929                 */
4930                if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4931                    info->params.mode == MGSL_MODE_RAW)
4932                        set_desc_eof(*d, 1);
4933                else
4934                        set_desc_eof(*d, 0);
4935
4936                /* set descriptor count for all but first buffer */
4937                if (i != info->tbuf_start)
4938                        set_desc_count(*d, count);
4939                d->buf_count = count;
4940
4941                if (++i == info->tbuf_count)
4942                        i = 0;
4943        }
4944
4945        info->tbuf_current = i;
4946
4947        /* set first buffer count to make new data visible to DMA controller */
4948        d = &info->tbufs[info->tbuf_start];
4949        set_desc_count(*d, d->buf_count);
4950
4951        /* start transmitter if needed and update transmit timeout */
4952        if (!info->tx_active)
4953                tx_start(info);
4954        update_tx_timer(info);
4955
4956        return true;
4957}
4958
4959static int register_test(struct slgt_info *info)
4960{
4961        static unsigned short patterns[] =
4962                {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4963        static unsigned int count = ARRAY_SIZE(patterns);
4964        unsigned int i;
4965        int rc = 0;
4966
4967        for (i=0 ; i < count ; i++) {
4968                wr_reg16(info, TIR, patterns[i]);
4969                wr_reg16(info, BDR, patterns[(i+1)%count]);
4970                if ((rd_reg16(info, TIR) != patterns[i]) ||
4971                    (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4972                        rc = -ENODEV;
4973                        break;
4974                }
4975        }
4976        info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4977        info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4978        return rc;
4979}
4980
4981static int irq_test(struct slgt_info *info)
4982{
4983        unsigned long timeout;
4984        unsigned long flags;
4985        struct tty_struct *oldtty = info->port.tty;
4986        u32 speed = info->params.data_rate;
4987
4988        info->params.data_rate = 921600;
4989        info->port.tty = NULL;
4990
4991        spin_lock_irqsave(&info->lock, flags);
4992        async_mode(info);
4993        slgt_irq_on(info, IRQ_TXIDLE);
4994
4995        /* enable transmitter */
4996        wr_reg16(info, TCR,
4997                (unsigned short)(rd_reg16(info, TCR) | BIT1));
4998
4999        /* write one byte and wait for tx idle */
5000        wr_reg16(info, TDR, 0);

5001
5002        /* assume failure */
5003        info->init_error = DiagStatus_IrqFailure;
5004        info->irq_occurred = false;
5005
5006        spin_unlock_irqrestore(&info->lock, flags);
5007
5008        timeout=100;
5009        while(timeout-- && !info->irq_occurred)
5010                msleep_interruptible(10);
5011
5012        spin_lock_irqsave(&info->lock,flags);
5013        reset_port(info);
5014        spin_unlock_irqrestore(&info->lock,flags);
5015
5016        info->params.data_rate = speed;
5017        info->port.tty = oldtty;
5018
5019        info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5020        return info->irq_occurred ? 0 : -ENODEV;
5021}
5022
5023static int loopback_test_rx(struct slgt_info *info)
5024{
5025        unsigned char *src, *dest;
5026        int count;
5027
5028        if (desc_complete(info->rbufs[0])) {
5029                count = desc_count(info->rbufs[0]);
5030                src   = info->rbufs[0].buf;
5031                dest  = info->tmp_rbuf;
5032
5033                for( ; count ; count-=2, src+=2) {
5034                        /* src=data byte (src+1)=status byte */
5035                        if (!(*(src+1) & (BIT9 + BIT8))) {
5036                                *dest = *src;
5037                                dest++;
5038                                info->tmp_rbuf_count++;
5039                        }
5040                }
5041                DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5042                return 1;
5043        }
5044        return 0;
5045}
5046
5047static int loopback_test(struct slgt_info *info)
5048{
5049#define TESTFRAMESIZE 20
5050
5051        unsigned long timeout;
5052        u16 count = TESTFRAMESIZE;
5053        unsigned char buf[TESTFRAMESIZE];
5054        int rc = -ENODEV;
5055        unsigned long flags;
5056
5057        struct tty_struct *oldtty = info->port.tty;
5058        MGSL_PARAMS params;
5059
5060        memcpy(&params, &info->params, sizeof(params));
5061
5062        info->params.mode = MGSL_MODE_ASYNC;
5063        info->params.data_rate = 921600;
5064        info->params.loopback = 1;
5065        info->port.tty = NULL;
5066
5067        /* build and send transmit frame */
5068        for (count = 0; count < TESTFRAMESIZE; ++count)
5069                buf[count] = (unsigned char)count;
5070
5071        info->tmp_rbuf_count = 0;
5072        memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5073
5074        /* program hardware for HDLC and enabled receiver */
5075        spin_lock_irqsave(&info->lock,flags);
5076        async_mode(info);
5077        rx_start(info);
5078        tx_load(info, buf, count);
5079        spin_unlock_irqrestore(&info->lock, flags);
5080
5081        /* wait for receive complete */
5082        for (timeout = 100; timeout; --timeout) {
5083                msleep_interruptible(10);
5084                if (loopback_test_rx(info)) {
5085                        rc = 0;
5086                        break;
5087                }
5088        }
5089
5090        /* verify received frame length and contents */
5091        if (!rc && (info->tmp_rbuf_count != count ||
5092                  memcmp(buf, info->tmp_rbuf, count))) {
5093                rc = -ENODEV;
5094        }
5095
5096        spin_lock_irqsave(&info->lock,flags);
5097        reset_adapter(info);
5098        spin_unlock_irqrestore(&info->lock,flags);
5099
5100        memcpy(&info->params, &params, sizeof(info->params));
5101        info->port.tty = oldtty;
5102
5103        info->init_error = rc ? DiagStatus_DmaFailure : 0;
5104        return rc;
5105}
5106
5107static int adapter_test(struct slgt_info *info)
5108{
5109        DBGINFO(("testing %s\n", info->device_name));
5110        if (register_test(info) < 0) {
5111                printk("register test failure %s addr=%08X\n",
5112                        info->device_name, info->phys_reg_addr);
5113        } else if (irq_test(info) < 0) {
5114                printk("IRQ test failure %s IRQ=%d\n",
5115                        info->device_name, info->irq_level);
5116        } else if (loopback_test(info) < 0) {
5117                printk("loopback test failure %s\n", info->device_name);
5118        }
5119        return info->init_error;
5120}
5121
5122/*
5123 * transmit timeout handler
5124 */
5125static void tx_timeout(unsigned long context)
5126{
5127        struct slgt_info *info = (struct slgt_info*)context;
5128        unsigned long flags;
5129
5130        DBGINFO(("%s tx_timeout\n", info->device_name));
5131        if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5132                info->icount.txtimeout++;
5133        }
5134        spin_lock_irqsave(&info->lock,flags);
5135        tx_stop(info);
5136        spin_unlock_irqrestore(&info->lock,flags);
5137
5138#if SYNCLINK_GENERIC_HDLC
5139        if (info->netcount)
5140                hdlcdev_tx_done(info);
5141        else
5142#endif
5143                bh_transmit(info);
5144}
5145
5146/*
5147 * receive buffer polling timer
5148 */
5149static void rx_timeout(unsigned long context)
5150{
5151        struct slgt_info *info = (struct slgt_info*)context;
5152        unsigned long flags;
5153
5154        DBGINFO(("%s rx_timeout\n", info->device_name));
5155        spin_lock_irqsave(&info->lock, flags);
5156        info->pending_bh |= BH_RECEIVE;
5157        spin_unlock_irqrestore(&info->lock, flags);
5158        bh_handler(&info->task);
5159}
5160
5161