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24#ifndef __LINUX_XHCI_HCD_H
25#define __LINUX_XHCI_HCD_H
26
27#include <linux/usb.h>
28#include <linux/timer.h>
29#include <linux/kernel.h>
30#include <linux/usb/hcd.h>
31
32#include <asm-generic/io-64-nonatomic-lo-hi.h>
33
34
35#include "xhci-ext-caps.h"
36#include "pci-quirks.h"
37
38
39#define XHCI_SBRN_OFFSET (0x60)
40
41
42#define MAX_HC_SLOTS 256
43
44#define MAX_HC_PORTS 127
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62
63struct xhci_cap_regs {
64 __le32 hc_capbase;
65 __le32 hcs_params1;
66 __le32 hcs_params2;
67 __le32 hcs_params3;
68 __le32 hcc_params;
69 __le32 db_off;
70 __le32 run_regs_off;
71 __le32 hcc_params2;
72
73};
74
75
76
77#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
78
79#define HC_VERSION(p) (((p) >> 16) & 0xffff)
80
81
82
83#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
84#define HCS_SLOTS_MASK 0xff
85
86#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
87
88#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
89
90
91
92
93#define HCS_IST(p) (((p) >> 0) & 0xf)
94
95#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
96
97
98
99#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
100
101
102
103#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
104
105#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
106
107
108
109#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
110
111#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
112
113
114
115#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
116
117#define HCC_PPC(p) ((p) & (1 << 3))
118
119#define HCS_INDICATOR(p) ((p) & (1 << 4))
120
121#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
122
123#define HCC_LTC(p) ((p) & (1 << 6))
124
125#define HCC_NSS(p) ((p) & (1 << 7))
126
127#define HCC_SPC(p) ((p) & (1 << 9))
128
129#define HCC_CFC(p) ((p) & (1 << 11))
130
131#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
132
133#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
134
135
136#define DBOFF_MASK (~0x3)
137
138
139#define RTSOFF_MASK (~0x1f)
140
141
142
143#define HCC2_U3C(p) ((p) & (1 << 0))
144
145#define HCC2_CMC(p) ((p) & (1 << 1))
146
147#define HCC2_FSC(p) ((p) & (1 << 2))
148
149#define HCC2_CTC(p) ((p) & (1 << 3))
150
151#define HCC2_LEC(p) ((p) & (1 << 4))
152
153#define HCC2_CIC(p) ((p) & (1 << 5))
154
155#define HCC2_ETC(p) ((p) & (1 << 6))
156
157
158#define NUM_PORT_REGS 4
159
160#define PORTSC 0
161#define PORTPMSC 1
162#define PORTLI 2
163#define PORTHLPMC 3
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186
187struct xhci_op_regs {
188 __le32 command;
189 __le32 status;
190 __le32 page_size;
191 __le32 reserved1;
192 __le32 reserved2;
193 __le32 dev_notification;
194 __le64 cmd_ring;
195
196 __le32 reserved3[4];
197 __le64 dcbaa_ptr;
198 __le32 config_reg;
199
200 __le32 reserved4[241];
201
202 __le32 port_status_base;
203 __le32 port_power_base;
204 __le32 port_link_base;
205 __le32 reserved5;
206
207 __le32 reserved6[NUM_PORT_REGS*254];
208};
209
210
211
212#define CMD_RUN XHCI_CMD_RUN
213
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215
216
217#define CMD_RESET (1 << 1)
218
219#define CMD_EIE XHCI_CMD_EIE
220
221#define CMD_HSEIE XHCI_CMD_HSEIE
222
223
224#define CMD_LRESET (1 << 7)
225
226#define CMD_CSS (1 << 8)
227#define CMD_CRS (1 << 9)
228
229#define CMD_EWE XHCI_CMD_EWE
230
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234
235#define CMD_PM_INDEX (1 << 11)
236
237#define CMD_ETE (1 << 14)
238
239
240
241#define IMAN_IE (1 << 1)
242#define IMAN_IP (1 << 0)
243
244
245
246#define STS_HALT XHCI_STS_HALT
247
248#define STS_FATAL (1 << 2)
249
250#define STS_EINT (1 << 3)
251
252#define STS_PORT (1 << 4)
253
254
255#define STS_SAVE (1 << 8)
256
257#define STS_RESTORE (1 << 9)
258
259#define STS_SRE (1 << 10)
260
261#define STS_CNR XHCI_STS_CNR
262
263#define STS_HCE (1 << 12)
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270
271#define DEV_NOTE_MASK (0xffff)
272#define ENABLE_DEV_NOTE(x) (1 << (x))
273
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275
276#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
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280
281#define CMD_RING_PAUSE (1 << 1)
282
283#define CMD_RING_ABORT (1 << 2)
284
285#define CMD_RING_RUNNING (1 << 3)
286
287
288#define CMD_RING_RSVD_BITS (0x3f)
289
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291
292#define MAX_DEVS(p) ((p) & 0xff)
293
294#define CONFIG_U3E (1 << 8)
295
296#define CONFIG_CIE (1 << 9)
297
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300
301#define PORT_CONNECT (1 << 0)
302
303#define PORT_PE (1 << 1)
304
305
306#define PORT_OC (1 << 3)
307
308#define PORT_RESET (1 << 4)
309
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312
313#define PORT_PLS_MASK (0xf << 5)
314#define XDEV_U0 (0x0 << 5)
315#define XDEV_U2 (0x2 << 5)
316#define XDEV_U3 (0x3 << 5)
317#define XDEV_INACTIVE (0x6 << 5)
318#define XDEV_POLLING (0x7 << 5)
319#define XDEV_COMP_MODE (0xa << 5)
320#define XDEV_RESUME (0xf << 5)
321
322#define PORT_POWER (1 << 9)
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331#define DEV_SPEED_MASK (0xf << 10)
332#define XDEV_FS (0x1 << 10)
333#define XDEV_LS (0x2 << 10)
334#define XDEV_HS (0x3 << 10)
335#define XDEV_SS (0x4 << 10)
336#define XDEV_SSP (0x5 << 10)
337#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
338#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
339#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
340#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
341#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
342#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
343#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
344#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
345
346
347#define SLOT_SPEED_FS (XDEV_FS << 10)
348#define SLOT_SPEED_LS (XDEV_LS << 10)
349#define SLOT_SPEED_HS (XDEV_HS << 10)
350#define SLOT_SPEED_SS (XDEV_SS << 10)
351#define SLOT_SPEED_SSP (XDEV_SSP << 10)
352
353#define PORT_LED_OFF (0 << 14)
354#define PORT_LED_AMBER (1 << 14)
355#define PORT_LED_GREEN (2 << 14)
356#define PORT_LED_MASK (3 << 14)
357
358#define PORT_LINK_STROBE (1 << 16)
359
360#define PORT_CSC (1 << 17)
361
362#define PORT_PEC (1 << 18)
363
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367
368#define PORT_WRC (1 << 19)
369
370#define PORT_OCC (1 << 20)
371
372#define PORT_RC (1 << 21)
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386#define PORT_PLC (1 << 22)
387
388#define PORT_CEC (1 << 23)
389
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393#define PORT_CAS (1 << 24)
394
395#define PORT_WKCONN_E (1 << 25)
396
397#define PORT_WKDISC_E (1 << 26)
398
399#define PORT_WKOC_E (1 << 27)
400
401
402#define PORT_DEV_REMOVE (1 << 30)
403
404#define PORT_WR (1 << 31)
405
406
407#define DUPLICATE_ENTRY ((u8)(-1))
408
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412
413#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
414#define PORT_U1_TIMEOUT_MASK 0xff
415
416#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
417#define PORT_U2_TIMEOUT_MASK (0xff << 8)
418
419
420
421#define PORT_L1S_MASK 7
422#define PORT_L1S_SUCCESS 1
423#define PORT_RWE (1 << 3)
424#define PORT_HIRD(p) (((p) & 0xf) << 4)
425#define PORT_HIRD_MASK (0xf << 4)
426#define PORT_L1DS_MASK (0xff << 8)
427#define PORT_L1DS(p) (((p) & 0xff) << 8)
428#define PORT_HLE (1 << 16)
429
430
431#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
432#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
433
434
435#define PORT_HIRDM(p)((p) & 3)
436#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
437#define PORT_BESLD(p)(((p) & 0xf) << 10)
438
439
440#define XHCI_L1_TIMEOUT 512
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451
452#define XHCI_DEFAULT_BESL 4
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471struct xhci_intr_reg {
472 __le32 irq_pending;
473 __le32 irq_control;
474 __le32 erst_size;
475 __le32 rsvd;
476 __le64 erst_base;
477 __le64 erst_dequeue;
478};
479
480
481#define ER_IRQ_PENDING(p) ((p) & 0x1)
482
483
484#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
485#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
486#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
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493#define ER_IRQ_INTERVAL_MASK (0xffff)
494
495#define ER_IRQ_COUNTER_MASK (0xffff << 16)
496
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499#define ERST_SIZE_MASK (0xffff << 16)
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505#define ERST_DESI_MASK (0x7)
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509#define ERST_EHB (1 << 3)
510#define ERST_PTR_MASK (0xf)
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521struct xhci_run_regs {
522 __le32 microframe_index;
523 __le32 rsvd[7];
524 struct xhci_intr_reg ir_set[128];
525};
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536struct xhci_doorbell_array {
537 __le32 doorbell[256];
538};
539
540#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
541#define DB_VALUE_HOST 0x00000000
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551struct xhci_protocol_caps {
552 u32 revision;
553 u32 name_string;
554 u32 port_info;
555};
556
557#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
558#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
559#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
560#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
561#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
562
563#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
564#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
565#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
566#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
567#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
568#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
569
570#define PLT_MASK (0x03 << 6)
571#define PLT_SYM (0x00 << 6)
572#define PLT_ASYM_RX (0x02 << 6)
573#define PLT_ASYM_TX (0x03 << 6)
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585struct xhci_container_ctx {
586 unsigned type;
587#define XHCI_CTX_TYPE_DEVICE 0x1
588#define XHCI_CTX_TYPE_INPUT 0x2
589
590 int size;
591
592 u8 *bytes;
593 dma_addr_t dma;
594};
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607struct xhci_slot_ctx {
608 __le32 dev_info;
609 __le32 dev_info2;
610 __le32 tt_info;
611 __le32 dev_state;
612
613 __le32 reserved[4];
614};
615
616
617
618#define ROUTE_STRING_MASK (0xfffff)
619
620#define DEV_SPEED (0xf << 20)
621
622
623#define DEV_MTT (0x1 << 25)
624
625#define DEV_HUB (0x1 << 26)
626
627#define LAST_CTX_MASK (0x1f << 27)
628#define LAST_CTX(p) ((p) << 27)
629#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
630#define SLOT_FLAG (1 << 0)
631#define EP0_FLAG (1 << 1)
632
633
634
635#define MAX_EXIT (0xffff)
636
637#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
638#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
639
640#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
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647
648#define TT_SLOT (0xff)
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653#define TT_PORT (0xff << 8)
654#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
655
656
657
658#define DEV_ADDR_MASK (0xff)
659
660
661#define SLOT_STATE (0x1f << 27)
662#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
663
664#define SLOT_STATE_DISABLED 0
665#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
666#define SLOT_STATE_DEFAULT 1
667#define SLOT_STATE_ADDRESSED 2
668#define SLOT_STATE_CONFIGURED 3
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688struct xhci_ep_ctx {
689 __le32 ep_info;
690 __le32 ep_info2;
691 __le64 deq;
692 __le32 tx_info;
693
694 __le32 reserved[3];
695};
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706
707#define EP_STATE_MASK (0xf)
708#define EP_STATE_DISABLED 0
709#define EP_STATE_RUNNING 1
710#define EP_STATE_HALTED 2
711#define EP_STATE_STOPPED 3
712#define EP_STATE_ERROR 4
713#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
714
715
716#define EP_MULT(p) (((p) & 0x3) << 8)
717#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
718
719
720
721#define EP_INTERVAL(p) (((p) & 0xff) << 16)
722#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
723#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
724#define EP_MAXPSTREAMS_MASK (0x1f << 10)
725#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
726
727#define EP_HAS_LSA (1 << 15)
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731
732
733
734#define FORCE_EVENT (0x1)
735#define ERROR_COUNT(p) (((p) & 0x3) << 1)
736#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
737#define EP_TYPE(p) ((p) << 3)
738#define ISOC_OUT_EP 1
739#define BULK_OUT_EP 2
740#define INT_OUT_EP 3
741#define CTRL_EP 4
742#define ISOC_IN_EP 5
743#define BULK_IN_EP 6
744#define INT_IN_EP 7
745
746
747#define MAX_BURST(p) (((p)&0xff) << 8)
748#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
749#define MAX_PACKET(p) (((p)&0xffff) << 16)
750#define MAX_PACKET_MASK (0xffff << 16)
751#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
752
753
754#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
755#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
756#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
757#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
758
759
760#define EP_CTX_CYCLE_MASK (1 << 0)
761#define SCTX_DEQ_MASK (~0xfL)
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771struct xhci_input_control_ctx {
772 __le32 drop_flags;
773 __le32 add_flags;
774 __le32 rsvd2[6];
775};
776
777#define EP_IS_ADDED(ctrl_ctx, i) \
778 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
779#define EP_IS_DROPPED(ctrl_ctx, i) \
780 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
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784
785
786struct xhci_command {
787
788 struct xhci_container_ctx *in_ctx;
789 u32 status;
790 int slot_id;
791
792
793
794 struct completion *completion;
795 union xhci_trb *command_trb;
796 struct list_head cmd_list;
797};
798
799
800#define DROP_EP(x) (0x1 << x)
801
802#define ADD_EP(x) (0x1 << x)
803
804struct xhci_stream_ctx {
805
806 __le64 stream_ring;
807
808 __le32 reserved[2];
809};
810
811
812#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
813
814#define SCT_SEC_TR 0
815
816#define SCT_PRI_TR 1
817
818#define SCT_SSA_8 2
819#define SCT_SSA_16 3
820#define SCT_SSA_32 4
821#define SCT_SSA_64 5
822#define SCT_SSA_128 6
823#define SCT_SSA_256 7
824
825
826struct xhci_stream_info {
827 struct xhci_ring **stream_rings;
828
829 unsigned int num_streams;
830
831
832
833 struct xhci_stream_ctx *stream_ctx_array;
834 unsigned int num_stream_ctxs;
835 dma_addr_t ctx_array_dma;
836
837 struct radix_tree_root trb_address_map;
838 struct xhci_command *free_streams_command;
839};
840
841#define SMALL_STREAM_ARRAY_SIZE 256
842#define MEDIUM_STREAM_ARRAY_SIZE 1024
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848
849
850struct xhci_bw_info {
851
852 unsigned int ep_interval;
853
854 unsigned int mult;
855 unsigned int num_packets;
856 unsigned int max_packet_size;
857 unsigned int max_esit_payload;
858 unsigned int type;
859};
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865
866#define FS_BLOCK 1
867#define HS_BLOCK 4
868#define SS_BLOCK 16
869#define DMI_BLOCK 32
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874
875
876#define DMI_OVERHEAD 8
877#define DMI_OVERHEAD_BURST 4
878#define SS_OVERHEAD 8
879#define SS_OVERHEAD_BURST 32
880#define HS_OVERHEAD 26
881#define FS_OVERHEAD 20
882#define LS_OVERHEAD 128
883
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886
887
888#define TT_HS_OVERHEAD (31 + 94)
889#define TT_DMI_OVERHEAD (25 + 12)
890
891
892#define FS_BW_LIMIT 1285
893#define TT_BW_LIMIT 1320
894#define HS_BW_LIMIT 1607
895#define SS_BW_LIMIT_IN 3906
896#define DMI_BW_LIMIT_IN 3906
897#define SS_BW_LIMIT_OUT 3906
898#define DMI_BW_LIMIT_OUT 3906
899
900
901#define FS_BW_RESERVED 10
902#define HS_BW_RESERVED 20
903#define SS_BW_RESERVED 10
904
905struct xhci_virt_ep {
906 struct xhci_ring *ring;
907
908 struct xhci_stream_info *stream_info;
909
910
911
912 struct xhci_ring *new_ring;
913 unsigned int ep_state;
914#define SET_DEQ_PENDING (1 << 0)
915#define EP_HALTED (1 << 1)
916#define EP_HALT_PENDING (1 << 2)
917
918#define EP_GETTING_STREAMS (1 << 3)
919#define EP_HAS_STREAMS (1 << 4)
920
921#define EP_GETTING_NO_STREAMS (1 << 5)
922
923 struct list_head cancelled_td_list;
924 struct xhci_td *stopped_td;
925 unsigned int stopped_stream;
926
927 struct timer_list stop_cmd_timer;
928 int stop_cmds_pending;
929 struct xhci_hcd *xhci;
930
931
932
933
934 struct xhci_segment *queued_deq_seg;
935 union xhci_trb *queued_deq_ptr;
936
937
938
939
940
941
942
943 bool skip;
944
945 struct xhci_bw_info bw_info;
946 struct list_head bw_endpoint_list;
947
948 int next_frame_id;
949
950 bool use_extended_tbc;
951};
952
953enum xhci_overhead_type {
954 LS_OVERHEAD_TYPE = 0,
955 FS_OVERHEAD_TYPE,
956 HS_OVERHEAD_TYPE,
957};
958
959struct xhci_interval_bw {
960 unsigned int num_packets;
961
962
963
964 struct list_head endpoints;
965
966 unsigned int overhead[3];
967};
968
969#define XHCI_MAX_INTERVAL 16
970
971struct xhci_interval_bw_table {
972 unsigned int interval0_esit_payload;
973 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
974
975 unsigned int bw_used;
976 unsigned int ss_bw_in;
977 unsigned int ss_bw_out;
978};
979
980
981struct xhci_virt_device {
982 struct usb_device *udev;
983
984
985
986
987
988
989
990
991 struct xhci_container_ctx *out_ctx;
992
993 struct xhci_container_ctx *in_ctx;
994
995 struct xhci_ring **ring_cache;
996 int num_rings_cached;
997#define XHCI_MAX_RINGS_CACHED 31
998 struct xhci_virt_ep eps[31];
999 u8 fake_port;
1000 u8 real_port;
1001 struct xhci_interval_bw_table *bw_table;
1002 struct xhci_tt_bw_info *tt_info;
1003
1004 u16 current_mel;
1005};
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015struct xhci_root_port_bw_info {
1016 struct list_head tts;
1017 unsigned int num_active_tts;
1018 struct xhci_interval_bw_table bw_table;
1019};
1020
1021struct xhci_tt_bw_info {
1022 struct list_head tt_list;
1023 int slot_id;
1024 int ttport;
1025 struct xhci_interval_bw_table bw_table;
1026 int active_eps;
1027};
1028
1029
1030
1031
1032
1033
1034struct xhci_device_context_array {
1035
1036 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1037
1038 dma_addr_t dma;
1039};
1040
1041
1042
1043
1044
1045
1046
1047struct xhci_transfer_event {
1048
1049 __le64 buffer;
1050 __le32 transfer_len;
1051
1052 __le32 flags;
1053};
1054
1055
1056
1057#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1058
1059
1060#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1061
1062
1063#define COMP_CODE_MASK (0xff << 24)
1064#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1065#define COMP_SUCCESS 1
1066
1067#define COMP_DB_ERR 2
1068
1069#define COMP_BABBLE 3
1070
1071#define COMP_TX_ERR 4
1072
1073#define COMP_TRB_ERR 5
1074
1075#define COMP_STALL 6
1076
1077#define COMP_ENOMEM 7
1078
1079#define COMP_BW_ERR 8
1080
1081#define COMP_ENOSLOTS 9
1082
1083#define COMP_STREAM_ERR 10
1084
1085#define COMP_EBADSLT 11
1086
1087#define COMP_EBADEP 12
1088
1089#define COMP_SHORT_TX 13
1090
1091#define COMP_UNDERRUN 14
1092
1093#define COMP_OVERRUN 15
1094
1095#define COMP_VF_FULL 16
1096
1097#define COMP_EINVAL 17
1098
1099#define COMP_BW_OVER 18
1100
1101#define COMP_CTX_STATE 19
1102
1103#define COMP_PING_ERR 20
1104
1105#define COMP_ER_FULL 21
1106
1107#define COMP_DEV_ERR 22
1108
1109#define COMP_MISSED_INT 23
1110
1111#define COMP_CMD_STOP 24
1112
1113#define COMP_CMD_ABORT 25
1114
1115#define COMP_STOP 26
1116
1117#define COMP_STOP_INVAL 27
1118
1119#define COMP_STOP_SHORT 28
1120
1121#define COMP_MEL_ERR 29
1122
1123
1124#define COMP_BUFF_OVER 31
1125
1126#define COMP_ISSUES 32
1127
1128#define COMP_UNKNOWN 33
1129
1130#define COMP_STRID_ERR 34
1131
1132#define COMP_2ND_BW_ERR 35
1133
1134#define COMP_SPLIT_ERR 36
1135
1136struct xhci_link_trb {
1137
1138 __le64 segment_ptr;
1139 __le32 intr_target;
1140 __le32 control;
1141};
1142
1143
1144#define LINK_TOGGLE (0x1<<1)
1145
1146
1147struct xhci_event_cmd {
1148
1149 __le64 cmd_trb;
1150 __le32 status;
1151 __le32 flags;
1152};
1153
1154
1155
1156
1157#define TRB_BSR (1<<9)
1158enum xhci_setup_dev {
1159 SETUP_CONTEXT_ONLY,
1160 SETUP_CONTEXT_ADDRESS,
1161};
1162
1163
1164
1165#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1166#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1167
1168
1169#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1170#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1171
1172#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1173#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1174#define LAST_EP_INDEX 30
1175
1176
1177#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1178#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1179#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1180
1181
1182
1183
1184#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1185
1186
1187
1188#define TRB_LEN(p) ((p) & 0x1ffff)
1189
1190#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1191
1192#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1193
1194#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1195#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1196
1197#define TRB_TBC(p) (((p) & 0x3) << 7)
1198#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1199
1200
1201#define TRB_CYCLE (1<<0)
1202
1203
1204
1205
1206#define TRB_ENT (1<<1)
1207
1208#define TRB_ISP (1<<2)
1209
1210#define TRB_NO_SNOOP (1<<3)
1211
1212#define TRB_CHAIN (1<<4)
1213
1214#define TRB_IOC (1<<5)
1215
1216#define TRB_IDT (1<<6)
1217
1218
1219#define TRB_BEI (1<<9)
1220
1221
1222#define TRB_DIR_IN (1<<16)
1223#define TRB_TX_TYPE(p) ((p) << 16)
1224#define TRB_DATA_OUT 2
1225#define TRB_DATA_IN 3
1226
1227
1228#define TRB_SIA (1<<31)
1229#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1230
1231struct xhci_generic_trb {
1232 __le32 field[4];
1233};
1234
1235union xhci_trb {
1236 struct xhci_link_trb link;
1237 struct xhci_transfer_event trans_event;
1238 struct xhci_event_cmd event_cmd;
1239 struct xhci_generic_trb generic;
1240};
1241
1242
1243#define TRB_TYPE_BITMASK (0xfc00)
1244#define TRB_TYPE(p) ((p) << 10)
1245#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1246
1247
1248#define TRB_NORMAL 1
1249
1250#define TRB_SETUP 2
1251
1252#define TRB_DATA 3
1253
1254#define TRB_STATUS 4
1255
1256#define TRB_ISOC 5
1257
1258#define TRB_LINK 6
1259#define TRB_EVENT_DATA 7
1260
1261#define TRB_TR_NOOP 8
1262
1263
1264#define TRB_ENABLE_SLOT 9
1265
1266#define TRB_DISABLE_SLOT 10
1267
1268#define TRB_ADDR_DEV 11
1269
1270#define TRB_CONFIG_EP 12
1271
1272#define TRB_EVAL_CONTEXT 13
1273
1274#define TRB_RESET_EP 14
1275
1276#define TRB_STOP_RING 15
1277
1278#define TRB_SET_DEQ 16
1279
1280#define TRB_RESET_DEV 17
1281
1282#define TRB_FORCE_EVENT 18
1283
1284#define TRB_NEG_BANDWIDTH 19
1285
1286#define TRB_SET_LT 20
1287
1288#define TRB_GET_BW 21
1289
1290#define TRB_FORCE_HEADER 22
1291
1292#define TRB_CMD_NOOP 23
1293
1294
1295
1296#define TRB_TRANSFER 32
1297
1298#define TRB_COMPLETION 33
1299
1300#define TRB_PORT_STATUS 34
1301
1302#define TRB_BANDWIDTH_EVENT 35
1303
1304#define TRB_DOORBELL 36
1305
1306#define TRB_HC_EVENT 37
1307
1308#define TRB_DEV_NOTE 38
1309
1310#define TRB_MFINDEX_WRAP 39
1311
1312
1313
1314#define TRB_NEC_CMD_COMP 48
1315
1316#define TRB_NEC_GET_FW 49
1317
1318#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1319
1320#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1321 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1322#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1323 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1324
1325#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1326#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1327
1328
1329
1330
1331
1332
1333#define TRBS_PER_SEGMENT 256
1334
1335#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1336#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1337#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1338
1339#define TRB_MAX_BUFF_SHIFT 16
1340#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1341
1342#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1343 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1344
1345struct xhci_segment {
1346 union xhci_trb *trbs;
1347
1348 struct xhci_segment *next;
1349 dma_addr_t dma;
1350
1351 dma_addr_t bounce_dma;
1352 void *bounce_buf;
1353 unsigned int bounce_offs;
1354 unsigned int bounce_len;
1355};
1356
1357struct xhci_td {
1358 struct list_head td_list;
1359 struct list_head cancelled_td_list;
1360 struct urb *urb;
1361 struct xhci_segment *start_seg;
1362 union xhci_trb *first_trb;
1363 union xhci_trb *last_trb;
1364 struct xhci_segment *bounce_seg;
1365
1366 bool urb_length_set;
1367};
1368
1369
1370#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1371
1372
1373struct xhci_cd {
1374 struct xhci_command *command;
1375 union xhci_trb *cmd_trb;
1376};
1377
1378struct xhci_dequeue_state {
1379 struct xhci_segment *new_deq_seg;
1380 union xhci_trb *new_deq_ptr;
1381 int new_cycle_state;
1382};
1383
1384enum xhci_ring_type {
1385 TYPE_CTRL = 0,
1386 TYPE_ISOC,
1387 TYPE_BULK,
1388 TYPE_INTR,
1389 TYPE_STREAM,
1390 TYPE_COMMAND,
1391 TYPE_EVENT,
1392};
1393
1394struct xhci_ring {
1395 struct xhci_segment *first_seg;
1396 struct xhci_segment *last_seg;
1397 union xhci_trb *enqueue;
1398 struct xhci_segment *enq_seg;
1399 unsigned int enq_updates;
1400 union xhci_trb *dequeue;
1401 struct xhci_segment *deq_seg;
1402 unsigned int deq_updates;
1403 struct list_head td_list;
1404
1405
1406
1407
1408
1409 u32 cycle_state;
1410 unsigned int stream_id;
1411 unsigned int num_segs;
1412 unsigned int num_trbs_free;
1413 unsigned int num_trbs_free_temp;
1414 unsigned int bounce_buf_len;
1415 enum xhci_ring_type type;
1416 bool last_td_was_short;
1417 struct radix_tree_root *trb_address_map;
1418};
1419
1420struct xhci_erst_entry {
1421
1422 __le64 seg_addr;
1423 __le32 seg_size;
1424
1425 __le32 rsvd;
1426};
1427
1428struct xhci_erst {
1429 struct xhci_erst_entry *entries;
1430 unsigned int num_entries;
1431
1432 dma_addr_t erst_dma_addr;
1433
1434 unsigned int erst_size;
1435};
1436
1437struct xhci_scratchpad {
1438 u64 *sp_array;
1439 dma_addr_t sp_dma;
1440 void **sp_buffers;
1441 dma_addr_t *sp_dma_buffers;
1442};
1443
1444struct urb_priv {
1445 int length;
1446 int td_cnt;
1447 struct xhci_td *td[0];
1448};
1449
1450
1451
1452
1453
1454
1455#define ERST_NUM_SEGS 1
1456
1457#define ERST_SIZE 64
1458
1459#define ERST_ENTRIES 1
1460
1461#define POLL_TIMEOUT 60
1462
1463#define XHCI_STOP_EP_CMD_TIMEOUT 5
1464
1465
1466struct s3_save {
1467 u32 command;
1468 u32 dev_nt;
1469 u64 dcbaa_ptr;
1470 u32 config_reg;
1471 u32 irq_pending;
1472 u32 irq_control;
1473 u32 erst_size;
1474 u64 erst_base;
1475 u64 erst_dequeue;
1476};
1477
1478
1479struct dev_info {
1480 u32 dev_id;
1481 struct list_head list;
1482};
1483
1484struct xhci_bus_state {
1485 unsigned long bus_suspended;
1486 unsigned long next_statechange;
1487
1488
1489
1490 u32 port_c_suspend;
1491 u32 suspended_ports;
1492 u32 port_remote_wakeup;
1493 unsigned long resume_done[USB_MAXCHILDREN];
1494
1495 unsigned long resuming_ports;
1496
1497 unsigned long rexit_ports;
1498 struct completion rexit_done[USB_MAXCHILDREN];
1499};
1500
1501
1502
1503
1504
1505
1506#define XHCI_MAX_REXIT_TIMEOUT (20 * 1000)
1507
1508static inline unsigned int hcd_index(struct usb_hcd *hcd)
1509{
1510 if (hcd->speed == HCD_USB3)
1511 return 0;
1512 else
1513 return 1;
1514}
1515
1516struct xhci_hub {
1517 u8 maj_rev;
1518 u8 min_rev;
1519 u32 *psi;
1520 u8 psi_count;
1521 u8 psi_uid_count;
1522};
1523
1524
1525struct xhci_hcd {
1526 struct usb_hcd *main_hcd;
1527 struct usb_hcd *shared_hcd;
1528
1529 struct xhci_cap_regs __iomem *cap_regs;
1530 struct xhci_op_regs __iomem *op_regs;
1531 struct xhci_run_regs __iomem *run_regs;
1532 struct xhci_doorbell_array __iomem *dba;
1533
1534 struct xhci_intr_reg __iomem *ir_set;
1535
1536
1537 __u32 hcs_params1;
1538 __u32 hcs_params2;
1539 __u32 hcs_params3;
1540 __u32 hcc_params;
1541 __u32 hcc_params2;
1542
1543 spinlock_t lock;
1544
1545
1546 u8 sbrn;
1547 u16 hci_version;
1548 u8 max_slots;
1549 u8 max_interrupters;
1550 u8 max_ports;
1551 u8 isoc_threshold;
1552 int event_ring_max;
1553 int addr_64;
1554
1555 int page_size;
1556
1557 int page_shift;
1558
1559 int msix_count;
1560 struct msix_entry *msix_entries;
1561
1562 struct clk *clk;
1563
1564 struct xhci_device_context_array *dcbaa;
1565 struct xhci_ring *cmd_ring;
1566 unsigned int cmd_ring_state;
1567#define CMD_RING_STATE_RUNNING (1 << 0)
1568#define CMD_RING_STATE_ABORTED (1 << 1)
1569#define CMD_RING_STATE_STOPPED (1 << 2)
1570 struct list_head cmd_list;
1571 unsigned int cmd_ring_reserved_trbs;
1572 struct timer_list cmd_timer;
1573 struct xhci_command *current_cmd;
1574 struct xhci_ring *event_ring;
1575 struct xhci_erst erst;
1576
1577 struct xhci_scratchpad *scratchpad;
1578
1579 struct list_head lpm_failed_devs;
1580
1581
1582
1583 struct mutex mutex;
1584
1585 struct xhci_command *lpm_command;
1586
1587 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1588
1589 struct xhci_root_port_bw_info *rh_bw;
1590
1591
1592 struct dma_pool *device_pool;
1593 struct dma_pool *segment_pool;
1594 struct dma_pool *small_streams_pool;
1595 struct dma_pool *medium_streams_pool;
1596
1597
1598 unsigned int xhc_state;
1599
1600 u32 command;
1601 struct s3_save s3;
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614#define XHCI_STATE_DYING (1 << 0)
1615#define XHCI_STATE_HALTED (1 << 1)
1616#define XHCI_STATE_REMOVING (1 << 2)
1617 unsigned int quirks;
1618#define XHCI_LINK_TRB_QUIRK (1 << 0)
1619#define XHCI_RESET_EP_QUIRK (1 << 1)
1620#define XHCI_NEC_HOST (1 << 2)
1621#define XHCI_AMD_PLL_FIX (1 << 3)
1622#define XHCI_SPURIOUS_SUCCESS (1 << 4)
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632#define XHCI_EP_LIMIT_QUIRK (1 << 5)
1633#define XHCI_BROKEN_MSI (1 << 6)
1634#define XHCI_RESET_ON_RESUME (1 << 7)
1635#define XHCI_SW_BW_CHECKING (1 << 8)
1636#define XHCI_AMD_0x96_HOST (1 << 9)
1637#define XHCI_TRUST_TX_LENGTH (1 << 10)
1638#define XHCI_LPM_SUPPORT (1 << 11)
1639#define XHCI_INTEL_HOST (1 << 12)
1640#define XHCI_SPURIOUS_REBOOT (1 << 13)
1641#define XHCI_COMP_MODE_QUIRK (1 << 14)
1642#define XHCI_AVOID_BEI (1 << 15)
1643#define XHCI_PLAT (1 << 16)
1644#define XHCI_SLOW_SUSPEND (1 << 17)
1645#define XHCI_SPURIOUS_WAKEUP (1 << 18)
1646
1647#define XHCI_BROKEN_STREAMS (1 << 19)
1648#define XHCI_PME_STUCK_QUIRK (1 << 20)
1649#define XHCI_MTK_HOST (1 << 21)
1650#define XHCI_SSIC_PORT_UNUSED (1 << 22)
1651#define XHCI_NO_64BIT_SUPPORT (1 << 23)
1652#define XHCI_MISSING_CAS (1 << 24)
1653 unsigned int num_active_eps;
1654 unsigned int limit_active_eps;
1655
1656 struct xhci_bus_state bus_state[2];
1657
1658 u8 *port_array;
1659
1660 __le32 __iomem **usb3_ports;
1661 unsigned int num_usb3_ports;
1662
1663 __le32 __iomem **usb2_ports;
1664 struct xhci_hub usb2_rhub;
1665 struct xhci_hub usb3_rhub;
1666 unsigned int num_usb2_ports;
1667
1668 unsigned sw_lpm_support:1;
1669
1670 unsigned hw_lpm_support:1;
1671
1672 u32 *ext_caps;
1673 unsigned int num_ext_caps;
1674
1675 struct timer_list comp_mode_recovery_timer;
1676 u32 port_status_u0;
1677
1678#define COMP_MODE_RCVRY_MSECS 2000
1679
1680
1681 unsigned long priv[0] __aligned(sizeof(s64));
1682};
1683
1684
1685struct xhci_driver_overrides {
1686 size_t extra_priv_size;
1687 int (*reset)(struct usb_hcd *hcd);
1688 int (*start)(struct usb_hcd *hcd);
1689};
1690
1691#define XHCI_CFC_DELAY 10
1692
1693
1694static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1695{
1696 struct usb_hcd *primary_hcd;
1697
1698 if (usb_hcd_is_primary_hcd(hcd))
1699 primary_hcd = hcd;
1700 else
1701 primary_hcd = hcd->primary_hcd;
1702
1703 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1704}
1705
1706static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1707{
1708 return xhci->main_hcd;
1709}
1710
1711#define xhci_dbg(xhci, fmt, args...) \
1712 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1713#define xhci_err(xhci, fmt, args...) \
1714 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1715#define xhci_warn(xhci, fmt, args...) \
1716 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1717#define xhci_warn_ratelimited(xhci, fmt, args...) \
1718 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1719#define xhci_info(xhci, fmt, args...) \
1720 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1732 __le64 __iomem *regs)
1733{
1734 return lo_hi_readq(regs);
1735}
1736static inline void xhci_write_64(struct xhci_hcd *xhci,
1737 const u64 val, __le64 __iomem *regs)
1738{
1739 lo_hi_writeq(val, regs);
1740}
1741
1742static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1743{
1744 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1745}
1746
1747
1748void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1749void xhci_print_registers(struct xhci_hcd *xhci);
1750void xhci_dbg_regs(struct xhci_hcd *xhci);
1751void xhci_print_run_regs(struct xhci_hcd *xhci);
1752void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1753void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1754void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1755void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1756void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1757void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1758void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1759void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1760char *xhci_get_slot_state(struct xhci_hcd *xhci,
1761 struct xhci_container_ctx *ctx);
1762void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1763 unsigned int slot_id, unsigned int ep_index,
1764 struct xhci_virt_ep *ep);
1765void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1766 const char *fmt, ...);
1767
1768
1769void xhci_mem_cleanup(struct xhci_hcd *xhci);
1770int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1771void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1772int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1773int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1774void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1775 struct usb_device *udev);
1776unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1777unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1778unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1779unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1780unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1781void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1782void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1783 struct xhci_bw_info *ep_bw,
1784 struct xhci_interval_bw_table *bw_table,
1785 struct usb_device *udev,
1786 struct xhci_virt_ep *virt_ep,
1787 struct xhci_tt_bw_info *tt_info);
1788void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1789 struct xhci_virt_device *virt_dev,
1790 int old_active_eps);
1791void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1792void xhci_update_bw_info(struct xhci_hcd *xhci,
1793 struct xhci_container_ctx *in_ctx,
1794 struct xhci_input_control_ctx *ctrl_ctx,
1795 struct xhci_virt_device *virt_dev);
1796void xhci_endpoint_copy(struct xhci_hcd *xhci,
1797 struct xhci_container_ctx *in_ctx,
1798 struct xhci_container_ctx *out_ctx,
1799 unsigned int ep_index);
1800void xhci_slot_copy(struct xhci_hcd *xhci,
1801 struct xhci_container_ctx *in_ctx,
1802 struct xhci_container_ctx *out_ctx);
1803int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1804 struct usb_device *udev, struct usb_host_endpoint *ep,
1805 gfp_t mem_flags);
1806void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1807int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1808 unsigned int num_trbs, gfp_t flags);
1809void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1810 struct xhci_virt_device *virt_dev,
1811 unsigned int ep_index);
1812struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1813 unsigned int num_stream_ctxs,
1814 unsigned int num_streams,
1815 unsigned int max_packet, gfp_t flags);
1816void xhci_free_stream_info(struct xhci_hcd *xhci,
1817 struct xhci_stream_info *stream_info);
1818void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1819 struct xhci_ep_ctx *ep_ctx,
1820 struct xhci_stream_info *stream_info);
1821void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1822 struct xhci_virt_ep *ep);
1823void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1824 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1825struct xhci_ring *xhci_dma_to_transfer_ring(
1826 struct xhci_virt_ep *ep,
1827 u64 address);
1828struct xhci_ring *xhci_stream_id_to_ring(
1829 struct xhci_virt_device *dev,
1830 unsigned int ep_index,
1831 unsigned int stream_id);
1832struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1833 bool allocate_in_ctx, bool allocate_completion,
1834 gfp_t mem_flags);
1835void xhci_urb_free_priv(struct urb_priv *urb_priv);
1836void xhci_free_command(struct xhci_hcd *xhci,
1837 struct xhci_command *command);
1838
1839
1840typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1841int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
1842void xhci_quiesce(struct xhci_hcd *xhci);
1843int xhci_halt(struct xhci_hcd *xhci);
1844int xhci_reset(struct xhci_hcd *xhci);
1845int xhci_init(struct usb_hcd *hcd);
1846int xhci_run(struct usb_hcd *hcd);
1847void xhci_stop(struct usb_hcd *hcd);
1848void xhci_shutdown(struct usb_hcd *hcd);
1849int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1850void xhci_init_driver(struct hc_driver *drv,
1851 const struct xhci_driver_overrides *over);
1852
1853#ifdef CONFIG_PM
1854int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1855int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1856#else
1857#define xhci_suspend NULL
1858#define xhci_resume NULL
1859#endif
1860
1861int xhci_get_frame(struct usb_hcd *hcd);
1862irqreturn_t xhci_irq(struct usb_hcd *hcd);
1863irqreturn_t xhci_msi_irq(int irq, void *hcd);
1864int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1865void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1866int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1867 struct xhci_virt_device *virt_dev,
1868 struct usb_device *hdev,
1869 struct usb_tt *tt, gfp_t mem_flags);
1870int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1871 struct usb_host_endpoint **eps, unsigned int num_eps,
1872 unsigned int num_streams, gfp_t mem_flags);
1873int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1874 struct usb_host_endpoint **eps, unsigned int num_eps,
1875 gfp_t mem_flags);
1876int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1877int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev);
1878int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1879int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1880 struct usb_device *udev, int enable);
1881int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1882 struct usb_tt *tt, gfp_t mem_flags);
1883int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1884int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1885int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1886int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1887void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1888int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1889int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1890void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1891
1892
1893dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1894struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1895 struct xhci_segment *start_seg, union xhci_trb *start_trb,
1896 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
1897int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1898void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1899int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1900 u32 trb_type, u32 slot_id);
1901int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1902 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1903int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1904 u32 field1, u32 field2, u32 field3, u32 field4);
1905int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1906 int slot_id, unsigned int ep_index, int suspend);
1907int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1908 int slot_id, unsigned int ep_index);
1909int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1910 int slot_id, unsigned int ep_index);
1911int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1912 int slot_id, unsigned int ep_index);
1913int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1914 struct urb *urb, int slot_id, unsigned int ep_index);
1915int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1916 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1917 bool command_must_succeed);
1918int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1919 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1920int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1921 int slot_id, unsigned int ep_index);
1922int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1923 u32 slot_id);
1924void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1925 unsigned int slot_id, unsigned int ep_index,
1926 unsigned int stream_id, struct xhci_td *cur_td,
1927 struct xhci_dequeue_state *state);
1928void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1929 unsigned int slot_id, unsigned int ep_index,
1930 unsigned int stream_id,
1931 struct xhci_dequeue_state *deq_state);
1932void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1933 unsigned int ep_index, struct xhci_td *td);
1934void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1935 unsigned int slot_id, unsigned int ep_index,
1936 struct xhci_dequeue_state *deq_state);
1937void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1938void xhci_handle_command_timeout(unsigned long data);
1939
1940void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1941 unsigned int ep_index, unsigned int stream_id);
1942void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1943
1944
1945void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1946 int port_id, u32 link_state);
1947int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1948 struct usb_device *udev, enum usb3_link_state state);
1949int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1950 struct usb_device *udev, enum usb3_link_state state);
1951void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1952 int port_id, u32 port_bit);
1953int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1954 char *buf, u16 wLength);
1955int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1956int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1957
1958#ifdef CONFIG_PM
1959int xhci_bus_suspend(struct usb_hcd *hcd);
1960int xhci_bus_resume(struct usb_hcd *hcd);
1961#else
1962#define xhci_bus_suspend NULL
1963#define xhci_bus_resume NULL
1964#endif
1965
1966u32 xhci_port_state_to_neutral(u32 state);
1967int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1968 u16 port);
1969void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1970
1971
1972struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1973struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1974struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1975
1976struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1977 unsigned int slot_id, unsigned int ep_index,
1978 unsigned int stream_id);
1979static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1980 struct urb *urb)
1981{
1982 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
1983 xhci_get_endpoint_index(&urb->ep->desc),
1984 urb->stream_id);
1985}
1986
1987#endif
1988