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15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/errno.h>
18#include <linux/mutex.h>
19#include <linux/wait.h>
20#include <linux/delay.h>
21#include <linux/fs.h>
22#include <linux/mm.h>
23#include <linux/ctype.h>
24#include <linux/platform_device.h>
25#include <linux/io.h>
26
27#include <video/exynos_mipi_dsim.h>
28
29#include "exynos_mipi_dsi_regs.h"
30
31void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim)
32{
33 unsigned int reg;
34
35 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
36
37 reg |= DSIM_FUNCRST;
38
39 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
40}
41
42void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim)
43{
44 unsigned int reg;
45
46 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
47
48 reg |= DSIM_SWRST;
49
50 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST);
51}
52
53void exynos_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim)
54{
55 unsigned int reg;
56
57 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
58
59 reg |= INTSRC_SW_RST_RELEASE;
60
61 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
62}
63
64int exynos_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim)
65{
66 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) &
67 INTSRC_SW_RST_RELEASE;
68}
69
70unsigned int exynos_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim)
71{
72 unsigned int reg;
73
74 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK);
75
76 return reg;
77}
78
79void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
80 unsigned int mode, unsigned int mask)
81{
82 unsigned int reg = 0;
83
84 if (mask)
85 reg |= mode;
86 else
87 reg &= ~mode;
88
89 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK);
90}
91
92void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
93 unsigned int cfg)
94{
95 unsigned int reg;
96
97 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
98
99 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
100 mdelay(10);
101 reg |= cfg;
102
103 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
104}
105
106
107
108
109void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
110 unsigned int value)
111{
112 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
113}
114
115void exynos_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim,
116 unsigned int enable)
117{
118 unsigned int reg;
119
120 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL);
121
122 reg &= ~DSIM_MAIN_STAND_BY;
123
124 if (enable)
125 reg |= DSIM_MAIN_STAND_BY;
126
127 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
128}
129
130void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
131 unsigned int width_resol, unsigned int height_resol)
132{
133 unsigned int reg;
134
135
136 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) &
137 ~(DSIM_MAIN_STAND_BY);
138 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
139
140 reg &= ~((0x7ff << 16) | (0x7ff << 0));
141 reg |= DSIM_MAIN_VRESOL(height_resol) | DSIM_MAIN_HRESOL(width_resol);
142
143 reg |= DSIM_MAIN_STAND_BY;
144 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL);
145}
146
147void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
148 unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
149{
150 unsigned int reg;
151
152 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) &
153 ~((DSIM_CMD_ALLOW_MASK) | (DSIM_STABLE_VFP_MASK) |
154 (DSIM_MAIN_VBP_MASK));
155
156 reg |= (DSIM_CMD_ALLOW_SHIFT(cmd_allow & 0xf) |
157 DSIM_STABLE_VFP_SHIFT(vfront & 0x7ff) |
158 DSIM_MAIN_VBP_SHIFT(vback & 0x7ff));
159
160 writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH);
161}
162
163void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
164 unsigned int front, unsigned int back)
165{
166 unsigned int reg;
167
168 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) &
169 ~((DSIM_MAIN_HFP_MASK) | (DSIM_MAIN_HBP_MASK));
170
171 reg |= DSIM_MAIN_HFP_SHIFT(front) | DSIM_MAIN_HBP_SHIFT(back);
172
173 writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH);
174}
175
176void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
177 unsigned int vert, unsigned int hori)
178{
179 unsigned int reg;
180
181 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) &
182 ~((DSIM_MAIN_VSA_MASK) | (DSIM_MAIN_HSA_MASK));
183
184 reg |= (DSIM_MAIN_VSA_SHIFT(vert & 0x3ff) |
185 DSIM_MAIN_HSA_SHIFT(hori));
186
187 writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC);
188}
189
190void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
191 unsigned int vert, unsigned int hori)
192{
193 unsigned int reg;
194
195 reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) &
196 ~(DSIM_SUB_STANDY_MASK);
197
198 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
199
200 reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
201 reg |= (DSIM_SUB_VRESOL_SHIFT(vert & 0x7ff) |
202 DSIM_SUB_HRESOL_SHIFT(hori & 0x7ff));
203 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
204
205 reg |= DSIM_SUB_STANDY_SHIFT(1);
206 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL);
207}
208
209void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim)
210{
211 struct mipi_dsim_config *dsim_config = dsim->dsim_config;
212
213 unsigned int cfg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
214 ~((1 << 28) | (0x1f << 20) | (0x3 << 5));
215
216 cfg = ((DSIM_AUTO_FLUSH(dsim_config->auto_flush)) |
217 (DSIM_EOT_DISABLE(dsim_config->eot_disable)) |
218 (DSIM_AUTO_MODE_SHIFT(dsim_config->auto_vertical_cnt)) |
219 (DSIM_HSE_MODE_SHIFT(dsim_config->hse)) |
220 (DSIM_HFP_MODE_SHIFT(dsim_config->hfp)) |
221 (DSIM_HBP_MODE_SHIFT(dsim_config->hbp)) |
222 (DSIM_HSA_MODE_SHIFT(dsim_config->hsa)) |
223 (DSIM_NUM_OF_DATALANE_SHIFT(dsim_config->e_no_data_lane)));
224
225 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
226}
227
228void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
229 struct mipi_dsim_config *dsim_config)
230{
231 u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) &
232 ~((0x3 << 26) | (1 << 25) | (0x3 << 18) | (0x7 << 12) |
233 (0x3 << 16) | (0x7 << 8));
234
235 if (dsim_config->e_interface == DSIM_VIDEO)
236 reg |= (1 << 25);
237 else if (dsim_config->e_interface == DSIM_COMMAND)
238 reg &= ~(1 << 25);
239 else {
240 dev_err(dsim->dev, "unknown lcd type.\n");
241 return;
242 }
243
244
245 reg |= ((u8) (dsim_config->e_burst_mode) & 0x3) << 26 |
246 ((u8) (dsim_config->e_virtual_ch) & 0x3) << 18 |
247 ((u8) (dsim_config->e_pixel_format) & 0x7) << 12;
248
249 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
250}
251
252void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
253 unsigned int enable)
254{
255 unsigned int reg;
256
257 reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG);
258
259 if (enable)
260 reg |= DSIM_LANE_ENx(lane);
261 else
262 reg &= ~DSIM_LANE_ENx(lane);
263
264 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
265}
266
267
268void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
269 unsigned int count)
270{
271 unsigned int cfg;
272
273
274 cfg = DSIM_NUM_OF_DATALANE_SHIFT(count);
275
276 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG);
277}
278
279void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable,
280 unsigned int afc_code)
281{
282 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
283
284 if (enable) {
285 reg |= (1 << 14);
286 reg &= ~(0x7 << 5);
287 reg |= (afc_code & 0x7) << 5;
288 } else
289 reg &= ~(1 << 14);
290
291 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR);
292}
293
294void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
295 unsigned int enable)
296{
297 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
298 ~(DSIM_PLL_BYPASS_SHIFT(0x1));
299
300 reg |= DSIM_PLL_BYPASS_SHIFT(enable);
301
302 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
303}
304
305void exynos_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p,
306 unsigned int m, unsigned int s)
307{
308 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
309
310 reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1);
311
312 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
313}
314
315void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
316 unsigned int freq_band)
317{
318 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
319 ~(DSIM_FREQ_BAND_SHIFT(0x1f));
320
321 reg |= DSIM_FREQ_BAND_SHIFT(freq_band & 0x1f);
322
323 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
324}
325
326void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
327 unsigned int pre_divider, unsigned int main_divider,
328 unsigned int scaler)
329{
330 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
331 ~(0x7ffff << 1);
332
333 reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 |
334 (scaler & 0x7) << 1;
335
336 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
337}
338
339void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
340 unsigned int lock_time)
341{
342 writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR);
343}
344
345void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, unsigned int enable)
346{
347 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
348 ~(DSIM_PLL_EN_SHIFT(0x1));
349
350 reg |= DSIM_PLL_EN_SHIFT(enable & 0x1);
351
352 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
353}
354
355void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
356 unsigned int src)
357{
358 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
359 ~(DSIM_BYTE_CLK_SRC_SHIFT(0x3));
360
361 reg |= (DSIM_BYTE_CLK_SRC_SHIFT(src));
362
363 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
364}
365
366void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
367 unsigned int enable)
368{
369 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
370 ~(DSIM_BYTE_CLKEN_SHIFT(0x1));
371
372 reg |= DSIM_BYTE_CLKEN_SHIFT(enable);
373
374 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
375}
376
377void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
378 unsigned int enable, unsigned int prs_val)
379{
380 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
381 ~(DSIM_ESC_CLKEN_SHIFT(0x1) | 0xffff);
382
383 reg |= DSIM_ESC_CLKEN_SHIFT(enable);
384 if (enable)
385 reg |= prs_val;
386
387 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
388}
389
390void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
391 unsigned int lane_sel, unsigned int enable)
392{
393 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
394
395 if (enable)
396 reg |= DSIM_LANE_ESC_CLKEN(lane_sel);
397 else
398
399 reg &= ~DSIM_LANE_ESC_CLKEN(lane_sel);
400
401 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
402}
403
404void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
405 unsigned int enable)
406{
407 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
408 ~(DSIM_FORCE_STOP_STATE_SHIFT(0x1));
409
410 reg |= (DSIM_FORCE_STOP_STATE_SHIFT(enable & 0x1));
411
412 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
413}
414
415unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim)
416{
417 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
418
419
420
421
422
423
424
425 if ((reg & DSIM_STOP_STATE_DAT(0xf)) &&
426 ((reg & DSIM_STOP_STATE_CLK) ||
427 (reg & DSIM_TX_READY_HS_CLK)))
428 return 1;
429
430 return 0;
431}
432
433void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
434 unsigned int cnt_val)
435{
436 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) &
437 ~(DSIM_STOP_STATE_CNT_SHIFT(0x7ff));
438
439 reg |= (DSIM_STOP_STATE_CNT_SHIFT(cnt_val & 0x7ff));
440
441 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
442}
443
444void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
445 unsigned int timeout)
446{
447 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
448 ~(DSIM_BTA_TOUT_SHIFT(0xff));
449
450 reg |= (DSIM_BTA_TOUT_SHIFT(timeout));
451
452 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
453}
454
455void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
456 unsigned int timeout)
457{
458 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) &
459 ~(DSIM_LPDR_TOUT_SHIFT(0xffff));
460
461 reg |= (DSIM_LPDR_TOUT_SHIFT(timeout));
462
463 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT);
464}
465
466void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
467 unsigned int lp)
468{
469 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
470
471 reg &= ~DSIM_CMD_LPDT_LP;
472
473 if (lp)
474 reg |= DSIM_CMD_LPDT_LP;
475
476 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
477}
478
479void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
480 unsigned int lp)
481{
482 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE);
483
484 reg &= ~DSIM_TX_LPDT_LP;
485
486 if (lp)
487 reg |= DSIM_TX_LPDT_LP;
488
489 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE);
490}
491
492void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
493 unsigned int enable)
494{
495 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) &
496 ~(DSIM_TX_REQUEST_HSCLK_SHIFT(0x1));
497
498 reg |= DSIM_TX_REQUEST_HSCLK_SHIFT(enable);
499
500 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL);
501}
502
503void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
504 unsigned int swap_en)
505{
506 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
507
508 reg &= ~(0x3 << 0);
509 reg |= (swap_en & 0x3) << 0;
510
511 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1);
512}
513
514void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
515 unsigned int hs_zero)
516{
517 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
518 ~(0xf << 28);
519
520 reg |= ((hs_zero & 0xf) << 28);
521
522 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
523}
524
525void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep)
526{
527 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) &
528 ~(0x7 << 20);
529
530 reg |= ((prep & 0x7) << 20);
531
532 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL);
533}
534
535unsigned int exynos_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim)
536{
537 return readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
538}
539
540void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim,
541 unsigned int src)
542{
543 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
544
545 reg |= src;
546
547 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
548}
549
550void exynos_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim,
551 unsigned int src, unsigned int enable)
552{
553 unsigned int reg = 0;
554
555 if (enable)
556 reg |= src;
557 else
558 reg &= ~src;
559
560 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC);
561}
562
563unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim)
564{
565 unsigned int reg;
566
567 reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS);
568
569 return reg & (1 << 31) ? 1 : 0;
570}
571
572unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim)
573{
574 return readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL) & ~(0x1f);
575}
576
577void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim,
578 unsigned int di, unsigned int data0, unsigned int data1)
579{
580 unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0);
581
582 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
583}
584
585void exynos_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim,
586 unsigned int di, unsigned int data0)
587{
588 unsigned int reg = (data0 << 8) | (di << 0);
589
590 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR);
591}
592
593unsigned int exynos_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim)
594{
595 return readl(dsim->reg_base + EXYNOS_DSIM_RXFIFO);
596}
597
598unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
599{
600 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
601
602 return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
603}
604
605void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
606{
607 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
608
609 writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +
610 EXYNOS_DSIM_INTSRC);
611}
612
613void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
614 unsigned int tx_data)
615{
616 writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD);
617}
618
