LXR linux/arch/arm/mach-omap2/powerdomains44xx

   1/*
   2 * OMAP4 Power domains framework
   3 *
   4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5 * Copyright (C) 2009-2011 Nokia Corporation
   6 *
   7 * Abhijit Pagare (abhijitpagare@ti.com)
   8 * Benoit Cousson (b-cousson@ti.com)
   9 * Paul Walmsley (paul@pwsan.com)
  10 *
  11 * This file is automatically generated from the OMAP hardware databases.
  12 * We respectfully ask that any modifications to this file be coordinated
  13 * with the public linux-omap@vger.kernel.org mailing list and the
  14 * authors above to ensure that the autogeneration scripts are kept
  15 * up-to-date with the file contents.
  16 *
  17 * This program is free software; you can redistribute it and/or modify
  18 * it under the terms of the GNU General Public License version 2 as
  19 * published by the Free Software Foundation.
  20 */
  21
  22#include <linux/kernel.h>
  23#include <linux/init.h>
  24
  25#include "powerdomain.h"
  26
  27#include "prcm-common.h"
  28#include "prcm44xx.h"
  29#include "prm-regbits-44xx.h"
  30#include "prm44xx.h"
  31#include "prcm_mpu44xx.h"
  32
  33/* core_44xx_pwrdm: CORE power domain */
  34static struct powerdomain core_44xx_pwrdm = {
  35        .name             = "core_pwrdm",
  36        .voltdm           = { .name = "core" },
  37        .prcm_offs        = OMAP4430_PRM_CORE_INST,
  38        .prcm_partition   = OMAP4430_PRM_PARTITION,
  39        .pwrsts           = PWRSTS_RET_ON,
  40        .pwrsts_logic_ret = PWRSTS_OFF_RET,
  41        .banks            = 5,
  42        .pwrsts_mem_ret = {
  43                [0] = PWRSTS_OFF,       /* core_nret_bank */
  44                [1] = PWRSTS_RET,       /* core_ocmram */
  45                [2] = PWRSTS_RET,       /* core_other_bank */
  46                [3] = PWRSTS_OFF_RET,   /* ducati_l2ram */
  47                [4] = PWRSTS_OFF_RET,   /* ducati_unicache */
  48        },
  49        .pwrsts_mem_on  = {
  50                [0] = PWRSTS_ON,        /* core_nret_bank */
  51                [1] = PWRSTS_ON,        /* core_ocmram */
  52                [2] = PWRSTS_ON,        /* core_other_bank */
  53                [3] = PWRSTS_ON,        /* ducati_l2ram */
  54                [4] = PWRSTS_ON,        /* ducati_unicache */
  55        },
  56        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  57};
  58
  59/* gfx_44xx_pwrdm: 3D accelerator power domain */
  60static struct powerdomain gfx_44xx_pwrdm = {
  61        .name             = "gfx_pwrdm",
  62        .voltdm           = { .name = "core" },
  63        .prcm_offs        = OMAP4430_PRM_GFX_INST,
  64        .prcm_partition   = OMAP4430_PRM_PARTITION,
  65        .pwrsts           = PWRSTS_OFF_ON,
  66        .banks            = 1,
  67        .pwrsts_mem_ret = {
  68                [0] = PWRSTS_OFF,       /* gfx_mem */
  69        },
  70        .pwrsts_mem_on  = {
  71                [0] = PWRSTS_ON,        /* gfx_mem */
  72        },
  73        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  74};
  75
  76/* abe_44xx_pwrdm: Audio back end power domain */
  77static struct powerdomain abe_44xx_pwrdm = {
  78        .name             = "abe_pwrdm",
  79        .voltdm           = { .name = "iva" },
  80        .prcm_offs        = OMAP4430_PRM_ABE_INST,
  81        .prcm_partition   = OMAP4430_PRM_PARTITION,
  82        .pwrsts           = PWRSTS_OFF_RET_ON,
  83        .pwrsts_logic_ret = PWRSTS_OFF,
  84        .banks            = 2,
  85        .pwrsts_mem_ret = {
  86                [0] = PWRSTS_RET,       /* aessmem */
  87                [1] = PWRSTS_OFF,       /* periphmem */
  88        },
  89        .pwrsts_mem_on  = {
  90                [0] = PWRSTS_ON,        /* aessmem */
  91                [1] = PWRSTS_ON,        /* periphmem */
  92        },
  93        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  94};
  95
  96/* dss_44xx_pwrdm: Display subsystem power domain */
  97static struct powerdomain dss_44xx_pwrdm = {
  98        .name             = "dss_pwrdm",
  99        .voltdm           = { .name = "core" },
 100        .prcm_offs        = OMAP4430_PRM_DSS_INST,
 101        .prcm_partition   = OMAP4430_PRM_PARTITION,
 102        .pwrsts           = PWRSTS_OFF_RET_ON,
 103        .pwrsts_logic_ret = PWRSTS_OFF,
 104        .banks            = 1,
 105        .pwrsts_mem_ret = {
 106                [0] = PWRSTS_OFF,       /* dss_mem */
 107        },
 108        .pwrsts_mem_on  = {
 109                [0] = PWRSTS_ON,        /* dss_mem */
 110        },
 111        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 112};
 113
 114/* tesla_44xx_pwrdm: Tesla processor power domain */
 115static struct powerdomain tesla_44xx_pwrdm = {
 116        .name             = "tesla_pwrdm",
 117        .voltdm           = { .name = "iva" },
 118        .prcm_offs        = OMAP4430_PRM_TESLA_INST,
 119        .prcm_partition   = OMAP4430_PRM_PARTITION,
 120        .pwrsts           = PWRSTS_OFF_RET_ON,
 121        .pwrsts_logic_ret = PWRSTS_OFF_RET,
 122        .banks            = 3,
 123        .pwrsts_mem_ret = {
 124                [0] = PWRSTS_RET,       /* tesla_edma */
 125                [1] = PWRSTS_OFF_RET,   /* tesla_l1 */
 126                [2] = PWRSTS_OFF_RET,   /* tesla_l2 */
 127        },
 128        .pwrsts_mem_on  = {
 129                [0] = PWRSTS_ON,        /* tesla_edma */
 130                [1] = PWRSTS_ON,        /* tesla_l1 */
 131                [2] = PWRSTS_ON,        /* tesla_l2 */
 132        },
 133        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 134};
 135
 136/* wkup_44xx_pwrdm: Wake-up power domain */
 137static struct powerdomain wkup_44xx_pwrdm = {
 138        .name             = "wkup_pwrdm",
 139        .voltdm           = { .name = "wakeup" },
 140        .prcm_offs        = OMAP4430_PRM_WKUP_INST,
 141        .prcm_partition   = OMAP4430_PRM_PARTITION,
 142        .pwrsts           = PWRSTS_ON,
 143        .banks            = 1,
 144        .pwrsts_mem_ret = {
 145                [0] = PWRSTS_OFF,       /* wkup_bank */
 146        },
 147        .pwrsts_mem_on  = {
 148                [0] = PWRSTS_ON,        /* wkup_bank */
 149        },
 150};
 151
 152/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
 153static struct powerdomain cpu0_44xx_pwrdm = {
 154        .name             = "cpu0_pwrdm",
 155        .voltdm           = { .name = "mpu" },
 156        .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_INST,
 157        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
 158        .pwrsts           = PWRSTS_OFF_RET_ON,
 159        .pwrsts_logic_ret = PWRSTS_OFF_RET,
 160        .banks            = 1,
 161        .pwrsts_mem_ret = {
 162                [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
 163        },
 164        .pwrsts_mem_on  = {
 165                [0] = PWRSTS_ON,        /* cpu0_l1 */
 166        },
 167};
 168
 169/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
 170static struct powerdomain cpu1_44xx_pwrdm = {
 171        .name             = "cpu1_pwrdm",
 172        .voltdm           = { .name = "mpu" },
 173        .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_INST,
 174        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
 175        .pwrsts           = PWRSTS_OFF_RET_ON,
 176        .pwrsts_logic_ret = PWRSTS_OFF_RET,
 177        .banks            = 1,
 178        .pwrsts_mem_ret = {
 179                [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
 180        },
 181        .pwrsts_mem_on  = {
 182                [0] = PWRSTS_ON,        /* cpu1_l1 */
 183        },
 184};
 185
 186/* emu_44xx_pwrdm: Emulation power domain */
 187static struct powerdomain emu_44xx_pwrdm = {
 188        .name             = "emu_pwrdm",
 189        .voltdm           = { .name = "wakeup" },
 190        .prcm_offs        = OMAP4430_PRM_EMU_INST,
 191        .prcm_partition   = OMAP4430_PRM_PARTITION,
 192        .pwrsts           = PWRSTS_OFF_ON,
 193        .banks            = 1,
 194        .pwrsts_mem_ret = {
 195                [0] = PWRSTS_OFF,       /* emu_bank */
 196        },
 197        .pwrsts_mem_on  = {
 198                [0] = PWRSTS_ON,        /* emu_bank */
 199        },
 200};
 201
 202/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
 203static struct powerdomain mpu_44xx_pwrdm = {
 204        .name             = "mpu_pwrdm",
 205        .voltdm           = { .name = "mpu" },
 206        .prcm_offs        = OMAP4430_PRM_MPU_INST,
 207        .prcm_partition   = OMAP4430_PRM_PARTITION,
 208        .pwrsts           = PWRSTS_RET_ON,
 209        .pwrsts_logic_ret = PWRSTS_OFF_RET,
 210        .banks            = 3,
 211        .pwrsts_mem_ret = {
 212                [0] = PWRSTS_OFF_RET,   /* mpu_l1 */
 213                [1] = PWRSTS_OFF_RET,   /* mpu_l2 */
 214                [2] = PWRSTS_RET,       /* mpu_ram */
 215        },
 216        .pwrsts_mem_on  = {
 217                [0] = PWRSTS_ON,        /* mpu_l1 */
 218                [1] = PWRSTS_ON,        /* mpu_l2 */
 219                [2] = PWRSTS_ON,        /* mpu_ram */
 220        },
 221};
 222
 223/* ivahd_44xx_pwrdm: IVA-HD power domain */
 224static struct powerdomain ivahd_44xx_pwrdm = {
 225        .name             = "ivahd_pwrdm",
 226        .voltdm           = { .name = "iva" },
 227        .prcm_offs        = OMAP4430_PRM_IVAHD_INST,
 228        .prcm_partition   = OMAP4430_PRM_PARTITION,
 229        .pwrsts           = PWRSTS_OFF_RET_ON,
 230        .pwrsts_logic_ret = PWRSTS_OFF,
 231        .banks            = 4,
 232        .pwrsts_mem_ret = {
 233                [0] = PWRSTS_OFF,       /* hwa_mem */
 234                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
 235                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
 236                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
 237        },
 238        .pwrsts_mem_on  = {
 239                [0] = PWRSTS_ON,        /* hwa_mem */
 240                [1] = PWRSTS_ON,        /* sl2_mem */
 241                [2] = PWRSTS_ON,        /* tcm1_mem */
 242                [3] = PWRSTS_ON,        /* tcm2_mem */
 243        },
 244        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 245};
 246
 247/* cam_44xx_pwrdm: Camera subsystem power domain */
 248static struct powerdomain cam_44xx_pwrdm = {
 249        .name             = "cam_pwrdm",
 250        .voltdm           = { .name = "core" },
 251        .prcm_offs        = OMAP4430_PRM_CAM_INST,
 252        .prcm_partition   = OMAP4430_PRM_PARTITION,
 253        .pwrsts           = PWRSTS_OFF_ON,
 254        .banks            = 1,
 255        .pwrsts_mem_ret = {
 256                [0] = PWRSTS_OFF,       /* cam_mem */
 257        },
 258        .pwrsts_mem_on  = {
 259                [0] = PWRSTS_ON,        /* cam_mem */
 260        },
 261        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 262};
 263
 264/* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
 265static struct powerdomain l3init_44xx_pwrdm = {
 266        .name             = "l3init_pwrdm",
 267        .voltdm           = { .name = "core" },
 268        .prcm_offs        = OMAP4430_PRM_L3INIT_INST,
 269        .prcm_partition   = OMAP4430_PRM_PARTITION,
 270        .pwrsts           = PWRSTS_RET_ON,
 271        .pwrsts_logic_ret = PWRSTS_OFF_RET,
 272        .banks            = 1,
 273        .pwrsts_mem_ret = {
 274                [0] = PWRSTS_OFF,       /* l3init_bank1 */
 275        },
 276        .pwrsts_mem_on  = {
 277                [0] = PWRSTS_ON,        /* l3init_bank1 */
 278        },
 279        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 280};
 281
 282/* l4per_44xx_pwrdm: Target peripherals power domain */
 283static struct powerdomain l4per_44xx_pwrdm = {
 284        .name             = "l4per_pwrdm",
 285        .voltdm           = { .name = "core" },
 286        .prcm_offs        = OMAP4430_PRM_L4PER_INST,
 287        .prcm_partition   = OMAP4430_PRM_PARTITION,
 288        .pwrsts           = PWRSTS_RET_ON,
 289        .pwrsts_logic_ret = PWRSTS_OFF_RET,
 290        .banks            = 2,
 291        .pwrsts_mem_ret = {
 292                [0] = PWRSTS_OFF,       /* nonretained_bank */
 293                [1] = PWRSTS_RET,       /* retained_bank */
 294        },
 295        .pwrsts_mem_on  = {
 296                [0] = PWRSTS_ON,        /* nonretained_bank */
 297                [1] = PWRSTS_ON,        /* retained_bank */
 298        },
 299        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 300};
 301
 302/*
 303 * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
 304 * domain
 305 */
 306static struct powerdomain always_on_core_44xx_pwrdm = {
 307        .name             = "always_on_core_pwrdm",
 308        .voltdm           = { .name = "core" },
 309        .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_INST,
 310        .prcm_partition   = OMAP4430_PRM_PARTITION,
 311        .pwrsts           = PWRSTS_ON,
 312};
 313
 314/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
 315static struct powerdomain cefuse_44xx_pwrdm = {
 316        .name             = "cefuse_pwrdm",
 317        .voltdm           = { .name = "core" },
 318        .prcm_offs        = OMAP4430_PRM_CEFUSE_INST,
 319        .prcm_partition   = OMAP4430_PRM_PARTITION,
 320        .pwrsts           = PWRSTS_OFF_ON,
 321        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 322};
 323
 324/*
 325 * The following power domains are not under SW control
 326 *
 327 * always_on_iva
 328 * always_on_mpu
 329 * stdefuse
 330 */
 331
 332/* As powerdomains are added or removed above, this list must also be changed */
 333static struct powerdomain *powerdomains_omap44xx[] __initdata = {
 334        &core_44xx_pwrdm,
 335        &gfx_44xx_pwrdm,
 336        &abe_44xx_pwrdm,
 337        &dss_44xx_pwrdm,
 338        &tesla_44xx_pwrdm,
 339        &wkup_44xx_pwrdm,
 340        &cpu0_44xx_pwrdm,
 341        &cpu1_44xx_pwrdm,
 342        &emu_44xx_pwrdm,
 343        &mpu_44xx_pwrdm,
 344        &ivahd_44xx_pwrdm,
 345        &cam_44xx_pwrdm,
 346        &l3init_44xx_pwrdm,
 347        &l4per_44xx_pwrdm,
 348        &always_on_core_44xx_pwrdm,
 349        &cefuse_44xx_pwrdm,
 350        NULL
 351};
 352
 353void __init omap44xx_powerdomains_init(void)
 354{
 355        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
 356        pwrdm_register_pwrdms(powerdomains_omap44xx);
 357        pwrdm_complete_init();
 358}
 359