1/* 2 * Register definitions for the AT32AP SDRAM Controller 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 */ 10 11/* Register offsets */ 12#define SDRAMC_MR 0x0000 13#define SDRAMC_TR 0x0004 14#define SDRAMC_CR 0x0008 15#define SDRAMC_HSR 0x000c 16#define SDRAMC_LPR 0x0010 17#define SDRAMC_IER 0x0014 18#define SDRAMC_IDR 0x0018 19#define SDRAMC_IMR 0x001c 20#define SDRAMC_ISR 0x0020 21#define SDRAMC_MDR 0x0024 22 23/* MR - Mode Register */ 24#define SDRAMC_MR_MODE_NORMAL ( 0 << 0) 25#define SDRAMC_MR_MODE_NOP ( 1 << 0) 26#define SDRAMC_MR_MODE_BANKS_PRECHARGE ( 2 << 0) 27#define SDRAMC_MR_MODE_LOAD_MODE ( 3 << 0) 28#define SDRAMC_MR_MODE_AUTO_REFRESH ( 4 << 0) 29#define SDRAMC_MR_MODE_EXT_LOAD_MODE ( 5 << 0) 30#define SDRAMC_MR_MODE_POWER_DOWN ( 6 << 0) 31 32/* CR - Configuration Register */ 33#define SDRAMC_CR_NC_8_BITS ( 0 << 0) 34#define SDRAMC_CR_NC_9_BITS ( 1 << 0) 35#define SDRAMC_CR_NC_10_BITS ( 2 << 0) 36#define SDRAMC_CR_NC_11_BITS ( 3 << 0) 37#define SDRAMC_CR_NR_11_BITS ( 0 << 2) 38#define SDRAMC_CR_NR_12_BITS ( 1 << 2) 39#define SDRAMC_CR_NR_13_BITS ( 2 << 2) 40#define SDRAMC_CR_NB_2_BANKS ( 0 << 4) 41#define SDRAMC_CR_NB_4_BANKS ( 1 << 4) 42#define SDRAMC_CR_CAS(x) ((x) << 5) 43#define SDRAMC_CR_DBW_32_BITS ( 0 << 7) 44#define SDRAMC_CR_DBW_16_BITS ( 1 << 7) 45#define SDRAMC_CR_TWR(x) ((x) << 8) 46#define SDRAMC_CR_TRC(x) ((x) << 12) 47#define SDRAMC_CR_TRP(x) ((x) << 16) 48#define SDRAMC_CR_TRCD(x) ((x) << 20) 49#define SDRAMC_CR_TRAS(x) ((x) << 24) 50#define SDRAMC_CR_TXSR(x) ((x) << 28) 51 52/* HSR - High Speed Register */ 53#define SDRAMC_HSR_DA ( 1 << 0) 54 55/* LPR - Low Power Register */ 56#define SDRAMC_LPR_LPCB_INHIBIT ( 0 << 0) 57#define SDRAMC_LPR_LPCB_SELF_RFR ( 1 << 0) 58#define SDRAMC_LPR_LPCB_PDOWN ( 2 << 0) 59#define SDRAMC_LPR_LPCB_DEEP_PDOWN ( 3 << 0) 60#define SDRAMC_LPR_PASR(x) ((x) << 4) 61#define SDRAMC_LPR_TCSR(x) ((x) << 8) 62#define SDRAMC_LPR_DS(x) ((x) << 10) 63#define SDRAMC_LPR_TIMEOUT(x) ((x) << 12) 64 65/* IER/IDR/IMR/ISR - Interrupt Enable/Disable/Mask/Status Register */ 66#define SDRAMC_ISR_RES ( 1 << 0) 67 68/* MDR - Memory Device Register */ 69#define SDRAMC_MDR_MD_SDRAM ( 0 << 0) 70#define SDRAMC_MDR_MD_LOW_PWR_SDRAM ( 1 << 0) 71 72/* Register access macros */ 73#define sdramc_readl(reg) \ 74 __raw_readl((void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg) 75#define sdramc_writel(reg, value) \ 76 __raw_writel(value, (void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg) 77