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36#include <linux/device.h>
37#include <linux/platform_device.h>
38#include <linux/mtd/mtd.h>
39#include <linux/mtd/partitions.h>
40#include <linux/mtd/physmap.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/plat-ram.h>
43#include <linux/spi/spi.h>
44#include <linux/spi/flash.h>
45#include <linux/irq.h>
46#include <linux/interrupt.h>
47#include <linux/jiffies.h>
48#include <linux/i2c-pca-platform.h>
49#include <linux/delay.h>
50#include <linux/io.h>
51#include <asm/dma.h>
52#include <asm/bfin5xx_spi.h>
53#include <asm/portmux.h>
54#include <asm/dpmc.h>
55#include <asm/cacheflush.h>
56#include <linux/i2c.h>
57
58
59
60
61const char bfin_board_name[] = "Acvilon board";
62
63#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
64#include <linux/usb/isp1760.h>
65static struct resource bfin_isp1760_resources[] = {
66 [0] = {
67 .start = 0x20000000,
68 .end = 0x20000000 + 0x000fffff,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = IRQ_PF15,
73 .end = IRQ_PF15,
74 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
75 },
76};
77
78static struct isp1760_platform_data isp1760_priv = {
79 .is_isp1761 = 0,
80 .port1_disable = 0,
81 .bus_width_16 = 1,
82 .port1_otg = 0,
83 .analog_oc = 0,
84 .dack_polarity_high = 0,
85 .dreq_polarity_high = 0,
86};
87
88static struct platform_device bfin_isp1760_device = {
89 .name = "isp1760-hcd",
90 .id = 0,
91 .dev = {
92 .platform_data = &isp1760_priv,
93 },
94 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
95 .resource = bfin_isp1760_resources,
96};
97#endif
98
99static struct resource bfin_i2c_pca_resources[] = {
100 {
101 .name = "pca9564-regs",
102 .start = 0x2C000000,
103 .end = 0x2C000000 + 16,
104 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
105 }, {
106
107 .start = IRQ_PF8,
108 .end = IRQ_PF8,
109 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
110 },
111};
112
113struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
114 .gpio = -1,
115 .i2c_clock_speed = 330000,
116 .timeout = HZ,
117};
118
119
120static struct platform_device bfin_i2c_pca_device = {
121 .name = "i2c-pca-platform",
122 .id = 0,
123 .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
124 .resource = bfin_i2c_pca_resources,
125 .dev = {
126 .platform_data = &pca9564_platform_data,
127 }
128};
129
130
131static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
132 {
133 I2C_BOARD_INFO("ds1339", 0x68),
134 },
135 {
136 I2C_BOARD_INFO("tcn75", 0x49),
137 },
138};
139
140#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
141static struct platdata_mtd_ram mtd_ram_data = {
142 .mapname = "rootfs(RAM)",
143 .bankwidth = 4,
144};
145
146static struct resource mtd_ram_resource = {
147 .start = 0x4000000,
148 .end = 0x5ffffff,
149 .flags = IORESOURCE_MEM,
150};
151
152static struct platform_device mtd_ram_device = {
153 .name = "mtd-ram",
154 .id = 0,
155 .dev = {
156 .platform_data = &mtd_ram_data,
157 },
158 .num_resources = 1,
159 .resource = &mtd_ram_resource,
160};
161#endif
162
163#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
164#include <linux/smsc911x.h>
165static struct resource smsc911x_resources[] = {
166 {
167 .name = "smsc911x-memory",
168 .start = 0x28000000,
169 .end = 0x28000000 + 0xFF,
170 .flags = IORESOURCE_MEM,
171 },
172 {
173 .start = IRQ_PF7,
174 .end = IRQ_PF7,
175 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
176 },
177};
178
179static struct smsc911x_platform_config smsc911x_config = {
180 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
181 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
182 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
183 .phy_interface = PHY_INTERFACE_MODE_MII,
184};
185
186static struct platform_device smsc911x_device = {
187 .name = "smsc911x",
188 .id = 0,
189 .num_resources = ARRAY_SIZE(smsc911x_resources),
190 .resource = smsc911x_resources,
191 .dev = {
192 .platform_data = &smsc911x_config,
193 },
194};
195#endif
196
197#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
198#ifdef CONFIG_SERIAL_BFIN_UART0
199static struct resource bfin_uart0_resources[] = {
200 {
201 .start = BFIN_UART_THR,
202 .end = BFIN_UART_GCTL + 2,
203 .flags = IORESOURCE_MEM,
204 },
205 {
206 .start = IRQ_UART_TX,
207 .end = IRQ_UART_TX,
208 .flags = IORESOURCE_IRQ,
209 },
210 {
211 .start = IRQ_UART_RX,
212 .end = IRQ_UART_RX,
213 .flags = IORESOURCE_IRQ,
214 },
215 {
216 .start = IRQ_UART_ERROR,
217 .end = IRQ_UART_ERROR,
218 .flags = IORESOURCE_IRQ,
219 },
220 {
221 .start = CH_UART_TX,
222 .end = CH_UART_TX,
223 .flags = IORESOURCE_DMA,
224 },
225 {
226 .start = CH_UART_RX,
227 .end = CH_UART_RX,
228 .flags = IORESOURCE_DMA,
229 },
230};
231
232static unsigned short bfin_uart0_peripherals[] = {
233 P_UART0_TX, P_UART0_RX, 0
234};
235
236static struct platform_device bfin_uart0_device = {
237 .name = "bfin-uart",
238 .id = 0,
239 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
240 .resource = bfin_uart0_resources,
241 .dev = {
242
243 .platform_data = &bfin_uart0_peripherals,
244 },
245};
246#endif
247#endif
248
249#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
250
251static struct mtd_partition bfin_plat_nand_partitions[] = {
252 {
253 .name = "params(nand)",
254 .size = 32 * 1024 * 1024,
255 .offset = 0,
256 }, {
257 .name = "userfs(nand)",
258 .size = MTDPART_SIZ_FULL,
259 .offset = MTDPART_OFS_APPEND,
260 },
261};
262
263#define BFIN_NAND_PLAT_CLE 2
264#define BFIN_NAND_PLAT_ALE 3
265
266static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
267 unsigned int ctrl)
268{
269 struct nand_chip *this = mtd->priv;
270
271 if (cmd == NAND_CMD_NONE)
272 return;
273
274 if (ctrl & NAND_CLE)
275 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
276 else
277 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
278}
279
280#define BFIN_NAND_PLAT_READY GPIO_PF10
281static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
282{
283 return gpio_get_value(BFIN_NAND_PLAT_READY);
284}
285
286static struct platform_nand_data bfin_plat_nand_data = {
287 .chip = {
288 .nr_chips = 1,
289 .chip_delay = 30,
290 .partitions = bfin_plat_nand_partitions,
291 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
292 },
293 .ctrl = {
294 .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
295 .dev_ready = bfin_plat_nand_dev_ready,
296 },
297};
298
299#define MAX(x, y) (x > y ? x : y)
300static struct resource bfin_plat_nand_resources = {
301 .start = 0x24000000,
302 .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
303 .flags = IORESOURCE_MEM,
304};
305
306static struct platform_device bfin_async_nand_device = {
307 .name = "gen_nand",
308 .id = -1,
309 .num_resources = 1,
310 .resource = &bfin_plat_nand_resources,
311 .dev = {
312 .platform_data = &bfin_plat_nand_data,
313 },
314};
315
316static void bfin_plat_nand_init(void)
317{
318 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
319}
320#else
321static void bfin_plat_nand_init(void)
322{
323}
324#endif
325
326#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
327static struct mtd_partition bfin_spi_dataflash_partitions[] = {
328 {
329 .name = "bootloader",
330 .size = 0x4200,
331 .offset = 0,
332 .mask_flags = MTD_CAP_ROM},
333 {
334 .name = "u-boot",
335 .size = 0x42000,
336 .offset = MTDPART_OFS_APPEND,
337 },
338 {
339 .name = "u-boot(params)",
340 .size = 0x4200,
341 .offset = MTDPART_OFS_APPEND,
342 },
343 {
344 .name = "kernel",
345 .size = 0x294000,
346 .offset = MTDPART_OFS_APPEND,
347 },
348 {
349 .name = "params",
350 .size = 0x42000,
351 .offset = MTDPART_OFS_APPEND,
352 },
353 {
354 .name = "rootfs",
355 .size = MTDPART_SIZ_FULL,
356 .offset = MTDPART_OFS_APPEND,
357 }
358};
359
360static struct flash_platform_data bfin_spi_dataflash_data = {
361 .name = "SPI Dataflash",
362 .parts = bfin_spi_dataflash_partitions,
363 .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
364};
365
366
367static struct bfin5xx_spi_chip data_flash_chip_info = {
368 .enable_dma = 0,
369};
370#endif
371
372#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
373
374static struct resource bfin_spi0_resource[] = {
375 [0] = {
376 .start = SPI0_REGBASE,
377 .end = SPI0_REGBASE + 0xFF,
378 .flags = IORESOURCE_MEM,
379 },
380 [1] = {
381 .start = CH_SPI,
382 .end = CH_SPI,
383 .flags = IORESOURCE_DMA,
384 },
385 [2] = {
386 .start = IRQ_SPI,
387 .end = IRQ_SPI,
388 .flags = IORESOURCE_IRQ,
389 },
390};
391
392
393static struct bfin5xx_spi_master bfin_spi0_info = {
394 .num_chipselect = 8,
395 .enable_dma = 1,
396 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
397};
398
399static struct platform_device bfin_spi0_device = {
400 .name = "bfin-spi",
401 .id = 0,
402 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
403 .resource = bfin_spi0_resource,
404 .dev = {
405 .platform_data = &bfin_spi0_info,
406 },
407};
408#endif
409
410static struct spi_board_info bfin_spi_board_info[] __initdata = {
411#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
412 {
413 .modalias = "spidev",
414 .max_speed_hz = 3125000,
415 .bus_num = 0,
416 .chip_select = 3,
417 },
418#endif
419#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
420 {
421 .modalias = "mtd_dataflash",
422 .max_speed_hz = 33250000,
423 .bus_num = 0,
424 .chip_select = 2,
425 .platform_data = &bfin_spi_dataflash_data,
426 .controller_data = &data_flash_chip_info,
427 .mode = SPI_MODE_3,
428 },
429#endif
430};
431
432static struct resource bfin_gpios_resources = {
433 .start = 31,
434
435 .end = 32,
436 .flags = IORESOURCE_IRQ,
437};
438
439static struct platform_device bfin_gpios_device = {
440 .name = "simple-gpio",
441 .id = -1,
442 .num_resources = 1,
443 .resource = &bfin_gpios_resources,
444};
445
446static const unsigned int cclk_vlev_datasheet[] = {
447 VRPAIR(VLEV_085, 250000000),
448 VRPAIR(VLEV_090, 300000000),
449 VRPAIR(VLEV_095, 313000000),
450 VRPAIR(VLEV_100, 350000000),
451 VRPAIR(VLEV_105, 400000000),
452 VRPAIR(VLEV_110, 444000000),
453 VRPAIR(VLEV_115, 450000000),
454 VRPAIR(VLEV_120, 475000000),
455 VRPAIR(VLEV_125, 500000000),
456 VRPAIR(VLEV_130, 600000000),
457};
458
459static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
460 .tuple_tab = cclk_vlev_datasheet,
461 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
462 .vr_settling_time = 25 ,
463};
464
465static struct platform_device bfin_dpmc = {
466 .name = "bfin dpmc",
467 .dev = {
468 .platform_data = &bfin_dmpc_vreg_data,
469 },
470};
471
472static struct platform_device *acvilon_devices[] __initdata = {
473 &bfin_dpmc,
474
475#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
476 &bfin_spi0_device,
477#endif
478
479#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
480#ifdef CONFIG_SERIAL_BFIN_UART0
481 &bfin_uart0_device,
482#endif
483#endif
484
485 &bfin_gpios_device,
486
487#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
488 &smsc911x_device,
489#endif
490
491 &bfin_i2c_pca_device,
492
493#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
494 &bfin_async_nand_device,
495#endif
496
497#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
498 &mtd_ram_device,
499#endif
500
501};
502
503static int __init acvilon_init(void)
504{
505 int ret;
506
507 printk(KERN_INFO "%s(): registering device resources\n", __func__);
508
509 bfin_plat_nand_init();
510 ret =
511 platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
512 if (ret < 0)
513 return ret;
514
515 i2c_register_board_info(0, acvilon_i2c_devs,
516 ARRAY_SIZE(acvilon_i2c_devs));
517
518 bfin_write_FIO0_FLAG_C(1 << 14);
519 msleep(5);
520 bfin_write_FIO0_FLAG_S(1 << 14);
521
522 spi_register_board_info(bfin_spi_board_info,
523 ARRAY_SIZE(bfin_spi_board_info));
524 return 0;
525}
526
527arch_initcall(acvilon_init);
528
529static struct platform_device *acvilon_early_devices[] __initdata = {
530#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
531#ifdef CONFIG_SERIAL_BFIN_UART0
532 &bfin_uart0_device,
533#endif
534#endif
535};
536
537void __init native_machine_early_platform_add_devices(void)
538{
539 printk(KERN_INFO "register early platform devices\n");
540 early_platform_add_devices(acvilon_early_devices,
541 ARRAY_SIZE(acvilon_early_devices));
542}
543
