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28#include <linux/atomic.h>
29#include <linux/delay.h>
30#include <linux/export.h>
31#include <linux/init.h>
32#include <linux/list.h>
33#include <linux/of.h>
34#include <linux/pci.h>
35#include <linux/proc_fs.h>
36#include <linux/rbtree.h>
37#include <linux/sched.h>
38#include <linux/seq_file.h>
39#include <linux/spinlock.h>
40
41#include <asm/eeh.h>
42#include <asm/eeh_event.h>
43#include <asm/io.h>
44#include <asm/machdep.h>
45#include <asm/ppc-pci.h>
46#include <asm/rtas.h>
47
48
49static int ibm_set_eeh_option;
50static int ibm_set_slot_reset;
51static int ibm_read_slot_reset_state;
52static int ibm_read_slot_reset_state2;
53static int ibm_slot_error_detail;
54static int ibm_get_config_addr_info;
55static int ibm_get_config_addr_info2;
56static int ibm_configure_pe;
57
58
59
60
61
62
63static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
64static DEFINE_SPINLOCK(slot_errbuf_lock);
65static int eeh_error_buf_size;
66
67
68
69
70
71
72static int pseries_eeh_init(void)
73{
74
75 ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
76 ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
77 ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
78 ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
79 ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
80 ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
81 ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
82 ibm_configure_pe = rtas_token("ibm,configure-pe");
83
84
85
86
87
88
89 if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE)
90 ibm_configure_pe = rtas_token("ibm,configure-bridge");
91
92
93
94
95
96
97 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE ||
98 ibm_set_slot_reset == RTAS_UNKNOWN_SERVICE ||
99 (ibm_read_slot_reset_state2 == RTAS_UNKNOWN_SERVICE &&
100 ibm_read_slot_reset_state == RTAS_UNKNOWN_SERVICE) ||
101 ibm_slot_error_detail == RTAS_UNKNOWN_SERVICE ||
102 ibm_configure_pe == RTAS_UNKNOWN_SERVICE) {
103 pr_info("EEH functionality not supported\n");
104 return -EINVAL;
105 }
106
107
108 spin_lock_init(&slot_errbuf_lock);
109 eeh_error_buf_size = rtas_token("rtas-error-log-max");
110 if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
111 pr_info("%s: unknown EEH error log size\n",
112 __func__);
113 eeh_error_buf_size = 1024;
114 } else if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
115 pr_info("%s: EEH error log size %d exceeds the maximal %d\n",
116 __func__, eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
117 eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
118 }
119
120
121 eeh_add_flag(EEH_PROBE_MODE_DEVTREE | EEH_ENABLE_IO_FOR_LOG);
122
123 return 0;
124}
125
126static int pseries_eeh_cap_start(struct pci_dn *pdn)
127{
128 u32 status;
129
130 if (!pdn)
131 return 0;
132
133 rtas_read_config(pdn, PCI_STATUS, 2, &status);
134 if (!(status & PCI_STATUS_CAP_LIST))
135 return 0;
136
137 return PCI_CAPABILITY_LIST;
138}
139
140
141static int pseries_eeh_find_cap(struct pci_dn *pdn, int cap)
142{
143 int pos = pseries_eeh_cap_start(pdn);
144 int cnt = 48;
145 u32 id;
146
147 if (!pos)
148 return 0;
149
150 while (cnt--) {
151 rtas_read_config(pdn, pos, 1, &pos);
152 if (pos < 0x40)
153 break;
154 pos &= ~3;
155 rtas_read_config(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
156 if (id == 0xff)
157 break;
158 if (id == cap)
159 return pos;
160 pos += PCI_CAP_LIST_NEXT;
161 }
162
163 return 0;
164}
165
166static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
167{
168 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
169 u32 header;
170 int pos = 256;
171 int ttl = (4096 - 256) / 8;
172
173 if (!edev || !edev->pcie_cap)
174 return 0;
175 if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
176 return 0;
177 else if (!header)
178 return 0;
179
180 while (ttl-- > 0) {
181 if (PCI_EXT_CAP_ID(header) == cap && pos)
182 return pos;
183
184 pos = PCI_EXT_CAP_NEXT(header);
185 if (pos < 256)
186 break;
187
188 if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
189 break;
190 }
191
192 return 0;
193}
194
195
196
197
198
199
200
201
202
203
204static void *pseries_eeh_probe(struct pci_dn *pdn, void *data)
205{
206 struct eeh_dev *edev;
207 struct eeh_pe pe;
208 u32 pcie_flags;
209 int enable = 0;
210 int ret;
211
212
213 edev = pdn_to_eeh_dev(pdn);
214 if (!edev || edev->pe)
215 return NULL;
216
217
218 if (!pdn->vendor_id || !pdn->device_id || !pdn->class_code)
219 return NULL;
220
221
222 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
223 return NULL;
224
225
226
227
228
229
230 edev->class_code = pdn->class_code;
231 edev->pcix_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
232 edev->pcie_cap = pseries_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
233 edev->aer_cap = pseries_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
234 edev->mode &= 0xFFFFFF00;
235 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
236 edev->mode |= EEH_DEV_BRIDGE;
237 if (edev->pcie_cap) {
238 rtas_read_config(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
239 2, &pcie_flags);
240 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
241 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
242 edev->mode |= EEH_DEV_ROOT_PORT;
243 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
244 edev->mode |= EEH_DEV_DS_PORT;
245 }
246 }
247
248
249 memset(&pe, 0, sizeof(struct eeh_pe));
250 pe.phb = edev->phb;
251 pe.config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
252
253
254 ret = eeh_ops->set_option(&pe, EEH_OPT_ENABLE);
255 if (!ret) {
256
257 edev->config_addr = (pdn->busno << 16) | (pdn->devfn << 8);
258 edev->pe_config_addr = eeh_ops->get_pe_addr(&pe);
259 pe.addr = edev->pe_config_addr;
260
261
262
263
264
265 ret = eeh_ops->get_state(&pe, NULL);
266 if (ret > 0 && ret != EEH_STATE_NOT_SUPPORT)
267 enable = 1;
268
269 if (enable) {
270 eeh_add_flag(EEH_ENABLED);
271 eeh_add_to_parent_pe(edev);
272
273 pr_debug("%s: EEH enabled on %02x:%02x.%01x PHB#%d-PE#%x\n",
274 __func__, pdn->busno, PCI_SLOT(pdn->devfn),
275 PCI_FUNC(pdn->devfn), pe.phb->global_number,
276 pe.addr);
277 } else if (pdn->parent && pdn_to_eeh_dev(pdn->parent) &&
278 (pdn_to_eeh_dev(pdn->parent))->pe) {
279
280
281
282 edev->config_addr = pdn_to_eeh_dev(pdn->parent)->config_addr;
283 edev->pe_config_addr = pdn_to_eeh_dev(pdn->parent)->pe_config_addr;
284 eeh_add_to_parent_pe(edev);
285 }
286 }
287
288
289 eeh_save_bars(edev);
290
291 return NULL;
292}
293
294
295
296
297
298
299
300
301
302
303static int pseries_eeh_set_option(struct eeh_pe *pe, int option)
304{
305 int ret = 0;
306 int config_addr;
307
308
309
310
311
312
313
314 switch (option) {
315 case EEH_OPT_DISABLE:
316 case EEH_OPT_ENABLE:
317 case EEH_OPT_THAW_MMIO:
318 case EEH_OPT_THAW_DMA:
319 config_addr = pe->config_addr;
320 if (pe->addr)
321 config_addr = pe->addr;
322 break;
323 case EEH_OPT_FREEZE_PE:
324
325 return 0;
326 default:
327 pr_err("%s: Invalid option %d\n",
328 __func__, option);
329 return -EINVAL;
330 }
331
332 ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
333 config_addr, BUID_HI(pe->phb->buid),
334 BUID_LO(pe->phb->buid), option);
335
336 return ret;
337}
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352static int pseries_eeh_get_pe_addr(struct eeh_pe *pe)
353{
354 int ret = 0;
355 int rets[3];
356
357 if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
358
359
360
361
362
363 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
364 pe->config_addr, BUID_HI(pe->phb->buid),
365 BUID_LO(pe->phb->buid), 1);
366 if (ret || (rets[0] == 0))
367 return 0;
368
369
370 ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
371 pe->config_addr, BUID_HI(pe->phb->buid),
372 BUID_LO(pe->phb->buid), 0);
373 if (ret) {
374 pr_warn("%s: Failed to get address for PHB#%d-PE#%x\n",
375 __func__, pe->phb->global_number, pe->config_addr);
376 return 0;
377 }
378
379 return rets[0];
380 }
381
382 if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
383 ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
384 pe->config_addr, BUID_HI(pe->phb->buid),
385 BUID_LO(pe->phb->buid), 0);
386 if (ret) {
387 pr_warn("%s: Failed to get address for PHB#%d-PE#%x\n",
388 __func__, pe->phb->global_number, pe->config_addr);
389 return 0;
390 }
391
392 return rets[0];
393 }
394
395 return ret;
396}
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411static int pseries_eeh_get_state(struct eeh_pe *pe, int *state)
412{
413 int config_addr;
414 int ret;
415 int rets[4];
416 int result;
417
418
419 config_addr = pe->config_addr;
420 if (pe->addr)
421 config_addr = pe->addr;
422
423 if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
424 ret = rtas_call(ibm_read_slot_reset_state2, 3, 4, rets,
425 config_addr, BUID_HI(pe->phb->buid),
426 BUID_LO(pe->phb->buid));
427 } else if (ibm_read_slot_reset_state != RTAS_UNKNOWN_SERVICE) {
428
429 rets[2] = 0;
430 ret = rtas_call(ibm_read_slot_reset_state, 3, 3, rets,
431 config_addr, BUID_HI(pe->phb->buid),
432 BUID_LO(pe->phb->buid));
433 } else {
434 return EEH_STATE_NOT_SUPPORT;
435 }
436
437 if (ret)
438 return ret;
439
440
441 result = 0;
442 if (rets[1]) {
443 switch(rets[0]) {
444 case 0:
445 result &= ~EEH_STATE_RESET_ACTIVE;
446 result |= EEH_STATE_MMIO_ACTIVE;
447 result |= EEH_STATE_DMA_ACTIVE;
448 break;
449 case 1:
450 result |= EEH_STATE_RESET_ACTIVE;
451 result |= EEH_STATE_MMIO_ACTIVE;
452 result |= EEH_STATE_DMA_ACTIVE;
453 break;
454 case 2:
455 result &= ~EEH_STATE_RESET_ACTIVE;
456 result &= ~EEH_STATE_MMIO_ACTIVE;
457 result &= ~EEH_STATE_DMA_ACTIVE;
458 break;
459 case 4:
460 result &= ~EEH_STATE_RESET_ACTIVE;
461 result &= ~EEH_STATE_MMIO_ACTIVE;
462 result &= ~EEH_STATE_DMA_ACTIVE;
463 result |= EEH_STATE_MMIO_ENABLED;
464 break;
465 case 5:
466 if (rets[2]) {
467 if (state) *state = rets[2];
468 result = EEH_STATE_UNAVAILABLE;
469 } else {
470 result = EEH_STATE_NOT_SUPPORT;
471 }
472 break;
473 default:
474 result = EEH_STATE_NOT_SUPPORT;
475 }
476 } else {
477 result = EEH_STATE_NOT_SUPPORT;
478 }
479
480 return result;
481}
482
483
484
485
486
487
488
489
490static int pseries_eeh_reset(struct eeh_pe *pe, int option)
491{
492 int config_addr;
493 int ret;
494
495
496 config_addr = pe->config_addr;
497 if (pe->addr)
498 config_addr = pe->addr;
499
500
501 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
502 config_addr, BUID_HI(pe->phb->buid),
503 BUID_LO(pe->phb->buid), option);
504
505
506 if (option == EEH_RESET_FUNDAMENTAL &&
507 ret == -8) {
508 option = EEH_RESET_HOT;
509 ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
510 config_addr, BUID_HI(pe->phb->buid),
511 BUID_LO(pe->phb->buid), option);
512 }
513
514
515 if (option == EEH_RESET_FUNDAMENTAL ||
516 option == EEH_RESET_HOT)
517 msleep(EEH_PE_RST_HOLD_TIME);
518 else
519 msleep(EEH_PE_RST_SETTLE_TIME);
520
521 return ret;
522}
523
524
525
526
527
528
529
530
531
532static int pseries_eeh_wait_state(struct eeh_pe *pe, int max_wait)
533{
534 int ret;
535 int mwait;
536
537
538
539
540
541
542
543
544
545#define EEH_STATE_MIN_WAIT_TIME (1000)
546#define EEH_STATE_MAX_WAIT_TIME (300 * 1000)
547
548 while (1) {
549 ret = pseries_eeh_get_state(pe, &mwait);
550
551
552
553
554
555
556 if (ret != EEH_STATE_UNAVAILABLE)
557 return ret;
558
559 if (max_wait <= 0) {
560 pr_warn("%s: Timeout when getting PE's state (%d)\n",
561 __func__, max_wait);
562 return EEH_STATE_NOT_SUPPORT;
563 }
564
565 if (mwait <= 0) {
566 pr_warn("%s: Firmware returned bad wait value %d\n",
567 __func__, mwait);
568 mwait = EEH_STATE_MIN_WAIT_TIME;
569 } else if (mwait > EEH_STATE_MAX_WAIT_TIME) {
570 pr_warn("%s: Firmware returned too long wait value %d\n",
571 __func__, mwait);
572 mwait = EEH_STATE_MAX_WAIT_TIME;
573 }
574
575 max_wait -= mwait;
576 msleep(mwait);
577 }
578
579 return EEH_STATE_NOT_SUPPORT;
580}
581
582
583
584
585
586
587
588
589
590
591
592
593static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len)
594{
595 int config_addr;
596 unsigned long flags;
597 int ret;
598
599 spin_lock_irqsave(&slot_errbuf_lock, flags);
600 memset(slot_errbuf, 0, eeh_error_buf_size);
601
602
603 config_addr = pe->config_addr;
604 if (pe->addr)
605 config_addr = pe->addr;
606
607 ret = rtas_call(ibm_slot_error_detail, 8, 1, NULL, config_addr,
608 BUID_HI(pe->phb->buid), BUID_LO(pe->phb->buid),
609 virt_to_phys(drv_log), len,
610 virt_to_phys(slot_errbuf), eeh_error_buf_size,
611 severity);
612 if (!ret)
613 log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
614 spin_unlock_irqrestore(&slot_errbuf_lock, flags);
615
616 return ret;
617}
618
619
620
621
622
623
624
625
626
627static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
628{
629 int config_addr;
630 int ret;
631
632 int max_wait = 200;
633
634
635 config_addr = pe->config_addr;
636 if (pe->addr)
637 config_addr = pe->addr;
638
639 while (max_wait > 0) {
640 ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
641 config_addr, BUID_HI(pe->phb->buid),
642 BUID_LO(pe->phb->buid));
643
644 if (!ret)
645 return ret;
646
647
648
649
650
651
652 if (ret > RTAS_EXTENDED_DELAY_MIN+2 &&
653 ret <= RTAS_EXTENDED_DELAY_MAX)
654 ret = RTAS_EXTENDED_DELAY_MIN+2;
655
656 max_wait -= rtas_busy_delay_time(ret);
657
658 if (max_wait < 0)
659 break;
660
661 rtas_busy_delay(ret);
662 }
663
664 pr_warn("%s: Unable to configure bridge PHB#%d-PE#%x (%d)\n",
665 __func__, pe->phb->global_number, pe->addr, ret);
666 return ret;
667}
668
669
670
671
672
673
674
675
676
677
678static int pseries_eeh_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
679{
680 return rtas_read_config(pdn, where, size, val);
681}
682
683
684
685
686
687
688
689
690
691
692static int pseries_eeh_write_config(struct pci_dn *pdn, int where, int size, u32 val)
693{
694 return rtas_write_config(pdn, where, size, val);
695}
696
697static struct eeh_ops pseries_eeh_ops = {
698 .name = "pseries",
699 .init = pseries_eeh_init,
700 .probe = pseries_eeh_probe,
701 .set_option = pseries_eeh_set_option,
702 .get_pe_addr = pseries_eeh_get_pe_addr,
703 .get_state = pseries_eeh_get_state,
704 .reset = pseries_eeh_reset,
705 .wait_state = pseries_eeh_wait_state,
706 .get_log = pseries_eeh_get_log,
707 .configure_bridge = pseries_eeh_configure_bridge,
708 .err_inject = NULL,
709 .read_config = pseries_eeh_read_config,
710 .write_config = pseries_eeh_write_config,
711 .next_error = NULL,
712 .restore_config = NULL
713};
714
715
716
717
718
719
720
721static int __init eeh_pseries_init(void)
722{
723 int ret = -EINVAL;
724
725 if (!machine_is(pseries))
726 return ret;
727
728 ret = eeh_ops_register(&pseries_eeh_ops);
729 if (!ret)
730 pr_info("EEH: pSeries platform initialized\n");
731 else
732 pr_info("EEH: pSeries platform initialization failure (%d)\n",
733 ret);
734
735 return ret;
736}
737
738early_initcall(eeh_pseries_init);
739