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20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/bootmem.h>
26#include <linux/memblock.h>
27#include <linux/log2.h>
28#include <linux/slab.h>
29
30#include <asm/io.h>
31#include <asm/prom.h>
32#include <asm/pci-bridge.h>
33#include <asm/machdep.h>
34#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h>
36
37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38
39static void quirk_fsl_pcie_header(struct pci_dev *dev)
40{
41 u8 hdr_type;
42
43
44 if (!pci_is_pcie(dev))
45 return;
46
47
48 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
49 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
50 return;
51
52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
54 return;
55}
56
57static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
58 int, int, u32 *);
59
60static int fsl_pcie_check_link(struct pci_controller *hose)
61{
62 u32 val = 0;
63
64 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
65 if (hose->ops->read == fsl_indirect_read_config) {
66 struct pci_bus bus;
67 bus.number = hose->first_busno;
68 bus.sysdata = hose;
69 bus.ops = hose->ops;
70 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
71 } else
72 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
73 if (val < PCIE_LTSSM_L0)
74 return 1;
75 } else {
76 struct ccsr_pci __iomem *pci = hose->private_data;
77
78 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
79 >> PEX_CSR0_LTSSM_SHIFT;
80 if (val != PEX_CSR0_LTSSM_L0)
81 return 1;
82 }
83
84 return 0;
85}
86
87static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
88 int offset, int len, u32 *val)
89{
90 struct pci_controller *hose = pci_bus_to_host(bus);
91
92 if (fsl_pcie_check_link(hose))
93 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
94 else
95 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
96
97 return indirect_read_config(bus, devfn, offset, len, val);
98}
99
100#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
101
102static struct pci_ops fsl_indirect_pcie_ops =
103{
104 .read = fsl_indirect_read_config,
105 .write = indirect_write_config,
106};
107
108#define MAX_PHYS_ADDR_BITS 40
109static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
110
111#ifdef CONFIG_SWIOTLB
112static void setup_swiotlb_ops(struct pci_controller *hose)
113{
114 if (ppc_swiotlb_enable) {
115 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;
116 set_pci_dma_ops(&swiotlb_dma_ops);
117 }
118}
119#else
120static inline void setup_swiotlb_ops(struct pci_controller *hose) {}
121#endif
122
123static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
124{
125 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
126 return -EIO;
127
128
129
130
131
132
133 if ((dev->bus == &pci_bus_type) &&
134 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
135 set_dma_ops(dev, &dma_direct_ops);
136 set_dma_offset(dev, pci64_dma_offset);
137 }
138
139 *dev->dma_mask = dma_mask;
140 return 0;
141}
142
143static int setup_one_atmu(struct ccsr_pci __iomem *pci,
144 unsigned int index, const struct resource *res,
145 resource_size_t offset)
146{
147 resource_size_t pci_addr = res->start - offset;
148 resource_size_t phys_addr = res->start;
149 resource_size_t size = resource_size(res);
150 u32 flags = 0x80044000;
151 unsigned int i;
152
153 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
154 (u64)res->start, (u64)size);
155
156 if (res->flags & IORESOURCE_PREFETCH)
157 flags |= 0x10000000;
158
159 for (i = 0; size > 0; i++) {
160 unsigned int bits = min(ilog2(size),
161 __ffs(pci_addr | phys_addr));
162
163 if (index + i >= 5)
164 return -1;
165
166 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
167 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
168 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
169 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
170
171 pci_addr += (resource_size_t)1U << bits;
172 phys_addr += (resource_size_t)1U << bits;
173 size -= (resource_size_t)1U << bits;
174 }
175
176 return i;
177}
178
179
180static void setup_pci_atmu(struct pci_controller *hose)
181{
182 struct ccsr_pci __iomem *pci = hose->private_data;
183 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
184 u64 mem, sz, paddr_hi = 0;
185 u64 offset = 0, paddr_lo = ULLONG_MAX;
186 u32 pcicsrbar = 0, pcicsrbar_sz;
187 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
188 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
189 const char *name = hose->dn->full_name;
190 const u64 *reg;
191 int len;
192
193 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
194 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
195 win_idx = 2;
196 start_idx = 0;
197 end_idx = 3;
198 }
199 }
200
201
202 for(i = 1; i < 5; i++)
203 out_be32(&pci->pow[i].powar, 0);
204 for (i = start_idx; i < end_idx; i++)
205 out_be32(&pci->piw[i].piwar, 0);
206
207
208 for(i = 0, j = 1; i < 3; i++) {
209 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
210 continue;
211
212 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
213 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
214
215
216 offset = hose->mem_offset[i];
217 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
218
219 if (n < 0 || j >= 5) {
220 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
221 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
222 } else
223 j += n;
224 }
225
226
227 if (hose->io_resource.flags & IORESOURCE_IO) {
228 if (j >= 5) {
229 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
230 } else {
231 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
232 "phy base 0x%016llx.\n",
233 (u64)hose->io_resource.start,
234 (u64)resource_size(&hose->io_resource),
235 (u64)hose->io_base_phys);
236 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
237 out_be32(&pci->pow[j].potear, 0);
238 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
239
240 out_be32(&pci->pow[j].powar, 0x80088000
241 | (ilog2(hose->io_resource.end
242 - hose->io_resource.start + 1) - 1));
243 }
244 }
245
246
247 paddr_hi -= offset;
248 paddr_lo -= offset;
249
250 if (paddr_hi == paddr_lo) {
251 pr_err("%s: No outbound window space\n", name);
252 return;
253 }
254
255 if (paddr_lo == 0) {
256 pr_err("%s: No space for inbound window\n", name);
257 return;
258 }
259
260
261 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
262 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
263 pcicsrbar_sz = ~pcicsrbar_sz + 1;
264
265 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
266 (paddr_lo > 0x100000000ull))
267 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
268 else
269 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
270 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
271
272 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
273
274 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
275
276
277 mem = memblock_end_of_DRAM();
278
279
280
281
282
283
284
285
286
287
288
289
290
291 reg = of_get_property(hose->dn, "msi-address-64", &len);
292 if (reg && (len == sizeof(u64))) {
293 u64 address = be64_to_cpup(reg);
294
295 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
296 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
297 mem += PAGE_SIZE;
298 } else {
299
300 pr_warn("%s: msi-address-64 address of %llx is "
301 "unsupported\n", name, address);
302 }
303 }
304
305 sz = min(mem, paddr_lo);
306 mem_log = ilog2(sz);
307
308
309 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
310
311 if ((1ull << mem_log) != mem) {
312 if ((1ull << mem_log) > mem)
313 pr_info("%s: Setting PCI inbound window "
314 "greater than memory size\n", name);
315 mem_log++;
316 }
317
318 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
319
320
321 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
322 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
323 out_be32(&pci->piw[win_idx].piwar, piwar);
324 win_idx--;
325
326 hose->dma_window_base_cur = 0x00000000;
327 hose->dma_window_size = (resource_size_t)sz;
328
329
330
331
332
333
334 if (sz != mem) {
335 mem_log = ilog2(mem);
336
337
338 if ((1ull << mem_log) != mem)
339 mem_log++;
340
341 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
342
343
344 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
345 out_be32(&pci->piw[win_idx].piwbear,
346 pci64_dma_offset >> 44);
347 out_be32(&pci->piw[win_idx].piwbar,
348 pci64_dma_offset >> 12);
349 out_be32(&pci->piw[win_idx].piwar, piwar);
350
351
352
353
354
355 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
356
357 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
358 }
359 } else {
360 u64 paddr = 0;
361
362
363 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
364 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
365 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
366 win_idx--;
367
368 paddr += 1ull << mem_log;
369 sz -= 1ull << mem_log;
370
371 if (sz) {
372 mem_log = ilog2(sz);
373 piwar |= (mem_log - 1);
374
375 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
376 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
377 out_be32(&pci->piw[win_idx].piwar, piwar);
378 win_idx--;
379
380 paddr += 1ull << mem_log;
381 }
382
383 hose->dma_window_base_cur = 0x00000000;
384 hose->dma_window_size = (resource_size_t)paddr;
385 }
386
387 if (hose->dma_window_size < mem) {
388#ifndef CONFIG_SWIOTLB
389 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
390 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
391 name);
392#endif
393
394 if (paddr_hi < 0xffffffffull)
395 pr_warning("%s: WARNING: Outbound window cfg leaves "
396 "gaps in memory map. Adjusting the memory map "
397 "could reduce unnecessary bounce buffering.\n",
398 name);
399
400 pr_info("%s: DMA window size is 0x%llx\n", name,
401 (u64)hose->dma_window_size);
402 }
403}
404
405static void __init setup_pci_cmd(struct pci_controller *hose)
406{
407 u16 cmd;
408 int cap_x;
409
410 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
411 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
412 | PCI_COMMAND_IO;
413 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
414
415 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
416 if (cap_x) {
417 int pci_x_cmd = cap_x + PCI_X_CMD;
418 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
419 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
420 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
421 } else {
422 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
423 }
424}
425
426void fsl_pcibios_fixup_bus(struct pci_bus *bus)
427{
428 struct pci_controller *hose = pci_bus_to_host(bus);
429 int i, is_pcie = 0, no_link;
430
431
432
433
434
435
436
437
438
439 if (fsl_pcie_bus_fixup)
440 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
441 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
442
443 if (bus->parent == hose->bus && (is_pcie || no_link)) {
444 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
445 struct resource *res = bus->resource[i];
446 struct resource *par;
447
448 if (!res)
449 continue;
450 if (i == 0)
451 par = &hose->io_resource;
452 else if (i < 4)
453 par = &hose->mem_resources[i-1];
454 else par = NULL;
455
456 res->start = par ? par->start : 0;
457 res->end = par ? par->end : 0;
458 res->flags = par ? par->flags : 0;
459 }
460 }
461}
462
463int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
464{
465 int len;
466 struct pci_controller *hose;
467 struct resource rsrc;
468 const int *bus_range;
469 u8 hdr_type, progif;
470 struct device_node *dev;
471 struct ccsr_pci __iomem *pci;
472
473 dev = pdev->dev.of_node;
474
475 if (!of_device_is_available(dev)) {
476 pr_warning("%s: disabled\n", dev->full_name);
477 return -ENODEV;
478 }
479
480 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
481
482
483 if (of_address_to_resource(dev, 0, &rsrc)) {
484 printk(KERN_WARNING "Can't get pci register base!");
485 return -ENOMEM;
486 }
487
488
489 bus_range = of_get_property(dev, "bus-range", &len);
490 if (bus_range == NULL || len < 2 * sizeof(int))
491 printk(KERN_WARNING "Can't get bus-range for %s, assume"
492 " bus 0\n", dev->full_name);
493
494 pci_add_flags(PCI_REASSIGN_ALL_BUS);
495 hose = pcibios_alloc_controller(dev);
496 if (!hose)
497 return -ENOMEM;
498
499
500 hose->parent = &pdev->dev;
501 hose->first_busno = bus_range ? bus_range[0] : 0x0;
502 hose->last_busno = bus_range ? bus_range[1] : 0xff;
503
504 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
505 (u64)rsrc.start, (u64)resource_size(&rsrc));
506
507 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
508 if (!hose->private_data)
509 goto no_bridge;
510
511 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
512 PPC_INDIRECT_TYPE_BIG_ENDIAN);
513
514 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
515 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
516
517 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
518
519 hose->ops = &fsl_indirect_pcie_ops;
520
521 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
522 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
523 goto no_bridge;
524
525 } else {
526
527 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
528 if ((progif & 1) == 1)
529 goto no_bridge;
530 }
531
532 setup_pci_cmd(hose);
533
534
535 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
536 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
537 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
538 if (fsl_pcie_check_link(hose))
539 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
540 }
541
542 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
543 "Firmware bus number: %d->%d\n",
544 (unsigned long long)rsrc.start, hose->first_busno,
545 hose->last_busno);
546
547 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
548 hose, hose->cfg_addr, hose->cfg_data);
549
550
551
552 pci_process_bridge_OF_ranges(hose, dev, is_primary);
553
554
555 setup_pci_atmu(hose);
556
557
558 setup_swiotlb_ops(hose);
559
560 return 0;
561
562no_bridge:
563 iounmap(hose->private_data);
564
565 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
566 ((unsigned long)hose->cfg_addr & PAGE_MASK))
567 iounmap(hose->cfg_data);
568 iounmap(hose->cfg_addr);
569 pcibios_free_controller(hose);
570 return -ENODEV;
571}
572#endif
573
574DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
575
576#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
577struct mpc83xx_pcie_priv {
578 void __iomem *cfg_type0;
579 void __iomem *cfg_type1;
580 u32 dev_base;
581};
582
583struct pex_inbound_window {
584 u32 ar;
585 u32 tar;
586 u32 barl;
587 u32 barh;
588};
589
590
591
592
593
594#define PEX_OUTWIN0_BAR 0xCA4
595#define PEX_OUTWIN0_TAL 0xCA8
596#define PEX_OUTWIN0_TAH 0xCAC
597#define PEX_RC_INWIN_BASE 0xE60
598#define PEX_RCIWARn_EN 0x1
599
600static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
601{
602 struct pci_controller *hose = pci_bus_to_host(bus);
603
604 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
605 return PCIBIOS_DEVICE_NOT_FOUND;
606
607
608
609
610
611 if (bus->number == hose->first_busno ||
612 bus->primary == hose->first_busno) {
613 if (devfn & 0xf8)
614 return PCIBIOS_DEVICE_NOT_FOUND;
615 }
616
617 if (ppc_md.pci_exclude_device) {
618 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
619 return PCIBIOS_DEVICE_NOT_FOUND;
620 }
621
622 return PCIBIOS_SUCCESSFUL;
623}
624
625static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
626 unsigned int devfn, int offset)
627{
628 struct pci_controller *hose = pci_bus_to_host(bus);
629 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
630 u32 dev_base = bus->number << 24 | devfn << 16;
631 int ret;
632
633 ret = mpc83xx_pcie_exclude_device(bus, devfn);
634 if (ret)
635 return NULL;
636
637 offset &= 0xfff;
638
639
640 if (bus->number == hose->first_busno)
641 return pcie->cfg_type0 + offset;
642
643 if (pcie->dev_base == dev_base)
644 goto mapped;
645
646 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
647
648 pcie->dev_base = dev_base;
649mapped:
650 return pcie->cfg_type1 + offset;
651}
652
653static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
654 int offset, int len, u32 *val)
655{
656 void __iomem *cfg_addr;
657
658 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
659 if (!cfg_addr)
660 return PCIBIOS_DEVICE_NOT_FOUND;
661
662 switch (len) {
663 case 1:
664 *val = in_8(cfg_addr);
665 break;
666 case 2:
667 *val = in_le16(cfg_addr);
668 break;
669 default:
670 *val = in_le32(cfg_addr);
671 break;
672 }
673
674 return PCIBIOS_SUCCESSFUL;
675}
676
677static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
678 int offset, int len, u32 val)
679{
680 struct pci_controller *hose = pci_bus_to_host(bus);
681 void __iomem *cfg_addr;
682
683 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
684 if (!cfg_addr)
685 return PCIBIOS_DEVICE_NOT_FOUND;
686
687
688 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
689 val &= 0xffffff00;
690
691 switch (len) {
692 case 1:
693 out_8(cfg_addr, val);
694 break;
695 case 2:
696 out_le16(cfg_addr, val);
697 break;
698 default:
699 out_le32(cfg_addr, val);
700 break;
701 }
702
703 return PCIBIOS_SUCCESSFUL;
704}
705
706static struct pci_ops mpc83xx_pcie_ops = {
707 .read = mpc83xx_pcie_read_config,
708 .write = mpc83xx_pcie_write_config,
709};
710
711static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
712 struct resource *reg)
713{
714 struct mpc83xx_pcie_priv *pcie;
715 u32 cfg_bar;
716 int ret = -ENOMEM;
717
718 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
719 if (!pcie)
720 return ret;
721
722 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
723 if (!pcie->cfg_type0)
724 goto err0;
725
726 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
727 if (!cfg_bar) {
728
729 ret = -ENODEV;
730 goto err1;
731 }
732
733 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
734 if (!pcie->cfg_type1)
735 goto err1;
736
737 WARN_ON(hose->dn->data);
738 hose->dn->data = pcie;
739 hose->ops = &mpc83xx_pcie_ops;
740 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
741
742 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
743 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
744
745 if (fsl_pcie_check_link(hose))
746 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
747
748 return 0;
749err1:
750 iounmap(pcie->cfg_type0);
751err0:
752 kfree(pcie);
753 return ret;
754
755}
756
757int __init mpc83xx_add_bridge(struct device_node *dev)
758{
759 int ret;
760 int len;
761 struct pci_controller *hose;
762 struct resource rsrc_reg;
763 struct resource rsrc_cfg;
764 const int *bus_range;
765 int primary;
766
767 is_mpc83xx_pci = 1;
768
769 if (!of_device_is_available(dev)) {
770 pr_warning("%s: disabled by the firmware.\n",
771 dev->full_name);
772 return -ENODEV;
773 }
774 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
775
776
777 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
778 printk(KERN_WARNING "Can't get pci register base!\n");
779 return -ENOMEM;
780 }
781
782 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
783
784 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
785 printk(KERN_WARNING
786 "No pci config register base in dev tree, "
787 "using default\n");
788
789
790
791
792
793 if ((rsrc_reg.start & 0xfffff) == 0x8500)
794 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
795 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
796 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
797 }
798
799
800
801 if ((rsrc_reg.start & 0xfffff) == 0x8500)
802 primary = 1;
803 else
804 primary = 0;
805
806
807 bus_range = of_get_property(dev, "bus-range", &len);
808 if (bus_range == NULL || len < 2 * sizeof(int)) {
809 printk(KERN_WARNING "Can't get bus-range for %s, assume"
810 " bus 0\n", dev->full_name);
811 }
812
813 pci_add_flags(PCI_REASSIGN_ALL_BUS);
814 hose = pcibios_alloc_controller(dev);
815 if (!hose)
816 return -ENOMEM;
817
818 hose->first_busno = bus_range ? bus_range[0] : 0;
819 hose->last_busno = bus_range ? bus_range[1] : 0xff;
820
821 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
822 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
823 if (ret)
824 goto err0;
825 } else {
826 setup_indirect_pci(hose, rsrc_cfg.start,
827 rsrc_cfg.start + 4, 0);
828 }
829
830 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
831 "Firmware bus number: %d->%d\n",
832 (unsigned long long)rsrc_reg.start, hose->first_busno,
833 hose->last_busno);
834
835 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
836 hose, hose->cfg_addr, hose->cfg_data);
837
838
839
840 pci_process_bridge_OF_ranges(hose, dev, primary);
841
842 return 0;
843err0:
844 pcibios_free_controller(hose);
845 return ret;
846}
847#endif
848
849u64 fsl_pci_immrbar_base(struct pci_controller *hose)
850{
851#ifdef CONFIG_PPC_83xx
852 if (is_mpc83xx_pci) {
853 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
854 struct pex_inbound_window *in;
855 int i;
856
857
858 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
859 for (i = 0; i < 4; i++) {
860
861 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
862 continue;
863
864 if (get_immrbase() == in_le32(&in[i].tar))
865 return (u64)in_le32(&in[i].barh) << 32 |
866 in_le32(&in[i].barl);
867 }
868
869 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
870 }
871#endif
872
873#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
874 if (!is_mpc83xx_pci) {
875 u32 base;
876
877 pci_bus_read_config_dword(hose->bus,
878 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
879 return base;
880 }
881#endif
882
883 return 0;
884}
885
886#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
887static const struct of_device_id pci_ids[] = {
888 { .compatible = "fsl,mpc8540-pci", },
889 { .compatible = "fsl,mpc8548-pcie", },
890 { .compatible = "fsl,mpc8610-pci", },
891 { .compatible = "fsl,mpc8641-pcie", },
892 { .compatible = "fsl,qoriq-pcie-v2.1", },
893 { .compatible = "fsl,qoriq-pcie-v2.2", },
894 { .compatible = "fsl,qoriq-pcie-v2.3", },
895 { .compatible = "fsl,qoriq-pcie-v2.4", },
896 { .compatible = "fsl,qoriq-pcie-v3.0", },
897
898
899
900
901
902 { .compatible = "fsl,p1022-pcie", },
903 { .compatible = "fsl,p4080-pcie", },
904
905 {},
906};
907
908struct device_node *fsl_pci_primary;
909
910void fsl_pci_assign_primary(void)
911{
912 struct device_node *np;
913
914
915 if (fsl_pci_primary)
916 return;
917
918
919 np = of_find_node_by_type(NULL, "isa");
920 while ((fsl_pci_primary = of_get_parent(np))) {
921 of_node_put(np);
922 np = fsl_pci_primary;
923
924 if (of_match_node(pci_ids, np) && of_device_is_available(np))
925 return;
926 }
927
928
929
930
931
932
933 for_each_matching_node(np, pci_ids) {
934 if (of_device_is_available(np)) {
935 fsl_pci_primary = np;
936 of_node_put(np);
937 return;
938 }
939 }
940}
941
942static int fsl_pci_probe(struct platform_device *pdev)
943{
944 int ret;
945 struct device_node *node;
946#ifdef CONFIG_SWIOTLB
947 struct pci_controller *hose;
948#endif
949
950 node = pdev->dev.of_node;
951 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
952
953#ifdef CONFIG_SWIOTLB
954 if (ret == 0) {
955 hose = pci_find_hose_for_OF_device(pdev->dev.of_node);
956
957
958
959
960
961
962 if (memblock_end_of_DRAM() - 1 > hose->dma_window_base_cur +
963 hose->dma_window_size)
964 ppc_swiotlb_enable = 1;
965 }
966#endif
967
968 mpc85xx_pci_err_probe(pdev);
969
970 return 0;
971}
972
973#ifdef CONFIG_PM
974static int fsl_pci_resume(struct device *dev)
975{
976 struct pci_controller *hose;
977 struct resource pci_rsrc;
978
979 hose = pci_find_hose_for_OF_device(dev->of_node);
980 if (!hose)
981 return -ENODEV;
982
983 if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
984 dev_err(dev, "Get pci register base failed.");
985 return -ENODEV;
986 }
987
988 setup_pci_atmu(hose);
989
990 return 0;
991}
992
993static const struct dev_pm_ops pci_pm_ops = {
994 .resume = fsl_pci_resume,
995};
996
997#define PCI_PM_OPS (&pci_pm_ops)
998
999#else
1000
1001#define PCI_PM_OPS NULL
1002
1003#endif
1004
1005static struct platform_driver fsl_pci_driver = {
1006 .driver = {
1007 .name = "fsl-pci",
1008 .pm = PCI_PM_OPS,
1009 .of_match_table = pci_ids,
1010 },
1011 .probe = fsl_pci_probe,
1012};
1013
1014static int __init fsl_pci_init(void)
1015{
1016 return platform_driver_register(&fsl_pci_driver);
1017}
1018arch_initcall(fsl_pci_init);
1019#endif
1020