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7#ifndef _SPARC_PGTSRMMU_H
8#define _SPARC_PGTSRMMU_H
9
10#include <asm/page.h>
11
12#ifdef __ASSEMBLY__
13#include <asm/thread_info.h>
14#endif
15
16
17#define SRMMU_MAX_CONTEXTS 65536
18
19
20#define SRMMU_REAL_PMD_SHIFT 18
21#define SRMMU_REAL_PMD_SIZE (1UL << SRMMU_REAL_PMD_SHIFT)
22#define SRMMU_REAL_PMD_MASK (~(SRMMU_REAL_PMD_SIZE-1))
23#define SRMMU_REAL_PMD_ALIGN(__addr) (((__addr)+SRMMU_REAL_PMD_SIZE-1)&SRMMU_REAL_PMD_MASK)
24
25
26#define SRMMU_PGDIR_SHIFT 24
27#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
28#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
29#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
30
31#define SRMMU_REAL_PTRS_PER_PTE 64
32#define SRMMU_REAL_PTRS_PER_PMD 64
33#define SRMMU_PTRS_PER_PGD 256
34
35#define SRMMU_REAL_PTE_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PTE*4)
36#define SRMMU_PMD_TABLE_SIZE (SRMMU_REAL_PTRS_PER_PMD*4)
37#define SRMMU_PGD_TABLE_SIZE (SRMMU_PTRS_PER_PGD*4)
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50
51#define SRMMU_PTRS_PER_PMD 4
52
53
54#define SRMMU_ET_MASK 0x3
55#define SRMMU_ET_INVALID 0x0
56#define SRMMU_ET_PTD 0x1
57#define SRMMU_ET_PTE 0x2
58#define SRMMU_ET_REPTE 0x3
59
60
61#define SRMMU_CTX_PMASK 0xfffffff0
62#define SRMMU_PTD_PMASK 0xfffffff0
63#define SRMMU_PTE_PMASK 0xffffff00
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72
73#define SRMMU_CACHE 0x80
74#define SRMMU_DIRTY 0x40
75#define SRMMU_REF 0x20
76#define SRMMU_NOREAD 0x10
77#define SRMMU_EXEC 0x08
78#define SRMMU_WRITE 0x04
79#define SRMMU_VALID 0x02
80#define SRMMU_PRIV 0x1c
81#define SRMMU_PRIV_RDONLY 0x18
82
83#define SRMMU_FILE 0x40
84
85#define SRMMU_PTE_FILE_SHIFT 8
86
87#define SRMMU_CHG_MASK (0xffffff00 | SRMMU_REF | SRMMU_DIRTY)
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100#define SRMMU_SWP_TYPE_MASK 0x1f
101#define SRMMU_SWP_TYPE_SHIFT SRMMU_PTE_FILE_SHIFT
102#define SRMMU_SWP_OFF_MASK 0x7ffff
103#define SRMMU_SWP_OFF_SHIFT (SRMMU_PTE_FILE_SHIFT + 5)
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109
110#define SRMMU_PAGE_NONE __pgprot(SRMMU_CACHE | \
111 SRMMU_PRIV | SRMMU_REF)
112#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
113 SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
114#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
115 SRMMU_EXEC | SRMMU_REF)
116#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
117 SRMMU_EXEC | SRMMU_REF)
118#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV | \
119 SRMMU_DIRTY | SRMMU_REF)
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123
124#define SRMMU_CTRL_REG 0x00000000
125#define SRMMU_CTXTBL_PTR 0x00000100
126#define SRMMU_CTX_REG 0x00000200
127#define SRMMU_FAULT_STATUS 0x00000300
128#define SRMMU_FAULT_ADDR 0x00000400
129
130#define WINDOW_FLUSH(tmp1, tmp2) \
131 mov 0, tmp1; \
13298: ld [%g6 + TI_UWINMASK], tmp2; \
133 orcc %g0, tmp2, %g0; \
134 add tmp1, 1, tmp1; \
135 bne 98b; \
136 save %sp, -64, %sp; \
13799: subcc tmp1, 1, tmp1; \
138 bne 99b; \
139 restore %g0, %g0, %g0;
140
141#ifndef __ASSEMBLY__
142extern unsigned long last_valid_pfn;
143
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145
146extern void *srmmu_nocache_pool;
147#define __nocache_pa(VADDR) (((unsigned long)VADDR) - SRMMU_NOCACHE_VADDR + __pa((unsigned long)srmmu_nocache_pool))
148#define __nocache_va(PADDR) (__va((unsigned long)PADDR) - (unsigned long)srmmu_nocache_pool + SRMMU_NOCACHE_VADDR)
149#define __nocache_fix(VADDR) __va(__nocache_pa(VADDR))
150
151
152unsigned int srmmu_get_mmureg(void);
153void srmmu_set_mmureg(unsigned long regval);
154void srmmu_set_ctable_ptr(unsigned long paddr);
155void srmmu_set_context(int context);
156int srmmu_get_context(void);
157unsigned int srmmu_get_fstatus(void);
158unsigned int srmmu_get_faddr(void);
159
160
161static inline void srmmu_flush_whole_tlb(void)
162{
163 __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
164 "r" (0x400),
165 "i" (ASI_M_FLUSH_PROBE) : "memory");
166
167}
168
169static inline int
170srmmu_get_pte (unsigned long addr)
171{
172 register unsigned long entry;
173
174 __asm__ __volatile__("\n\tlda [%1] %2,%0\n\t" :
175 "=r" (entry):
176 "r" ((addr & 0xfffff000) | 0x400), "i" (ASI_M_FLUSH_PROBE));
177 return entry;
178}
179
180#endif
181
182#endif
183