1#ifndef _ASM_X86_MSR_INDEX_H 2#define _ASM_X86_MSR_INDEX_H 3 4/* CPU model specific register (MSR) numbers */ 5 6/* x86-64 specific MSRs */ 7#define MSR_EFER 0xc0000080 /* extended feature register */ 8#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 9#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 10#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 11#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 12#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 13#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 14#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 15#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 16 17/* EFER bits: */ 18#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 19#define _EFER_LME 8 /* Long mode enable */ 20#define _EFER_LMA 10 /* Long mode active (read-only) */ 21#define _EFER_NX 11 /* No execute enable */ 22#define _EFER_SVME 12 /* Enable virtualization */ 23#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 24#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 25 26#define EFER_SCE (1<<_EFER_SCE) 27#define EFER_LME (1<<_EFER_LME) 28#define EFER_LMA (1<<_EFER_LMA) 29#define EFER_NX (1<<_EFER_NX) 30#define EFER_SVME (1<<_EFER_SVME) 31#define EFER_LMSLE (1<<_EFER_LMSLE) 32#define EFER_FFXSR (1<<_EFER_FFXSR) 33 34/* Intel MSRs. Some also available on other CPUs */ 35 36#define MSR_IA32_SPEC_CTRL 0x00000048 37#define MSR_IA32_PRED_CMD 0x00000049 38 39#define MSR_PPIN_CTL 0x0000004e 40#define MSR_PPIN 0x0000004f 41 42#define MSR_IA32_PERFCTR0 0x000000c1 43#define MSR_IA32_PERFCTR1 0x000000c2 44#define MSR_FSB_FREQ 0x000000cd 45#define MSR_NHM_PLATFORM_INFO 0x000000ce 46 47#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 48#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 49#define NHM_C3_AUTO_DEMOTE (1UL << 25) 50#define NHM_C1_AUTO_DEMOTE (1UL << 26) 51#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 52#define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 53#define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 54 55#define MSR_PLATFORM_INFO 0x000000ce 56#define MSR_MTRRcap 0x000000fe 57#define MSR_IA32_BBL_CR_CTL 0x00000119 58#define MSR_IA32_BBL_CR_CTL3 0x0000011e 59 60#define MSR_IA32_SYSENTER_CS 0x00000174 61#define MSR_IA32_SYSENTER_ESP 0x00000175 62#define MSR_IA32_SYSENTER_EIP 0x00000176 63 64#define MSR_IA32_MCG_CAP 0x00000179 65#define MSR_IA32_MCG_STATUS 0x0000017a 66#define MSR_IA32_MCG_CTL 0x0000017b 67#define MSR_IA32_MCG_EXT_CTL 0x000004d0 68 69#define MSR_OFFCORE_RSP_0 0x000001a6 70#define MSR_OFFCORE_RSP_1 0x000001a7 71#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 72#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 73#define MSR_TURBO_RATIO_LIMIT 0x000001ad 74#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 75#define MSR_TURBO_RATIO_LIMIT2 0x000001af 76 77#define MSR_LBR_SELECT 0x000001c8 78#define MSR_LBR_TOS 0x000001c9 79#define MSR_LBR_NHM_FROM 0x00000680 80#define MSR_LBR_NHM_TO 0x000006c0 81#define MSR_LBR_CORE_FROM 0x00000040 82#define MSR_LBR_CORE_TO 0x00000060 83 84#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 85#define LBR_INFO_MISPRED BIT_ULL(63) 86#define LBR_INFO_IN_TX BIT_ULL(62) 87#define LBR_INFO_ABORT BIT_ULL(61) 88#define LBR_INFO_CYCLES 0xffff 89 90#define MSR_IA32_PEBS_ENABLE 0x000003f1 91#define MSR_IA32_DS_AREA 0x00000600 92#define MSR_IA32_PERF_CAPABILITIES 0x00000345 93#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 94 95#define MSR_IA32_RTIT_CTL 0x00000570 96#define MSR_IA32_RTIT_STATUS 0x00000571 97#define MSR_IA32_RTIT_STATUS 0x00000571 98#define MSR_IA32_RTIT_ADDR0_A 0x00000580 99#define MSR_IA32_RTIT_ADDR0_B 0x00000581 100#define MSR_IA32_RTIT_ADDR1_A 0x00000582 101#define MSR_IA32_RTIT_ADDR1_B 0x00000583 102#define MSR_IA32_RTIT_ADDR2_A 0x00000584 103#define MSR_IA32_RTIT_ADDR2_B 0x00000585 104#define MSR_IA32_RTIT_ADDR3_A 0x00000586 105#define MSR_IA32_RTIT_ADDR3_B 0x00000587 106#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 107#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 108#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 109 110#define MSR_MTRRfix64K_00000 0x00000250 111#define MSR_MTRRfix16K_80000 0x00000258 112#define MSR_MTRRfix16K_A0000 0x00000259 113#define MSR_MTRRfix4K_C0000 0x00000268 114#define MSR_MTRRfix4K_C8000 0x00000269 115#define MSR_MTRRfix4K_D0000 0x0000026a 116#define MSR_MTRRfix4K_D8000 0x0000026b 117#define MSR_MTRRfix4K_E0000 0x0000026c 118#define MSR_MTRRfix4K_E8000 0x0000026d 119#define MSR_MTRRfix4K_F0000 0x0000026e 120#define MSR_MTRRfix4K_F8000 0x0000026f 121#define MSR_MTRRdefType 0x000002ff 122 123#define MSR_IA32_CR_PAT 0x00000277 124 125#define MSR_IA32_DEBUGCTLMSR 0x000001d9 126#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 127#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 128#define MSR_IA32_LASTINTFROMIP 0x000001dd 129#define MSR_IA32_LASTINTTOIP 0x000001de 130 131/* DEBUGCTLMSR bits (others vary by model): */ 132#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 133#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 134#define DEBUGCTLMSR_TR (1UL << 6) 135#define DEBUGCTLMSR_BTS (1UL << 7) 136#define DEBUGCTLMSR_BTINT (1UL << 8) 137#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 138#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 139#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 140#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 141#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 142 143#define MSR_PEBS_FRONTEND 0x000003f7 144 145#define MSR_IA32_POWER_CTL 0x000001fc 146 147#define MSR_IA32_MC0_CTL 0x00000400 148#define MSR_IA32_MC0_STATUS 0x00000401 149#define MSR_IA32_MC0_ADDR 0x00000402 150#define MSR_IA32_MC0_MISC 0x00000403 151 152/* C-state Residency Counters */ 153#define MSR_PKG_C3_RESIDENCY 0x000003f8 154#define MSR_PKG_C6_RESIDENCY 0x000003f9 155#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 156#define MSR_PKG_C7_RESIDENCY 0x000003fa 157#define MSR_CORE_C3_RESIDENCY 0x000003fc 158#define MSR_CORE_C6_RESIDENCY 0x000003fd 159#define MSR_CORE_C7_RESIDENCY 0x000003fe 160#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 161#define MSR_PKG_C2_RESIDENCY 0x0000060d 162#define MSR_PKG_C8_RESIDENCY 0x00000630 163#define MSR_PKG_C9_RESIDENCY 0x00000631 164#define MSR_PKG_C10_RESIDENCY 0x00000632 165 166/* Interrupt Response Limit */ 167#define MSR_PKGC3_IRTL 0x0000060a 168#define MSR_PKGC6_IRTL 0x0000060b 169#define MSR_PKGC7_IRTL 0x0000060c 170#define MSR_PKGC8_IRTL 0x00000633 171#define MSR_PKGC9_IRTL 0x00000634 172#define MSR_PKGC10_IRTL 0x00000635 173 174/* Run Time Average Power Limiting (RAPL) Interface */ 175 176#define MSR_RAPL_POWER_UNIT 0x00000606 177 178#define MSR_PKG_POWER_LIMIT 0x00000610 179#define MSR_PKG_ENERGY_STATUS 0x00000611 180#define MSR_PKG_PERF_STATUS 0x00000613 181#define MSR_PKG_POWER_INFO 0x00000614 182 183#define MSR_DRAM_POWER_LIMIT 0x00000618 184#define MSR_DRAM_ENERGY_STATUS 0x00000619 185#define MSR_DRAM_PERF_STATUS 0x0000061b 186#define MSR_DRAM_POWER_INFO 0x0000061c 187 188#define MSR_PP0_POWER_LIMIT 0x00000638 189#define MSR_PP0_ENERGY_STATUS 0x00000639 190#define MSR_PP0_POLICY 0x0000063a 191#define MSR_PP0_PERF_STATUS 0x0000063b 192 193#define MSR_PP1_POWER_LIMIT 0x00000640 194#define MSR_PP1_ENERGY_STATUS 0x00000641 195#define MSR_PP1_POLICY 0x00000642 196 197#define MSR_CONFIG_TDP_NOMINAL 0x00000648 198#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 199#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 200#define MSR_CONFIG_TDP_CONTROL 0x0000064B 201#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 202 203#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 204 205#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 206#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 207#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 208#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 209 210#define MSR_CORE_C1_RES 0x00000660 211#define MSR_MODULE_C6_RES_MS 0x00000664 212 213#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 214#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 215 216/* Config TDP MSRs */ 217#define MSR_CONFIG_TDP_NOMINAL 0x00000648 218#define MSR_CONFIG_TDP_LEVEL1 0x00000649 219#define MSR_CONFIG_TDP_LEVEL2 0x0000064A 220#define MSR_CONFIG_TDP_CONTROL 0x0000064B 221#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 222 223/* Hardware P state interface */ 224#define MSR_PPERF 0x0000064e 225#define MSR_PERF_LIMIT_REASONS 0x0000064f 226#define MSR_PM_ENABLE 0x00000770 227#define MSR_HWP_CAPABILITIES 0x00000771 228#define MSR_HWP_REQUEST_PKG 0x00000772 229#define MSR_HWP_INTERRUPT 0x00000773 230#define MSR_HWP_REQUEST 0x00000774 231#define MSR_HWP_STATUS 0x00000777 232 233/* CPUID.6.EAX */ 234#define HWP_BASE_BIT (1<<7) 235#define HWP_NOTIFICATIONS_BIT (1<<8) 236#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 237#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 238#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 239 240/* IA32_HWP_CAPABILITIES */ 241#define HWP_HIGHEST_PERF(x) (x & 0xff) 242#define HWP_GUARANTEED_PERF(x) ((x & (0xff << 8)) >>8) 243#define HWP_MOSTEFFICIENT_PERF(x) ((x & (0xff << 16)) >>16) 244#define HWP_LOWEST_PERF(x) ((x & (0xff << 24)) >>24) 245 246/* IA32_HWP_REQUEST */ 247#define HWP_MIN_PERF(x) (x & 0xff) 248#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 249#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 250#define HWP_ENERGY_PERF_PREFERENCE(x) ((x & 0xff) << 24) 251#define HWP_EPP_PERFORMANCE 0x00 252#define HWP_EPP_BALANCE_PERFORMANCE 0x80 253#define HWP_EPP_BALANCE_POWERSAVE 0xC0 254#define HWP_EPP_POWERSAVE 0xFF 255#define HWP_ACTIVITY_WINDOW(x) ((x & 0xff3) << 32) 256#define HWP_PACKAGE_CONTROL(x) ((x & 0x1) << 42) 257 258/* IA32_HWP_STATUS */ 259#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 260#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 261 262/* IA32_HWP_INTERRUPT */ 263#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 264#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 265 266#define MSR_AMD64_MC0_MASK 0xc0010044 267 268#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 269#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 270#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 271#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 272 273#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 274 275/* These are consecutive and not in the normal 4er MCE bank block */ 276#define MSR_IA32_MC0_CTL2 0x00000280 277#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 278 279#define MSR_P6_PERFCTR0 0x000000c1 280#define MSR_P6_PERFCTR1 0x000000c2 281#define MSR_P6_EVNTSEL0 0x00000186 282#define MSR_P6_EVNTSEL1 0x00000187 283 284#define MSR_KNC_PERFCTR0 0x00000020 285#define MSR_KNC_PERFCTR1 0x00000021 286#define MSR_KNC_EVNTSEL0 0x00000028 287#define MSR_KNC_EVNTSEL1 0x00000029 288 289/* Alternative perfctr range with full access. */ 290#define MSR_IA32_PMC0 0x000004c1 291 292/* AMD64 MSRs. Not complete. See the architecture manual for a more 293 complete list. */ 294 295#define MSR_AMD64_PATCH_LEVEL 0x0000008b 296#define MSR_AMD64_TSC_RATIO 0xc0000104 297#define MSR_AMD64_NB_CFG 0xc001001f 298#define MSR_AMD64_PATCH_LOADER 0xc0010020 299#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 300#define MSR_AMD64_OSVW_STATUS 0xc0010141 301#define MSR_AMD64_DC_CFG 0xc0011022 302#define MSR_AMD64_BU_CFG2 0xc001102a 303#define MSR_AMD64_IBSFETCHCTL 0xc0011030 304#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 305#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 306#define MSR_AMD64_IBSFETCH_REG_COUNT 3 307#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 308#define MSR_AMD64_IBSOPCTL 0xc0011033 309#define MSR_AMD64_IBSOPRIP 0xc0011034 310#define MSR_AMD64_IBSOPDATA 0xc0011035 311#define MSR_AMD64_IBSOPDATA2 0xc0011036 312#define MSR_AMD64_IBSOPDATA3 0xc0011037 313#define MSR_AMD64_IBSDCLINAD 0xc0011038 314#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 315#define MSR_AMD64_IBSOP_REG_COUNT 7 316#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 317#define MSR_AMD64_IBSCTL 0xc001103a 318#define MSR_AMD64_IBSBRTARGET 0xc001103b 319#define MSR_AMD64_IBSOPDATA4 0xc001103d 320#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 321 322/* Fam 16h MSRs */ 323#define MSR_F16H_L2I_PERF_CTL 0xc0010230 324#define MSR_F16H_L2I_PERF_CTR 0xc0010231 325#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 326#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 327#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 328#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 329 330/* Fam 15h MSRs */ 331#define MSR_F15H_PERF_CTL 0xc0010200 332#define MSR_F15H_PERF_CTR 0xc0010201 333#define MSR_F15H_NB_PERF_CTL 0xc0010240 334#define MSR_F15H_NB_PERF_CTR 0xc0010241 335#define MSR_F15H_PTSC 0xc0010280 336#define MSR_F15H_IC_CFG 0xc0011021 337#define MSR_F15H_IC_CFG_DIS_IND BIT_ULL(14) 338 339/* Fam 10h MSRs */ 340#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 341#define FAM10H_MMIO_CONF_ENABLE (1<<0) 342#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 343#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 344#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 345#define FAM10H_MMIO_CONF_BASE_SHIFT 20 346#define MSR_FAM10H_NODE_ID 0xc001100c 347#define MSR_F10H_DECFG 0xc0011029 348#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 349 350/* K8 MSRs */ 351#define MSR_K8_TOP_MEM1 0xc001001a 352#define MSR_K8_TOP_MEM2 0xc001001d 353#define MSR_K8_SYSCFG 0xc0010010 354#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 355#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 356#define MSR_K8_INT_PENDING_MSG 0xc0010055 357/* C1E active bits in int pending message */ 358#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 359#define MSR_K8_TSEG_ADDR 0xc0010112 360#define MSR_K8_TSEG_MASK 0xc0010113 361#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 362#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 363#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 364 365/* K7 MSRs */ 366#define MSR_K7_EVNTSEL0 0xc0010000 367#define MSR_K7_PERFCTR0 0xc0010004 368#define MSR_K7_EVNTSEL1 0xc0010001 369#define MSR_K7_PERFCTR1 0xc0010005 370#define MSR_K7_EVNTSEL2 0xc0010002 371#define MSR_K7_PERFCTR2 0xc0010006 372#define MSR_K7_EVNTSEL3 0xc0010003 373#define MSR_K7_PERFCTR3 0xc0010007 374#define MSR_K7_CLK_CTL 0xc001001b 375#define MSR_K7_HWCR 0xc0010015 376#define MSR_K7_FID_VID_CTL 0xc0010041 377#define MSR_K7_FID_VID_STATUS 0xc0010042 378 379/* K6 MSRs */ 380#define MSR_K6_WHCR 0xc0000082 381#define MSR_K6_UWCCR 0xc0000085 382#define MSR_K6_EPMR 0xc0000086 383#define MSR_K6_PSOR 0xc0000087 384#define MSR_K6_PFIR 0xc0000088 385 386/* Centaur-Hauls/IDT defined MSRs. */ 387#define MSR_IDT_FCR1 0x00000107 388#define MSR_IDT_FCR2 0x00000108 389#define MSR_IDT_FCR3 0x00000109 390#define MSR_IDT_FCR4 0x0000010a 391 392#define MSR_IDT_MCR0 0x00000110 393#define MSR_IDT_MCR1 0x00000111 394#define MSR_IDT_MCR2 0x00000112 395#define MSR_IDT_MCR3 0x00000113 396#define MSR_IDT_MCR4 0x00000114 397#define MSR_IDT_MCR5 0x00000115 398#define MSR_IDT_MCR6 0x00000116 399#define MSR_IDT_MCR7 0x00000117 400#define MSR_IDT_MCR_CTRL 0x00000120 401 402/* VIA Cyrix defined MSRs*/ 403#define MSR_VIA_FCR 0x00001107 404#define MSR_VIA_LONGHAUL 0x0000110a 405#define MSR_VIA_RNG 0x0000110b 406#define MSR_VIA_BCR2 0x00001147 407 408/* Transmeta defined MSRs */ 409#define MSR_TMTA_LONGRUN_CTRL 0x80868010 410#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 411#define MSR_TMTA_LRTI_READOUT 0x80868018 412#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 413 414/* Intel defined MSRs. */ 415#define MSR_IA32_P5_MC_ADDR 0x00000000 416#define MSR_IA32_P5_MC_TYPE 0x00000001 417#define MSR_IA32_TSC 0x00000010 418#define MSR_IA32_PLATFORM_ID 0x00000017 419#define MSR_IA32_EBL_CR_POWERON 0x0000002a 420#define MSR_EBC_FREQUENCY_ID 0x0000002c 421#define MSR_SMI_COUNT 0x00000034 422#define MSR_IA32_FEATURE_CONTROL 0x0000003a 423#define MSR_IA32_TSC_ADJUST 0x0000003b 424#define MSR_IA32_BNDCFGS 0x00000d90 425 426#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 427 428#define MSR_IA32_XSS 0x00000da0 429 430#define FEATURE_CONTROL_LOCKED (1<<0) 431#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 432#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 433#define FEATURE_CONTROL_LMCE (1<<20) 434#define FEATURE_ENABLE_IBRS (1<<0) 435#define FEATURE_ENABLE_STIBP (1<<1) 436#define FEATURE_SET_IBPB (1<<0) 437 438#define MSR_IA32_APICBASE 0x0000001b 439#define MSR_IA32_APICBASE_BSP (1<<8) 440#define MSR_IA32_APICBASE_ENABLE (1<<11) 441#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 442 443#define MSR_IA32_TSCDEADLINE 0x000006e0 444 445#define MSR_IA32_UCODE_WRITE 0x00000079 446#define MSR_IA32_UCODE_REV 0x0000008b 447 448#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 449#define MSR_IA32_SMBASE 0x0000009e 450 451#define MSR_IA32_PERF_STATUS 0x00000198 452#define MSR_IA32_PERF_CTL 0x00000199 453#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 454#define MSR_AMD_PERF_STATUS 0xc0010063 455#define MSR_AMD_PERF_CTL 0xc0010062 456 457#define MSR_IA32_MPERF 0x000000e7 458#define MSR_IA32_APERF 0x000000e8 459 460#define MSR_IA32_THERM_CONTROL 0x0000019a 461#define MSR_IA32_THERM_INTERRUPT 0x0000019b 462 463#define THERM_INT_HIGH_ENABLE (1 << 0) 464#define THERM_INT_LOW_ENABLE (1 << 1) 465#define THERM_INT_PLN_ENABLE (1 << 24) 466 467#define MSR_IA32_THERM_STATUS 0x0000019c 468 469#define THERM_STATUS_PROCHOT (1 << 0) 470#define THERM_STATUS_POWER_LIMIT (1 << 10) 471 472#define MSR_THERM2_CTL 0x0000019d 473 474#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 475 476#define MSR_IA32_MISC_ENABLE 0x000001a0 477 478#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 479 480#define MSR_MISC_FEATURE_CONTROL 0x000001a4 481#define MSR_MISC_PWR_MGMT 0x000001aa 482 483#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 484#define ENERGY_PERF_BIAS_PERFORMANCE 0 485#define ENERGY_PERF_BIAS_NORMAL 6 486#define ENERGY_PERF_BIAS_POWERSAVE 15 487 488#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 489 490#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 491#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 492 493#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 494 495#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 496#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 497#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 498 499/* Thermal Thresholds Support */ 500#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 501#define THERM_SHIFT_THRESHOLD0 8 502#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 503#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 504#define THERM_SHIFT_THRESHOLD1 16 505#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 506#define THERM_STATUS_THRESHOLD0 (1 << 6) 507#define THERM_LOG_THRESHOLD0 (1 << 7) 508#define THERM_STATUS_THRESHOLD1 (1 << 8) 509#define THERM_LOG_THRESHOLD1 (1 << 9) 510 511/* MISC_ENABLE bits: architectural */ 512#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 513#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 514#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 515#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 516#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 517#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 518#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 519#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 520#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 521#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 522 523/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 524#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 525#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 526#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 527#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 528#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 529#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 530#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 531#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 532#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 533#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 534#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 535#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 536#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 537#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 538#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 539 540/* MISC_FEATURE_ENABLES non-architectural features */ 541#define MSR_MISC_FEATURE_ENABLES 0x00000140 542 543#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1 544 545#define MSR_IA32_TSC_DEADLINE 0x000006E0 546 547/* P4/Xeon+ specific */ 548#define MSR_IA32_MCG_EAX 0x00000180 549#define MSR_IA32_MCG_EBX 0x00000181 550#define MSR_IA32_MCG_ECX 0x00000182 551#define MSR_IA32_MCG_EDX 0x00000183 552#define MSR_IA32_MCG_ESI 0x00000184 553#define MSR_IA32_MCG_EDI 0x00000185 554#define MSR_IA32_MCG_EBP 0x00000186 555#define MSR_IA32_MCG_ESP 0x00000187 556#define MSR_IA32_MCG_EFLAGS 0x00000188 557#define MSR_IA32_MCG_EIP 0x00000189 558#define MSR_IA32_MCG_RESERVED 0x0000018a 559 560/* Pentium IV performance counter MSRs */ 561#define MSR_P4_BPU_PERFCTR0 0x00000300 562#define MSR_P4_BPU_PERFCTR1 0x00000301 563#define MSR_P4_BPU_PERFCTR2 0x00000302 564#define MSR_P4_BPU_PERFCTR3 0x00000303 565#define MSR_P4_MS_PERFCTR0 0x00000304 566#define MSR_P4_MS_PERFCTR1 0x00000305 567#define MSR_P4_MS_PERFCTR2 0x00000306 568#define MSR_P4_MS_PERFCTR3 0x00000307 569#define MSR_P4_FLAME_PERFCTR0 0x00000308 570#define MSR_P4_FLAME_PERFCTR1 0x00000309 571#define MSR_P4_FLAME_PERFCTR2 0x0000030a 572#define MSR_P4_FLAME_PERFCTR3 0x0000030b 573#define MSR_P4_IQ_PERFCTR0 0x0000030c 574#define MSR_P4_IQ_PERFCTR1 0x0000030d 575#define MSR_P4_IQ_PERFCTR2 0x0000030e 576#define MSR_P4_IQ_PERFCTR3 0x0000030f 577#define MSR_P4_IQ_PERFCTR4 0x00000310 578#define MSR_P4_IQ_PERFCTR5 0x00000311 579#define MSR_P4_BPU_CCCR0 0x00000360 580#define MSR_P4_BPU_CCCR1 0x00000361 581#define MSR_P4_BPU_CCCR2 0x00000362 582#define MSR_P4_BPU_CCCR3 0x00000363 583#define MSR_P4_MS_CCCR0 0x00000364 584#define MSR_P4_MS_CCCR1 0x00000365 585#define MSR_P4_MS_CCCR2 0x00000366 586#define MSR_P4_MS_CCCR3 0x00000367 587#define MSR_P4_FLAME_CCCR0 0x00000368 588#define MSR_P4_FLAME_CCCR1 0x00000369 589#define MSR_P4_FLAME_CCCR2 0x0000036a 590#define MSR_P4_FLAME_CCCR3 0x0000036b 591#define MSR_P4_IQ_CCCR0 0x0000036c 592#define MSR_P4_IQ_CCCR1 0x0000036d 593#define MSR_P4_IQ_CCCR2 0x0000036e 594#define MSR_P4_IQ_CCCR3 0x0000036f 595#define MSR_P4_IQ_CCCR4 0x00000370 596#define MSR_P4_IQ_CCCR5 0x00000371 597#define MSR_P4_ALF_ESCR0 0x000003ca 598#define MSR_P4_ALF_ESCR1 0x000003cb 599#define MSR_P4_BPU_ESCR0 0x000003b2 600#define MSR_P4_BPU_ESCR1 0x000003b3 601#define MSR_P4_BSU_ESCR0 0x000003a0 602#define MSR_P4_BSU_ESCR1 0x000003a1 603#define MSR_P4_CRU_ESCR0 0x000003b8 604#define MSR_P4_CRU_ESCR1 0x000003b9 605#define MSR_P4_CRU_ESCR2 0x000003cc 606#define MSR_P4_CRU_ESCR3 0x000003cd 607#define MSR_P4_CRU_ESCR4 0x000003e0 608#define MSR_P4_CRU_ESCR5 0x000003e1 609#define MSR_P4_DAC_ESCR0 0x000003a8 610#define MSR_P4_DAC_ESCR1 0x000003a9 611#define MSR_P4_FIRM_ESCR0 0x000003a4 612#define MSR_P4_FIRM_ESCR1 0x000003a5 613#define MSR_P4_FLAME_ESCR0 0x000003a6 614#define MSR_P4_FLAME_ESCR1 0x000003a7 615#define MSR_P4_FSB_ESCR0 0x000003a2 616#define MSR_P4_FSB_ESCR1 0x000003a3 617#define MSR_P4_IQ_ESCR0 0x000003ba 618#define MSR_P4_IQ_ESCR1 0x000003bb 619#define MSR_P4_IS_ESCR0 0x000003b4 620#define MSR_P4_IS_ESCR1 0x000003b5 621#define MSR_P4_ITLB_ESCR0 0x000003b6 622#define MSR_P4_ITLB_ESCR1 0x000003b7 623#define MSR_P4_IX_ESCR0 0x000003c8 624#define MSR_P4_IX_ESCR1 0x000003c9 625#define MSR_P4_MOB_ESCR0 0x000003aa 626#define MSR_P4_MOB_ESCR1 0x000003ab 627#define MSR_P4_MS_ESCR0 0x000003c0 628#define MSR_P4_MS_ESCR1 0x000003c1 629#define MSR_P4_PMH_ESCR0 0x000003ac 630#define MSR_P4_PMH_ESCR1 0x000003ad 631#define MSR_P4_RAT_ESCR0 0x000003bc 632#define MSR_P4_RAT_ESCR1 0x000003bd 633#define MSR_P4_SAAT_ESCR0 0x000003ae 634#define MSR_P4_SAAT_ESCR1 0x000003af 635#define MSR_P4_SSU_ESCR0 0x000003be 636#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 637 638#define MSR_P4_TBPU_ESCR0 0x000003c2 639#define MSR_P4_TBPU_ESCR1 0x000003c3 640#define MSR_P4_TC_ESCR0 0x000003c4 641#define MSR_P4_TC_ESCR1 0x000003c5 642#define MSR_P4_U2L_ESCR0 0x000003b0 643#define MSR_P4_U2L_ESCR1 0x000003b1 644 645#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 646 647/* Intel Core-based CPU performance counters */ 648#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 649#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 650#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 651#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 652#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 653#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 654#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 655 656/* Geode defined MSRs */ 657#define MSR_GEODE_BUSCONT_CONF0 0x00001900 658 659/* Intel VT MSRs */ 660#define MSR_IA32_VMX_BASIC 0x00000480 661#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 662#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 663#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 664#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 665#define MSR_IA32_VMX_MISC 0x00000485 666#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 667#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 668#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 669#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 670#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 671#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 672#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 673#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 674#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 675#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 676#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 677#define MSR_IA32_VMX_VMFUNC 0x00000491 678 679/* VMX_BASIC bits and bitmasks */ 680#define VMX_BASIC_VMCS_SIZE_SHIFT 32 681#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 682#define VMX_BASIC_64 0x0001000000000000LLU 683#define VMX_BASIC_MEM_TYPE_SHIFT 50 684#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 685#define VMX_BASIC_MEM_TYPE_WB 6LLU 686#define VMX_BASIC_INOUT 0x0040000000000000LLU 687 688/* MSR_IA32_VMX_MISC bits */ 689#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 690#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 691/* AMD-V MSRs */ 692 693#define MSR_VM_CR 0xc0010114 694#define MSR_VM_IGNNE 0xc0010115 695#define MSR_VM_HSAVE_PA 0xc0010117 696 697#define MSR_ATOM_CORE_RATIOS 0x0000066a 698#define MSR_ATOM_CORE_VIDS 0x0000066b 699#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 700#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 701 702 703#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 704#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 705#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 706 707#endif /* _ASM_X86_MSR_INDEX_H */ 708