LXR linux/arch/xtensa/kernel/align.S

   1/*
   2 * arch/xtensa/kernel/align.S
   3 *
   4 * Handle unalignment exceptions in kernel space.
   5 *
   6 * This file is subject to the terms and conditions of the GNU General
   7 * Public License.  See the file "COPYING" in the main directory of
   8 * this archive for more details.
   9 *
  10 * Copyright (C) 2001 - 2005 Tensilica, Inc.
  11 *
  12 * Rewritten by Chris Zankel <chris@zankel.net>
  13 *
  14 * Based on work from Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
  15 * and Marc Gauthier <marc@tensilica.com, marc@alimni.uwaterloo.ca>
  16 */
  17
  18#include <linux/linkage.h>
  19#include <asm/current.h>
  20#include <asm/asm-offsets.h>
  21#include <asm/processor.h>
  22
  23#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
  24
  25/*  First-level exception handler for unaligned exceptions.
  26 *
  27 *  Note: This handler works only for kernel exceptions.  Unaligned user
  28 *        access should get a seg fault.
  29 */
  30
  31/* Big and little endian 16-bit values are located in
  32 * different halves of a register.  HWORD_START helps to
  33 * abstract the notion of extracting a 16-bit value from a
  34 * register.
  35 * We also have to define new shifting instructions because
  36 * lsb and msb are on 'opposite' ends in a register for
  37 * different endian machines.
  38 *
  39 * Assume a memory region in ascending address:
  40 *      0 1 2 3|4 5 6 7
  41 *
  42 * When loading one word into a register, the content of that register is:
  43 *  LE  3 2 1 0, 7 6 5 4
  44 *  BE  0 1 2 3, 4 5 6 7
  45 *
  46 * Masking the bits of the higher/lower address means:
  47 *  LE  X X 0 0, 0 0 X X
  48 *  BE  0 0 X X, X X 0 0
  49 *
  50 * Shifting to higher/lower addresses, means:
  51 *  LE  shift left / shift right
  52 *  BE  shift right / shift left
  53 *
  54 * Extracting 16 bits from a 32 bit reg. value to higher/lower address means:
  55 *  LE  mask 0 0 X X / shift left
  56 *  BE  shift left / mask 0 0 X X
  57 */
  58
  59#define UNALIGNED_USER_EXCEPTION
  60
  61#if XCHAL_HAVE_BE
  62
  63#define HWORD_START     16
  64#define INSN_OP0        28
  65#define INSN_T          24
  66#define INSN_OP1        16
  67
  68.macro __src_b  r, w0, w1;      src     \r, \w0, \w1;   .endm
  69.macro __ssa8   r;              ssa8b   \r;             .endm
  70.macro __ssa8r  r;              ssa8l   \r;             .endm
  71.macro __sh     r, s;           srl     \r, \s;         .endm
  72.macro __sl     r, s;           sll     \r, \s;         .endm
  73.macro __exth   r, s;           extui   \r, \s, 0, 16;  .endm
  74.macro __extl   r, s;           slli    \r, \s, 16;     .endm
  75
  76#else
  77
  78#define HWORD_START     0
  79#define INSN_OP0        0
  80#define INSN_T          4
  81#define INSN_OP1        12
  82
  83.macro __src_b  r, w0, w1;      src     \r, \w1, \w0;   .endm
  84.macro __ssa8   r;              ssa8l   \r;             .endm
  85.macro __ssa8r  r;              ssa8b   \r;             .endm
  86.macro __sh     r, s;           sll     \r, \s;         .endm
  87.macro __sl     r, s;           srl     \r, \s;         .endm
  88.macro __exth   r, s;           slli    \r, \s, 16;     .endm
  89.macro __extl   r, s;           extui   \r, \s, 0, 16;  .endm
  90
  91#endif
  92
  93/*
  94 *      xxxx xxxx = imm8 field
  95 *           yyyy = imm4 field
  96 *           ssss = s field
  97 *           tttt = t field
  98 *
  99 *                       16                 0
 100 *                        -------------------
 101 *      L32I.N            yyyy ssss tttt 1000
 102 *      S32I.N            yyyy ssss tttt 1001
 103 *
 104 *             23                           0
 105 *              -----------------------------
 106 *      res               0000           0010
 107 *      L16UI   xxxx xxxx 0001 ssss tttt 0010
 108 *      L32I    xxxx xxxx 0010 ssss tttt 0010
 109 *      XXX               0011 ssss tttt 0010
 110 *      XXX               0100 ssss tttt 0010
 111 *      S16I    xxxx xxxx 0101 ssss tttt 0010
 112 *      S32I    xxxx xxxx 0110 ssss tttt 0010
 113 *      XXX               0111 ssss tttt 0010
 114 *      XXX               1000 ssss tttt 0010
 115 *      L16SI   xxxx xxxx 1001 ssss tttt 0010
 116 *      XXX               1010           0010
 117 *      **L32AI xxxx xxxx 1011 ssss tttt 0010 unsupported
 118 *      XXX               1100           0010
 119 *      XXX               1101           0010
 120 *      XXX               1110           0010
 121 *      **S32RI xxxx xxxx 1111 ssss tttt 0010 unsupported
 122 *              -----------------------------
 123 *                           ^         ^    ^
 124 *    sub-opcode (NIBBLE_R) -+         |    |
 125 *       t field (NIBBLE_T) -----------+    |
 126 *  major opcode (NIBBLE_OP0) --------------+
 127 */
 128
 129#define OP0_L32I_N      0x8             /* load immediate narrow */
 130#define OP0_S32I_N      0x9             /* store immediate narrow */
 131#define OP1_SI_MASK     0x4             /* OP1 bit set for stores */
 132#define OP1_SI_BIT      2               /* OP1 bit number for stores */
 133
 134#define OP1_L32I        0x2
 135#define OP1_L16UI       0x1
 136#define OP1_L16SI       0x9
 137#define OP1_L32AI       0xb
 138
 139#define OP1_S32I        0x6
 140#define OP1_S16I        0x5
 141#define OP1_S32RI       0xf
 142
 143/*
 144 * Entry condition:
 145 *
 146 *   a0:        trashed, original value saved on stack (PT_AREG0)
 147 *   a1:        a1
 148 *   a2:        new stack pointer, original in DEPC
 149 *   a3:        dispatch table
 150 *   depc:      a2, original value saved on stack (PT_DEPC)
 151 *   excsave_1: a3
 152 *
 153 *   PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
 154 *           <  VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
 155 */
 156
 157
 158ENTRY(fast_unaligned)
 159
 160        /* Note: We don't expect the address to be aligned on a word
 161         *       boundary. After all, the processor generated that exception
 162         *       and it would be a hardware fault.
 163         */
 164
 165        /* Save some working register */
 166
 167        s32i    a4, a2, PT_AREG4
 168        s32i    a5, a2, PT_AREG5
 169        s32i    a6, a2, PT_AREG6
 170        s32i    a7, a2, PT_AREG7
 171        s32i    a8, a2, PT_AREG8
 172
 173        rsr     a0, depc
 174        xsr     a3, excsave1
 175        s32i    a0, a2, PT_AREG2
 176        s32i    a3, a2, PT_AREG3
 177
 178        /* Keep value of SAR in a0 */
 179
 180        rsr     a0, sar
 181        rsr     a8, excvaddr            # load unaligned memory address
 182
 183        /* Now, identify one of the following load/store instructions.
 184         *
 185         * The only possible danger of a double exception on the
 186         * following l32i instructions is kernel code in vmalloc
 187         * memory. The processor was just executing at the EPC_1
 188         * address, and indeed, already fetched the instruction.  That
 189         * guarantees a TLB mapping, which hasn't been replaced by
 190         * this unaligned exception handler that uses only static TLB
 191         * mappings. However, high-level interrupt handlers might
 192         * modify TLB entries, so for the generic case, we register a
 193         * TABLE_FIXUP handler here, too.
 194         */
 195
 196        /* a3...a6 saved on stack, a2 = SP */
 197
 198        /* Extract the instruction that caused the unaligned access. */
 199
 200        rsr     a7, epc1        # load exception address
 201        movi    a3, ~3
 202        and     a3, a3, a7      # mask lower bits
 203
 204        l32i    a4, a3, 0       # load 2 words
 205        l32i    a5, a3, 4
 206
 207        __ssa8  a7
 208        __src_b a4, a4, a5      # a4 has the instruction
 209
 210        /* Analyze the instruction (load or store?). */
 211
 212        extui   a5, a4, INSN_OP0, 4     # get insn.op0 nibble
 213
 214#if XCHAL_HAVE_DENSITY
 215        _beqi   a5, OP0_L32I_N, .Lload  # L32I.N, jump
 216        addi    a6, a5, -OP0_S32I_N
 217        _beqz   a6, .Lstore             # S32I.N, do a store
 218#endif
 219        /* 'store indicator bit' not set, jump */
 220        _bbci.l a4, OP1_SI_BIT + INSN_OP1, .Lload
 221
 222        /* Store: Jump to table entry to get the value in the source register.*/
 223
 224.Lstore:movi    a5, .Lstore_table       # table
 225        extui   a6, a4, INSN_T, 4       # get source register
 226        addx8   a5, a6, a5
 227        jx      a5                      # jump into table
 228
 229        /* Invalid instruction, CRITICAL! */
 230.Linvalid_instruction_load:
 231        j       .Linvalid_instruction
 232
 233        /* Load: Load memory address. */
 234
 235.Lload: movi    a3, ~3
 236        and     a3, a3, a8              # align memory address
 237
 238        __ssa8  a8
 239#ifdef UNALIGNED_USER_EXCEPTION
 240        addi    a3, a3, 8
 241        l32e    a5, a3, -8
 242        l32e    a6, a3, -4
 243#else
 244        l32i    a5, a3, 0
 245        l32i    a6, a3, 4
 246#endif
 247        __src_b a3, a5, a6              # a3 has the data word
 248
 249#if XCHAL_HAVE_DENSITY
 250        addi    a7, a7, 2               # increment PC (assume 16-bit insn)
 251
 252        extui   a5, a4, INSN_OP0, 4
 253        _beqi   a5, OP0_L32I_N, 1f      # l32i.n: jump
 254
 255        addi    a7, a7, 1
 256#else
 257        addi    a7, a7, 3
 258#endif
 259
 260        extui   a5, a4, INSN_OP1, 4
 261        _beqi   a5, OP1_L32I, 1f        # l32i: jump
 262
 263        extui   a3, a3, 0, 16           # extract lower 16 bits
 264        _beqi   a5, OP1_L16UI, 1f
 265        addi    a5, a5, -OP1_L16SI
 266        _bnez   a5, .Linvalid_instruction_load
 267
 268        /* sign extend value */
 269
 270        slli    a3, a3, 16
 271        srai    a3, a3, 16
 272
 273        /* Set target register. */
 274
 2751:
 276
 277#if XCHAL_HAVE_LOOPS
 278        rsr     a5, lend                # check if we reached LEND
 279        bne     a7, a5, 1f
 280        rsr     a5, lcount              # and LCOUNT != 0
 281        beqz    a5, 1f
 282        addi    a5, a5, -1              # decrement LCOUNT and set
 283        rsr     a7, lbeg                # set PC to LBEGIN
 284        wsr     a5, lcount
 285#endif
 286
 2871:      wsr     a7, epc1                # skip load instruction
 288        extui   a4, a4, INSN_T, 4       # extract target register
 289        movi    a5, .Lload_table
 290        addx8   a4, a4, a5
 291        jx      a4                      # jump to entry for target register
 292
 293        .align  8
 294.Lload_table:
 295        s32i    a3, a2, PT_AREG0;       _j .Lexit;      .align 8
 296        mov     a1, a3;                 _j .Lexit;      .align 8 # fishy??
 297        s32i    a3, a2, PT_AREG2;       _j .Lexit;      .align 8
 298        s32i    a3, a2, PT_AREG3;       _j .Lexit;      .align 8
 299        s32i    a3, a2, PT_AREG4;       _j .Lexit;      .align 8
 300        s32i    a3, a2, PT_AREG5;       _j .Lexit;      .align 8
 301        s32i    a3, a2, PT_AREG6;       _j .Lexit;      .align 8
 302        s32i    a3, a2, PT_AREG7;       _j .Lexit;      .align 8
 303        s32i    a3, a2, PT_AREG8;       _j .Lexit;      .align 8
 304        mov     a9, a3          ;       _j .Lexit;      .align 8
 305        mov     a10, a3         ;       _j .Lexit;      .align 8
 306        mov     a11, a3         ;       _j .Lexit;      .align 8
 307        mov     a12, a3         ;       _j .Lexit;      .align 8
 308        mov     a13, a3         ;       _j .Lexit;      .align 8
 309        mov     a14, a3         ;       _j .Lexit;      .align 8
 310        mov     a15, a3         ;       _j .Lexit;      .align 8
 311
 312.Lstore_table:
 313        l32i    a3, a2, PT_AREG0;       _j 1f;  .align 8
 314        mov     a3, a1;                 _j 1f;  .align 8        # fishy??
 315        l32i    a3, a2, PT_AREG2;       _j 1f;  .align 8
 316        l32i    a3, a2, PT_AREG3;       _j 1f;  .align 8
 317        l32i    a3, a2, PT_AREG4;       _j 1f;  .align 8
 318        l32i    a3, a2, PT_AREG5;       _j 1f;  .align 8
 319        l32i    a3, a2, PT_AREG6;       _j 1f;  .align 8
 320        l32i    a3, a2, PT_AREG7;       _j 1f;  .align 8
 321        l32i    a3, a2, PT_AREG8;       _j 1f;  .align 8
 322        mov     a3, a9          ;       _j 1f;  .align 8
 323        mov     a3, a10         ;       _j 1f;  .align 8
 324        mov     a3, a11         ;       _j 1f;  .align 8
 325        mov     a3, a12         ;       _j 1f;  .align 8
 326        mov     a3, a13         ;       _j 1f;  .align 8
 327        mov     a3, a14         ;       _j 1f;  .align 8
 328        mov     a3, a15         ;       _j 1f;  .align 8
 329
 3301:      # a7: instruction pointer, a4: instruction, a3: value
 331
 332        movi    a6, 0                   # mask: ffffffff:00000000
 333
 334#if XCHAL_HAVE_DENSITY
 335        addi    a7, a7, 2               # incr. PC,assume 16-bit instruction
 336
 337        extui   a5, a4, INSN_OP0, 4     # extract OP0
 338        addi    a5, a5, -OP0_S32I_N
 339        _beqz   a5, 1f                  # s32i.n: jump
 340
 341        addi    a7, a7, 1               # increment PC, 32-bit instruction
 342#else
 343        addi    a7, a7, 3               # increment PC, 32-bit instruction
 344#endif
 345
 346        extui   a5, a4, INSN_OP1, 4     # extract OP1
 347        _beqi   a5, OP1_S32I, 1f        # jump if 32 bit store
 348        _bnei   a5, OP1_S16I, .Linvalid_instruction_store
 349
 350        movi    a5, -1
 351        __extl  a3, a3                  # get 16-bit value
 352        __exth  a6, a5                  # get 16-bit mask ffffffff:ffff0000
 353
 354        /* Get memory address */
 355
 3561:
 357#if XCHAL_HAVE_LOOPS
 358        rsr     a4, lend                # check if we reached LEND
 359        bne     a7, a4, 1f
 360        rsr     a4, lcount              # and LCOUNT != 0
 361        beqz    a4, 1f
 362        addi    a4, a4, -1              # decrement LCOUNT and set
 363        rsr     a7, lbeg                # set PC to LBEGIN
 364        wsr     a4, lcount
 365#endif
 366
 3671:      wsr     a7, epc1                # skip store instruction
 368        movi    a4, ~3
 369        and     a4, a4, a8              # align memory address
 370
 371        /* Insert value into memory */
 372
 373        movi    a5, -1                  # mask: ffffffff:XXXX0000
 374#ifdef UNALIGNED_USER_EXCEPTION
 375        addi    a4, a4, 8
 376#endif
 377
 378        __ssa8r a8
 379        __src_b a7, a5, a6              # lo-mask  F..F0..0 (BE) 0..0F..F (LE)
 380        __src_b a6, a6, a5              # hi-mask  0..0F..F (BE) F..F0..0 (LE)
 381#ifdef UNALIGNED_USER_EXCEPTION
 382        l32e    a5, a4, -8
 383#else
 384        l32i    a5, a4, 0               # load lower address word
 385#endif
 386        and     a5, a5, a7              # mask
 387        __sh    a7, a3                  # shift value
 388        or      a5, a5, a7              # or with original value
 389#ifdef UNALIGNED_USER_EXCEPTION
 390        s32e    a5, a4, -8
 391        l32e    a7, a4, -4
 392#else
 393        s32i    a5, a4, 0               # store
 394        l32i    a7, a4, 4               # same for upper address word
 395#endif
 396        __sl    a5, a3
 397        and     a6, a7, a6
 398        or      a6, a6, a5
 399#ifdef UNALIGNED_USER_EXCEPTION
 400        s32e    a6, a4, -4
 401#else
 402        s32i    a6, a4, 4
 403#endif
 404
 405        /* Done. restore stack and return */
 406
 407.Lexit:
 408        movi    a4, 0
 409        rsr     a3, excsave1
 410        s32i    a4, a3, EXC_TABLE_FIXUP
 411
 412        /* Restore working register */
 413
 414        l32i    a8, a2, PT_AREG8
 415        l32i    a7, a2, PT_AREG7
 416        l32i    a6, a2, PT_AREG6
 417        l32i    a5, a2, PT_AREG5
 418        l32i    a4, a2, PT_AREG4
 419        l32i    a3, a2, PT_AREG3
 420
 421        /* restore SAR and return */
 422
 423        wsr     a0, sar
 424        l32i    a0, a2, PT_AREG0
 425        l32i    a2, a2, PT_AREG2
 426        rfe
 427
 428        /* We cannot handle this exception. */
 429
 430        .extern _kernel_exception
 431.Linvalid_instruction_store:
 432.Linvalid_instruction:
 433
 434        /* Restore a4...a8 and SAR, set SP, and jump to default exception. */
 435
 436        l32i    a8, a2, PT_AREG8
 437        l32i    a7, a2, PT_AREG7
 438        l32i    a6, a2, PT_AREG6
 439        l32i    a5, a2, PT_AREG5
 440        l32i    a4, a2, PT_AREG4
 441        wsr     a0, sar
 442        mov     a1, a2
 443
 444        rsr     a0, ps
 445        bbsi.l  a2, PS_UM_BIT, 1f     # jump if user mode
 446
 447        movi    a0, _kernel_exception
 448        jx      a0
 449
 4501:      movi    a0, _user_exception
 451        jx      a0
 452
 453ENDPROC(fast_unaligned)
 454
 455#endif /* XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION */
 456