linux/arch/xtensa/kernel/irq.c
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   1/*
   2 * linux/arch/xtensa/kernel/irq.c
   3 *
   4 * Xtensa built-in interrupt controller and some generic functions copied
   5 * from i386.
   6 *
   7 * Copyright (C) 2002 - 2006 Tensilica, Inc.
   8 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
   9 *
  10 *
  11 * Chris Zankel <chris@zankel.net>
  12 * Kevin Chea
  13 *
  14 */
  15
  16#include <linux/module.h>
  17#include <linux/seq_file.h>
  18#include <linux/interrupt.h>
  19#include <linux/irq.h>
  20#include <linux/kernel_stat.h>
  21#include <linux/irqdomain.h>
  22#include <linux/of.h>
  23
  24#include <asm/uaccess.h>
  25#include <asm/platform.h>
  26
  27static unsigned int cached_irq_mask;
  28
  29atomic_t irq_err_count;
  30
  31static struct irq_domain *root_domain;
  32
  33/*
  34 * do_IRQ handles all normal device IRQ's (the special
  35 * SMP cross-CPU interrupts have their own specific
  36 * handlers).
  37 */
  38
  39asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
  40{
  41        struct pt_regs *old_regs = set_irq_regs(regs);
  42        int irq = irq_find_mapping(root_domain, hwirq);
  43
  44        if (hwirq >= NR_IRQS) {
  45                printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
  46                                __func__, hwirq);
  47        }
  48
  49        irq_enter();
  50
  51#ifdef CONFIG_DEBUG_STACKOVERFLOW
  52        /* Debugging check for stack overflow: is there less than 1KB free? */
  53        {
  54                unsigned long sp;
  55
  56                __asm__ __volatile__ ("mov %0, a1\n" : "=a" (sp));
  57                sp &= THREAD_SIZE - 1;
  58
  59                if (unlikely(sp < (sizeof(thread_info) + 1024)))
  60                        printk("Stack overflow in do_IRQ: %ld\n",
  61                               sp - sizeof(struct thread_info));
  62        }
  63#endif
  64        generic_handle_irq(irq);
  65
  66        irq_exit();
  67        set_irq_regs(old_regs);
  68}
  69
  70int arch_show_interrupts(struct seq_file *p, int prec)
  71{
  72        seq_printf(p, "%*s: ", prec, "ERR");
  73        seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
  74        return 0;
  75}
  76
  77static void xtensa_irq_mask(struct irq_data *d)
  78{
  79        cached_irq_mask &= ~(1 << d->hwirq);
  80        set_sr (cached_irq_mask, intenable);
  81}
  82
  83static void xtensa_irq_unmask(struct irq_data *d)
  84{
  85        cached_irq_mask |= 1 << d->hwirq;
  86        set_sr (cached_irq_mask, intenable);
  87}
  88
  89static void xtensa_irq_enable(struct irq_data *d)
  90{
  91        variant_irq_enable(d->hwirq);
  92        xtensa_irq_unmask(d);
  93}
  94
  95static void xtensa_irq_disable(struct irq_data *d)
  96{
  97        xtensa_irq_mask(d);
  98        variant_irq_disable(d->hwirq);
  99}
 100
 101static void xtensa_irq_ack(struct irq_data *d)
 102{
 103        set_sr(1 << d->hwirq, intclear);
 104}
 105
 106static int xtensa_irq_retrigger(struct irq_data *d)
 107{
 108        set_sr(1 << d->hwirq, intset);
 109        return 1;
 110}
 111
 112static struct irq_chip xtensa_irq_chip = {
 113        .name           = "xtensa",
 114        .irq_enable     = xtensa_irq_enable,
 115        .irq_disable    = xtensa_irq_disable,
 116        .irq_mask       = xtensa_irq_mask,
 117        .irq_unmask     = xtensa_irq_unmask,
 118        .irq_ack        = xtensa_irq_ack,
 119        .irq_retrigger  = xtensa_irq_retrigger,
 120};
 121
 122static int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
 123                irq_hw_number_t hw)
 124{
 125        u32 mask = 1 << hw;
 126
 127        if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
 128                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
 129                                handle_simple_irq, "level");
 130                irq_set_status_flags(irq, IRQ_LEVEL);
 131        } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
 132                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
 133                                handle_edge_irq, "edge");
 134                irq_clear_status_flags(irq, IRQ_LEVEL);
 135        } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
 136                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
 137                                handle_level_irq, "level");
 138                irq_set_status_flags(irq, IRQ_LEVEL);
 139        } else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
 140                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
 141                                handle_edge_irq, "edge");
 142                irq_clear_status_flags(irq, IRQ_LEVEL);
 143        } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
 144                /* XCHAL_INTTYPE_MASK_NMI */
 145
 146                irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
 147                                handle_level_irq, "level");
 148                irq_set_status_flags(irq, IRQ_LEVEL);
 149        }
 150        return 0;
 151}
 152
 153static unsigned map_ext_irq(unsigned ext_irq)
 154{
 155        unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
 156                XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
 157        unsigned i;
 158
 159        for (i = 0; mask; ++i, mask >>= 1) {
 160                if ((mask & 1) && ext_irq-- == 0)
 161                        return i;
 162        }
 163        return XCHAL_NUM_INTERRUPTS;
 164}
 165
 166/*
 167 * Device Tree IRQ specifier translation function which works with one or
 168 * two cell bindings. First cell value maps directly to the hwirq number.
 169 * Second cell if present specifies whether hwirq number is external (1) or
 170 * internal (0).
 171 */
 172int xtensa_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
 173                const u32 *intspec, unsigned int intsize,
 174                unsigned long *out_hwirq, unsigned int *out_type)
 175{
 176        if (WARN_ON(intsize < 1 || intsize > 2))
 177                return -EINVAL;
 178        if (intsize == 2 && intspec[1] == 1) {
 179                unsigned int_irq = map_ext_irq(intspec[0]);
 180                if (int_irq < XCHAL_NUM_INTERRUPTS)
 181                        *out_hwirq = int_irq;
 182                else
 183                        return -EINVAL;
 184        } else {
 185                *out_hwirq = intspec[0];
 186        }
 187        *out_type = IRQ_TYPE_NONE;
 188        return 0;
 189}
 190
 191static const struct irq_domain_ops xtensa_irq_domain_ops = {
 192        .xlate = xtensa_irq_domain_xlate,
 193        .map = xtensa_irq_map,
 194};
 195
 196void __init init_IRQ(void)
 197{
 198        struct device_node *intc = NULL;
 199
 200        cached_irq_mask = 0;
 201        set_sr(~0, intclear);
 202
 203#ifdef CONFIG_OF
 204        /* The interrupt controller device node is mandatory */
 205        intc = of_find_compatible_node(NULL, NULL, "xtensa,pic");
 206        BUG_ON(!intc);
 207
 208        root_domain = irq_domain_add_linear(intc, NR_IRQS,
 209                        &xtensa_irq_domain_ops, NULL);
 210#else
 211        root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0,
 212                        &xtensa_irq_domain_ops, NULL);
 213#endif
 214        irq_set_default_host(root_domain);
 215
 216        variant_init_irq();
 217}
 218