1/* 2 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the Free 6 * Software Foundation; either version 2 of the License, or (at your option) 7 * any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called COPYING. 20 */ 21#ifndef _IOAT_HW_H_ 22#define _IOAT_HW_H_ 23 24/* PCI Configuration Space Values */ 25#define IOAT_MMIO_BAR 0 26 27/* CB device ID's */ 28#define IOAT_PCI_DID_5000 0x1A38 29#define IOAT_PCI_DID_CNB 0x360B 30#define IOAT_PCI_DID_SCNB 0x65FF 31#define IOAT_PCI_DID_SNB 0x402F 32 33#define PCI_DEVICE_ID_INTEL_IOAT_IVB0 0x0e20 34#define PCI_DEVICE_ID_INTEL_IOAT_IVB1 0x0e21 35#define PCI_DEVICE_ID_INTEL_IOAT_IVB2 0x0e22 36#define PCI_DEVICE_ID_INTEL_IOAT_IVB3 0x0e23 37#define PCI_DEVICE_ID_INTEL_IOAT_IVB4 0x0e24 38#define PCI_DEVICE_ID_INTEL_IOAT_IVB5 0x0e25 39#define PCI_DEVICE_ID_INTEL_IOAT_IVB6 0x0e26 40#define PCI_DEVICE_ID_INTEL_IOAT_IVB7 0x0e27 41#define PCI_DEVICE_ID_INTEL_IOAT_IVB8 0x0e2e 42#define PCI_DEVICE_ID_INTEL_IOAT_IVB9 0x0e2f 43 44#define PCI_DEVICE_ID_INTEL_IOAT_HSW0 0x2f20 45#define PCI_DEVICE_ID_INTEL_IOAT_HSW1 0x2f21 46#define PCI_DEVICE_ID_INTEL_IOAT_HSW2 0x2f22 47#define PCI_DEVICE_ID_INTEL_IOAT_HSW3 0x2f23 48#define PCI_DEVICE_ID_INTEL_IOAT_HSW4 0x2f24 49#define PCI_DEVICE_ID_INTEL_IOAT_HSW5 0x2f25 50#define PCI_DEVICE_ID_INTEL_IOAT_HSW6 0x2f26 51#define PCI_DEVICE_ID_INTEL_IOAT_HSW7 0x2f27 52#define PCI_DEVICE_ID_INTEL_IOAT_HSW8 0x2f2e 53#define PCI_DEVICE_ID_INTEL_IOAT_HSW9 0x2f2f 54 55#define PCI_DEVICE_ID_INTEL_IOAT_BWD0 0x0C50 56#define PCI_DEVICE_ID_INTEL_IOAT_BWD1 0x0C51 57#define PCI_DEVICE_ID_INTEL_IOAT_BWD2 0x0C52 58#define PCI_DEVICE_ID_INTEL_IOAT_BWD3 0x0C53 59 60#define PCI_DEVICE_ID_INTEL_IOAT_BDX0 0x6f20 61#define PCI_DEVICE_ID_INTEL_IOAT_BDX1 0x6f21 62#define PCI_DEVICE_ID_INTEL_IOAT_BDX2 0x6f22 63#define PCI_DEVICE_ID_INTEL_IOAT_BDX3 0x6f23 64#define PCI_DEVICE_ID_INTEL_IOAT_BDX4 0x6f24 65#define PCI_DEVICE_ID_INTEL_IOAT_BDX5 0x6f25 66#define PCI_DEVICE_ID_INTEL_IOAT_BDX6 0x6f26 67#define PCI_DEVICE_ID_INTEL_IOAT_BDX7 0x6f27 68#define PCI_DEVICE_ID_INTEL_IOAT_BDX8 0x6f2e 69#define PCI_DEVICE_ID_INTEL_IOAT_BDX9 0x6f2f 70 71#define IOAT_VER_1_2 0x12 /* Version 1.2 */ 72#define IOAT_VER_2_0 0x20 /* Version 2.0 */ 73#define IOAT_VER_3_0 0x30 /* Version 3.0 */ 74#define IOAT_VER_3_2 0x32 /* Version 3.2 */ 75#define IOAT_VER_3_3 0x33 /* Version 3.3 */ 76 77 78int system_has_dca_enabled(struct pci_dev *pdev); 79 80struct ioat_dma_descriptor { 81 uint32_t size; 82 union { 83 uint32_t ctl; 84 struct { 85 unsigned int int_en:1; 86 unsigned int src_snoop_dis:1; 87 unsigned int dest_snoop_dis:1; 88 unsigned int compl_write:1; 89 unsigned int fence:1; 90 unsigned int null:1; 91 unsigned int src_brk:1; 92 unsigned int dest_brk:1; 93 unsigned int bundle:1; 94 unsigned int dest_dca:1; 95 unsigned int hint:1; 96 unsigned int rsvd2:13; 97 #define IOAT_OP_COPY 0x00 98 unsigned int op:8; 99 } ctl_f; 100 }; 101 uint64_t src_addr; 102 uint64_t dst_addr; 103 uint64_t next; 104 uint64_t rsv1; 105 uint64_t rsv2; 106 /* store some driver data in an unused portion of the descriptor */ 107 union { 108 uint64_t user1; 109 uint64_t tx_cnt; 110 }; 111 uint64_t user2; 112}; 113 114struct ioat_fill_descriptor { 115 uint32_t size; 116 union { 117 uint32_t ctl; 118 struct { 119 unsigned int int_en:1; 120 unsigned int rsvd:1; 121 unsigned int dest_snoop_dis:1; 122 unsigned int compl_write:1; 123 unsigned int fence:1; 124 unsigned int rsvd2:2; 125 unsigned int dest_brk:1; 126 unsigned int bundle:1; 127 unsigned int rsvd4:15; 128 #define IOAT_OP_FILL 0x01 129 unsigned int op:8; 130 } ctl_f; 131 }; 132 uint64_t src_data; 133 uint64_t dst_addr; 134 uint64_t next; 135 uint64_t rsv1; 136 uint64_t next_dst_addr; 137 uint64_t user1; 138 uint64_t user2; 139}; 140 141struct ioat_xor_descriptor { 142 uint32_t size; 143 union { 144 uint32_t ctl; 145 struct { 146 unsigned int int_en:1; 147 unsigned int src_snoop_dis:1; 148 unsigned int dest_snoop_dis:1; 149 unsigned int compl_write:1; 150 unsigned int fence:1; 151 unsigned int src_cnt:3; 152 unsigned int bundle:1; 153 unsigned int dest_dca:1; 154 unsigned int hint:1; 155 unsigned int rsvd:13; 156 #define IOAT_OP_XOR 0x87 157 #define IOAT_OP_XOR_VAL 0x88 158 unsigned int op:8; 159 } ctl_f; 160 }; 161 uint64_t src_addr; 162 uint64_t dst_addr; 163 uint64_t next; 164 uint64_t src_addr2; 165 uint64_t src_addr3; 166 uint64_t src_addr4; 167 uint64_t src_addr5; 168}; 169 170struct ioat_xor_ext_descriptor { 171 uint64_t src_addr6; 172 uint64_t src_addr7; 173 uint64_t src_addr8; 174 uint64_t next; 175 uint64_t rsvd[4]; 176}; 177 178struct ioat_pq_descriptor { 179 union { 180 uint32_t size; 181 uint32_t dwbes; 182 struct { 183 unsigned int rsvd:25; 184 unsigned int p_val_err:1; 185 unsigned int q_val_err:1; 186 unsigned int rsvd1:4; 187 unsigned int wbes:1; 188 } dwbes_f; 189 }; 190 union { 191 uint32_t ctl; 192 struct { 193 unsigned int int_en:1; 194 unsigned int src_snoop_dis:1; 195 unsigned int dest_snoop_dis:1; 196 unsigned int compl_write:1; 197 unsigned int fence:1; 198 unsigned int src_cnt:3; 199 unsigned int bundle:1; 200 unsigned int dest_dca:1; 201 unsigned int hint:1; 202 unsigned int p_disable:1; 203 unsigned int q_disable:1; 204 unsigned int rsvd2:2; 205 unsigned int wb_en:1; 206 unsigned int prl_en:1; 207 unsigned int rsvd3:7; 208 #define IOAT_OP_PQ 0x89 209 #define IOAT_OP_PQ_VAL 0x8a 210 #define IOAT_OP_PQ_16S 0xa0 211 #define IOAT_OP_PQ_VAL_16S 0xa1 212 unsigned int op:8; 213 } ctl_f; 214 }; 215 uint64_t src_addr; 216 uint64_t p_addr; 217 uint64_t next; 218 uint64_t src_addr2; 219 union { 220 uint64_t src_addr3; 221 uint64_t sed_addr; 222 }; 223 uint8_t coef[8]; 224 uint64_t q_addr; 225}; 226 227struct ioat_pq_ext_descriptor { 228 uint64_t src_addr4; 229 uint64_t src_addr5; 230 uint64_t src_addr6; 231 uint64_t next; 232 uint64_t src_addr7; 233 uint64_t src_addr8; 234 uint64_t rsvd[2]; 235}; 236 237struct ioat_pq_update_descriptor { 238 uint32_t size; 239 union { 240 uint32_t ctl; 241 struct { 242 unsigned int int_en:1; 243 unsigned int src_snoop_dis:1; 244 unsigned int dest_snoop_dis:1; 245 unsigned int compl_write:1; 246 unsigned int fence:1; 247 unsigned int src_cnt:3; 248 unsigned int bundle:1; 249 unsigned int dest_dca:1; 250 unsigned int hint:1; 251 unsigned int p_disable:1; 252 unsigned int q_disable:1; 253 unsigned int rsvd:3; 254 unsigned int coef:8; 255 #define IOAT_OP_PQ_UP 0x8b 256 unsigned int op:8; 257 } ctl_f; 258 }; 259 uint64_t src_addr; 260 uint64_t p_addr; 261 uint64_t next; 262 uint64_t src_addr2; 263 uint64_t p_src; 264 uint64_t q_src; 265 uint64_t q_addr; 266}; 267 268struct ioat_raw_descriptor { 269 uint64_t field[8]; 270}; 271 272struct ioat_pq16a_descriptor { 273 uint8_t coef[8]; 274 uint64_t src_addr3; 275 uint64_t src_addr4; 276 uint64_t src_addr5; 277 uint64_t src_addr6; 278 uint64_t src_addr7; 279 uint64_t src_addr8; 280 uint64_t src_addr9; 281}; 282 283struct ioat_pq16b_descriptor { 284 uint64_t src_addr10; 285 uint64_t src_addr11; 286 uint64_t src_addr12; 287 uint64_t src_addr13; 288 uint64_t src_addr14; 289 uint64_t src_addr15; 290 uint64_t src_addr16; 291 uint64_t rsvd; 292}; 293 294union ioat_sed_pq_descriptor { 295 struct ioat_pq16a_descriptor a; 296 struct ioat_pq16b_descriptor b; 297}; 298 299#define SED_SIZE 64 300 301struct ioat_sed_raw_descriptor { 302 uint64_t a[8]; 303 uint64_t b[8]; 304 uint64_t c[8]; 305}; 306 307#endif 308