LXR linux/drivers/gpu/drm/amd/include/asic_reg/vega10/vega10

   1/*
   2 * Copyright (C) 2017  Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included
  12 * in all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 */
  21#if !defined (_vega10_ENUM_HEADER)
  22#define _vega10_ENUM_HEADER
  23
  24#ifndef _DRIVER_BUILD
  25#ifndef GL_ZERO
  26#define GL__ZERO                      BLEND_ZERO
  27#define GL__ONE                       BLEND_ONE
  28#define GL__SRC_COLOR                 BLEND_SRC_COLOR
  29#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
  30#define GL__DST_COLOR                 BLEND_DST_COLOR
  31#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
  32#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
  33#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
  34#define GL__DST_ALPHA                 BLEND_DST_ALPHA
  35#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
  36#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
  37#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
  38#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
  39#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
  40#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
  41#endif
  42#endif
  43
  44/*******************************************************
  45 * GDS DATA_TYPE Enums
  46 *******************************************************/
  47
  48#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
  49#define ENUMS_GDS_PERFCOUNT_SELECT_H
  50typedef enum GDS_PERFCOUNT_SELECT {
  51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
  52 GDS_PERF_SEL_DS_BANK_CONFL = 1,
  53 GDS_PERF_SEL_WBUF_FLUSH = 2,
  54 GDS_PERF_SEL_WR_COMP = 3,
  55 GDS_PERF_SEL_WBUF_WR = 4,
  56 GDS_PERF_SEL_RBUF_HIT = 5,
  57 GDS_PERF_SEL_RBUF_MISS = 6,
  58 GDS_PERF_SEL_SE0_SH0_NORET = 7,
  59 GDS_PERF_SEL_SE0_SH0_RET = 8,
  60 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
  61 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
  62 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
  63 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
  64 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
  65 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
  66 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
  67 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
  68 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
  69 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
  70 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
  71 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
  72 GDS_PERF_SEL_SE0_SH1_NORET = 21,
  73 GDS_PERF_SEL_SE0_SH1_RET = 22,
  74 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
  75 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
  76 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
  77 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
  78 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
  79 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
  80 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
  81 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
  82 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
  83 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
  84 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
  85 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
  86 GDS_PERF_SEL_SE1_SH0_NORET = 35,
  87 GDS_PERF_SEL_SE1_SH0_RET = 36,
  88 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
  89 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
  90 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
  91 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
  92 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
  93 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
  94 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
  95 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
  96 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
  97 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
  98 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
  99 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
 100 GDS_PERF_SEL_SE1_SH1_NORET = 49,
 101 GDS_PERF_SEL_SE1_SH1_RET = 50,
 102 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
 103 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
 104 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
 105 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
 106 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
 107 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
 108 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
 109 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
 110 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
 111 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
 112 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
 113 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
 114 GDS_PERF_SEL_SE2_SH0_NORET = 63,
 115 GDS_PERF_SEL_SE2_SH0_RET = 64,
 116 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
 117 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
 118 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
 119 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
 120 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
 121 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
 122 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
 123 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
 124 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
 125 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
 126 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
 127 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
 128 GDS_PERF_SEL_SE2_SH1_NORET = 77,
 129 GDS_PERF_SEL_SE2_SH1_RET = 78,
 130 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
 131 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
 132 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
 133 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
 134 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
 135 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
 136 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
 137 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
 138 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
 139 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
 140 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
 141 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
 142 GDS_PERF_SEL_SE3_SH0_NORET = 91,
 143 GDS_PERF_SEL_SE3_SH0_RET = 92,
 144 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
 145 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
 146 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
 147 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
 148 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
 149 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
 150 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
 151 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
 152 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
 153 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
 154 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
 155 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
 156 GDS_PERF_SEL_SE3_SH1_NORET = 105,
 157 GDS_PERF_SEL_SE3_SH1_RET = 106,
 158 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
 159 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
 160 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
 161 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
 162 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
 163 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
 164 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
 165 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
 166 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
 167 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
 168 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
 169 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
 170 GDS_PERF_SEL_GWS_RELEASED = 119,
 171 GDS_PERF_SEL_GWS_BYPASS = 120,
 172} GDS_PERFCOUNT_SELECT;
 173#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
 174
 175/*******************************************************
 176 * Chip Enums
 177 *******************************************************/
 178
 179/*
 180 * MEM_PWR_FORCE_CTRL enum
 181 */
 182
 183typedef enum MEM_PWR_FORCE_CTRL {
 184NO_FORCE_REQUEST                         = 0x00000000,
 185FORCE_LIGHT_SLEEP_REQUEST                = 0x00000001,
 186FORCE_DEEP_SLEEP_REQUEST                 = 0x00000002,
 187FORCE_SHUT_DOWN_REQUEST                  = 0x00000003,
 188} MEM_PWR_FORCE_CTRL;
 189
 190/*
 191 * MEM_PWR_FORCE_CTRL2 enum
 192 */
 193
 194typedef enum MEM_PWR_FORCE_CTRL2 {
 195NO_FORCE_REQ                             = 0x00000000,
 196FORCE_LIGHT_SLEEP_REQ                    = 0x00000001,
 197} MEM_PWR_FORCE_CTRL2;
 198
 199/*
 200 * MEM_PWR_DIS_CTRL enum
 201 */
 202
 203typedef enum MEM_PWR_DIS_CTRL {
 204ENABLE_MEM_PWR_CTRL                      = 0x00000000,
 205DISABLE_MEM_PWR_CTRL                     = 0x00000001,
 206} MEM_PWR_DIS_CTRL;
 207
 208/*
 209 * MEM_PWR_SEL_CTRL enum
 210 */
 211
 212typedef enum MEM_PWR_SEL_CTRL {
 213DYNAMIC_SHUT_DOWN_ENABLE                 = 0x00000000,
 214DYNAMIC_DEEP_SLEEP_ENABLE                = 0x00000001,
 215DYNAMIC_LIGHT_SLEEP_ENABLE               = 0x00000002,
 216} MEM_PWR_SEL_CTRL;
 217
 218/*
 219 * MEM_PWR_SEL_CTRL2 enum
 220 */
 221
 222typedef enum MEM_PWR_SEL_CTRL2 {
 223DYNAMIC_DEEP_SLEEP_EN                    = 0x00000000,
 224DYNAMIC_LIGHT_SLEEP_EN                   = 0x00000001,
 225} MEM_PWR_SEL_CTRL2;
 226
 227/*
 228 * RowSize enum
 229 */
 230
 231typedef enum RowSize {
 232ADDR_CONFIG_1KB_ROW                      = 0x00000000,
 233ADDR_CONFIG_2KB_ROW                      = 0x00000001,
 234ADDR_CONFIG_4KB_ROW                      = 0x00000002,
 235} RowSize;
 236
 237/*
 238 * SurfaceEndian enum
 239 */
 240
 241typedef enum SurfaceEndian {
 242ENDIAN_NONE                              = 0x00000000,
 243ENDIAN_8IN16                             = 0x00000001,
 244ENDIAN_8IN32                             = 0x00000002,
 245ENDIAN_8IN64                             = 0x00000003,
 246} SurfaceEndian;
 247
 248/*
 249 * ArrayMode enum
 250 */
 251
 252typedef enum ArrayMode {
 253ARRAY_LINEAR_GENERAL                     = 0x00000000,
 254ARRAY_LINEAR_ALIGNED                     = 0x00000001,
 255ARRAY_1D_TILED_THIN1                     = 0x00000002,
 256ARRAY_1D_TILED_THICK                     = 0x00000003,
 257ARRAY_2D_TILED_THIN1                     = 0x00000004,
 258ARRAY_PRT_TILED_THIN1                    = 0x00000005,
 259ARRAY_PRT_2D_TILED_THIN1                 = 0x00000006,
 260ARRAY_2D_TILED_THICK                     = 0x00000007,
 261ARRAY_2D_TILED_XTHICK                    = 0x00000008,
 262ARRAY_PRT_TILED_THICK                    = 0x00000009,
 263ARRAY_PRT_2D_TILED_THICK                 = 0x0000000a,
 264ARRAY_PRT_3D_TILED_THIN1                 = 0x0000000b,
 265ARRAY_3D_TILED_THIN1                     = 0x0000000c,
 266ARRAY_3D_TILED_THICK                     = 0x0000000d,
 267ARRAY_3D_TILED_XTHICK                    = 0x0000000e,
 268ARRAY_PRT_3D_TILED_THICK                 = 0x0000000f,
 269} ArrayMode;
 270
 271/*
 272 * NumPipes enum
 273 */
 274
 275typedef enum NumPipes {
 276ADDR_CONFIG_1_PIPE                       = 0x00000000,
 277ADDR_CONFIG_2_PIPE                       = 0x00000001,
 278ADDR_CONFIG_4_PIPE                       = 0x00000002,
 279ADDR_CONFIG_8_PIPE                       = 0x00000003,
 280ADDR_CONFIG_16_PIPE                      = 0x00000004,
 281ADDR_CONFIG_32_PIPE                      = 0x00000005,
 282} NumPipes;
 283
 284/*
 285 * NumBanksConfig enum
 286 */
 287
 288typedef enum NumBanksConfig {
 289ADDR_CONFIG_1_BANK                       = 0x00000000,
 290ADDR_CONFIG_2_BANK                       = 0x00000001,
 291ADDR_CONFIG_4_BANK                       = 0x00000002,
 292ADDR_CONFIG_8_BANK                       = 0x00000003,
 293ADDR_CONFIG_16_BANK                      = 0x00000004,
 294} NumBanksConfig;
 295
 296/*
 297 * PipeInterleaveSize enum
 298 */
 299
 300typedef enum PipeInterleaveSize {
 301ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
 302ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
 303ADDR_CONFIG_PIPE_INTERLEAVE_1KB          = 0x00000002,
 304ADDR_CONFIG_PIPE_INTERLEAVE_2KB          = 0x00000003,
 305} PipeInterleaveSize;
 306
 307/*
 308 * BankInterleaveSize enum
 309 */
 310
 311typedef enum BankInterleaveSize {
 312ADDR_CONFIG_BANK_INTERLEAVE_1            = 0x00000000,
 313ADDR_CONFIG_BANK_INTERLEAVE_2            = 0x00000001,
 314ADDR_CONFIG_BANK_INTERLEAVE_4            = 0x00000002,
 315ADDR_CONFIG_BANK_INTERLEAVE_8            = 0x00000003,
 316} BankInterleaveSize;
 317
 318/*
 319 * NumShaderEngines enum
 320 */
 321
 322typedef enum NumShaderEngines {
 323ADDR_CONFIG_1_SHADER_ENGINE              = 0x00000000,
 324ADDR_CONFIG_2_SHADER_ENGINE              = 0x00000001,
 325ADDR_CONFIG_4_SHADER_ENGINE              = 0x00000002,
 326ADDR_CONFIG_8_SHADER_ENGINE              = 0x00000003,
 327} NumShaderEngines;
 328
 329/*
 330 * NumRbPerShaderEngine enum
 331 */
 332
 333typedef enum NumRbPerShaderEngine {
 334ADDR_CONFIG_1_RB_PER_SHADER_ENGINE       = 0x00000000,
 335ADDR_CONFIG_2_RB_PER_SHADER_ENGINE       = 0x00000001,
 336ADDR_CONFIG_4_RB_PER_SHADER_ENGINE       = 0x00000002,
 337} NumRbPerShaderEngine;
 338
 339/*
 340 * NumGPUs enum
 341 */
 342
 343typedef enum NumGPUs {
 344ADDR_CONFIG_1_GPU                        = 0x00000000,
 345ADDR_CONFIG_2_GPU                        = 0x00000001,
 346ADDR_CONFIG_4_GPU                        = 0x00000002,
 347ADDR_CONFIG_8_GPU                        = 0x00000003,
 348} NumGPUs;
 349
 350/*
 351 * NumMaxCompressedFragments enum
 352 */
 353
 354typedef enum NumMaxCompressedFragments {
 355ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS   = 0x00000000,
 356ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS   = 0x00000001,
 357ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS   = 0x00000002,
 358ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS   = 0x00000003,
 359} NumMaxCompressedFragments;
 360
 361/*
 362 * ShaderEngineTileSize enum
 363 */
 364
 365typedef enum ShaderEngineTileSize {
 366ADDR_CONFIG_SE_TILE_16                   = 0x00000000,
 367ADDR_CONFIG_SE_TILE_32                   = 0x00000001,
 368} ShaderEngineTileSize;
 369
 370/*
 371 * MultiGPUTileSize enum
 372 */
 373
 374typedef enum MultiGPUTileSize {
 375ADDR_CONFIG_GPU_TILE_16                  = 0x00000000,
 376ADDR_CONFIG_GPU_TILE_32                  = 0x00000001,
 377ADDR_CONFIG_GPU_TILE_64                  = 0x00000002,
 378ADDR_CONFIG_GPU_TILE_128                 = 0x00000003,
 379} MultiGPUTileSize;
 380
 381/*
 382 * NumLowerPipes enum
 383 */
 384
 385typedef enum NumLowerPipes {
 386ADDR_CONFIG_1_LOWER_PIPES                = 0x00000000,
 387ADDR_CONFIG_2_LOWER_PIPES                = 0x00000001,
 388} NumLowerPipes;
 389
 390/*
 391 * ColorTransform enum
 392 */
 393
 394typedef enum ColorTransform {
 395DCC_CT_AUTO                              = 0x00000000,
 396DCC_CT_NONE                              = 0x00000001,
 397ABGR_TO_A_BG_G_RB                        = 0x00000002,
 398BGRA_TO_BG_G_RB_A                        = 0x00000003,
 399} ColorTransform;
 400
 401/*
 402 * CompareRef enum
 403 */
 404
 405typedef enum CompareRef {
 406REF_NEVER                                = 0x00000000,
 407REF_LESS                                 = 0x00000001,
 408REF_EQUAL                                = 0x00000002,
 409REF_LEQUAL                               = 0x00000003,
 410REF_GREATER                              = 0x00000004,
 411REF_NOTEQUAL                             = 0x00000005,
 412REF_GEQUAL                               = 0x00000006,
 413REF_ALWAYS                               = 0x00000007,
 414} CompareRef;
 415
 416/*
 417 * ReadSize enum
 418 */
 419
 420typedef enum ReadSize {
 421READ_256_BITS                            = 0x00000000,
 422READ_512_BITS                            = 0x00000001,
 423} ReadSize;
 424
 425/*
 426 * DepthFormat enum
 427 */
 428
 429typedef enum DepthFormat {
 430DEPTH_INVALID                            = 0x00000000,
 431DEPTH_16                                 = 0x00000001,
 432DEPTH_X8_24                              = 0x00000002,
 433DEPTH_8_24                               = 0x00000003,
 434DEPTH_X8_24_FLOAT                        = 0x00000004,
 435DEPTH_8_24_FLOAT                         = 0x00000005,
 436DEPTH_32_FLOAT                           = 0x00000006,
 437DEPTH_X24_8_32_FLOAT                     = 0x00000007,
 438} DepthFormat;
 439
 440/*
 441 * ZFormat enum
 442 */
 443
 444typedef enum ZFormat {
 445Z_INVALID                                = 0x00000000,
 446Z_16                                     = 0x00000001,
 447Z_24                                     = 0x00000002,
 448Z_32_FLOAT                               = 0x00000003,
 449} ZFormat;
 450
 451/*
 452 * StencilFormat enum
 453 */
 454
 455typedef enum StencilFormat {
 456STENCIL_INVALID                          = 0x00000000,
 457STENCIL_8                                = 0x00000001,
 458} StencilFormat;
 459
 460/*
 461 * CmaskMode enum
 462 */
 463
 464typedef enum CmaskMode {
 465CMASK_CLEAR_NONE                         = 0x00000000,
 466CMASK_CLEAR_ONE                          = 0x00000001,
 467CMASK_CLEAR_ALL                          = 0x00000002,
 468CMASK_ANY_EXPANDED                       = 0x00000003,
 469CMASK_ALPHA0_FRAG1                       = 0x00000004,
 470CMASK_ALPHA0_FRAG2                       = 0x00000005,
 471CMASK_ALPHA0_FRAG4                       = 0x00000006,
 472CMASK_ALPHA0_FRAGS                       = 0x00000007,
 473CMASK_ALPHA1_FRAG1                       = 0x00000008,
 474CMASK_ALPHA1_FRAG2                       = 0x00000009,
 475CMASK_ALPHA1_FRAG4                       = 0x0000000a,
 476CMASK_ALPHA1_FRAGS                       = 0x0000000b,
 477CMASK_ALPHAX_FRAG1                       = 0x0000000c,
 478CMASK_ALPHAX_FRAG2                       = 0x0000000d,
 479CMASK_ALPHAX_FRAG4                       = 0x0000000e,
 480CMASK_ALPHAX_FRAGS                       = 0x0000000f,
 481} CmaskMode;
 482
 483/*
 484 * QuadExportFormat enum
 485 */
 486
 487typedef enum QuadExportFormat {
 488EXPORT_UNUSED                            = 0x00000000,
 489EXPORT_32_R                              = 0x00000001,
 490EXPORT_32_GR                             = 0x00000002,
 491EXPORT_32_AR                             = 0x00000003,
 492EXPORT_FP16_ABGR                         = 0x00000004,
 493EXPORT_UNSIGNED16_ABGR                   = 0x00000005,
 494EXPORT_SIGNED16_ABGR                     = 0x00000006,
 495EXPORT_32_ABGR                           = 0x00000007,
 496EXPORT_32BPP_8PIX                        = 0x00000008,
 497EXPORT_16_16_UNSIGNED_8PIX               = 0x00000009,
 498EXPORT_16_16_SIGNED_8PIX                 = 0x0000000a,
 499EXPORT_16_16_FLOAT_8PIX                  = 0x0000000b,
 500} QuadExportFormat;
 501
 502/*
 503 * QuadExportFormatOld enum
 504 */
 505
 506typedef enum QuadExportFormatOld {
 507EXPORT_4P_32BPC_ABGR                     = 0x00000000,
 508EXPORT_4P_16BPC_ABGR                     = 0x00000001,
 509EXPORT_4P_32BPC_GR                       = 0x00000002,
 510EXPORT_4P_32BPC_AR                       = 0x00000003,
 511EXPORT_2P_32BPC_ABGR                     = 0x00000004,
 512EXPORT_8P_32BPC_R                        = 0x00000005,
 513} QuadExportFormatOld;
 514
 515/*
 516 * ColorFormat enum
 517 */
 518
 519typedef enum ColorFormat {
 520COLOR_INVALID                            = 0x00000000,
 521COLOR_8                                  = 0x00000001,
 522COLOR_16                                 = 0x00000002,
 523COLOR_8_8                                = 0x00000003,
 524COLOR_32                                 = 0x00000004,
 525COLOR_16_16                              = 0x00000005,
 526COLOR_10_11_11                           = 0x00000006,
 527COLOR_11_11_10                           = 0x00000007,
 528COLOR_10_10_10_2                         = 0x00000008,
 529COLOR_2_10_10_10                         = 0x00000009,
 530COLOR_8_8_8_8                            = 0x0000000a,
 531COLOR_32_32                              = 0x0000000b,
 532COLOR_16_16_16_16                        = 0x0000000c,
 533COLOR_RESERVED_13                        = 0x0000000d,
 534COLOR_32_32_32_32                        = 0x0000000e,
 535COLOR_RESERVED_15                        = 0x0000000f,
 536COLOR_5_6_5                              = 0x00000010,
 537COLOR_1_5_5_5                            = 0x00000011,
 538COLOR_5_5_5_1                            = 0x00000012,
 539COLOR_4_4_4_4                            = 0x00000013,
 540COLOR_8_24                               = 0x00000014,
 541COLOR_24_8                               = 0x00000015,
 542COLOR_X24_8_32_FLOAT                     = 0x00000016,
 543COLOR_RESERVED_23                        = 0x00000017,
 544COLOR_RESERVED_24                        = 0x00000018,
 545COLOR_RESERVED_25                        = 0x00000019,
 546COLOR_RESERVED_26                        = 0x0000001a,
 547COLOR_RESERVED_27                        = 0x0000001b,
 548COLOR_RESERVED_28                        = 0x0000001c,
 549COLOR_RESERVED_29                        = 0x0000001d,
 550COLOR_RESERVED_30                        = 0x0000001e,
 551COLOR_2_10_10_10_6E4                     = 0x0000001f,
 552} ColorFormat;
 553
 554/*
 555 * SurfaceFormat enum
 556 */
 557
 558typedef enum SurfaceFormat {
 559FMT_INVALID                              = 0x00000000,
 560FMT_8                                    = 0x00000001,
 561FMT_16                                   = 0x00000002,
 562FMT_8_8                                  = 0x00000003,
 563FMT_32                                   = 0x00000004,
 564FMT_16_16                                = 0x00000005,
 565FMT_10_11_11                             = 0x00000006,
 566FMT_11_11_10                             = 0x00000007,
 567FMT_10_10_10_2                           = 0x00000008,
 568FMT_2_10_10_10                           = 0x00000009,
 569FMT_8_8_8_8                              = 0x0000000a,
 570FMT_32_32                                = 0x0000000b,
 571FMT_16_16_16_16                          = 0x0000000c,
 572FMT_32_32_32                             = 0x0000000d,
 573FMT_32_32_32_32                          = 0x0000000e,
 574FMT_RESERVED_4                           = 0x0000000f,
 575FMT_5_6_5                                = 0x00000010,
 576FMT_1_5_5_5                              = 0x00000011,
 577FMT_5_5_5_1                              = 0x00000012,
 578FMT_4_4_4_4                              = 0x00000013,
 579FMT_8_24                                 = 0x00000014,
 580FMT_24_8                                 = 0x00000015,
 581FMT_X24_8_32_FLOAT                       = 0x00000016,
 582FMT_RESERVED_33                          = 0x00000017,
 583FMT_11_11_10_FLOAT                       = 0x00000018,
 584FMT_16_FLOAT                             = 0x00000019,
 585FMT_32_FLOAT                             = 0x0000001a,
 586FMT_16_16_FLOAT                          = 0x0000001b,
 587FMT_8_24_FLOAT                           = 0x0000001c,
 588FMT_24_8_FLOAT                           = 0x0000001d,
 589FMT_32_32_FLOAT                          = 0x0000001e,
 590FMT_10_11_11_FLOAT                       = 0x0000001f,
 591FMT_16_16_16_16_FLOAT                    = 0x00000020,
 592FMT_3_3_2                                = 0x00000021,
 593FMT_6_5_5                                = 0x00000022,
 594FMT_32_32_32_32_FLOAT                    = 0x00000023,
 595FMT_RESERVED_36                          = 0x00000024,
 596FMT_1                                    = 0x00000025,
 597FMT_1_REVERSED                           = 0x00000026,
 598FMT_GB_GR                                = 0x00000027,
 599FMT_BG_RG                                = 0x00000028,
 600FMT_32_AS_8                              = 0x00000029,
 601FMT_32_AS_8_8                            = 0x0000002a,
 602FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
 603FMT_8_8_8                                = 0x0000002c,
 604FMT_16_16_16                             = 0x0000002d,
 605FMT_16_16_16_FLOAT                       = 0x0000002e,
 606FMT_4_4                                  = 0x0000002f,
 607FMT_32_32_32_FLOAT                       = 0x00000030,
 608FMT_BC1                                  = 0x00000031,
 609FMT_BC2                                  = 0x00000032,
 610FMT_BC3                                  = 0x00000033,
 611FMT_BC4                                  = 0x00000034,
 612FMT_BC5                                  = 0x00000035,
 613FMT_BC6                                  = 0x00000036,
 614FMT_BC7                                  = 0x00000037,
 615FMT_32_AS_32_32_32_32                    = 0x00000038,
 616FMT_APC3                                 = 0x00000039,
 617FMT_APC4                                 = 0x0000003a,
 618FMT_APC5                                 = 0x0000003b,
 619FMT_APC6                                 = 0x0000003c,
 620FMT_APC7                                 = 0x0000003d,
 621FMT_CTX1                                 = 0x0000003e,
 622FMT_RESERVED_63                          = 0x0000003f,
 623} SurfaceFormat;
 624
 625/*
 626 * BUF_DATA_FORMAT enum
 627 */
 628
 629typedef enum BUF_DATA_FORMAT {
 630BUF_DATA_FORMAT_INVALID                  = 0x00000000,
 631BUF_DATA_FORMAT_8                        = 0x00000001,
 632BUF_DATA_FORMAT_16                       = 0x00000002,
 633BUF_DATA_FORMAT_8_8                      = 0x00000003,
 634BUF_DATA_FORMAT_32                       = 0x00000004,
 635BUF_DATA_FORMAT_16_16                    = 0x00000005,
 636BUF_DATA_FORMAT_10_11_11                 = 0x00000006,
 637BUF_DATA_FORMAT_11_11_10                 = 0x00000007,
 638BUF_DATA_FORMAT_10_10_10_2               = 0x00000008,
 639BUF_DATA_FORMAT_2_10_10_10               = 0x00000009,
 640BUF_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
 641BUF_DATA_FORMAT_32_32                    = 0x0000000b,
 642BUF_DATA_FORMAT_16_16_16_16              = 0x0000000c,
 643BUF_DATA_FORMAT_32_32_32                 = 0x0000000d,
 644BUF_DATA_FORMAT_32_32_32_32              = 0x0000000e,
 645BUF_DATA_FORMAT_RESERVED_15              = 0x0000000f,
 646} BUF_DATA_FORMAT;
 647
 648/*
 649 * IMG_DATA_FORMAT enum
 650 */
 651
 652typedef enum IMG_DATA_FORMAT {
 653IMG_DATA_FORMAT_INVALID                  = 0x00000000,
 654IMG_DATA_FORMAT_8                        = 0x00000001,
 655IMG_DATA_FORMAT_16                       = 0x00000002,
 656IMG_DATA_FORMAT_8_8                      = 0x00000003,
 657IMG_DATA_FORMAT_32                       = 0x00000004,
 658IMG_DATA_FORMAT_16_16                    = 0x00000005,
 659IMG_DATA_FORMAT_10_11_11                 = 0x00000006,
 660IMG_DATA_FORMAT_11_11_10                 = 0x00000007,
 661IMG_DATA_FORMAT_10_10_10_2               = 0x00000008,
 662IMG_DATA_FORMAT_2_10_10_10               = 0x00000009,
 663IMG_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
 664IMG_DATA_FORMAT_32_32                    = 0x0000000b,
 665IMG_DATA_FORMAT_16_16_16_16              = 0x0000000c,
 666IMG_DATA_FORMAT_32_32_32                 = 0x0000000d,
 667IMG_DATA_FORMAT_32_32_32_32              = 0x0000000e,
 668IMG_DATA_FORMAT_RESERVED_15              = 0x0000000f,
 669IMG_DATA_FORMAT_5_6_5                    = 0x00000010,
 670IMG_DATA_FORMAT_1_5_5_5                  = 0x00000011,
 671IMG_DATA_FORMAT_5_5_5_1                  = 0x00000012,
 672IMG_DATA_FORMAT_4_4_4_4                  = 0x00000013,
 673IMG_DATA_FORMAT_8_24                     = 0x00000014,
 674IMG_DATA_FORMAT_24_8                     = 0x00000015,
 675IMG_DATA_FORMAT_X24_8_32                 = 0x00000016,
 676IMG_DATA_FORMAT_8_AS_8_8_8_8             = 0x00000017,
 677IMG_DATA_FORMAT_ETC2_RGB                 = 0x00000018,
 678IMG_DATA_FORMAT_ETC2_RGBA                = 0x00000019,
 679IMG_DATA_FORMAT_ETC2_R                   = 0x0000001a,
 680IMG_DATA_FORMAT_ETC2_RG                  = 0x0000001b,
 681IMG_DATA_FORMAT_ETC2_RGBA1               = 0x0000001c,
 682IMG_DATA_FORMAT_RESERVED_29              = 0x0000001d,
 683IMG_DATA_FORMAT_RESERVED_30              = 0x0000001e,
 684IMG_DATA_FORMAT_6E4                      = 0x0000001f,
 685IMG_DATA_FORMAT_GB_GR                    = 0x00000020,
 686IMG_DATA_FORMAT_BG_RG                    = 0x00000021,
 687IMG_DATA_FORMAT_5_9_9_9                  = 0x00000022,
 688IMG_DATA_FORMAT_BC1                      = 0x00000023,
 689IMG_DATA_FORMAT_BC2                      = 0x00000024,
 690IMG_DATA_FORMAT_BC3                      = 0x00000025,
 691IMG_DATA_FORMAT_BC4                      = 0x00000026,
 692IMG_DATA_FORMAT_BC5                      = 0x00000027,
 693IMG_DATA_FORMAT_BC6                      = 0x00000028,
 694IMG_DATA_FORMAT_BC7                      = 0x00000029,
 695IMG_DATA_FORMAT_16_AS_32_32              = 0x0000002a,
 696IMG_DATA_FORMAT_16_AS_16_16_16_16        = 0x0000002b,
 697IMG_DATA_FORMAT_16_AS_32_32_32_32        = 0x0000002c,
 698IMG_DATA_FORMAT_FMASK                    = 0x0000002d,
 699IMG_DATA_FORMAT_ASTC_2D_LDR              = 0x0000002e,
 700IMG_DATA_FORMAT_ASTC_2D_HDR              = 0x0000002f,
 701IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB         = 0x00000030,
 702IMG_DATA_FORMAT_ASTC_3D_LDR              = 0x00000031,
 703IMG_DATA_FORMAT_ASTC_3D_HDR              = 0x00000032,
 704IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB         = 0x00000033,
 705IMG_DATA_FORMAT_N_IN_16                  = 0x00000034,
 706IMG_DATA_FORMAT_N_IN_16_16               = 0x00000035,
 707IMG_DATA_FORMAT_N_IN_16_16_16_16         = 0x00000036,
 708IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16   = 0x00000037,
 709IMG_DATA_FORMAT_RESERVED_56              = 0x00000038,
 710IMG_DATA_FORMAT_4_4                      = 0x00000039,
 711IMG_DATA_FORMAT_6_5_5                    = 0x0000003a,
 712IMG_DATA_FORMAT_RESERVED_59              = 0x0000003b,
 713IMG_DATA_FORMAT_RESERVED_60              = 0x0000003c,
 714IMG_DATA_FORMAT_8_AS_32                  = 0x0000003d,
 715IMG_DATA_FORMAT_8_AS_32_32               = 0x0000003e,
 716IMG_DATA_FORMAT_32_AS_32_32_32_32        = 0x0000003f,
 717} IMG_DATA_FORMAT;
 718
 719/*
 720 * BUF_NUM_FORMAT enum
 721 */
 722
 723typedef enum BUF_NUM_FORMAT {
 724BUF_NUM_FORMAT_UNORM                     = 0x00000000,
 725BUF_NUM_FORMAT_SNORM                     = 0x00000001,
 726BUF_NUM_FORMAT_USCALED                   = 0x00000002,
 727BUF_NUM_FORMAT_SSCALED                   = 0x00000003,
 728BUF_NUM_FORMAT_UINT                      = 0x00000004,
 729BUF_NUM_FORMAT_SINT                      = 0x00000005,
 730BUF_NUM_FORMAT_UNORM_UINT                = 0x00000006,
 731BUF_NUM_FORMAT_FLOAT                     = 0x00000007,
 732} BUF_NUM_FORMAT;
 733
 734/*
 735 * IMG_NUM_FORMAT enum
 736 */
 737
 738typedef enum IMG_NUM_FORMAT {
 739IMG_NUM_FORMAT_UNORM                     = 0x00000000,
 740IMG_NUM_FORMAT_SNORM                     = 0x00000001,
 741IMG_NUM_FORMAT_USCALED                   = 0x00000002,
 742IMG_NUM_FORMAT_SSCALED                   = 0x00000003,
 743IMG_NUM_FORMAT_UINT                      = 0x00000004,
 744IMG_NUM_FORMAT_SINT                      = 0x00000005,
 745IMG_NUM_FORMAT_UNORM_UINT                = 0x00000006,
 746IMG_NUM_FORMAT_FLOAT                     = 0x00000007,
 747IMG_NUM_FORMAT_RESERVED_8                = 0x00000008,
 748IMG_NUM_FORMAT_SRGB                      = 0x00000009,
 749IMG_NUM_FORMAT_RESERVED_10               = 0x0000000a,
 750IMG_NUM_FORMAT_RESERVED_11               = 0x0000000b,
 751IMG_NUM_FORMAT_RESERVED_12               = 0x0000000c,
 752IMG_NUM_FORMAT_RESERVED_13               = 0x0000000d,
 753IMG_NUM_FORMAT_RESERVED_14               = 0x0000000e,
 754IMG_NUM_FORMAT_RESERVED_15               = 0x0000000f,
 755} IMG_NUM_FORMAT;
 756
 757/*
 758 * IMG_NUM_FORMAT_FMASK enum
 759 */
 760
 761typedef enum IMG_NUM_FORMAT_FMASK {
 762IMG_NUM_FORMAT_FMASK_8_2_1               = 0x00000000,
 763IMG_NUM_FORMAT_FMASK_8_4_1               = 0x00000001,
 764IMG_NUM_FORMAT_FMASK_8_8_1               = 0x00000002,
 765IMG_NUM_FORMAT_FMASK_8_2_2               = 0x00000003,
 766IMG_NUM_FORMAT_FMASK_8_4_2               = 0x00000004,
 767IMG_NUM_FORMAT_FMASK_8_4_4               = 0x00000005,
 768IMG_NUM_FORMAT_FMASK_16_16_1             = 0x00000006,
 769IMG_NUM_FORMAT_FMASK_16_8_2              = 0x00000007,
 770IMG_NUM_FORMAT_FMASK_32_16_2             = 0x00000008,
 771IMG_NUM_FORMAT_FMASK_32_8_4              = 0x00000009,
 772IMG_NUM_FORMAT_FMASK_32_8_8              = 0x0000000a,
 773IMG_NUM_FORMAT_FMASK_64_16_4             = 0x0000000b,
 774IMG_NUM_FORMAT_FMASK_64_16_8             = 0x0000000c,
 775IMG_NUM_FORMAT_FMASK_RESERVED_13         = 0x0000000d,
 776IMG_NUM_FORMAT_FMASK_RESERVED_14         = 0x0000000e,
 777IMG_NUM_FORMAT_FMASK_RESERVED_15         = 0x0000000f,
 778} IMG_NUM_FORMAT_FMASK;
 779
 780/*
 781 * IMG_NUM_FORMAT_N_IN_16 enum
 782 */
 783
 784typedef enum IMG_NUM_FORMAT_N_IN_16 {
 785IMG_NUM_FORMAT_N_IN_16_RESERVED_0        = 0x00000000,
 786IMG_NUM_FORMAT_N_IN_16_UNORM_10          = 0x00000001,
 787IMG_NUM_FORMAT_N_IN_16_UNORM_9           = 0x00000002,
 788IMG_NUM_FORMAT_N_IN_16_RESERVED_3        = 0x00000003,
 789IMG_NUM_FORMAT_N_IN_16_UINT_10           = 0x00000004,
 790IMG_NUM_FORMAT_N_IN_16_UINT_9            = 0x00000005,
 791IMG_NUM_FORMAT_N_IN_16_RESERVED_6        = 0x00000006,
 792IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10     = 0x00000007,
 793IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9      = 0x00000008,
 794IMG_NUM_FORMAT_N_IN_16_RESERVED_9        = 0x00000009,
 795IMG_NUM_FORMAT_N_IN_16_RESERVED_10       = 0x0000000a,
 796IMG_NUM_FORMAT_N_IN_16_RESERVED_11       = 0x0000000b,
 797IMG_NUM_FORMAT_N_IN_16_RESERVED_12       = 0x0000000c,
 798IMG_NUM_FORMAT_N_IN_16_RESERVED_13       = 0x0000000d,
 799IMG_NUM_FORMAT_N_IN_16_RESERVED_14       = 0x0000000e,
 800IMG_NUM_FORMAT_N_IN_16_RESERVED_15       = 0x0000000f,
 801} IMG_NUM_FORMAT_N_IN_16;
 802
 803/*
 804 * IMG_NUM_FORMAT_ASTC_2D enum
 805 */
 806
 807typedef enum IMG_NUM_FORMAT_ASTC_2D {
 808IMG_NUM_FORMAT_ASTC_2D_4x4               = 0x00000000,
 809IMG_NUM_FORMAT_ASTC_2D_5x4               = 0x00000001,
 810IMG_NUM_FORMAT_ASTC_2D_5x5               = 0x00000002,
 811IMG_NUM_FORMAT_ASTC_2D_6x5               = 0x00000003,
 812IMG_NUM_FORMAT_ASTC_2D_6x6               = 0x00000004,
 813IMG_NUM_FORMAT_ASTC_2D_8x5               = 0x00000005,
 814IMG_NUM_FORMAT_ASTC_2D_8x6               = 0x00000006,
 815IMG_NUM_FORMAT_ASTC_2D_8x8               = 0x00000007,
 816IMG_NUM_FORMAT_ASTC_2D_10x5              = 0x00000008,
 817IMG_NUM_FORMAT_ASTC_2D_10x6              = 0x00000009,
 818IMG_NUM_FORMAT_ASTC_2D_10x8              = 0x0000000a,
 819IMG_NUM_FORMAT_ASTC_2D_10x10             = 0x0000000b,
 820IMG_NUM_FORMAT_ASTC_2D_12x10             = 0x0000000c,
 821IMG_NUM_FORMAT_ASTC_2D_12x12             = 0x0000000d,
 822IMG_NUM_FORMAT_ASTC_2D_RESERVED_14       = 0x0000000e,
 823IMG_NUM_FORMAT_ASTC_2D_RESERVED_15       = 0x0000000f,
 824} IMG_NUM_FORMAT_ASTC_2D;
 825
 826/*
 827 * IMG_NUM_FORMAT_ASTC_3D enum
 828 */
 829
 830typedef enum IMG_NUM_FORMAT_ASTC_3D {
 831IMG_NUM_FORMAT_ASTC_3D_3x3x3             = 0x00000000,
 832IMG_NUM_FORMAT_ASTC_3D_4x3x3             = 0x00000001,
 833IMG_NUM_FORMAT_ASTC_3D_4x4x3             = 0x00000002,
 834IMG_NUM_FORMAT_ASTC_3D_4x4x4             = 0x00000003,
 835IMG_NUM_FORMAT_ASTC_3D_5x4x4             = 0x00000004,
 836IMG_NUM_FORMAT_ASTC_3D_5x5x4             = 0x00000005,
 837IMG_NUM_FORMAT_ASTC_3D_5x5x5             = 0x00000006,
 838IMG_NUM_FORMAT_ASTC_3D_6x5x5             = 0x00000007,
 839IMG_NUM_FORMAT_ASTC_3D_6x6x5             = 0x00000008,
 840IMG_NUM_FORMAT_ASTC_3D_6x6x6             = 0x00000009,
 841IMG_NUM_FORMAT_ASTC_3D_RESERVED_10       = 0x0000000a,
 842IMG_NUM_FORMAT_ASTC_3D_RESERVED_11       = 0x0000000b,
 843IMG_NUM_FORMAT_ASTC_3D_RESERVED_12       = 0x0000000c,
 844IMG_NUM_FORMAT_ASTC_3D_RESERVED_13       = 0x0000000d,
 845IMG_NUM_FORMAT_ASTC_3D_RESERVED_14       = 0x0000000e,
 846IMG_NUM_FORMAT_ASTC_3D_RESERVED_15       = 0x0000000f,
 847} IMG_NUM_FORMAT_ASTC_3D;
 848
 849/*
 850 * TileType enum
 851 */
 852
 853typedef enum TileType {
 854ARRAY_COLOR_TILE                         = 0x00000000,
 855ARRAY_DEPTH_TILE                         = 0x00000001,
 856} TileType;
 857
 858/*
 859 * NonDispTilingOrder enum
 860 */
 861
 862typedef enum NonDispTilingOrder {
 863ADDR_SURF_MICRO_TILING_DISPLAY           = 0x00000000,
 864ADDR_SURF_MICRO_TILING_NON_DISPLAY       = 0x00000001,
 865} NonDispTilingOrder;
 866
 867/*
 868 * MicroTileMode enum
 869 */
 870
 871typedef enum MicroTileMode {
 872ADDR_SURF_DISPLAY_MICRO_TILING           = 0x00000000,
 873ADDR_SURF_THIN_MICRO_TILING              = 0x00000001,
 874ADDR_SURF_DEPTH_MICRO_TILING             = 0x00000002,
 875ADDR_SURF_ROTATED_MICRO_TILING           = 0x00000003,
 876ADDR_SURF_THICK_MICRO_TILING             = 0x00000004,
 877} MicroTileMode;
 878
 879/*
 880 * TileSplit enum
 881 */
 882
 883typedef enum TileSplit {
 884ADDR_SURF_TILE_SPLIT_64B                 = 0x00000000,
 885ADDR_SURF_TILE_SPLIT_128B                = 0x00000001,
 886ADDR_SURF_TILE_SPLIT_256B                = 0x00000002,
 887ADDR_SURF_TILE_SPLIT_512B                = 0x00000003,
 888ADDR_SURF_TILE_SPLIT_1KB                 = 0x00000004,
 889ADDR_SURF_TILE_SPLIT_2KB                 = 0x00000005,
 890ADDR_SURF_TILE_SPLIT_4KB                 = 0x00000006,
 891} TileSplit;
 892
 893/*
 894 * SampleSplit enum
 895 */
 896
 897typedef enum SampleSplit {
 898ADDR_SURF_SAMPLE_SPLIT_1                 = 0x00000000,
 899ADDR_SURF_SAMPLE_SPLIT_2                 = 0x00000001,
 900ADDR_SURF_SAMPLE_SPLIT_4                 = 0x00000002,
 901ADDR_SURF_SAMPLE_SPLIT_8                 = 0x00000003,
 902} SampleSplit;
 903
 904/*
 905 * PipeConfig enum
 906 */
 907
 908typedef enum PipeConfig {
 909ADDR_SURF_P2                             = 0x00000000,
 910ADDR_SURF_P2_RESERVED0                   = 0x00000001,
 911ADDR_SURF_P2_RESERVED1                   = 0x00000002,
 912ADDR_SURF_P2_RESERVED2                   = 0x00000003,
 913ADDR_SURF_P4_8x16                        = 0x00000004,
 914ADDR_SURF_P4_16x16                       = 0x00000005,
 915ADDR_SURF_P4_16x32                       = 0x00000006,
 916ADDR_SURF_P4_32x32                       = 0x00000007,
 917ADDR_SURF_P8_16x16_8x16                  = 0x00000008,
 918ADDR_SURF_P8_16x32_8x16                  = 0x00000009,
 919ADDR_SURF_P8_32x32_8x16                  = 0x0000000a,
 920ADDR_SURF_P8_16x32_16x16                 = 0x0000000b,
 921ADDR_SURF_P8_32x32_16x16                 = 0x0000000c,
 922ADDR_SURF_P8_32x32_16x32                 = 0x0000000d,
 923ADDR_SURF_P8_32x64_32x32                 = 0x0000000e,
 924ADDR_SURF_P8_RESERVED0                   = 0x0000000f,
 925ADDR_SURF_P16_32x32_8x16                 = 0x00000010,
 926ADDR_SURF_P16_32x32_16x16                = 0x00000011,
 927} PipeConfig;
 928
 929/*
 930 * SeEnable enum
 931 */
 932
 933typedef enum SeEnable {
 934ADDR_CONFIG_DISABLE_SE                   = 0x00000000,
 935ADDR_CONFIG_ENABLE_SE                    = 0x00000001,
 936} SeEnable;
 937
 938/*
 939 * NumBanks enum
 940 */
 941
 942typedef enum NumBanks {
 943ADDR_SURF_2_BANK                         = 0x00000000,
 944ADDR_SURF_4_BANK                         = 0x00000001,
 945ADDR_SURF_8_BANK                         = 0x00000002,
 946ADDR_SURF_16_BANK                        = 0x00000003,
 947} NumBanks;
 948
 949/*
 950 * BankWidth enum
 951 */
 952
 953typedef enum BankWidth {
 954ADDR_SURF_BANK_WIDTH_1                   = 0x00000000,
 955ADDR_SURF_BANK_WIDTH_2                   = 0x00000001,
 956ADDR_SURF_BANK_WIDTH_4                   = 0x00000002,
 957ADDR_SURF_BANK_WIDTH_8                   = 0x00000003,
 958} BankWidth;
 959
 960/*
 961 * BankHeight enum
 962 */
 963
 964typedef enum BankHeight {
 965ADDR_SURF_BANK_HEIGHT_1                  = 0x00000000,
 966ADDR_SURF_BANK_HEIGHT_2                  = 0x00000001,
 967ADDR_SURF_BANK_HEIGHT_4                  = 0x00000002,
 968ADDR_SURF_BANK_HEIGHT_8                  = 0x00000003,
 969} BankHeight;
 970
 971/*
 972 * BankWidthHeight enum
 973 */
 974
 975typedef enum BankWidthHeight {
 976ADDR_SURF_BANK_WH_1                      = 0x00000000,
 977ADDR_SURF_BANK_WH_2                      = 0x00000001,
 978ADDR_SURF_BANK_WH_4                      = 0x00000002,
 979ADDR_SURF_BANK_WH_8                      = 0x00000003,
 980} BankWidthHeight;
 981
 982/*
 983 * MacroTileAspect enum
 984 */
 985
 986typedef enum MacroTileAspect {
 987ADDR_SURF_MACRO_ASPECT_1                 = 0x00000000,
 988ADDR_SURF_MACRO_ASPECT_2                 = 0x00000001,
 989ADDR_SURF_MACRO_ASPECT_4                 = 0x00000002,
 990ADDR_SURF_MACRO_ASPECT_8                 = 0x00000003,
 991} MacroTileAspect;
 992
 993/*
 994 * GATCL1RequestType enum
 995 */
 996
 997typedef enum GATCL1RequestType {
 998GATCL1_TYPE_NORMAL                       = 0x00000000,
 999GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
1000GATCL1_TYPE_BYPASS                       = 0x00000002,

1001} GATCL1RequestType;
1002
1003/*
1004 * UTCL1RequestType enum
1005 */
1006
1007typedef enum UTCL1RequestType {
1008UTCL1_TYPE_NORMAL                        = 0x00000000,
1009UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,
1010UTCL1_TYPE_BYPASS                        = 0x00000002,
1011} UTCL1RequestType;
1012
1013/*
1014 * UTCL1FaultType enum
1015 */
1016
1017typedef enum UTCL1FaultType {
1018UTCL1_XNACK_SUCCESS                      = 0x00000000,
1019UTCL1_XNACK_RETRY                        = 0x00000001,
1020UTCL1_XNACK_PRT                          = 0x00000002,
1021UTCL1_XNACK_NO_RETRY                     = 0x00000003,
1022} UTCL1FaultType;
1023
1024/*
1025 * TCC_CACHE_POLICIES enum
1026 */
1027
1028typedef enum TCC_CACHE_POLICIES {
1029TCC_CACHE_POLICY_LRU                     = 0x00000000,
1030TCC_CACHE_POLICY_STREAM                  = 0x00000001,
1031} TCC_CACHE_POLICIES;
1032
1033/*
1034 * MTYPE enum
1035 */
1036
1037typedef enum MTYPE {
1038MTYPE_NC                                 = 0x00000000,
1039MTYPE_WC                                 = 0x00000001,
1040MTYPE_CC                                 = 0x00000002,
1041MTYPE_UC                                 = 0x00000003,
1042} MTYPE;
1043
1044/*
1045 * RMI_CID enum
1046 */
1047
1048typedef enum RMI_CID {
1049RMI_CID_CC                               = 0x00000000,
1050RMI_CID_FC                               = 0x00000001,
1051RMI_CID_CM                               = 0x00000002,
1052RMI_CID_DC                               = 0x00000003,
1053RMI_CID_Z                                = 0x00000004,
1054RMI_CID_S                                = 0x00000005,
1055RMI_CID_TILE                             = 0x00000006,
1056RMI_CID_ZPCPSD                           = 0x00000007,
1057} RMI_CID;
1058
1059/*
1060 * PERFMON_COUNTER_MODE enum
1061 */
1062
1063typedef enum PERFMON_COUNTER_MODE {
1064PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
1065PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
1066PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
1067PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
1068PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
1069PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT  = 0x00000005,
1070PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT  = 0x00000006,
1071PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
1072PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
1073PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
1074PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
1075} PERFMON_COUNTER_MODE;
1076
1077/*
1078 * PERFMON_SPM_MODE enum
1079 */
1080
1081typedef enum PERFMON_SPM_MODE {
1082PERFMON_SPM_MODE_OFF                     = 0x00000000,
1083PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
1084PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
1085PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
1086PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
1087PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
1088PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
1089PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
1090PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
1091PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
1092PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
1093} PERFMON_SPM_MODE;
1094
1095/*
1096 * SurfaceTiling enum
1097 */
1098
1099typedef enum SurfaceTiling {
1100ARRAY_LINEAR                             = 0x00000000,
1101ARRAY_TILED                              = 0x00000001,
1102} SurfaceTiling;
1103
1104/*
1105 * SurfaceArray enum
1106 */
1107
1108typedef enum SurfaceArray {
1109ARRAY_1D                                 = 0x00000000,
1110ARRAY_2D                                 = 0x00000001,
1111ARRAY_3D                                 = 0x00000002,
1112ARRAY_3D_SLICE                           = 0x00000003,
1113} SurfaceArray;
1114
1115/*
1116 * ColorArray enum
1117 */
1118
1119typedef enum ColorArray {
1120ARRAY_2D_ALT_COLOR                       = 0x00000000,
1121ARRAY_2D_COLOR                           = 0x00000001,
1122ARRAY_3D_SLICE_COLOR                     = 0x00000003,
1123} ColorArray;
1124
1125/*
1126 * DepthArray enum
1127 */
1128
1129typedef enum DepthArray {
1130ARRAY_2D_ALT_DEPTH                       = 0x00000000,
1131ARRAY_2D_DEPTH                           = 0x00000001,
1132} DepthArray;
1133
1134/*
1135 * ENUM_NUM_SIMD_PER_CU enum
1136 */
1137
1138typedef enum ENUM_NUM_SIMD_PER_CU {
1139NUM_SIMD_PER_CU                          = 0x00000004,
1140} ENUM_NUM_SIMD_PER_CU;
1141
1142/*
1143 * DSM_ENABLE_ERROR_INJECT enum
1144 */
1145
1146typedef enum DSM_ENABLE_ERROR_INJECT {
1147DSM_ENABLE_ERROR_INJECT_FED_IN           = 0x00000000,
1148DSM_ENABLE_ERROR_INJECT_SINGLE           = 0x00000001,
1149DSM_ENABLE_ERROR_INJECT_DOUBLE           = 0x00000002,
1150DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED   = 0x00000003,
1151} DSM_ENABLE_ERROR_INJECT;
1152
1153/*
1154 * DSM_SELECT_INJECT_DELAY enum
1155 */
1156
1157typedef enum DSM_SELECT_INJECT_DELAY {
1158DSM_SELECT_INJECT_DELAY_NO_DELAY         = 0x00000000,
1159DSM_SELECT_INJECT_DELAY_DELAY_ERROR      = 0x00000001,
1160} DSM_SELECT_INJECT_DELAY;
1161
1162/*
1163 * SWIZZLE_TYPE_ENUM enum
1164 */
1165
1166typedef enum SWIZZLE_TYPE_ENUM {
1167SW_Z                                     = 0x00000000,
1168SW_S                                     = 0x00000001,
1169SW_D                                     = 0x00000002,
1170SW_R                                     = 0x00000003,
1171SW_L                                     = 0x00000004,
1172} SWIZZLE_TYPE_ENUM;
1173
1174/*
1175 * TC_MICRO_TILE_MODE enum
1176 */
1177
1178typedef enum TC_MICRO_TILE_MODE {
1179MICRO_TILE_MODE_LINEAR                   = 0x00000000,
1180MICRO_TILE_MODE_ROTATED                  = 0x00000001,
1181MICRO_TILE_MODE_STD_2D                   = 0x00000002,
1182MICRO_TILE_MODE_STD_3D                   = 0x00000003,
1183MICRO_TILE_MODE_DISPLAY_2D               = 0x00000004,
1184MICRO_TILE_MODE_DISPLAY_3D               = 0x00000005,
1185MICRO_TILE_MODE_Z_2D                     = 0x00000006,
1186MICRO_TILE_MODE_Z_3D                     = 0x00000007,
1187} TC_MICRO_TILE_MODE;
1188
1189/*
1190 * SWIZZLE_MODE_ENUM enum
1191 */
1192
1193typedef enum SWIZZLE_MODE_ENUM {
1194SW_LINEAR                                = 0x00000000,
1195SW_256B_S                                = 0x00000001,
1196SW_256B_D                                = 0x00000002,
1197SW_256B_R                                = 0x00000003,
1198SW_4KB_Z                                 = 0x00000004,
1199SW_4KB_S                                 = 0x00000005,
1200SW_4KB_D                                 = 0x00000006,
1201SW_4KB_R                                 = 0x00000007,
1202SW_64KB_Z                                = 0x00000008,
1203SW_64KB_S                                = 0x00000009,
1204SW_64KB_D                                = 0x0000000a,
1205SW_64KB_R                                = 0x0000000b,
1206SW_VAR_Z                                 = 0x0000000c,
1207SW_VAR_S                                 = 0x0000000d,
1208SW_VAR_D                                 = 0x0000000e,
1209SW_VAR_R                                 = 0x0000000f,
1210SW_RESERVED_16                           = 0x00000010,
1211SW_RESERVED_17                           = 0x00000011,
1212SW_RESERVED_18                           = 0x00000012,
1213SW_RESERVED_19                           = 0x00000013,
1214SW_4KB_Z_X                               = 0x00000014,
1215SW_4KB_S_X                               = 0x00000015,
1216SW_4KB_D_X                               = 0x00000016,
1217SW_4KB_R_X                               = 0x00000017,
1218SW_64KB_Z_X                              = 0x00000018,
1219SW_64KB_S_X                              = 0x00000019,
1220SW_64KB_D_X                              = 0x0000001a,
1221SW_64KB_R_X                              = 0x0000001b,
1222SW_VAR_Z_X                               = 0x0000001c,
1223SW_VAR_S_X                               = 0x0000001d,
1224SW_VAR_D_X                               = 0x0000001e,
1225SW_VAR_R_X                               = 0x0000001f,
1226SW_RESERVED_12                           = 0x00000020,
1227SW_RESERVED_13                           = 0x00000021,
1228SW_RESERVED_14                           = 0x00000022,
1229SW_RESERVED_15                           = 0x00000023,
1230} SWIZZLE_MODE_ENUM;
1231
1232/*
1233 * PipeTiling enum
1234 */
1235
1236typedef enum PipeTiling {
1237CONFIG_1_PIPE                            = 0x00000000,
1238CONFIG_2_PIPE                            = 0x00000001,
1239CONFIG_4_PIPE                            = 0x00000002,
1240CONFIG_8_PIPE                            = 0x00000003,
1241} PipeTiling;
1242
1243/*
1244 * BankTiling enum
1245 */
1246
1247typedef enum BankTiling {
1248CONFIG_4_BANK                            = 0x00000000,
1249CONFIG_8_BANK                            = 0x00000001,
1250} BankTiling;
1251
1252/*
1253 * GroupInterleave enum
1254 */
1255
1256typedef enum GroupInterleave {
1257CONFIG_256B_GROUP                        = 0x00000000,
1258CONFIG_512B_GROUP                        = 0x00000001,
1259} GroupInterleave;
1260
1261/*
1262 * RowTiling enum
1263 */
1264
1265typedef enum RowTiling {
1266CONFIG_1KB_ROW                           = 0x00000000,
1267CONFIG_2KB_ROW                           = 0x00000001,
1268CONFIG_4KB_ROW                           = 0x00000002,
1269CONFIG_8KB_ROW                           = 0x00000003,
1270CONFIG_1KB_ROW_OPT                       = 0x00000004,
1271CONFIG_2KB_ROW_OPT                       = 0x00000005,
1272CONFIG_4KB_ROW_OPT                       = 0x00000006,
1273CONFIG_8KB_ROW_OPT                       = 0x00000007,
1274} RowTiling;
1275
1276/*
1277 * BankSwapBytes enum
1278 */
1279
1280typedef enum BankSwapBytes {
1281CONFIG_128B_SWAPS                        = 0x00000000,
1282CONFIG_256B_SWAPS                        = 0x00000001,
1283CONFIG_512B_SWAPS                        = 0x00000002,
1284CONFIG_1KB_SWAPS                         = 0x00000003,
1285} BankSwapBytes;
1286
1287/*
1288 * SampleSplitBytes enum
1289 */
1290
1291typedef enum SampleSplitBytes {
1292CONFIG_1KB_SPLIT                         = 0x00000000,
1293CONFIG_2KB_SPLIT                         = 0x00000001,
1294CONFIG_4KB_SPLIT                         = 0x00000002,
1295CONFIG_8KB_SPLIT                         = 0x00000003,
1296} SampleSplitBytes;
1297
1298/*******************************************************
1299 * AZSTREAM Enums
1300 *******************************************************/
1301
1302/*
1303 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
1304 */
1305
1306typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
1307OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET  = 0x00000000,
1308OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET  = 0x00000001,
1309} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
1310
1311/*
1312 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
1313 */
1314
1315typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
1316OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET  = 0x00000000,
1317OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET  = 0x00000001,
1318} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
1319
1320/*
1321 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
1322 */
1323
1324typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
1325OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET  = 0x00000000,
1326OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET  = 0x00000001,
1327} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
1328
1329/*
1330 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
1331 */
1332
1333typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
1334OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY  = 0x00000000,
1335OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY  = 0x00000001,
1336} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
1337
1338/*
1339 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
1340 */
1341
1342typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
1343OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED  = 0x00000000,
1344OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED  = 0x00000001,
1345} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
1346
1347/*
1348 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
1349 */
1350
1351typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
1352OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED  = 0x00000000,
1353OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED  = 0x00000001,
1354} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
1355
1356/*
1357 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
1358 */
1359
1360typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
1361OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED  = 0x00000000,
1362OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED  = 0x00000001,
1363} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
1364
1365/*
1366 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
1367 */
1368
1369typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
1370OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN  = 0x00000000,
1371OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN  = 0x00000001,
1372} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
1373
1374/*
1375 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
1376 */
1377
1378typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
1379OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET  = 0x00000000,
1380OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET  = 0x00000001,
1381} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
1382
1383/*
1384 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
1385 */
1386
1387typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
1388OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
1389OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
1390} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
1391
1392/*
1393 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
1394 */
1395
1396typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
1397OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
1398OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
1399OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
1400OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
1401OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
1402} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
1403
1404/*
1405 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
1406 */
1407
1408typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
1409OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
1410OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
1411OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
1412OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
1413OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
1414OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
1415OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
1416OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
1417} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
1418
1419/*
1420 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
1421 */
1422
1423typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
1424OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
1425OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
1426OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
1427OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
1428OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
1429OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
1430} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
1431
1432/*
1433 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
1434 */
1435
1436typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
1437OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
1438OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
1439OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
1440OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
1441OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
1442OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
1443OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
1444OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
1445OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED  = 0x00000008,
1446OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED  = 0x00000009,
1447OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED  = 0x0000000a,
1448OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED  = 0x0000000b,
1449OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED  = 0x0000000c,
1450OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED  = 0x0000000d,
1451OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED  = 0x0000000e,
1452OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED  = 0x0000000f,
1453} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
1454
1455/*******************************************************
1456 * BLNDV Enums
1457 *******************************************************/
1458
1459/*
1460 * BLNDV_CONTROL_BLND_MODE enum
1461 */
1462
1463typedef enum BLNDV_CONTROL_BLND_MODE {
1464BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
1465BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY  = 0x00000001,
1466BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
1467BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
1468} BLNDV_CONTROL_BLND_MODE;
1469
1470/*
1471 * BLNDV_CONTROL_BLND_STEREO_TYPE enum
1472 */
1473
1474typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
1475BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
1476BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
1477BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
1478BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED    = 0x00000003,
1479} BLNDV_CONTROL_BLND_STEREO_TYPE;
1480
1481/*
1482 * BLNDV_CONTROL_BLND_STEREO_POLARITY enum
1483 */
1484
1485typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
1486BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW   = 0x00000000,
1487BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH  = 0x00000001,
1488} BLNDV_CONTROL_BLND_STEREO_POLARITY;
1489
1490/*
1491 * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
1492 */
1493
1494typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
1495BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE  = 0x00000000,
1496BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE   = 0x00000001,
1497} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
1498
1499/*
1500 * BLNDV_CONTROL_BLND_ALPHA_MODE enum
1501 */
1502
1503typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
1504BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
1505BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
1506BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
1507BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED     = 0x00000003,
1508} BLNDV_CONTROL_BLND_ALPHA_MODE;
1509
1510/*
1511 * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
1512 */
1513
1514typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
1515BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE  = 0x00000000,
1516BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE  = 0x00000001,
1517} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
1518
1519/*
1520 * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
1521 */
1522
1523typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
1524BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
1525BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE  = 0x00000001,
1526} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
1527
1528/*
1529 * BLNDV_SM_CONTROL2_SM_MODE enum
1530 */
1531
1532typedef enum BLNDV_SM_CONTROL2_SM_MODE {
1533BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE   = 0x00000000,
1534BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
1535BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
1536BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
1537} BLNDV_SM_CONTROL2_SM_MODE;
1538
1539/*
1540 * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
1541 */
1542
1543typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
1544BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
1545BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
1546} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
1547
1548/*
1549 * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
1550 */
1551
1552typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
1553BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
1554BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
1555} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
1556
1557/*
1558 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
1559 */
1560
1561typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
1562BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
1563BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
1564BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
1565BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
1566} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
1567
1568/*
1569 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
1570 */
1571
1572typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
1573BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
1574BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
1575BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
1576BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
1577} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
1578
1579/*
1580 * BLNDV_CONTROL2_PTI_ENABLE enum
1581 */
1582
1583typedef enum BLNDV_CONTROL2_PTI_ENABLE {
1584BLNDV_CONTROL2_PTI_ENABLE_FALSE          = 0x00000000,
1585BLNDV_CONTROL2_PTI_ENABLE_TRUE           = 0x00000001,
1586} BLNDV_CONTROL2_PTI_ENABLE;
1587
1588/*
1589 * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
1590 */
1591
1592typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
1593BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
1594BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
1595} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
1596
1597/*
1598 * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
1599 */
1600
1601typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
1602BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
1603BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
1604} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
1605
1606/*
1607 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
1608 */
1609
1610typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
1611BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
1612BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
1613} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
1614
1615/*
1616 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
1617 */
1618
1619typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
1620BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
1621BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
1622} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
1623
1624/*
1625 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
1626 */
1627
1628typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
1629BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
1630BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
1631} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
1632
1633/*
1634 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
1635 */
1636
1637typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
1638BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
1639BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
1640} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
1641
1642/*
1643 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
1644 */
1645
1646typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
1647BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
1648BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
1649} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
1650
1651/*
1652 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
1653 */
1654
1655typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
1656BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
1657BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
1658} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
1659
1660/*
1661 * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
1662 */
1663
1664typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
1665BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
1666BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
1667} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
1668
1669/*
1670 * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
1671 */
1672
1673typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
1674BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
1675BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
1676} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
1677
1678/*
1679 * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
1680 */
1681
1682typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
1683BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
1684BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
1685} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
1686
1687/*
1688 * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
1689 */
1690
1691typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
1692BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW      = 0x00000000,
1693BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH     = 0x00000001,
1694} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
1695
1696/*
1697 * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
1698 */
1699
1700typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
1701BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
1702BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
1703} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
1704
1705/*******************************************************
1706 * LBV Enums
1707 *******************************************************/
1708
1709/*
1710 * LBV_PIXEL_DEPTH enum
1711 */
1712
1713typedef enum LBV_PIXEL_DEPTH {
1714PIXEL_DEPTH_30BPP                        = 0x00000000,
1715PIXEL_DEPTH_24BPP                        = 0x00000001,
1716PIXEL_DEPTH_18BPP                        = 0x00000002,
1717PIXEL_DEPTH_38BPP                        = 0x00000003,
1718} LBV_PIXEL_DEPTH;
1719
1720/*
1721 * LBV_PIXEL_EXPAN_MODE enum
1722 */
1723
1724typedef enum LBV_PIXEL_EXPAN_MODE {
1725PIXEL_EXPAN_MODE_ZERO_EXP                = 0x00000000,
1726PIXEL_EXPAN_MODE_DYN_EXP                 = 0x00000001,
1727} LBV_PIXEL_EXPAN_MODE;
1728
1729/*
1730 * LBV_INTERLEAVE_EN enum
1731 */
1732
1733typedef enum LBV_INTERLEAVE_EN {
1734INTERLEAVE_DIS                           = 0x00000000,
1735INTERLEAVE_EN                            = 0x00000001,
1736} LBV_INTERLEAVE_EN;
1737
1738/*
1739 * LBV_PIXEL_REDUCE_MODE enum
1740 */
1741
1742typedef enum LBV_PIXEL_REDUCE_MODE {
1743PIXEL_REDUCE_MODE_TRUNCATION             = 0x00000000,
1744PIXEL_REDUCE_MODE_ROUNDING               = 0x00000001,
1745} LBV_PIXEL_REDUCE_MODE;
1746
1747/*
1748 * LBV_DYNAMIC_PIXEL_DEPTH enum
1749 */
1750
1751typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
1752DYNAMIC_PIXEL_DEPTH_36BPP                = 0x00000000,
1753DYNAMIC_PIXEL_DEPTH_30BPP                = 0x00000001,
1754} LBV_DYNAMIC_PIXEL_DEPTH;
1755
1756/*
1757 * LBV_DITHER_EN enum
1758 */
1759
1760typedef enum LBV_DITHER_EN {
1761DITHER_DIS                               = 0x00000000,
1762DITHER_EN                                = 0x00000001,
1763} LBV_DITHER_EN;
1764
1765/*
1766 * LBV_DOWNSCALE_PREFETCH_EN enum
1767 */
1768
1769typedef enum LBV_DOWNSCALE_PREFETCH_EN {
1770DOWNSCALE_PREFETCH_DIS                   = 0x00000000,
1771DOWNSCALE_PREFETCH_EN                    = 0x00000001,
1772} LBV_DOWNSCALE_PREFETCH_EN;
1773
1774/*
1775 * LBV_MEMORY_CONFIG enum
1776 */
1777
1778typedef enum LBV_MEMORY_CONFIG {
1779MEMORY_CONFIG_0                          = 0x00000000,
1780MEMORY_CONFIG_1                          = 0x00000001,
1781MEMORY_CONFIG_2                          = 0x00000002,
1782MEMORY_CONFIG_3                          = 0x00000003,
1783} LBV_MEMORY_CONFIG;
1784
1785/*
1786 * LBV_SYNC_RESET_SEL2 enum
1787 */
1788
1789typedef enum LBV_SYNC_RESET_SEL2 {
1790SYNC_RESET_SEL2_VBLANK                   = 0x00000000,
1791SYNC_RESET_SEL2_VSYNC                    = 0x00000001,
1792} LBV_SYNC_RESET_SEL2;
1793
1794/*
1795 * LBV_SYNC_DURATION enum
1796 */
1797
1798typedef enum LBV_SYNC_DURATION {
1799SYNC_DURATION_16                         = 0x00000000,
1800SYNC_DURATION_32                         = 0x00000001,
1801SYNC_DURATION_64                         = 0x00000002,
1802SYNC_DURATION_128                        = 0x00000003,
1803} LBV_SYNC_DURATION;
1804
1805/*******************************************************
1806 * CRTC Enums
1807 *******************************************************/
1808
1809/*
1810 * CRTC_CONTROL_CRTC_START_POINT_CNTL enum
1811 */
1812
1813typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
1814CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
1815CRTC_CONTROL_CRTC_START_POINT_CNTL_DP    = 0x00000001,
1816} CRTC_CONTROL_CRTC_START_POINT_CNTL;
1817
1818/*
1819 * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
1820 */
1821
1822typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
1823CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
1824CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP   = 0x00000001,
1825} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
1826
1827/*
1828 * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
1829 */
1830
1831typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
1832CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE  = 0x00000000,
1833CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT  = 0x00000001,
1834CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED  = 0x00000002,
1835CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST  = 0x00000003,
1836} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
1837
1838/*
1839 * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
1840 */
1841
1842typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
1843CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE  = 0x00000000,
1844CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE  = 0x00000001,
1845} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
1846
1847/*
1848 * CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE enum
1849 */
1850
1851typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
1852CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE  = 0x00000000,
1853CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE  = 0x00000001,
1854} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
1855
1856/*
1857 * CRTC_CONTROL_CRTC_SOF_PULL_EN enum
1858 */
1859
1860typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
1861CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE      = 0x00000000,
1862CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE       = 0x00000001,
1863} CRTC_CONTROL_CRTC_SOF_PULL_EN;
1864
1865/*
1866 * CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL enum
1867 */
1868
1869typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
1870CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE  = 0x00000000,
1871CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE  = 0x00000001,
1872} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
1873
1874/*
1875 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL enum
1876 */
1877
1878typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
1879CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE  = 0x00000000,
1880CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE  = 0x00000001,
1881} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
1882
1883/*
1884 * CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL enum
1885 */
1886
1887typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
1888CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE  = 0x00000000,
1889CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE  = 0x00000001,
1890} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
1891
1892/*
1893 * CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN enum
1894 */
1895
1896typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
1897CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE  = 0x00000000,
1898CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE  = 0x00000001,
1899} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
1900
1901/*
1902 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC enum
1903 */
1904
1905typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
1906CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
1907CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE  = 0x00000001,
1908} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
1909
1910/*
1911 * CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT enum
1912 */
1913
1914typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
1915CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
1916CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE  = 0x00000001,
1917} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
1918
1919/*
1920 * CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
1921 */
1922
1923typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
1924CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
1925CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE  = 0x00000001,
1926} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
1927
1928/*
1929 * CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR enum
1930 */
1931
1932typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
1933CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
1934CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE  = 0x00000001,
1935} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
1936
1937/*
1938 * CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL enum
1939 */
1940
1941typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
1942CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE  = 0x00000000,
1943CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE  = 0x00000001,
1944} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
1945
1946/*
1947 * CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN enum
1948 */
1949
1950typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
1951CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE  = 0x00000000,
1952CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE  = 0x00000001,
1953} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
1954
1955/*
1956 * CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT enum
1957 */
1958
1959typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
1960CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER  = 0x00000001,
1961CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER  = 0x00000002,
1962CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF  = 0x00000005,
1963CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE  = 0x00000006,
1964CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA  = 0x00000007,
1965CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA  = 0x00000008,
1966CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB  = 0x00000009,
1967CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB  = 0x0000000a,
1968CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1  = 0x0000000b,
1969CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2  = 0x0000000c,
1970CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD  = 0x0000000d,
1971CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC  = 0x0000000e,
1972CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0  = 0x00000010,
1973CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1  = 0x00000011,
1974CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2  = 0x00000012,
1975CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON  = 0x00000013,
1976CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA  = 0x00000014,
1977CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB  = 0x00000015,
1978CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW  = 0x00000016,
1979CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW  = 0x00000017,
1980} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
1981
1982/*
1983 * CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT enum
1984 */
1985
1986typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
1987CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE  = 0x00000001,
1988CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA  = 0x00000002,
1989CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB  = 0x00000003,
1990CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA  = 0x00000004,
1991CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB  = 0x00000005,
1992CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO  = 0x00000006,
1993CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC  = 0x00000007,
1994} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
1995
1996/*
1997 * CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN enum
1998 */
1999
2000typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {

2001CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
2002CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
2003} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
2004
2005/*
2006 * CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR enum
2007 */
2008
2009typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
2010CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE   = 0x00000000,
2011CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE    = 0x00000001,
2012} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
2013
2014/*
2015 * CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT enum
2016 */
2017
2018typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
2019CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER  = 0x00000001,
2020CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER  = 0x00000002,
2021CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF  = 0x00000005,
2022CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE  = 0x00000006,
2023CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA  = 0x00000007,
2024CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA  = 0x00000008,
2025CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB  = 0x00000009,
2026CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB  = 0x0000000a,
2027CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1  = 0x0000000b,
2028CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2  = 0x0000000c,
2029CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD  = 0x0000000d,
2030CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC  = 0x0000000e,
2031CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0  = 0x00000010,
2032CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1  = 0x00000011,
2033CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2  = 0x00000012,
2034CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON  = 0x00000013,
2035CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA  = 0x00000014,
2036CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB  = 0x00000015,
2037CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW  = 0x00000016,
2038CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW  = 0x00000017,
2039} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
2040
2041/*
2042 * CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT enum
2043 */
2044
2045typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
2046CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE  = 0x00000001,
2047CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA  = 0x00000002,
2048CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB  = 0x00000003,
2049CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA  = 0x00000004,
2050CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB  = 0x00000005,
2051CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO  = 0x00000006,
2052CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC  = 0x00000007,
2053} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
2054
2055/*
2056 * CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN enum
2057 */
2058
2059typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
2060CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE  = 0x00000000,
2061CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE  = 0x00000001,
2062} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
2063
2064/*
2065 * CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR enum
2066 */
2067
2068typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
2069CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE   = 0x00000000,
2070CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE    = 0x00000001,
2071} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
2072
2073/*
2074 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE enum
2075 */
2076
2077typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
2078CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE  = 0x00000000,
2079CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT  = 0x00000001,
2080CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT  = 0x00000002,
2081CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED  = 0x00000003,
2082} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
2083
2084/*
2085 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK enum
2086 */
2087
2088typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
2089CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE  = 0x00000000,
2090CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE  = 0x00000001,
2091} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
2092
2093/*
2094 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL enum
2095 */
2096
2097typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
2098CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE  = 0x00000000,
2099CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE  = 0x00000001,
2100} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
2101
2102/*
2103 * CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR enum
2104 */
2105
2106typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
2107CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
2108CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE  = 0x00000001,
2109} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
2110
2111/*
2112 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT enum
2113 */
2114
2115typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
2116CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0  = 0x00000000,
2117CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF  = 0x00000001,
2118CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE  = 0x00000002,
2119CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1  = 0x00000003,
2120CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2  = 0x00000004,
2121CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA  = 0x00000005,
2122CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK  = 0x00000006,
2123CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA  = 0x00000007,
2124CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK  = 0x00000008,
2125CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK  = 0x00000009,
2126CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL  = 0x0000000a,
2127CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1  = 0x0000000b,
2128CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB  = 0x0000000c,
2129CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA  = 0x0000000d,
2130CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD  = 0x0000000e,
2131CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC  = 0x0000000f,
2132} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
2133
2134/*
2135 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY enum
2136 */
2137
2138typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
2139CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE  = 0x00000000,
2140CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE  = 0x00000001,
2141} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
2142
2143/*
2144 * CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY enum
2145 */
2146
2147typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
2148CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE  = 0x00000000,
2149CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE  = 0x00000001,
2150} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
2151
2152/*
2153 * CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE enum
2154 */
2155
2156typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
2157CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO  = 0x00000000,
2158CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT  = 0x00000001,
2159CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT  = 0x00000002,
2160CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED  = 0x00000003,
2161} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
2162
2163/*
2164 * CRTC_CONTROL_CRTC_MASTER_EN enum
2165 */
2166
2167typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
2168CRTC_CONTROL_CRTC_MASTER_EN_FALSE        = 0x00000000,
2169CRTC_CONTROL_CRTC_MASTER_EN_TRUE         = 0x00000001,
2170} CRTC_CONTROL_CRTC_MASTER_EN;
2171
2172/*
2173 * CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN enum
2174 */
2175
2176typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
2177CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE  = 0x00000000,
2178CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE  = 0x00000001,
2179} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
2180
2181/*
2182 * CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE enum
2183 */
2184
2185typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
2186CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE  = 0x00000000,
2187CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE  = 0x00000001,
2188} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
2189
2190/*
2191 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE enum
2192 */
2193
2194typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
2195CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE  = 0x00000000,
2196CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE  = 0x00000001,
2197} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
2198
2199/*
2200 * CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD enum
2201 */
2202
2203typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
2204CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT  = 0x00000000,
2205CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD  = 0x00000001,
2206CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN  = 0x00000002,
2207CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2  = 0x00000003,
2208} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
2209
2210/*
2211 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY enum
2212 */
2213
2214typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
2215CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE  = 0x00000000,
2216CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE  = 0x00000001,
2217} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
2218
2219/*
2220 * CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT enum
2221 */
2222
2223typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
2224CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE  = 0x00000000,
2225CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE  = 0x00000001,
2226} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
2227
2228/*
2229 * CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN enum
2230 */
2231
2232typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
2233CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE  = 0x00000000,
2234CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE  = 0x00000001,
2235} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
2236
2237/*
2238 * CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE enum
2239 */
2240
2241typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
2242CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
2243CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE  = 0x00000001,
2244} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
2245
2246/*
2247 * CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR enum
2248 */
2249
2250typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
2251CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
2252CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE  = 0x00000001,
2253} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
2254
2255/*
2256 * CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE enum
2257 */
2258
2259typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
2260CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE  = 0x00000000,
2261CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA  = 0x00000001,
2262CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB  = 0x00000002,
2263CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED  = 0x00000003,
2264} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
2265
2266/*
2267 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY enum
2268 */
2269
2270typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
2271CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE  = 0x00000000,
2272CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE  = 0x00000001,
2273} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
2274
2275/*
2276 * CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY enum
2277 */
2278
2279typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
2280CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE  = 0x00000000,
2281CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE  = 0x00000001,
2282} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
2283
2284/*
2285 * CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY enum
2286 */
2287
2288typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
2289CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE  = 0x00000000,
2290CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE  = 0x00000001,
2291} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
2292
2293/*
2294 * CRTC_STEREO_CONTROL_CRTC_STEREO_EN enum
2295 */
2296
2297typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
2298CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE  = 0x00000000,
2299CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE  = 0x00000001,
2300} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
2301
2302/*
2303 * CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR enum
2304 */
2305
2306typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
2307CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE = 0x00000000,
2308CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE  = 0x00000001,
2309} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
2310
2311/*
2312 * CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL enum
2313 */
2314
2315typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
2316CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE  = 0x00000000,
2317CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA  = 0x00000001,
2318CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB  = 0x00000002,
2319CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED  = 0x00000003,
2320} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
2321
2322/*
2323 * CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY enum
2324 */
2325
2326typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
2327CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
2328CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE  = 0x00000001,
2329} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
2330
2331/*
2332 * CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY enum
2333 */
2334
2335typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
2336CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
2337CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE  = 0x00000001,
2338} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
2339
2340/*
2341 * CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN enum
2342 */
2343
2344typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
2345CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE  = 0x00000000,
2346CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE  = 0x00000001,
2347} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
2348
2349/*
2350 * CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN enum
2351 */
2352
2353typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
2354CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE  = 0x00000000,
2355CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE  = 0x00000001,
2356} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
2357
2358/*
2359 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK enum
2360 */
2361
2362typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
2363CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE  = 0x00000000,
2364CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE  = 0x00000001,
2365} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
2366
2367/*
2368 * CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE enum
2369 */
2370
2371typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
2372CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE  = 0x00000000,
2373CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE  = 0x00000001,
2374} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
2375
2376/*
2377 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK enum
2378 */
2379
2380typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
2381CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE  = 0x00000000,
2382CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE  = 0x00000001,
2383} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
2384
2385/*
2386 * CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE enum
2387 */
2388
2389typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
2390CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE  = 0x00000000,
2391CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE  = 0x00000001,
2392} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
2393
2394/*
2395 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK enum
2396 */
2397
2398typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
2399CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE  = 0x00000000,
2400CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE  = 0x00000001,
2401} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
2402
2403/*
2404 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE enum
2405 */
2406
2407typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
2408CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE  = 0x00000000,
2409CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE  = 0x00000001,
2410} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
2411
2412/*
2413 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
2414 */
2415
2416typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
2417CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE  = 0x00000000,
2418CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE  = 0x00000001,
2419} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
2420
2421/*
2422 * CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
2423 */
2424
2425typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
2426CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE  = 0x00000000,
2427CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE  = 0x00000001,
2428} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
2429
2430/*
2431 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK enum
2432 */
2433
2434typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
2435CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE  = 0x00000000,
2436CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE  = 0x00000001,
2437} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
2438
2439/*
2440 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE enum
2441 */
2442
2443typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
2444CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE  = 0x00000000,
2445CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE  = 0x00000001,
2446} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
2447
2448/*
2449 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK enum
2450 */
2451
2452typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
2453CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE  = 0x00000000,
2454CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE  = 0x00000001,
2455} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
2456
2457/*
2458 * CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE enum
2459 */
2460
2461typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
2462CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE  = 0x00000000,
2463CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE  = 0x00000001,
2464} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
2465
2466/*
2467 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK enum
2468 */
2469
2470typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
2471CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE  = 0x00000000,
2472CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE  = 0x00000001,
2473} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
2474
2475/*
2476 * CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE enum
2477 */
2478
2479typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
2480CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE  = 0x00000000,
2481CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE  = 0x00000001,
2482} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
2483
2484/*
2485 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK enum
2486 */
2487
2488typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
2489CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE  = 0x00000000,
2490CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE  = 0x00000001,
2491} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
2492
2493/*
2494 * CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE enum
2495 */
2496
2497typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
2498CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE  = 0x00000000,
2499CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE  = 0x00000001,
2500} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
2501
2502/*
2503 * CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK enum
2504 */
2505
2506typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
2507CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE  = 0x00000000,
2508CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE   = 0x00000001,
2509} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
2510
2511/*
2512 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY enum
2513 */
2514
2515typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
2516CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE  = 0x00000000,
2517CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE  = 0x00000001,
2518} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
2519
2520/*
2521 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN enum
2522 */
2523
2524typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
2525CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE  = 0x00000000,
2526CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE  = 0x00000001,
2527} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
2528
2529/*
2530 * CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE enum
2531 */
2532
2533typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE {
2534CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_0  = 0x00000000,
2535CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE_1  = 0x00000001,
2536} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_RANGE_TIMING_DBUF_UPDATE_MODE;
2537
2538/*
2539 * CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE enum
2540 */
2541
2542typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
2543CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE  = 0x00000000,
2544CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE  = 0x00000001,
2545} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
2546
2547/*
2548 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN enum
2549 */
2550
2551typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
2552CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE  = 0x00000000,
2553CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE  = 0x00000001,
2554} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
2555
2556/*
2557 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE enum
2558 */
2559
2560typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
2561CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB  = 0x00000000,
2562CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601  = 0x00000001,
2563CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709  = 0x00000002,
2564CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS  = 0x00000003,
2565CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS  = 0x00000004,
2566CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB  = 0x00000005,
2567CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB  = 0x00000006,
2568CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS  = 0x00000007,
2569} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
2570
2571/*
2572 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE enum
2573 */
2574
2575typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
2576CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE  = 0x00000000,
2577CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE  = 0x00000001,
2578} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
2579
2580/*
2581 * CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT enum
2582 */
2583
2584typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
2585CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC  = 0x00000000,
2586CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC  = 0x00000001,
2587CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC  = 0x00000002,
2588CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED  = 0x00000003,
2589} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
2590
2591/*
2592 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
2593 */
2594
2595typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
2596MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
2597MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
2598} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
2599
2600/*
2601 * MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK enum
2602 */
2603
2604typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
2605MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE  = 0x00000000,
2606MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE  = 0x00000001,
2607} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
2608
2609/*
2610 * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
2611 */
2612
2613typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
2614MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE  = 0x00000000,
2615MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE  = 0x00000001,
2616} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
2617
2618/*
2619 * MASTER_UPDATE_MODE_MASTER_UPDATE_MODE enum
2620 */
2621
2622typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
2623MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN  = 0x00000000,
2624MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA  = 0x00000001,
2625MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA  = 0x00000002,
2626MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE  = 0x00000003,
2627} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
2628
2629/*
2630 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
2631 */
2632
2633typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
2634MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH  = 0x00000000,
2635MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN  = 0x00000001,
2636MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD  = 0x00000002,
2637MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED  = 0x00000003,
2638} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
2639
2640/*
2641 * CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE enum
2642 */
2643
2644typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
2645CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE  = 0x00000000,
2646CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG  = 0x00000001,
2647CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL  = 0x00000002,
2648} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
2649
2650/*
2651 * CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR enum
2652 */
2653
2654typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
2655CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE = 0x00000000,
2656CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE  = 0x00000001,
2657} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
2658
2659/*
2660 * CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR enum
2661 */
2662
2663typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
2664CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
2665CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE  = 0x00000001,
2666} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
2667
2668/*
2669 * CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR enum
2670 */
2671
2672typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
2673CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
2674CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE  = 0x00000001,
2675} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
2676
2677/*
2678 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
2679 */
2680
2681typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
2682CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE  = 0x00000000,
2683CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE  = 0x00000001,
2684} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
2685
2686/*
2687 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE enum
2688 */
2689
2690typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
2691CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
2692CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE  = 0x00000001,
2693} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
2694
2695/*
2696 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR enum
2697 */
2698
2699typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
2700CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
2701CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE  = 0x00000001,
2702} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
2703
2704/*
2705 * CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE enum
2706 */
2707
2708typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
2709CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE  = 0x00000000,
2710CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE  = 0x00000001,
2711} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
2712
2713/*
2714 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR enum
2715 */
2716
2717typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
2718CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
2719CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE  = 0x00000001,
2720} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
2721
2722/*
2723 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE enum
2724 */
2725
2726typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
2727CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
2728CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE  = 0x00000001,
2729} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
2730
2731/*
2732 * CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE enum
2733 */
2734
2735typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
2736CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE  = 0x00000000,
2737CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE  = 0x00000001,
2738} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
2739
2740/*
2741 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR enum
2742 */
2743
2744typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
2745CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
2746CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE  = 0x00000001,
2747} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
2748
2749/*
2750 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE enum
2751 */
2752
2753typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
2754CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
2755CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE  = 0x00000001,
2756} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
2757
2758/*
2759 * CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE enum
2760 */
2761
2762typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
2763CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE  = 0x00000000,
2764CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE  = 0x00000001,
2765} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
2766
2767/*
2768 * CRTC_CRC_CNTL_CRTC_CRC_EN enum
2769 */
2770
2771typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
2772CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE          = 0x00000000,
2773CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE           = 0x00000001,
2774} CRTC_CRC_CNTL_CRTC_CRC_EN;
2775
2776/*
2777 * CRTC_CRC_CNTL_CRTC_CRC_CONT_EN enum
2778 */
2779
2780typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
2781CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE     = 0x00000000,
2782CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE      = 0x00000001,
2783} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
2784
2785/*
2786 * CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE enum
2787 */
2788
2789typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
2790CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT  = 0x00000000,
2791CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT  = 0x00000001,
2792CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES  = 0x00000002,
2793CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS  = 0x00000003,
2794} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
2795
2796/*
2797 * CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE enum
2798 */
2799
2800typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
2801CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP  = 0x00000000,
2802CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM  = 0x00000001,
2803CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
2804CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD  = 0x00000003,
2805} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
2806
2807/*
2808 * CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS enum
2809 */
2810
2811typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
2812CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
2813CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE  = 0x00000001,
2814} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
2815
2816/*
2817 * CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT enum
2818 */
2819
2820typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
2821CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB  = 0x00000000,
2822CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B  = 0x00000001,
2823CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB  = 0x00000002,
2824CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B  = 0x00000003,
2825CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB  = 0x00000004,
2826CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B  = 0x00000005,
2827CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB  = 0x00000006,
2828CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B  = 0x00000007,
2829} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
2830
2831/*
2832 * CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT enum
2833 */
2834
2835typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
2836CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB  = 0x00000000,
2837CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B  = 0x00000001,
2838CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB  = 0x00000002,
2839CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B  = 0x00000003,
2840CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB  = 0x00000004,
2841CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B  = 0x00000005,
2842CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB  = 0x00000006,
2843CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B  = 0x00000007,
2844} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
2845
2846/*
2847 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE enum
2848 */
2849
2850typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE {
2851CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_DISABLE  = 0x00000000,
2852CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_ONESHOT  = 0x00000001,
2853CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_CONTINUOUS  = 0x00000002,
2854CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE_RESERVED  = 0x00000003,
2855} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_ENABLE;
2856
2857/*
2858 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
2859 */
2860
2861typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
2862CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE  = 0x00000000,
2863CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE  = 0x00000001,
2864} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
2865
2866/*
2867 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
2868 */
2869
2870typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
2871CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE  = 0x00000000,
2872CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE  = 0x00000001,
2873} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
2874
2875/*
2876 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
2877 */
2878
2879typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
2880CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel  = 0x00000000,
2881CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel  = 0x00000001,
2882CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel  = 0x00000002,
2883CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel  = 0x00000003,
2884} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
2885
2886/*
2887 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE enum
2888 */
2889
2890typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE {
2891CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE  = 0x00000000,
2892CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE  = 0x00000001,
2893} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE;
2894
2895/*
2896 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE enum
2897 */
2898
2899typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE {
2900CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
2901CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE  = 0x00000001,
2902} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE;
2903
2904/*
2905 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY enum
2906 */
2907
2908typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY {
2909CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE  = 0x00000000,
2910CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE  = 0x00000001,
2911} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY;
2912
2913/*
2914 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY enum
2915 */
2916
2917typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY {
2918CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE  = 0x00000000,
2919CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE  = 0x00000001,
2920} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY;
2921
2922/*
2923 * CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE enum
2924 */
2925
2926typedef enum CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE {
2927CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE  = 0x00000000,
2928CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE  = 0x00000001,
2929} CRTC_EXT_TIMING_SYNC_CONTROL_CRTC_EXT_TIMING_SYNC_INTERLACE_MODE;
2930
2931/*
2932 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
2933 */
2934
2935typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
2936CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE  = 0x00000000,
2937CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE  = 0x00000001,
2938} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
2939
2940/*
2941 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR enum
2942 */
2943
2944typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR {
2945CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
2946CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE  = 0x00000001,
2947} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_CLEAR;
2948
2949/*
2950 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
2951 */
2952
2953typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE {
2954CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE  = 0x00000000,
2955CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE  = 0x00000001,
2956} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE;
2957
2958/*
2959 * CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
2960 */
2961
2962typedef enum CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
2963CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME  = 0x00000000,
2964CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME  = 0x00000001,
2965CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME  = 0x00000002,
2966CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME  = 0x00000003,
2967CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME  = 0x00000004,
2968CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME  = 0x00000005,
2969CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME  = 0x00000006,
2970CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME  = 0x00000007,
2971} CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
2972
2973/*
2974 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE enum
2975 */
2976
2977typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE {
2978CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_FALSE  = 0x00000000,
2979CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE_TRUE  = 0x00000001,
2980} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_ENABLE;
2981
2982/*
2983 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR enum
2984 */
2985
2986typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR {
2987CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
2988CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR_TRUE  = 0x00000001,
2989} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_CLEAR;
2990
2991/*
2992 * CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE enum
2993 */
2994
2995typedef enum CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE {
2996CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_FALSE  = 0x00000000,
2997CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE_TRUE  = 0x00000001,
2998} CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_INT_TYPE;
2999
3000/*

3001 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
3002 */
3003
3004typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
3005CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE  = 0x00000000,
3006CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE  = 0x00000001,
3007} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
3008
3009/*
3010 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
3011 */
3012
3013typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR {
3014CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
3015CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE  = 0x00000001,
3016} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR;
3017
3018/*
3019 * CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
3020 */
3021
3022typedef enum CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
3023CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE  = 0x00000000,
3024CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE  = 0x00000001,
3025} CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
3026
3027/*
3028 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE enum
3029 */
3030
3031typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
3032CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE  = 0x00000000,
3033CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE  = 0x00000001,
3034} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
3035
3036/*
3037 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR enum
3038 */
3039
3040typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
3041CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
3042CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE  = 0x00000001,
3043} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
3044
3045/*
3046 * CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE enum
3047 */
3048
3049typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
3050CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE  = 0x00000000,
3051CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE  = 0x00000001,
3052} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
3053
3054/*
3055 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE enum
3056 */
3057
3058typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE {
3059CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_FALSE  = 0x00000000,
3060CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_TRUE  = 0x00000001,
3061} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE;
3062
3063/*
3064 * CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE enum
3065 */
3066
3067typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE {
3068CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_OFF  = 0x00000000,
3069CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE_ON  = 0x00000001,
3070} CRTC_STATIC_SCREEN_CONTROL_CRTC_STATIC_SCREEN_OVERRIDE_VALUE;
3071
3072/*
3073 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN enum
3074 */
3075
3076typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
3077CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE  = 0x00000000,
3078CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE  = 0x00000001,
3079} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
3080
3081/*
3082 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB enum
3083 */
3084
3085typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
3086CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE  = 0x00000000,
3087CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE  = 0x00000001,
3088} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
3089
3090/*
3091 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE enum
3092 */
3093
3094typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
3095CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH  = 0x00000000,
3096CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE  = 0x00000001,
3097CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE  = 0x00000002,
3098CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED  = 0x00000003,
3099} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
3100
3101/*
3102 * CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR enum
3103 */
3104
3105typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
3106CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE  = 0x00000000,
3107CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE  = 0x00000001,
3108} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
3109
3110/*
3111 * CRTC_V_SYNC_A_POL enum
3112 */
3113
3114typedef enum CRTC_V_SYNC_A_POL {
3115CRTC_V_SYNC_A_POL_HIGH                   = 0x00000000,
3116CRTC_V_SYNC_A_POL_LOW                    = 0x00000001,
3117} CRTC_V_SYNC_A_POL;
3118
3119/*
3120 * CRTC_H_SYNC_A_POL enum
3121 */
3122
3123typedef enum CRTC_H_SYNC_A_POL {
3124CRTC_H_SYNC_A_POL_HIGH                   = 0x00000000,
3125CRTC_H_SYNC_A_POL_LOW                    = 0x00000001,
3126} CRTC_H_SYNC_A_POL;
3127
3128/*
3129 * CRTC_HORZ_REPETITION_COUNT enum
3130 */
3131
3132typedef enum CRTC_HORZ_REPETITION_COUNT {
3133CRTC_HORZ_REPETITION_COUNT_0             = 0x00000000,
3134CRTC_HORZ_REPETITION_COUNT_1             = 0x00000001,
3135CRTC_HORZ_REPETITION_COUNT_2             = 0x00000002,
3136CRTC_HORZ_REPETITION_COUNT_3             = 0x00000003,
3137CRTC_HORZ_REPETITION_COUNT_4             = 0x00000004,
3138CRTC_HORZ_REPETITION_COUNT_5             = 0x00000005,
3139CRTC_HORZ_REPETITION_COUNT_6             = 0x00000006,
3140CRTC_HORZ_REPETITION_COUNT_7             = 0x00000007,
3141CRTC_HORZ_REPETITION_COUNT_8             = 0x00000008,
3142CRTC_HORZ_REPETITION_COUNT_9             = 0x00000009,
3143CRTC_HORZ_REPETITION_COUNT_10            = 0x0000000a,
3144CRTC_HORZ_REPETITION_COUNT_11            = 0x0000000b,
3145CRTC_HORZ_REPETITION_COUNT_12            = 0x0000000c,
3146CRTC_HORZ_REPETITION_COUNT_13            = 0x0000000d,
3147CRTC_HORZ_REPETITION_COUNT_14            = 0x0000000e,
3148CRTC_HORZ_REPETITION_COUNT_15            = 0x0000000f,
3149} CRTC_HORZ_REPETITION_COUNT;
3150
3151/*
3152 * CRTC_DRR_MODE_DBUF_UPDATE_MODE enum
3153 */
3154
3155typedef enum CRTC_DRR_MODE_DBUF_UPDATE_MODE {
3156CRTC_DRR_MODE_DBUF_UPDATE_MODE_00_IMMEDIATE  = 0x00000000,
3157CRTC_DRR_MODE_DBUF_UPDATE_MODE_01_MANUAL  = 0x00000001,
3158CRTC_DRR_MODE_DBUF_UPDATE_MODE_10_DBUF   = 0x00000002,
3159CRTC_DRR_MODE_DBUF_UPDATE_MODE_11_SYNCED_DBUF  = 0x00000003,
3160} CRTC_DRR_MODE_DBUF_UPDATE_MODE;
3161
3162/*******************************************************
3163 * FMT Enums
3164 *******************************************************/
3165
3166/*
3167 * FMT_CONTROL_PIXEL_ENCODING enum
3168 */
3169
3170typedef enum FMT_CONTROL_PIXEL_ENCODING {
3171FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444  = 0x00000000,
3172FMT_CONTROL_PIXEL_ENCODING_YCBCR422      = 0x00000001,
3173FMT_CONTROL_PIXEL_ENCODING_YCBCR420      = 0x00000002,
3174FMT_CONTROL_PIXEL_ENCODING_RESERVED      = 0x00000003,
3175} FMT_CONTROL_PIXEL_ENCODING;
3176
3177/*
3178 * FMT_CONTROL_SUBSAMPLING_MODE enum
3179 */
3180
3181typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3182FMT_CONTROL_SUBSAMPLING_MODE_DROP        = 0x00000000,
3183FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE     = 0x00000001,
3184FMT_CONTROL_SUBSAMPLING_MOME_3_TAP       = 0x00000002,
3185FMT_CONTROL_SUBSAMPLING_MOME_RESERVED    = 0x00000003,
3186} FMT_CONTROL_SUBSAMPLING_MODE;
3187
3188/*
3189 * FMT_CONTROL_SUBSAMPLING_ORDER enum
3190 */
3191
3192typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3193FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR  = 0x00000000,
3194FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB  = 0x00000001,
3195} FMT_CONTROL_SUBSAMPLING_ORDER;
3196
3197/*
3198 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3199 */
3200
3201typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3202FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE  = 0x00000000,
3203FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE  = 0x00000001,
3204} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3205
3206/*
3207 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3208 */
3209
3210typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3211FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION  = 0x00000000,
3212FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING  = 0x00000001,
3213} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3214
3215/*
3216 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3217 */
3218
3219typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3220FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP  = 0x00000000,
3221FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP  = 0x00000001,
3222FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP  = 0x00000002,
3223} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3224
3225/*
3226 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3227 */
3228
3229typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3230FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP  = 0x00000000,
3231FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP  = 0x00000001,
3232FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP  = 0x00000002,
3233} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3234
3235/*
3236 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3237 */
3238
3239typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3240FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP  = 0x00000000,
3241FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP  = 0x00000001,
3242FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP  = 0x00000002,
3243} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3244
3245/*
3246 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3247 */
3248
3249typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3250FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2  = 0x00000000,
3251FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4  = 0x00000001,
3252} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3253
3254/*
3255 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3256 */
3257
3258typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3259FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei       = 0x00000000,
3260FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi       = 0x00000001,
3261FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi       = 0x00000002,
3262FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED  = 0x00000003,
3263} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3264
3265/*
3266 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3267 */
3268
3269typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3270FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A        = 0x00000000,
3271FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B        = 0x00000001,
3272FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C        = 0x00000002,
3273FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D        = 0x00000003,
3274} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3275
3276/*
3277 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3278 */
3279
3280typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3281FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E        = 0x00000000,
3282FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F        = 0x00000001,
3283FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G        = 0x00000002,
3284FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED  = 0x00000003,
3285} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3286
3287/*
3288 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT enum
3289 */
3290
3291typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3292FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN  = 0x00000000,
3293FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN  = 0x00000001,
3294} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3295
3296/*
3297 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3298 */
3299
3300typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3301FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR  = 0x00000000,
3302FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB  = 0x00000001,
3303} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3304
3305/*
3306 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3307 */
3308
3309typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3310FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC         = 0x00000000,
3311FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC         = 0x00000001,
3312FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC        = 0x00000002,
3313FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC        = 0x00000003,
3314FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1    = 0x00000004,
3315FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2    = 0x00000005,
3316FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3    = 0x00000006,
3317FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE  = 0x00000007,
3318} FMT_CLAMP_CNTL_COLOR_FORMAT;
3319
3320/*
3321 * FMT_CRC_CNTL_CONT_EN enum
3322 */
3323
3324typedef enum FMT_CRC_CNTL_CONT_EN {
3325FMT_CRC_CNTL_CONT_EN_ONE_SHOT            = 0x00000000,
3326FMT_CRC_CNTL_CONT_EN_CONT                = 0x00000001,
3327} FMT_CRC_CNTL_CONT_EN;
3328
3329/*
3330 * FMT_CRC_CNTL_INCLUDE_OVERSCAN enum
3331 */
3332
3333typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3334FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE  = 0x00000000,
3335FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE    = 0x00000001,
3336} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3337
3338/*
3339 * FMT_CRC_CNTL_ONLY_BLANKB enum
3340 */
3341
3342typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3343FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD    = 0x00000000,
3344FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK       = 0x00000001,
3345} FMT_CRC_CNTL_ONLY_BLANKB;
3346
3347/*
3348 * FMT_CRC_CNTL_PSR_MODE_ENABLE enum
3349 */
3350
3351typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3352FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL      = 0x00000000,
3353FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC  = 0x00000001,
3354} FMT_CRC_CNTL_PSR_MODE_ENABLE;
3355
3356/*
3357 * FMT_CRC_CNTL_INTERLACE_MODE enum
3358 */
3359
3360typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3361FMT_CRC_CNTL_INTERLACE_MODE_TOP          = 0x00000000,
3362FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM       = 0x00000001,
3363FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM  = 0x00000002,
3364FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH    = 0x00000003,
3365} FMT_CRC_CNTL_INTERLACE_MODE;
3366
3367/*
3368 * FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE enum
3369 */
3370
3371typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3372FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL     = 0x00000000,
3373FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN  = 0x00000001,
3374} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3375
3376/*
3377 * FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT enum
3378 */
3379
3380typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3381FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN    = 0x00000000,
3382FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD     = 0x00000001,
3383} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3384
3385/*
3386 * FMT_DEBUG_CNTL_COLOR_SELECT enum
3387 */
3388
3389typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3390FMT_DEBUG_CNTL_COLOR_SELECT_BLUE         = 0x00000000,
3391FMT_DEBUG_CNTL_COLOR_SELECT_GREEN        = 0x00000001,
3392FMT_DEBUG_CNTL_COLOR_SELECT_RED1         = 0x00000002,
3393FMT_DEBUG_CNTL_COLOR_SELECT_RED2         = 0x00000003,
3394} FMT_DEBUG_CNTL_COLOR_SELECT;
3395
3396/*
3397 * FMT_SPATIAL_DITHER_MODE enum
3398 */
3399
3400typedef enum FMT_SPATIAL_DITHER_MODE {
3401FMT_SPATIAL_DITHER_MODE_0                = 0x00000000,
3402FMT_SPATIAL_DITHER_MODE_1                = 0x00000001,
3403FMT_SPATIAL_DITHER_MODE_2                = 0x00000002,
3404FMT_SPATIAL_DITHER_MODE_3                = 0x00000003,
3405} FMT_SPATIAL_DITHER_MODE;
3406
3407/*
3408 * FMT_STEREOSYNC_OVR_POL enum
3409 */
3410
3411typedef enum FMT_STEREOSYNC_OVR_POL {
3412FMT_STEREOSYNC_OVR_POL_INVERTED          = 0x00000000,
3413FMT_STEREOSYNC_OVR_POL_NOT_INVERTED      = 0x00000001,
3414} FMT_STEREOSYNC_OVR_POL;
3415
3416/*
3417 * FMT_DYNAMIC_EXP_MODE enum
3418 */
3419
3420typedef enum FMT_DYNAMIC_EXP_MODE {
3421FMT_DYNAMIC_EXP_MODE_10to12              = 0x00000000,
3422FMT_DYNAMIC_EXP_MODE_8to12               = 0x00000001,
3423} FMT_DYNAMIC_EXP_MODE;
3424
3425/*******************************************************
3426 * HPD Enums
3427 *******************************************************/
3428
3429/*
3430 * HPD_INT_CONTROL_ACK enum
3431 */
3432
3433typedef enum HPD_INT_CONTROL_ACK {
3434HPD_INT_CONTROL_ACK_0                    = 0x00000000,
3435HPD_INT_CONTROL_ACK_1                    = 0x00000001,
3436} HPD_INT_CONTROL_ACK;
3437
3438/*
3439 * HPD_INT_CONTROL_POLARITY enum
3440 */
3441
3442typedef enum HPD_INT_CONTROL_POLARITY {
3443HPD_INT_CONTROL_GEN_INT_ON_DISCON        = 0x00000000,
3444HPD_INT_CONTROL_GEN_INT_ON_CON           = 0x00000001,
3445} HPD_INT_CONTROL_POLARITY;
3446
3447/*
3448 * HPD_INT_CONTROL_RX_INT_ACK enum
3449 */
3450
3451typedef enum HPD_INT_CONTROL_RX_INT_ACK {
3452HPD_INT_CONTROL_RX_INT_ACK_0             = 0x00000000,
3453HPD_INT_CONTROL_RX_INT_ACK_1             = 0x00000001,
3454} HPD_INT_CONTROL_RX_INT_ACK;
3455
3456/*******************************************************
3457 * LB Enums
3458 *******************************************************/
3459
3460/*
3461 * LB_DATA_FORMAT_PIXEL_DEPTH enum
3462 */
3463
3464typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3465LB_DATA_FORMAT_PIXEL_DEPTH_30BPP         = 0x00000000,
3466LB_DATA_FORMAT_PIXEL_DEPTH_24BPP         = 0x00000001,
3467LB_DATA_FORMAT_PIXEL_DEPTH_18BPP         = 0x00000002,
3468LB_DATA_FORMAT_PIXEL_DEPTH_36BPP         = 0x00000003,
3469} LB_DATA_FORMAT_PIXEL_DEPTH;
3470
3471/*
3472 * LB_DATA_FORMAT_PIXEL_EXPAN_MODE enum
3473 */
3474
3475typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3476LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION = 0x00000000,
3477LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION = 0x00000001,
3478} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3479
3480/*
3481 * LB_DATA_FORMAT_PIXEL_REDUCE_MODE enum
3482 */
3483
3484typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3485LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION = 0x00000000,
3486LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING = 0x00000001,
3487} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3488
3489/*
3490 * LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH enum
3491 */
3492
3493typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3494LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP = 0x00000000,
3495LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP = 0x00000001,
3496} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3497
3498/*
3499 * LB_DATA_FORMAT_INTERLEAVE_EN enum
3500 */
3501
3502typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3503LB_DATA_FORMAT_INTERLEAVE_DISABLE        = 0x00000000,
3504LB_DATA_FORMAT_INTERLEAVE_ENABLE         = 0x00000001,
3505} LB_DATA_FORMAT_INTERLEAVE_EN;
3506
3507/*
3508 * LB_DATA_FORMAT_REQUEST_MODE enum
3509 */
3510
3511typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3512LB_DATA_FORMAT_REQUEST_MODE_NORMAL       = 0x00000000,
3513LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE  = 0x00000001,
3514} LB_DATA_FORMAT_REQUEST_MODE;
3515
3516/*
3517 * LB_DATA_FORMAT_ALPHA_EN enum
3518 */
3519
3520typedef enum LB_DATA_FORMAT_ALPHA_EN {
3521LB_DATA_FORMAT_ALPHA_DISABLE             = 0x00000000,
3522LB_DATA_FORMAT_ALPHA_ENABLE              = 0x00000001,
3523} LB_DATA_FORMAT_ALPHA_EN;
3524
3525/*
3526 * LB_VLINE_START_END_VLINE_INV enum
3527 */
3528
3529typedef enum LB_VLINE_START_END_VLINE_INV {
3530LB_VLINE_START_END_VLINE_NORMAL          = 0x00000000,
3531LB_VLINE_START_END_VLINE_INVERSE         = 0x00000001,
3532} LB_VLINE_START_END_VLINE_INV;
3533
3534/*
3535 * LB_VLINE2_START_END_VLINE2_INV enum
3536 */
3537
3538typedef enum LB_VLINE2_START_END_VLINE2_INV {
3539LB_VLINE2_START_END_VLINE2_NORMAL        = 0x00000000,
3540LB_VLINE2_START_END_VLINE2_INVERSE       = 0x00000001,
3541} LB_VLINE2_START_END_VLINE2_INV;
3542
3543/*
3544 * LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK enum
3545 */
3546
3547typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3548LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE = 0x00000000,
3549LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE = 0x00000001,
3550} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3551
3552/*
3553 * LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK enum
3554 */
3555
3556typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3557LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE = 0x00000000,
3558LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE = 0x00000001,
3559} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3560
3561/*
3562 * LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK enum
3563 */
3564
3565typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3566LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE = 0x00000000,
3567LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE = 0x00000001,
3568} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3569
3570/*
3571 * LB_VLINE_STATUS_VLINE_ACK enum
3572 */
3573
3574typedef enum LB_VLINE_STATUS_VLINE_ACK {
3575LB_VLINE_STATUS_VLINE_NORMAL             = 0x00000000,
3576LB_VLINE_STATUS_VLINE_CLEAR              = 0x00000001,
3577} LB_VLINE_STATUS_VLINE_ACK;
3578
3579/*
3580 * LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE enum
3581 */
3582
3583typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3584LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3585LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3586} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3587
3588/*
3589 * LB_VLINE2_STATUS_VLINE2_ACK enum
3590 */
3591
3592typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3593LB_VLINE2_STATUS_VLINE2_NORMAL           = 0x00000000,
3594LB_VLINE2_STATUS_VLINE2_CLEAR            = 0x00000001,
3595} LB_VLINE2_STATUS_VLINE2_ACK;
3596
3597/*
3598 * LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE enum
3599 */
3600
3601typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3602LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3603LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3604} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3605
3606/*
3607 * LB_VBLANK_STATUS_VBLANK_ACK enum
3608 */
3609
3610typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3611LB_VBLANK_STATUS_VBLANK_NORMAL           = 0x00000000,
3612LB_VBLANK_STATUS_VBLANK_CLEAR            = 0x00000001,
3613} LB_VBLANK_STATUS_VBLANK_ACK;
3614
3615/*
3616 * LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE enum
3617 */
3618
3619typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3620LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED  = 0x00000000,
3621LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED  = 0x00000001,
3622} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3623
3624/*
3625 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL enum
3626 */
3627
3628typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3629LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE  = 0x00000000,
3630LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK  = 0x00000001,
3631LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET  = 0x00000002,
3632LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET  = 0x00000003,
3633} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3634
3635/*
3636 * LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 enum
3637 */
3638
3639typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3640LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK  = 0x00000000,
3641LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC  = 0x00000001,
3642} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3643
3644/*
3645 * LB_SYNC_RESET_SEL_LB_SYNC_DURATION enum
3646 */
3647
3648typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3649LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS = 0x00000000,
3650LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS = 0x00000001,
3651LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS = 0x00000002,
3652LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS = 0x00000003,
3653} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3654
3655/*
3656 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN enum
3657 */
3658
3659typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3660LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE = 0x00000000,
3661LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE = 0x00000001,
3662} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3663
3664/*
3665 * LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN enum
3666 */
3667
3668typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3669LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE = 0x00000000,
3670LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE = 0x00000001,
3671} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3672
3673/*
3674 * LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK enum
3675 */
3676
3677typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3678LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL  = 0x00000000,
3679LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET   = 0x00000001,
3680} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3681
3682/*
3683 * LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK enum
3684 */
3685
3686typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3687LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL   = 0x00000000,
3688LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET    = 0x00000001,
3689} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3690
3691/*
3692 * LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE enum
3693 */
3694
3695typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3696LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP  = 0x00000002,
3697LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP  = 0x00000003,
3698} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3699
3700/*
3701 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET enum
3702 */
3703
3704typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3705LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL = 0x00000000,
3706LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE  = 0x00000001,
3707} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3708
3709/*
3710 * LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK enum
3711 */
3712
3713typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3714LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0 = 0x00000000,
3715LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1 = 0x00000001,
3716} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3717
3718/*
3719 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE enum
3720 */
3721
3722typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3723LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT  = 0x00000000,
3724LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG  = 0x00000001,
3725LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE  = 0x00000002,
3726} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3727
3728/*
3729 * LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE enum
3730 */
3731
3732typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3733LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE  = 0x00000000,
3734LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN  = 0x00000001,
3735} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3736
3737/*
3738 * LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE enum
3739 */
3740
3741typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3742ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER  = 0x00000001,
3743ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE  = 0x00000002,
3744} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3745
3746/*
3747 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL enum
3748 */
3749
3750typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3751LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0 = 0x00000000,
3752LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1 = 0x00000001,
3753} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3754
3755/*
3756 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE enum
3757 */
3758
3759typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3760LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE = 0x00000000,
3761LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE  = 0x00000001,
3762} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3763
3764/*
3765 * LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO enum
3766 */
3767
3768typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3769LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO = 0x00000000,
3770LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO  = 0x00000001,
3771} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3772
3773/*
3774 * LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN enum
3775 */
3776
3777typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3778LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0 = 0x00000000,
3779LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1 = 0x00000001,
3780} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3781
3782/*******************************************************
3783 * DIG Enums
3784 *******************************************************/
3785
3786/*
3787 * HDMI_KEEPOUT_MODE enum
3788 */
3789
3790typedef enum HDMI_KEEPOUT_MODE {
3791HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC        = 0x00000000,
3792HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC      = 0x00000001,
3793} HDMI_KEEPOUT_MODE;
3794
3795/*
3796 * HDMI_DATA_SCRAMBLE_EN enum
3797 */
3798
3799typedef enum HDMI_DATA_SCRAMBLE_EN {
3800HDMI_DATA_SCRAMBLE_DISABLE               = 0x00000000,
3801HDMI_DATA_SCRAMBLE_ENABLE                = 0x00000001,
3802} HDMI_DATA_SCRAMBLE_EN;
3803
3804/*
3805 * HDMI_CLOCK_CHANNEL_RATE enum
3806 */
3807
3808typedef enum HDMI_CLOCK_CHANNEL_RATE {
3809HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE  = 0x00000000,
3810HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE  = 0x00000001,
3811} HDMI_CLOCK_CHANNEL_RATE;
3812
3813/*
3814 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
3815 */
3816
3817typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
3818HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE     = 0x00000000,
3819HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE    = 0x00000001,
3820} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
3821
3822/*
3823 * HDMI_PACKET_GEN_VERSION enum
3824 */
3825
3826typedef enum HDMI_PACKET_GEN_VERSION {
3827HDMI_PACKET_GEN_VERSION_OLD              = 0x00000000,
3828HDMI_PACKET_GEN_VERSION_NEW              = 0x00000001,
3829} HDMI_PACKET_GEN_VERSION;
3830
3831/*
3832 * HDMI_ERROR_ACK enum
3833 */
3834
3835typedef enum HDMI_ERROR_ACK {
3836HDMI_ERROR_ACK_INT                       = 0x00000000,
3837HDMI_ERROR_NOT_ACK                       = 0x00000001,
3838} HDMI_ERROR_ACK;
3839
3840/*
3841 * HDMI_ERROR_MASK enum
3842 */
3843
3844typedef enum HDMI_ERROR_MASK {
3845HDMI_ERROR_MASK_INT                      = 0x00000000,
3846HDMI_ERROR_NOT_MASK                      = 0x00000001,
3847} HDMI_ERROR_MASK;
3848
3849/*
3850 * HDMI_DEEP_COLOR_DEPTH enum
3851 */
3852
3853typedef enum HDMI_DEEP_COLOR_DEPTH {
3854HDMI_DEEP_COLOR_DEPTH_24BPP              = 0x00000000,
3855HDMI_DEEP_COLOR_DEPTH_30BPP              = 0x00000001,
3856HDMI_DEEP_COLOR_DEPTH_36BPP              = 0x00000002,
3857HDMI_DEEP_COLOR_DEPTH_RESERVED           = 0x00000003,
3858} HDMI_DEEP_COLOR_DEPTH;
3859
3860/*
3861 * HDMI_AUDIO_DELAY_EN enum
3862 */
3863
3864typedef enum HDMI_AUDIO_DELAY_EN {
3865HDMI_AUDIO_DELAY_DISABLE                 = 0x00000000,
3866HDMI_AUDIO_DELAY_58CLK                   = 0x00000001,
3867HDMI_AUDIO_DELAY_56CLK                   = 0x00000002,
3868HDMI_AUDIO_DELAY_RESERVED                = 0x00000003,
3869} HDMI_AUDIO_DELAY_EN;
3870
3871/*
3872 * HDMI_AUDIO_SEND_MAX_PACKETS enum
3873 */
3874
3875typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
3876HDMI_NOT_SEND_MAX_AUDIO_PACKETS          = 0x00000000,
3877HDMI_SEND_MAX_AUDIO_PACKETS              = 0x00000001,
3878} HDMI_AUDIO_SEND_MAX_PACKETS;
3879
3880/*
3881 * HDMI_ACR_SEND enum
3882 */
3883
3884typedef enum HDMI_ACR_SEND {
3885HDMI_ACR_NOT_SEND                        = 0x00000000,
3886HDMI_ACR_PKT_SEND                        = 0x00000001,
3887} HDMI_ACR_SEND;
3888
3889/*
3890 * HDMI_ACR_CONT enum
3891 */
3892
3893typedef enum HDMI_ACR_CONT {
3894HDMI_ACR_CONT_DISABLE                    = 0x00000000,
3895HDMI_ACR_CONT_ENABLE                     = 0x00000001,
3896} HDMI_ACR_CONT;
3897
3898/*
3899 * HDMI_ACR_SELECT enum
3900 */
3901
3902typedef enum HDMI_ACR_SELECT {
3903HDMI_ACR_SELECT_HW                       = 0x00000000,
3904HDMI_ACR_SELECT_32K                      = 0x00000001,
3905HDMI_ACR_SELECT_44K                      = 0x00000002,
3906HDMI_ACR_SELECT_48K                      = 0x00000003,
3907} HDMI_ACR_SELECT;
3908
3909/*
3910 * HDMI_ACR_SOURCE enum
3911 */
3912
3913typedef enum HDMI_ACR_SOURCE {
3914HDMI_ACR_SOURCE_HW                       = 0x00000000,
3915HDMI_ACR_SOURCE_SW                       = 0x00000001,
3916} HDMI_ACR_SOURCE;
3917
3918/*
3919 * HDMI_ACR_N_MULTIPLE enum
3920 */
3921
3922typedef enum HDMI_ACR_N_MULTIPLE {
3923HDMI_ACR_0_MULTIPLE_RESERVED             = 0x00000000,
3924HDMI_ACR_1_MULTIPLE                      = 0x00000001,
3925HDMI_ACR_2_MULTIPLE                      = 0x00000002,
3926HDMI_ACR_3_MULTIPLE_RESERVED             = 0x00000003,
3927HDMI_ACR_4_MULTIPLE                      = 0x00000004,
3928HDMI_ACR_5_MULTIPLE_RESERVED             = 0x00000005,
3929HDMI_ACR_6_MULTIPLE_RESERVED             = 0x00000006,
3930HDMI_ACR_7_MULTIPLE_RESERVED             = 0x00000007,
3931} HDMI_ACR_N_MULTIPLE;
3932
3933/*
3934 * HDMI_ACR_AUDIO_PRIORITY enum
3935 */
3936
3937typedef enum HDMI_ACR_AUDIO_PRIORITY {
3938HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE  = 0x00000000,
3939HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT  = 0x00000001,
3940} HDMI_ACR_AUDIO_PRIORITY;
3941
3942/*
3943 * HDMI_NULL_SEND enum
3944 */
3945
3946typedef enum HDMI_NULL_SEND {
3947HDMI_NULL_NOT_SEND                       = 0x00000000,
3948HDMI_NULL_PKT_SEND                       = 0x00000001,
3949} HDMI_NULL_SEND;
3950
3951/*
3952 * HDMI_GC_SEND enum
3953 */
3954
3955typedef enum HDMI_GC_SEND {
3956HDMI_GC_NOT_SEND                         = 0x00000000,
3957HDMI_GC_PKT_SEND                         = 0x00000001,
3958} HDMI_GC_SEND;
3959
3960/*
3961 * HDMI_GC_CONT enum
3962 */
3963
3964typedef enum HDMI_GC_CONT {
3965HDMI_GC_CONT_DISABLE                     = 0x00000000,
3966HDMI_GC_CONT_ENABLE                      = 0x00000001,
3967} HDMI_GC_CONT;
3968
3969/*
3970 * HDMI_ISRC_SEND enum
3971 */
3972
3973typedef enum HDMI_ISRC_SEND {
3974HDMI_ISRC_NOT_SEND                       = 0x00000000,
3975HDMI_ISRC_PKT_SEND                       = 0x00000001,
3976} HDMI_ISRC_SEND;
3977
3978/*
3979 * HDMI_ISRC_CONT enum
3980 */
3981
3982typedef enum HDMI_ISRC_CONT {
3983HDMI_ISRC_CONT_DISABLE                   = 0x00000000,
3984HDMI_ISRC_CONT_ENABLE                    = 0x00000001,
3985} HDMI_ISRC_CONT;
3986
3987/*
3988 * HDMI_AVI_INFO_SEND enum
3989 */
3990
3991typedef enum HDMI_AVI_INFO_SEND {
3992HDMI_AVI_INFO_NOT_SEND                   = 0x00000000,
3993HDMI_AVI_INFO_PKT_SEND                   = 0x00000001,
3994} HDMI_AVI_INFO_SEND;
3995
3996/*
3997 * HDMI_AVI_INFO_CONT enum
3998 */
3999
4000typedef enum HDMI_AVI_INFO_CONT {

4001HDMI_AVI_INFO_CONT_DISABLE               = 0x00000000,
4002HDMI_AVI_INFO_CONT_ENABLE                = 0x00000001,
4003} HDMI_AVI_INFO_CONT;
4004
4005/*
4006 * HDMI_AUDIO_INFO_SEND enum
4007 */
4008
4009typedef enum HDMI_AUDIO_INFO_SEND {
4010HDMI_AUDIO_INFO_NOT_SEND                 = 0x00000000,
4011HDMI_AUDIO_INFO_PKT_SEND                 = 0x00000001,
4012} HDMI_AUDIO_INFO_SEND;
4013
4014/*
4015 * HDMI_AUDIO_INFO_CONT enum
4016 */
4017
4018typedef enum HDMI_AUDIO_INFO_CONT {
4019HDMI_AUDIO_INFO_CONT_DISABLE             = 0x00000000,
4020HDMI_AUDIO_INFO_CONT_ENABLE              = 0x00000001,
4021} HDMI_AUDIO_INFO_CONT;
4022
4023/*
4024 * HDMI_MPEG_INFO_SEND enum
4025 */
4026
4027typedef enum HDMI_MPEG_INFO_SEND {
4028HDMI_MPEG_INFO_NOT_SEND                  = 0x00000000,
4029HDMI_MPEG_INFO_PKT_SEND                  = 0x00000001,
4030} HDMI_MPEG_INFO_SEND;
4031
4032/*
4033 * HDMI_MPEG_INFO_CONT enum
4034 */
4035
4036typedef enum HDMI_MPEG_INFO_CONT {
4037HDMI_MPEG_INFO_CONT_DISABLE              = 0x00000000,
4038HDMI_MPEG_INFO_CONT_ENABLE               = 0x00000001,
4039} HDMI_MPEG_INFO_CONT;
4040
4041/*
4042 * HDMI_GENERIC0_SEND enum
4043 */
4044
4045typedef enum HDMI_GENERIC0_SEND {
4046HDMI_GENERIC0_NOT_SEND                   = 0x00000000,
4047HDMI_GENERIC0_PKT_SEND                   = 0x00000001,
4048} HDMI_GENERIC0_SEND;
4049
4050/*
4051 * HDMI_GENERIC0_CONT enum
4052 */
4053
4054typedef enum HDMI_GENERIC0_CONT {
4055HDMI_GENERIC0_CONT_DISABLE               = 0x00000000,
4056HDMI_GENERIC0_CONT_ENABLE                = 0x00000001,
4057} HDMI_GENERIC0_CONT;
4058
4059/*
4060 * HDMI_GENERIC1_SEND enum
4061 */
4062
4063typedef enum HDMI_GENERIC1_SEND {
4064HDMI_GENERIC1_NOT_SEND                   = 0x00000000,
4065HDMI_GENERIC1_PKT_SEND                   = 0x00000001,
4066} HDMI_GENERIC1_SEND;
4067
4068/*
4069 * HDMI_GENERIC1_CONT enum
4070 */
4071
4072typedef enum HDMI_GENERIC1_CONT {
4073HDMI_GENERIC1_CONT_DISABLE               = 0x00000000,
4074HDMI_GENERIC1_CONT_ENABLE                = 0x00000001,
4075} HDMI_GENERIC1_CONT;
4076
4077/*
4078 * HDMI_GC_AVMUTE_CONT enum
4079 */
4080
4081typedef enum HDMI_GC_AVMUTE_CONT {
4082HDMI_GC_AVMUTE_CONT_DISABLE              = 0x00000000,
4083HDMI_GC_AVMUTE_CONT_ENABLE               = 0x00000001,
4084} HDMI_GC_AVMUTE_CONT;
4085
4086/*
4087 * HDMI_PACKING_PHASE_OVERRIDE enum
4088 */
4089
4090typedef enum HDMI_PACKING_PHASE_OVERRIDE {
4091HDMI_PACKING_PHASE_SET_BY_HW             = 0x00000000,
4092HDMI_PACKING_PHASE_SET_BY_SW             = 0x00000001,
4093} HDMI_PACKING_PHASE_OVERRIDE;
4094
4095/*
4096 * HDMI_GENERIC2_SEND enum
4097 */
4098
4099typedef enum HDMI_GENERIC2_SEND {
4100HDMI_GENERIC2_NOT_SEND                   = 0x00000000,
4101HDMI_GENERIC2_PKT_SEND                   = 0x00000001,
4102} HDMI_GENERIC2_SEND;
4103
4104/*
4105 * HDMI_GENERIC2_CONT enum
4106 */
4107
4108typedef enum HDMI_GENERIC2_CONT {
4109HDMI_GENERIC2_CONT_DISABLE               = 0x00000000,
4110HDMI_GENERIC2_CONT_ENABLE                = 0x00000001,
4111} HDMI_GENERIC2_CONT;
4112
4113/*
4114 * HDMI_GENERIC3_SEND enum
4115 */
4116
4117typedef enum HDMI_GENERIC3_SEND {
4118HDMI_GENERIC3_NOT_SEND                   = 0x00000000,
4119HDMI_GENERIC3_PKT_SEND                   = 0x00000001,
4120} HDMI_GENERIC3_SEND;
4121
4122/*
4123 * HDMI_GENERIC3_CONT enum
4124 */
4125
4126typedef enum HDMI_GENERIC3_CONT {
4127HDMI_GENERIC3_CONT_DISABLE               = 0x00000000,
4128HDMI_GENERIC3_CONT_ENABLE                = 0x00000001,
4129} HDMI_GENERIC3_CONT;
4130
4131/*
4132 * TMDS_PIXEL_ENCODING enum
4133 */
4134
4135typedef enum TMDS_PIXEL_ENCODING {
4136TMDS_PIXEL_ENCODING_444_OR_420           = 0x00000000,
4137TMDS_PIXEL_ENCODING_422                  = 0x00000001,
4138} TMDS_PIXEL_ENCODING;
4139
4140/*
4141 * TMDS_COLOR_FORMAT enum
4142 */
4143
4144typedef enum TMDS_COLOR_FORMAT {
4145TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP  = 0x00000000,
4146TMDS_COLOR_FORMAT_TWIN30BPP_LSB          = 0x00000001,
4147TMDS_COLOR_FORMAT_DUAL30BPP              = 0x00000002,
4148TMDS_COLOR_FORMAT_RESERVED               = 0x00000003,
4149} TMDS_COLOR_FORMAT;
4150
4151/*
4152 * TMDS_STEREOSYNC_CTL_SEL_REG enum
4153 */
4154
4155typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
4156TMDS_STEREOSYNC_CTL0                     = 0x00000000,
4157TMDS_STEREOSYNC_CTL1                     = 0x00000001,
4158TMDS_STEREOSYNC_CTL2                     = 0x00000002,
4159TMDS_STEREOSYNC_CTL3                     = 0x00000003,
4160} TMDS_STEREOSYNC_CTL_SEL_REG;
4161
4162/*
4163 * TMDS_CTL0_DATA_SEL enum
4164 */
4165
4166typedef enum TMDS_CTL0_DATA_SEL {
4167TMDS_CTL0_DATA_SEL0_RESERVED             = 0x00000000,
4168TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4169TMDS_CTL0_DATA_SEL2_VSYNC                = 0x00000002,
4170TMDS_CTL0_DATA_SEL3_RESERVED             = 0x00000003,
4171TMDS_CTL0_DATA_SEL4_HSYNC                = 0x00000004,
4172TMDS_CTL0_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4173TMDS_CTL0_DATA_SEL8_RANDOM_DATA          = 0x00000006,
4174TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA    = 0x00000007,
4175} TMDS_CTL0_DATA_SEL;
4176
4177/*
4178 * TMDS_CTL0_DATA_INVERT enum
4179 */
4180
4181typedef enum TMDS_CTL0_DATA_INVERT {
4182TMDS_CTL0_DATA_NORMAL                    = 0x00000000,
4183TMDS_CTL0_DATA_INVERT_EN                 = 0x00000001,
4184} TMDS_CTL0_DATA_INVERT;
4185
4186/*
4187 * TMDS_CTL0_DATA_MODULATION enum
4188 */
4189
4190typedef enum TMDS_CTL0_DATA_MODULATION {
4191TMDS_CTL0_DATA_MODULATION_DISABLE        = 0x00000000,
4192TMDS_CTL0_DATA_MODULATION_BIT0           = 0x00000001,
4193TMDS_CTL0_DATA_MODULATION_BIT1           = 0x00000002,
4194TMDS_CTL0_DATA_MODULATION_BIT2           = 0x00000003,
4195} TMDS_CTL0_DATA_MODULATION;
4196
4197/*
4198 * TMDS_CTL0_PATTERN_OUT_EN enum
4199 */
4200
4201typedef enum TMDS_CTL0_PATTERN_OUT_EN {
4202TMDS_CTL0_PATTERN_OUT_DISABLE            = 0x00000000,
4203TMDS_CTL0_PATTERN_OUT_ENABLE             = 0x00000001,
4204} TMDS_CTL0_PATTERN_OUT_EN;
4205
4206/*
4207 * TMDS_CTL1_DATA_SEL enum
4208 */
4209
4210typedef enum TMDS_CTL1_DATA_SEL {
4211TMDS_CTL1_DATA_SEL0_RESERVED             = 0x00000000,
4212TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4213TMDS_CTL1_DATA_SEL2_VSYNC                = 0x00000002,
4214TMDS_CTL1_DATA_SEL3_RESERVED             = 0x00000003,
4215TMDS_CTL1_DATA_SEL4_HSYNC                = 0x00000004,
4216TMDS_CTL1_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4217TMDS_CTL1_DATA_SEL8_BLANK_TIME           = 0x00000006,
4218TMDS_CTL1_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4219} TMDS_CTL1_DATA_SEL;
4220
4221/*
4222 * TMDS_CTL1_DATA_INVERT enum
4223 */
4224
4225typedef enum TMDS_CTL1_DATA_INVERT {
4226TMDS_CTL1_DATA_NORMAL                    = 0x00000000,
4227TMDS_CTL1_DATA_INVERT_EN                 = 0x00000001,
4228} TMDS_CTL1_DATA_INVERT;
4229
4230/*
4231 * TMDS_CTL1_DATA_MODULATION enum
4232 */
4233
4234typedef enum TMDS_CTL1_DATA_MODULATION {
4235TMDS_CTL1_DATA_MODULATION_DISABLE        = 0x00000000,
4236TMDS_CTL1_DATA_MODULATION_BIT0           = 0x00000001,
4237TMDS_CTL1_DATA_MODULATION_BIT1           = 0x00000002,
4238TMDS_CTL1_DATA_MODULATION_BIT2           = 0x00000003,
4239} TMDS_CTL1_DATA_MODULATION;
4240
4241/*
4242 * TMDS_CTL1_PATTERN_OUT_EN enum
4243 */
4244
4245typedef enum TMDS_CTL1_PATTERN_OUT_EN {
4246TMDS_CTL1_PATTERN_OUT_DISABLE            = 0x00000000,
4247TMDS_CTL1_PATTERN_OUT_ENABLE             = 0x00000001,
4248} TMDS_CTL1_PATTERN_OUT_EN;
4249
4250/*
4251 * TMDS_CTL2_DATA_SEL enum
4252 */
4253
4254typedef enum TMDS_CTL2_DATA_SEL {
4255TMDS_CTL2_DATA_SEL0_RESERVED             = 0x00000000,
4256TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4257TMDS_CTL2_DATA_SEL2_VSYNC                = 0x00000002,
4258TMDS_CTL2_DATA_SEL3_RESERVED             = 0x00000003,
4259TMDS_CTL2_DATA_SEL4_HSYNC                = 0x00000004,
4260TMDS_CTL2_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4261TMDS_CTL2_DATA_SEL8_BLANK_TIME           = 0x00000006,
4262TMDS_CTL2_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4263} TMDS_CTL2_DATA_SEL;
4264
4265/*
4266 * TMDS_CTL2_DATA_INVERT enum
4267 */
4268
4269typedef enum TMDS_CTL2_DATA_INVERT {
4270TMDS_CTL2_DATA_NORMAL                    = 0x00000000,
4271TMDS_CTL2_DATA_INVERT_EN                 = 0x00000001,
4272} TMDS_CTL2_DATA_INVERT;
4273
4274/*
4275 * TMDS_CTL2_DATA_MODULATION enum
4276 */
4277
4278typedef enum TMDS_CTL2_DATA_MODULATION {
4279TMDS_CTL2_DATA_MODULATION_DISABLE        = 0x00000000,
4280TMDS_CTL2_DATA_MODULATION_BIT0           = 0x00000001,
4281TMDS_CTL2_DATA_MODULATION_BIT1           = 0x00000002,
4282TMDS_CTL2_DATA_MODULATION_BIT2           = 0x00000003,
4283} TMDS_CTL2_DATA_MODULATION;
4284
4285/*
4286 * TMDS_CTL2_PATTERN_OUT_EN enum
4287 */
4288
4289typedef enum TMDS_CTL2_PATTERN_OUT_EN {
4290TMDS_CTL2_PATTERN_OUT_DISABLE            = 0x00000000,
4291TMDS_CTL2_PATTERN_OUT_ENABLE             = 0x00000001,
4292} TMDS_CTL2_PATTERN_OUT_EN;
4293
4294/*
4295 * TMDS_CTL3_DATA_INVERT enum
4296 */
4297
4298typedef enum TMDS_CTL3_DATA_INVERT {
4299TMDS_CTL3_DATA_NORMAL                    = 0x00000000,
4300TMDS_CTL3_DATA_INVERT_EN                 = 0x00000001,
4301} TMDS_CTL3_DATA_INVERT;
4302
4303/*
4304 * TMDS_CTL3_DATA_MODULATION enum
4305 */
4306
4307typedef enum TMDS_CTL3_DATA_MODULATION {
4308TMDS_CTL3_DATA_MODULATION_DISABLE        = 0x00000000,
4309TMDS_CTL3_DATA_MODULATION_BIT0           = 0x00000001,
4310TMDS_CTL3_DATA_MODULATION_BIT1           = 0x00000002,
4311TMDS_CTL3_DATA_MODULATION_BIT2           = 0x00000003,
4312} TMDS_CTL3_DATA_MODULATION;
4313
4314/*
4315 * TMDS_CTL3_PATTERN_OUT_EN enum
4316 */
4317
4318typedef enum TMDS_CTL3_PATTERN_OUT_EN {
4319TMDS_CTL3_PATTERN_OUT_DISABLE            = 0x00000000,
4320TMDS_CTL3_PATTERN_OUT_ENABLE             = 0x00000001,
4321} TMDS_CTL3_PATTERN_OUT_EN;
4322
4323/*
4324 * TMDS_CTL3_DATA_SEL enum
4325 */
4326
4327typedef enum TMDS_CTL3_DATA_SEL {
4328TMDS_CTL3_DATA_SEL0_RESERVED             = 0x00000000,
4329TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE       = 0x00000001,
4330TMDS_CTL3_DATA_SEL2_VSYNC                = 0x00000002,
4331TMDS_CTL3_DATA_SEL3_RESERVED             = 0x00000003,
4332TMDS_CTL3_DATA_SEL4_HSYNC                = 0x00000004,
4333TMDS_CTL3_DATA_SEL5_SEL7_RESERVED        = 0x00000005,
4334TMDS_CTL3_DATA_SEL8_BLANK_TIME           = 0x00000006,
4335TMDS_CTL3_DATA_SEL9_SEL15_RESERVED       = 0x00000007,
4336} TMDS_CTL3_DATA_SEL;
4337
4338/*
4339 * DIG_FE_CNTL_SOURCE_SELECT enum
4340 */
4341
4342typedef enum DIG_FE_CNTL_SOURCE_SELECT {
4343DIG_FE_SOURCE_FROM_FMT0                  = 0x00000000,
4344DIG_FE_SOURCE_FROM_FMT1                  = 0x00000001,
4345DIG_FE_SOURCE_FROM_FMT2                  = 0x00000002,
4346DIG_FE_SOURCE_FROM_FMT3                  = 0x00000003,
4347DIG_FE_SOURCE_FROM_FMT4                  = 0x00000004,
4348DIG_FE_SOURCE_FROM_FMT5                  = 0x00000005,
4349} DIG_FE_CNTL_SOURCE_SELECT;
4350
4351/*
4352 * DIG_FE_CNTL_STEREOSYNC_SELECT enum
4353 */
4354
4355typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
4356DIG_FE_STEREOSYNC_FROM_FMT0              = 0x00000000,
4357DIG_FE_STEREOSYNC_FROM_FMT1              = 0x00000001,
4358DIG_FE_STEREOSYNC_FROM_FMT2              = 0x00000002,
4359DIG_FE_STEREOSYNC_FROM_FMT3              = 0x00000003,
4360DIG_FE_STEREOSYNC_FROM_FMT4              = 0x00000004,
4361DIG_FE_STEREOSYNC_FROM_FMT5              = 0x00000005,
4362} DIG_FE_CNTL_STEREOSYNC_SELECT;
4363
4364/*
4365 * DIG_FIFO_READ_CLOCK_SRC enum
4366 */
4367
4368typedef enum DIG_FIFO_READ_CLOCK_SRC {
4369DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG        = 0x00000000,
4370DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE  = 0x00000001,
4371} DIG_FIFO_READ_CLOCK_SRC;
4372
4373/*
4374 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
4375 */
4376
4377typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
4378DIG_OUTPUT_CRC_ON_LINK0                  = 0x00000000,
4379DIG_OUTPUT_CRC_ON_LINK1                  = 0x00000001,
4380} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
4381
4382/*
4383 * DIG_OUTPUT_CRC_DATA_SEL enum
4384 */
4385
4386typedef enum DIG_OUTPUT_CRC_DATA_SEL {
4387DIG_OUTPUT_CRC_FOR_FULLFRAME             = 0x00000000,
4388DIG_OUTPUT_CRC_FOR_ACTIVEONLY            = 0x00000001,
4389DIG_OUTPUT_CRC_FOR_VBI                   = 0x00000002,
4390DIG_OUTPUT_CRC_FOR_AUDIO                 = 0x00000003,
4391} DIG_OUTPUT_CRC_DATA_SEL;
4392
4393/*
4394 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
4395 */
4396
4397typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
4398DIG_IN_NORMAL_OPERATION                  = 0x00000000,
4399DIG_IN_DEBUG_MODE                        = 0x00000001,
4400} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
4401
4402/*
4403 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
4404 */
4405
4406typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
4407DIG_10BIT_TEST_PATTERN                   = 0x00000000,
4408DIG_ALTERNATING_TEST_PATTERN             = 0x00000001,
4409} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
4410
4411/*
4412 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
4413 */
4414
4415typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
4416DIG_TEST_PATTERN_NORMAL                  = 0x00000000,
4417DIG_TEST_PATTERN_RANDOM                  = 0x00000001,
4418} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
4419
4420/*
4421 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
4422 */
4423
4424typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
4425DIG_RANDOM_PATTERN_ENABLED               = 0x00000000,
4426DIG_RANDOM_PATTERN_RESETED               = 0x00000001,
4427} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
4428
4429/*
4430 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
4431 */
4432
4433typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
4434DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE   = 0x00000000,
4435DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG  = 0x00000001,
4436} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
4437
4438/*
4439 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
4440 */
4441
4442typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
4443DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS  = 0x00000000,
4444DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH  = 0x00000001,
4445} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
4446
4447/*
4448 * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
4449 */
4450
4451typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
4452DIG_FIFO_USE_OVERWRITE_LEVEL             = 0x00000000,
4453DIG_FIFO_USE_CAL_AVERAGE_LEVEL           = 0x00000001,
4454} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
4455
4456/*
4457 * DIG_FIFO_ERROR_ACK enum
4458 */
4459
4460typedef enum DIG_FIFO_ERROR_ACK {
4461DIG_FIFO_ERROR_ACK_INT                   = 0x00000000,
4462DIG_FIFO_ERROR_NOT_ACK                   = 0x00000001,
4463} DIG_FIFO_ERROR_ACK;
4464
4465/*
4466 * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
4467 */
4468
4469typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
4470DIG_FIFO_NOT_FORCE_RECAL_AVERAGE         = 0x00000000,
4471DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL       = 0x00000001,
4472} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
4473
4474/*
4475 * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
4476 */
4477
4478typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
4479DIG_FIFO_NOT_FORCE_RECOMP_MINMAX         = 0x00000000,
4480DIG_FIFO_FORCE_RECOMP_MINMAX             = 0x00000001,
4481} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
4482
4483/*
4484 * AFMT_INTERRUPT_STATUS_CHG_MASK enum
4485 */
4486
4487typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
4488AFMT_INTERRUPT_DISABLE                   = 0x00000000,
4489AFMT_INTERRUPT_ENABLE                    = 0x00000001,
4490} AFMT_INTERRUPT_STATUS_CHG_MASK;
4491
4492/*
4493 * HDMI_GC_AVMUTE enum
4494 */
4495
4496typedef enum HDMI_GC_AVMUTE {
4497HDMI_GC_AVMUTE_SET                       = 0x00000000,
4498HDMI_GC_AVMUTE_UNSET                     = 0x00000001,
4499} HDMI_GC_AVMUTE;
4500
4501/*
4502 * HDMI_DEFAULT_PAHSE enum
4503 */
4504
4505typedef enum HDMI_DEFAULT_PAHSE {
4506HDMI_DEFAULT_PHASE_IS_0                  = 0x00000000,
4507HDMI_DEFAULT_PHASE_IS_1                  = 0x00000001,
4508} HDMI_DEFAULT_PAHSE;
4509
4510/*
4511 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
4512 */
4513
4514typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
4515AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS  = 0x00000000,
4516AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER       = 0x00000001,
4517} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
4518
4519/*
4520 * AUDIO_LAYOUT_SELECT enum
4521 */
4522
4523typedef enum AUDIO_LAYOUT_SELECT {
4524AUDIO_LAYOUT_0                           = 0x00000000,
4525AUDIO_LAYOUT_1                           = 0x00000001,
4526} AUDIO_LAYOUT_SELECT;
4527
4528/*
4529 * AFMT_AUDIO_CRC_CONTROL_CONT enum
4530 */
4531
4532typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
4533AFMT_AUDIO_CRC_ONESHOT                   = 0x00000000,
4534AFMT_AUDIO_CRC_AUTO_RESTART              = 0x00000001,
4535} AFMT_AUDIO_CRC_CONTROL_CONT;
4536
4537/*
4538 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
4539 */
4540
4541typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
4542AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT    = 0x00000000,
4543AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT   = 0x00000001,
4544} AFMT_AUDIO_CRC_CONTROL_SOURCE;
4545
4546/*
4547 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
4548 */
4549
4550typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
4551AFMT_AUDIO_CRC_CH0_SIG                   = 0x00000000,
4552AFMT_AUDIO_CRC_CH1_SIG                   = 0x00000001,
4553AFMT_AUDIO_CRC_CH2_SIG                   = 0x00000002,
4554AFMT_AUDIO_CRC_CH3_SIG                   = 0x00000003,
4555AFMT_AUDIO_CRC_CH4_SIG                   = 0x00000004,
4556AFMT_AUDIO_CRC_CH5_SIG                   = 0x00000005,
4557AFMT_AUDIO_CRC_CH6_SIG                   = 0x00000006,
4558AFMT_AUDIO_CRC_CH7_SIG                   = 0x00000007,
4559AFMT_AUDIO_CRC_RESERVED_8                = 0x00000008,
4560AFMT_AUDIO_CRC_RESERVED_9                = 0x00000009,
4561AFMT_AUDIO_CRC_RESERVED_10               = 0x0000000a,
4562AFMT_AUDIO_CRC_RESERVED_11               = 0x0000000b,
4563AFMT_AUDIO_CRC_RESERVED_12               = 0x0000000c,
4564AFMT_AUDIO_CRC_RESERVED_13               = 0x0000000d,
4565AFMT_AUDIO_CRC_RESERVED_14               = 0x0000000e,
4566AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT        = 0x0000000f,
4567} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
4568
4569/*
4570 * AFMT_RAMP_CONTROL0_SIGN enum
4571 */
4572
4573typedef enum AFMT_RAMP_CONTROL0_SIGN {
4574AFMT_RAMP_SIGNED                         = 0x00000000,
4575AFMT_RAMP_UNSIGNED                       = 0x00000001,
4576} AFMT_RAMP_CONTROL0_SIGN;
4577
4578/*
4579 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
4580 */
4581
4582typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
4583AFMT_AUDIO_PACKET_SENT_DISABLED          = 0x00000000,
4584AFMT_AUDIO_PACKET_SENT_ENABLED           = 0x00000001,
4585} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
4586
4587/*
4588 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
4589 */
4590
4591typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
4592AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED  = 0x00000000,
4593AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED  = 0x00000001,
4594} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
4595
4596/*
4597 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
4598 */
4599
4600typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
4601AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK  = 0x00000000,
4602AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS  = 0x00000001,
4603} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
4604
4605/*
4606 * AFMT_AUDIO_SRC_CONTROL_SELECT enum
4607 */
4608
4609typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
4610AFMT_AUDIO_SRC_FROM_AZ_STREAM0           = 0x00000000,
4611AFMT_AUDIO_SRC_FROM_AZ_STREAM1           = 0x00000001,
4612AFMT_AUDIO_SRC_FROM_AZ_STREAM2           = 0x00000002,
4613AFMT_AUDIO_SRC_FROM_AZ_STREAM3           = 0x00000003,
4614AFMT_AUDIO_SRC_FROM_AZ_STREAM4           = 0x00000004,
4615AFMT_AUDIO_SRC_FROM_AZ_STREAM5           = 0x00000005,
4616AFMT_AUDIO_SRC_RESERVED                  = 0x00000006,
4617} AFMT_AUDIO_SRC_CONTROL_SELECT;
4618
4619/*
4620 * DIG_BE_CNTL_MODE enum
4621 */
4622
4623typedef enum DIG_BE_CNTL_MODE {
4624DIG_BE_DP_SST_MODE                       = 0x00000000,
4625DIG_BE_RESERVED1                         = 0x00000001,
4626DIG_BE_TMDS_DVI_MODE                     = 0x00000002,
4627DIG_BE_TMDS_HDMI_MODE                    = 0x00000003,
4628DIG_BE_SDVO_RESERVED                     = 0x00000004,
4629DIG_BE_DP_MST_MODE                       = 0x00000005,
4630DIG_BE_RESERVED2                         = 0x00000006,
4631DIG_BE_RESERVED3                         = 0x00000007,
4632} DIG_BE_CNTL_MODE;
4633
4634/*
4635 * DIG_BE_CNTL_HPD_SELECT enum
4636 */
4637
4638typedef enum DIG_BE_CNTL_HPD_SELECT {
4639DIG_BE_CNTL_HPD1                         = 0x00000000,
4640DIG_BE_CNTL_HPD2                         = 0x00000001,
4641DIG_BE_CNTL_HPD3                         = 0x00000002,
4642DIG_BE_CNTL_HPD4                         = 0x00000003,
4643DIG_BE_CNTL_HPD5                         = 0x00000004,
4644DIG_BE_CNTL_HPD6                         = 0x00000005,
4645} DIG_BE_CNTL_HPD_SELECT;
4646
4647/*
4648 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
4649 */
4650
4651typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
4652LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS     = 0x00000000,
4653LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH   = 0x00000001,
4654} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
4655
4656/*
4657 * TMDS_SYNC_PHASE enum
4658 */
4659
4660typedef enum TMDS_SYNC_PHASE {
4661TMDS_NOT_SYNC_PHASE_ON_FRAME_START       = 0x00000000,
4662TMDS_SYNC_PHASE_ON_FRAME_START           = 0x00000001,
4663} TMDS_SYNC_PHASE;
4664
4665/*
4666 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
4667 */
4668
4669typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
4670TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS  = 0x00000000,
4671TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL  = 0x00000001,
4672} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
4673
4674/*
4675 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
4676 */
4677
4678typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
4679TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE   = 0x00000000,
4680TMDS_TRANSMITTER_HPD_MASK_OVERRIDE       = 0x00000001,
4681} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
4682
4683/*
4684 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
4685 */
4686
4687typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
4688TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
4689TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE  = 0x00000001,
4690} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
4691
4692/*
4693 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
4694 */
4695
4696typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
4697TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE  = 0x00000000,
4698TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE  = 0x00000001,
4699} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
4700
4701/*
4702 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
4703 */
4704
4705typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
4706TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE  = 0x00000000,
4707TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON  = 0x00000001,
4708TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x00000002,
4709TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE  = 0x00000003,
4710} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
4711
4712/*
4713 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
4714 */
4715
4716typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
4717TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK   = 0x00000000,
4718TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK     = 0x00000001,
4719} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
4720
4721/*
4722 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
4723 */
4724
4725typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
4726TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK   = 0x00000000,
4727TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK     = 0x00000001,
4728} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
4729
4730/*
4731 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
4732 */
4733
4734typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
4735TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE   = 0x00000000,
4736TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE    = 0x00000001,
4737} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
4738
4739/*
4740 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
4741 */
4742
4743typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
4744TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD      = 0x00000000,
4745TMDS_TRANSMITTER_PLL_RST_ON_HPD          = 0x00000001,
4746} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
4747
4748/*
4749 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
4750 */
4751
4752typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
4753TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK   = 0x00000000,
4754TMDS_TRANSMITTER_TMCLK_FROM_PADS         = 0x00000001,
4755} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
4756
4757/*
4758 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
4759 */
4760
4761typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
4762TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK   = 0x00000000,
4763TMDS_TRANSMITTER_TDCLK_FROM_PADS         = 0x00000001,
4764} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
4765
4766/*
4767 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
4768 */
4769
4770typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
4771TMDS_TRANSMITTER_PLLSEL_BY_HW            = 0x00000000,
4772TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW  = 0x00000001,
4773} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
4774
4775/*
4776 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
4777 */
4778
4779typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
4780TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT    = 0x00000000,
4781TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT  = 0x00000001,
4782} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
4783
4784/*
4785 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
4786 */
4787
4788typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
4789TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT    = 0x00000000,
4790TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT  = 0x00000001,
4791} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
4792
4793/*
4794 * TMDS_REG_TEST_OUTPUTA_CNTLA enum
4795 */
4796
4797typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
4798TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0      = 0x00000000,
4799TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1      = 0x00000001,
4800TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2      = 0x00000002,
4801TMDS_REG_TEST_OUTPUTA_CNTLA_NA           = 0x00000003,
4802} TMDS_REG_TEST_OUTPUTA_CNTLA;
4803
4804/*
4805 * TMDS_REG_TEST_OUTPUTB_CNTLB enum
4806 */
4807
4808typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
4809TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0      = 0x00000000,
4810TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1      = 0x00000001,
4811TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2      = 0x00000002,
4812TMDS_REG_TEST_OUTPUTB_CNTLB_NA           = 0x00000003,
4813} TMDS_REG_TEST_OUTPUTB_CNTLB;
4814
4815/*******************************************************
4816 * DCP Enums
4817 *******************************************************/
4818
4819/*
4820 * DCP_GRPH_ENABLE enum
4821 */
4822
4823typedef enum DCP_GRPH_ENABLE {
4824DCP_GRPH_ENABLE_FALSE                    = 0x00000000,
4825DCP_GRPH_ENABLE_TRUE                     = 0x00000001,
4826} DCP_GRPH_ENABLE;
4827
4828/*
4829 * DCP_GRPH_KEYER_ALPHA_SEL enum
4830 */
4831
4832typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
4833DCP_GRPH_KEYER_ALPHA_SEL_FALSE           = 0x00000000,
4834DCP_GRPH_KEYER_ALPHA_SEL_TRUE            = 0x00000001,
4835} DCP_GRPH_KEYER_ALPHA_SEL;
4836
4837/*
4838 * DCP_GRPH_DEPTH enum
4839 */
4840
4841typedef enum DCP_GRPH_DEPTH {
4842DCP_GRPH_DEPTH_8BPP                      = 0x00000000,
4843DCP_GRPH_DEPTH_16BPP                     = 0x00000001,
4844DCP_GRPH_DEPTH_32BPP                     = 0x00000002,
4845DCP_GRPH_DEPTH_64BPP                     = 0x00000003,
4846} DCP_GRPH_DEPTH;
4847
4848/*
4849 * DCP_GRPH_NUM_BANKS enum
4850 */
4851
4852typedef enum DCP_GRPH_NUM_BANKS {
4853DCP_GRPH_NUM_BANKS_1BANK                 = 0x00000000,
4854DCP_GRPH_NUM_BANKS_2BANK                 = 0x00000001,
4855DCP_GRPH_NUM_BANKS_4BANK                 = 0x00000002,
4856DCP_GRPH_NUM_BANKS_8BANK                 = 0x00000003,
4857DCP_GRPH_NUM_BANKS_16BANK                = 0x00000004,
4858} DCP_GRPH_NUM_BANKS;
4859
4860/*
4861 * DCP_GRPH_NUM_PIPES enum
4862 */
4863
4864typedef enum DCP_GRPH_NUM_PIPES {
4865DCP_GRPH_NUM_PIPES_1PIPE                 = 0x00000000,
4866DCP_GRPH_NUM_PIPES_2PIPE                 = 0x00000001,
4867DCP_GRPH_NUM_PIPES_4PIPE                 = 0x00000002,
4868DCP_GRPH_NUM_PIPES_8PIPE                 = 0x00000003,
4869} DCP_GRPH_NUM_PIPES;
4870
4871/*
4872 * DCP_GRPH_FORMAT enum
4873 */
4874
4875typedef enum DCP_GRPH_FORMAT {
4876DCP_GRPH_FORMAT_8BPP                     = 0x00000000,
4877DCP_GRPH_FORMAT_16BPP                    = 0x00000001,
4878DCP_GRPH_FORMAT_32BPP                    = 0x00000002,
4879DCP_GRPH_FORMAT_64BPP                    = 0x00000003,
4880} DCP_GRPH_FORMAT;
4881
4882/*
4883 * DCP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
4884 */
4885
4886typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
4887DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE  = 0x00000000,
4888DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE  = 0x00000001,
4889} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
4890
4891/*
4892 * DCP_GRPH_SW_MODE enum
4893 */
4894
4895typedef enum DCP_GRPH_SW_MODE {
4896DCP_GRPH_SW_MODE_0                       = 0x00000000,
4897DCP_GRPH_SW_MODE_2                       = 0x00000002,
4898DCP_GRPH_SW_MODE_3                       = 0x00000003,
4899DCP_GRPH_SW_MODE_22                      = 0x00000016,
4900DCP_GRPH_SW_MODE_23                      = 0x00000017,
4901DCP_GRPH_SW_MODE_26                      = 0x0000001a,
4902DCP_GRPH_SW_MODE_27                      = 0x0000001b,
4903DCP_GRPH_SW_MODE_30                      = 0x0000001e,
4904DCP_GRPH_SW_MODE_31                      = 0x0000001f,
4905} DCP_GRPH_SW_MODE;
4906
4907/*
4908 * DCP_GRPH_COLOR_EXPANSION_MODE enum
4909 */
4910
4911typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
4912DCP_GRPH_COLOR_EXPANSION_MODE_DEXP       = 0x00000000,
4913DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP       = 0x00000001,
4914} DCP_GRPH_COLOR_EXPANSION_MODE;
4915
4916/*
4917 * DCP_GRPH_LUT_10BIT_BYPASS_EN enum
4918 */
4919
4920typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
4921DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE       = 0x00000000,
4922DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE        = 0x00000001,
4923} DCP_GRPH_LUT_10BIT_BYPASS_EN;
4924
4925/*
4926 * DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN enum
4927 */
4928
4929typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
4930DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE  = 0x00000000,
4931DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE  = 0x00000001,
4932} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
4933
4934/*
4935 * DCP_GRPH_ENDIAN_SWAP enum
4936 */
4937
4938typedef enum DCP_GRPH_ENDIAN_SWAP {
4939DCP_GRPH_ENDIAN_SWAP_NONE                = 0x00000000,
4940DCP_GRPH_ENDIAN_SWAP_8IN16               = 0x00000001,
4941DCP_GRPH_ENDIAN_SWAP_8IN32               = 0x00000002,
4942DCP_GRPH_ENDIAN_SWAP_8IN64               = 0x00000003,
4943} DCP_GRPH_ENDIAN_SWAP;
4944
4945/*
4946 * DCP_GRPH_RED_CROSSBAR enum
4947 */
4948
4949typedef enum DCP_GRPH_RED_CROSSBAR {
4950DCP_GRPH_RED_CROSSBAR_FROM_R             = 0x00000000,
4951DCP_GRPH_RED_CROSSBAR_FROM_G             = 0x00000001,
4952DCP_GRPH_RED_CROSSBAR_FROM_B             = 0x00000002,
4953DCP_GRPH_RED_CROSSBAR_FROM_A             = 0x00000003,
4954} DCP_GRPH_RED_CROSSBAR;
4955
4956/*
4957 * DCP_GRPH_GREEN_CROSSBAR enum
4958 */
4959
4960typedef enum DCP_GRPH_GREEN_CROSSBAR {
4961DCP_GRPH_GREEN_CROSSBAR_FROM_G           = 0x00000000,
4962DCP_GRPH_GREEN_CROSSBAR_FROM_B           = 0x00000001,
4963DCP_GRPH_GREEN_CROSSBAR_FROM_A           = 0x00000002,
4964DCP_GRPH_GREEN_CROSSBAR_FROM_R           = 0x00000003,
4965} DCP_GRPH_GREEN_CROSSBAR;
4966
4967/*
4968 * DCP_GRPH_BLUE_CROSSBAR enum
4969 */
4970
4971typedef enum DCP_GRPH_BLUE_CROSSBAR {
4972DCP_GRPH_BLUE_CROSSBAR_FROM_B            = 0x00000000,
4973DCP_GRPH_BLUE_CROSSBAR_FROM_A            = 0x00000001,
4974DCP_GRPH_BLUE_CROSSBAR_FROM_R            = 0x00000002,
4975DCP_GRPH_BLUE_CROSSBAR_FROM_G            = 0x00000003,
4976} DCP_GRPH_BLUE_CROSSBAR;
4977
4978/*
4979 * DCP_GRPH_ALPHA_CROSSBAR enum
4980 */
4981
4982typedef enum DCP_GRPH_ALPHA_CROSSBAR {
4983DCP_GRPH_ALPHA_CROSSBAR_FROM_A           = 0x00000000,
4984DCP_GRPH_ALPHA_CROSSBAR_FROM_R           = 0x00000001,
4985DCP_GRPH_ALPHA_CROSSBAR_FROM_G           = 0x00000002,
4986DCP_GRPH_ALPHA_CROSSBAR_FROM_B           = 0x00000003,
4987} DCP_GRPH_ALPHA_CROSSBAR;
4988
4989/*
4990 * DCP_GRPH_PRIMARY_DFQ_ENABLE enum
4991 */
4992
4993typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
4994DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE        = 0x00000000,
4995DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE         = 0x00000001,
4996} DCP_GRPH_PRIMARY_DFQ_ENABLE;
4997
4998/*
4999 * DCP_GRPH_SECONDARY_DFQ_ENABLE enum
5000 */

5001
5002typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
5003DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE      = 0x00000000,
5004DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE       = 0x00000001,
5005} DCP_GRPH_SECONDARY_DFQ_ENABLE;
5006
5007/*
5008 * DCP_GRPH_INPUT_GAMMA_MODE enum
5009 */
5010
5011typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
5012DCP_GRPH_INPUT_GAMMA_MODE_LUT            = 0x00000000,
5013DCP_GRPH_INPUT_GAMMA_MODE_BYPASS         = 0x00000001,
5014} DCP_GRPH_INPUT_GAMMA_MODE;
5015
5016/*
5017 * DCP_GRPH_MODE_UPDATE_PENDING enum
5018 */
5019
5020typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
5021DCP_GRPH_MODE_UPDATE_PENDING_FALSE       = 0x00000000,
5022DCP_GRPH_MODE_UPDATE_PENDING_TRUE        = 0x00000001,
5023} DCP_GRPH_MODE_UPDATE_PENDING;
5024
5025/*
5026 * DCP_GRPH_MODE_UPDATE_TAKEN enum
5027 */
5028
5029typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
5030DCP_GRPH_MODE_UPDATE_TAKEN_FALSE         = 0x00000000,
5031DCP_GRPH_MODE_UPDATE_TAKEN_TRUE          = 0x00000001,
5032} DCP_GRPH_MODE_UPDATE_TAKEN;
5033
5034/*
5035 * DCP_GRPH_SURFACE_UPDATE_PENDING enum
5036 */
5037
5038typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
5039DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE    = 0x00000000,
5040DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE     = 0x00000001,
5041} DCP_GRPH_SURFACE_UPDATE_PENDING;
5042
5043/*
5044 * DCP_GRPH_SURFACE_UPDATE_TAKEN enum
5045 */
5046
5047typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
5048DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE      = 0x00000000,
5049DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE       = 0x00000001,
5050} DCP_GRPH_SURFACE_UPDATE_TAKEN;
5051
5052/*
5053 * DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE enum
5054 */
5055
5056typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
5057DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE = 0x00000000,
5058DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE = 0x00000001,
5059} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
5060
5061/*
5062 * DCP_GRPH_UPDATE_LOCK enum
5063 */
5064
5065typedef enum DCP_GRPH_UPDATE_LOCK {
5066DCP_GRPH_UPDATE_LOCK_FALSE               = 0x00000000,
5067DCP_GRPH_UPDATE_LOCK_TRUE                = 0x00000001,
5068} DCP_GRPH_UPDATE_LOCK;
5069
5070/*
5071 * DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
5072 */
5073
5074typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
5075DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE  = 0x00000000,
5076DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE  = 0x00000001,
5077} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
5078
5079/*
5080 * DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
5081 */
5082
5083typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
5084DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5085DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5086} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
5087
5088/*
5089 * DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
5090 */
5091
5092typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
5093DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5094DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5095} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
5096
5097/*
5098 * DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN enum
5099 */
5100
5101typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
5102DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE  = 0x00000000,
5103DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE  = 0x00000001,
5104} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
5105
5106/*
5107 * DCP_GRPH_XDMA_SUPER_AA_EN enum
5108 */
5109
5110typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
5111DCP_GRPH_XDMA_SUPER_AA_EN_FALSE          = 0x00000000,
5112DCP_GRPH_XDMA_SUPER_AA_EN_TRUE           = 0x00000001,
5113} DCP_GRPH_XDMA_SUPER_AA_EN;
5114
5115/*
5116 * DCP_GRPH_DFQ_RESET enum
5117 */
5118
5119typedef enum DCP_GRPH_DFQ_RESET {
5120DCP_GRPH_DFQ_RESET_FALSE                 = 0x00000000,
5121DCP_GRPH_DFQ_RESET_TRUE                  = 0x00000001,
5122} DCP_GRPH_DFQ_RESET;
5123
5124/*
5125 * DCP_GRPH_DFQ_SIZE enum
5126 */
5127
5128typedef enum DCP_GRPH_DFQ_SIZE {
5129DCP_GRPH_DFQ_SIZE_DEEP1                  = 0x00000000,
5130DCP_GRPH_DFQ_SIZE_DEEP2                  = 0x00000001,
5131DCP_GRPH_DFQ_SIZE_DEEP3                  = 0x00000002,
5132DCP_GRPH_DFQ_SIZE_DEEP4                  = 0x00000003,
5133DCP_GRPH_DFQ_SIZE_DEEP5                  = 0x00000004,
5134DCP_GRPH_DFQ_SIZE_DEEP6                  = 0x00000005,
5135DCP_GRPH_DFQ_SIZE_DEEP7                  = 0x00000006,
5136DCP_GRPH_DFQ_SIZE_DEEP8                  = 0x00000007,
5137} DCP_GRPH_DFQ_SIZE;
5138
5139/*
5140 * DCP_GRPH_DFQ_MIN_FREE_ENTRIES enum
5141 */
5142
5143typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
5144DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1          = 0x00000000,
5145DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2          = 0x00000001,
5146DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3          = 0x00000002,
5147DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4          = 0x00000003,
5148DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5          = 0x00000004,
5149DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6          = 0x00000005,
5150DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7          = 0x00000006,
5151DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8          = 0x00000007,
5152} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
5153
5154/*
5155 * DCP_GRPH_DFQ_RESET_ACK enum
5156 */
5157
5158typedef enum DCP_GRPH_DFQ_RESET_ACK {
5159DCP_GRPH_DFQ_RESET_ACK_FALSE             = 0x00000000,
5160DCP_GRPH_DFQ_RESET_ACK_TRUE              = 0x00000001,
5161} DCP_GRPH_DFQ_RESET_ACK;
5162
5163/*
5164 * DCP_GRPH_PFLIP_INT_CLEAR enum
5165 */
5166
5167typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
5168DCP_GRPH_PFLIP_INT_CLEAR_FALSE           = 0x00000000,
5169DCP_GRPH_PFLIP_INT_CLEAR_TRUE            = 0x00000001,
5170} DCP_GRPH_PFLIP_INT_CLEAR;
5171
5172/*
5173 * DCP_GRPH_PFLIP_INT_MASK enum
5174 */
5175
5176typedef enum DCP_GRPH_PFLIP_INT_MASK {
5177DCP_GRPH_PFLIP_INT_MASK_FALSE            = 0x00000000,
5178DCP_GRPH_PFLIP_INT_MASK_TRUE             = 0x00000001,
5179} DCP_GRPH_PFLIP_INT_MASK;
5180
5181/*
5182 * DCP_GRPH_PFLIP_INT_TYPE enum
5183 */
5184
5185typedef enum DCP_GRPH_PFLIP_INT_TYPE {
5186DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL     = 0x00000000,
5187DCP_GRPH_PFLIP_INT_TYPE_PULSE            = 0x00000001,
5188} DCP_GRPH_PFLIP_INT_TYPE;
5189
5190/*
5191 * DCP_GRPH_PRESCALE_SELECT enum
5192 */
5193
5194typedef enum DCP_GRPH_PRESCALE_SELECT {
5195DCP_GRPH_PRESCALE_SELECT_FIXED           = 0x00000000,
5196DCP_GRPH_PRESCALE_SELECT_FLOATING        = 0x00000001,
5197} DCP_GRPH_PRESCALE_SELECT;
5198
5199/*
5200 * DCP_GRPH_PRESCALE_R_SIGN enum
5201 */
5202
5203typedef enum DCP_GRPH_PRESCALE_R_SIGN {
5204DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED        = 0x00000000,
5205DCP_GRPH_PRESCALE_R_SIGN_SIGNED          = 0x00000001,
5206} DCP_GRPH_PRESCALE_R_SIGN;
5207
5208/*
5209 * DCP_GRPH_PRESCALE_G_SIGN enum
5210 */
5211
5212typedef enum DCP_GRPH_PRESCALE_G_SIGN {
5213DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED        = 0x00000000,
5214DCP_GRPH_PRESCALE_G_SIGN_SIGNED          = 0x00000001,
5215} DCP_GRPH_PRESCALE_G_SIGN;
5216
5217/*
5218 * DCP_GRPH_PRESCALE_B_SIGN enum
5219 */
5220
5221typedef enum DCP_GRPH_PRESCALE_B_SIGN {
5222DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED        = 0x00000000,
5223DCP_GRPH_PRESCALE_B_SIGN_SIGNED          = 0x00000001,
5224} DCP_GRPH_PRESCALE_B_SIGN;
5225
5226/*
5227 * DCP_GRPH_PRESCALE_BYPASS enum
5228 */
5229
5230typedef enum DCP_GRPH_PRESCALE_BYPASS {
5231DCP_GRPH_PRESCALE_BYPASS_FALSE           = 0x00000000,
5232DCP_GRPH_PRESCALE_BYPASS_TRUE            = 0x00000001,
5233} DCP_GRPH_PRESCALE_BYPASS;
5234
5235/*
5236 * DCP_INPUT_CSC_GRPH_MODE enum
5237 */
5238
5239typedef enum DCP_INPUT_CSC_GRPH_MODE {
5240DCP_INPUT_CSC_GRPH_MODE_BYPASS           = 0x00000000,
5241DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF   = 0x00000001,
5242DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF      = 0x00000002,
5243DCP_INPUT_CSC_GRPH_MODE_RESERVED         = 0x00000003,
5244} DCP_INPUT_CSC_GRPH_MODE;
5245
5246/*
5247 * DCP_OUTPUT_CSC_GRPH_MODE enum
5248 */
5249
5250typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
5251DCP_OUTPUT_CSC_GRPH_MODE_BYPASS          = 0x00000000,
5252DCP_OUTPUT_CSC_GRPH_MODE_RGB             = 0x00000001,
5253DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601        = 0x00000002,
5254DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709        = 0x00000003,
5255DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF  = 0x00000004,
5256DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF     = 0x00000005,
5257DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0       = 0x00000006,
5258DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1       = 0x00000007,
5259} DCP_OUTPUT_CSC_GRPH_MODE;
5260
5261/*
5262 * DCP_DENORM_MODE enum
5263 */
5264
5265typedef enum DCP_DENORM_MODE {
5266DCP_DENORM_MODE_UNITY                    = 0x00000000,
5267DCP_DENORM_MODE_6BIT                     = 0x00000001,
5268DCP_DENORM_MODE_8BIT                     = 0x00000002,
5269DCP_DENORM_MODE_10BIT                    = 0x00000003,
5270DCP_DENORM_MODE_11BIT                    = 0x00000004,
5271DCP_DENORM_MODE_12BIT                    = 0x00000005,
5272DCP_DENORM_MODE_RESERVED0                = 0x00000006,
5273DCP_DENORM_MODE_RESERVED1                = 0x00000007,
5274} DCP_DENORM_MODE;
5275
5276/*
5277 * DCP_DENORM_14BIT_OUT enum
5278 */
5279
5280typedef enum DCP_DENORM_14BIT_OUT {
5281DCP_DENORM_14BIT_OUT_FALSE               = 0x00000000,
5282DCP_DENORM_14BIT_OUT_TRUE                = 0x00000001,
5283} DCP_DENORM_14BIT_OUT;
5284
5285/*
5286 * DCP_OUT_ROUND_TRUNC_MODE enum
5287 */
5288
5289typedef enum DCP_OUT_ROUND_TRUNC_MODE {
5290DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12     = 0x00000000,
5291DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11     = 0x00000001,
5292DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10     = 0x00000002,
5293DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9      = 0x00000003,
5294DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8      = 0x00000004,
5295DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED  = 0x00000005,
5296DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14     = 0x00000006,
5297DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13     = 0x00000007,
5298DCP_OUT_ROUND_TRUNC_MODE_ROUND_12        = 0x00000008,
5299DCP_OUT_ROUND_TRUNC_MODE_ROUND_11        = 0x00000009,
5300DCP_OUT_ROUND_TRUNC_MODE_ROUND_10        = 0x0000000a,
5301DCP_OUT_ROUND_TRUNC_MODE_ROUND_9         = 0x0000000b,
5302DCP_OUT_ROUND_TRUNC_MODE_ROUND_8         = 0x0000000c,
5303DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED  = 0x0000000d,
5304DCP_OUT_ROUND_TRUNC_MODE_ROUND_14        = 0x0000000e,
5305DCP_OUT_ROUND_TRUNC_MODE_ROUND_13        = 0x0000000f,
5306} DCP_OUT_ROUND_TRUNC_MODE;
5307
5308/*
5309 * DCP_KEY_MODE enum
5310 */
5311
5312typedef enum DCP_KEY_MODE {
5313DCP_KEY_MODE_ALPHA0                      = 0x00000000,
5314DCP_KEY_MODE_ALPHA1                      = 0x00000001,
5315DCP_KEY_MODE_IN_RANGE_ALPHA1             = 0x00000002,
5316DCP_KEY_MODE_IN_RANGE_ALPHA0             = 0x00000003,
5317} DCP_KEY_MODE;
5318
5319/*
5320 * DCP_GRPH_DEGAMMA_MODE enum
5321 */
5322
5323typedef enum DCP_GRPH_DEGAMMA_MODE {
5324DCP_GRPH_DEGAMMA_MODE_BYPASS             = 0x00000000,
5325DCP_GRPH_DEGAMMA_MODE_ROMA               = 0x00000001,
5326DCP_GRPH_DEGAMMA_MODE_ROMB               = 0x00000002,
5327DCP_GRPH_DEGAMMA_MODE_RESERVED           = 0x00000003,
5328} DCP_GRPH_DEGAMMA_MODE;
5329
5330/*
5331 * DCP_CURSOR_DEGAMMA_MODE enum
5332 */
5333
5334typedef enum DCP_CURSOR_DEGAMMA_MODE {
5335DCP_CURSOR_DEGAMMA_MODE_BYPASS           = 0x00000000,
5336DCP_CURSOR_DEGAMMA_MODE_ROMA             = 0x00000001,
5337DCP_CURSOR_DEGAMMA_MODE_ROMB             = 0x00000002,
5338DCP_CURSOR_DEGAMMA_MODE_RESERVED         = 0x00000003,
5339} DCP_CURSOR_DEGAMMA_MODE;
5340
5341/*
5342 * DCP_GRPH_GAMUT_REMAP_MODE enum
5343 */
5344
5345typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
5346DCP_GRPH_GAMUT_REMAP_MODE_BYPASS         = 0x00000000,
5347DCP_GRPH_GAMUT_REMAP_MODE_ROMA           = 0x00000001,
5348DCP_GRPH_GAMUT_REMAP_MODE_ROMB           = 0x00000002,
5349DCP_GRPH_GAMUT_REMAP_MODE_RESERVED       = 0x00000003,
5350} DCP_GRPH_GAMUT_REMAP_MODE;
5351
5352/*
5353 * DCP_SPATIAL_DITHER_EN enum
5354 */
5355
5356typedef enum DCP_SPATIAL_DITHER_EN {
5357DCP_SPATIAL_DITHER_EN_FALSE              = 0x00000000,
5358DCP_SPATIAL_DITHER_EN_TRUE               = 0x00000001,
5359} DCP_SPATIAL_DITHER_EN;
5360
5361/*
5362 * DCP_SPATIAL_DITHER_MODE enum
5363 */
5364
5365typedef enum DCP_SPATIAL_DITHER_MODE {
5366DCP_SPATIAL_DITHER_MODE_BYPASS           = 0x00000000,
5367DCP_SPATIAL_DITHER_MODE_ROMA             = 0x00000001,
5368DCP_SPATIAL_DITHER_MODE_ROMB             = 0x00000002,
5369DCP_SPATIAL_DITHER_MODE_RESERVED         = 0x00000003,
5370} DCP_SPATIAL_DITHER_MODE;
5371
5372/*
5373 * DCP_SPATIAL_DITHER_DEPTH enum
5374 */
5375
5376typedef enum DCP_SPATIAL_DITHER_DEPTH {
5377DCP_SPATIAL_DITHER_DEPTH_30BPP           = 0x00000000,
5378DCP_SPATIAL_DITHER_DEPTH_24BPP           = 0x00000001,
5379DCP_SPATIAL_DITHER_DEPTH_36BPP           = 0x00000002,
5380DCP_SPATIAL_DITHER_DEPTH_UNDEFINED       = 0x00000003,
5381} DCP_SPATIAL_DITHER_DEPTH;
5382
5383/*
5384 * DCP_FRAME_RANDOM_ENABLE enum
5385 */
5386
5387typedef enum DCP_FRAME_RANDOM_ENABLE {
5388DCP_FRAME_RANDOM_ENABLE_FALSE            = 0x00000000,
5389DCP_FRAME_RANDOM_ENABLE_TRUE             = 0x00000001,
5390} DCP_FRAME_RANDOM_ENABLE;
5391
5392/*
5393 * DCP_RGB_RANDOM_ENABLE enum
5394 */
5395
5396typedef enum DCP_RGB_RANDOM_ENABLE {
5397DCP_RGB_RANDOM_ENABLE_FALSE              = 0x00000000,
5398DCP_RGB_RANDOM_ENABLE_TRUE               = 0x00000001,
5399} DCP_RGB_RANDOM_ENABLE;
5400
5401/*
5402 * DCP_HIGHPASS_RANDOM_ENABLE enum
5403 */
5404
5405typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
5406DCP_HIGHPASS_RANDOM_ENABLE_FALSE         = 0x00000000,
5407DCP_HIGHPASS_RANDOM_ENABLE_TRUE          = 0x00000001,
5408} DCP_HIGHPASS_RANDOM_ENABLE;
5409
5410/*
5411 * DCP_CURSOR_EN enum
5412 */
5413
5414typedef enum DCP_CURSOR_EN {
5415DCP_CURSOR_EN_FALSE                      = 0x00000000,
5416DCP_CURSOR_EN_TRUE                       = 0x00000001,
5417} DCP_CURSOR_EN;
5418
5419/*
5420 * DCP_CUR_INV_TRANS_CLAMP enum
5421 */
5422
5423typedef enum DCP_CUR_INV_TRANS_CLAMP {
5424DCP_CUR_INV_TRANS_CLAMP_FALSE            = 0x00000000,
5425DCP_CUR_INV_TRANS_CLAMP_TRUE             = 0x00000001,
5426} DCP_CUR_INV_TRANS_CLAMP;
5427
5428/*
5429 * DCP_CURSOR_MODE enum
5430 */
5431
5432typedef enum DCP_CURSOR_MODE {
5433DCP_CURSOR_MODE_MONO_2BPP                = 0x00000000,
5434DCP_CURSOR_MODE_24BPP_1BIT               = 0x00000001,
5435DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI      = 0x00000002,
5436DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI    = 0x00000003,
5437} DCP_CURSOR_MODE;
5438
5439/*
5440 * DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM enum
5441 */
5442
5443typedef enum DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM {
5444DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_ONE  = 0x00000000,
5445DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM_TWO  = 0x00000001,
5446} DCP_CURSOR_MAX_OUTSTANDING_GROUP_NUM;
5447
5448/*
5449 * DCP_CURSOR_2X_MAGNIFY enum
5450 */
5451
5452typedef enum DCP_CURSOR_2X_MAGNIFY {
5453DCP_CURSOR_2X_MAGNIFY_FALSE              = 0x00000000,
5454DCP_CURSOR_2X_MAGNIFY_TRUE               = 0x00000001,
5455} DCP_CURSOR_2X_MAGNIFY;
5456
5457/*
5458 * DCP_CURSOR_FORCE_MC_ON enum
5459 */
5460
5461typedef enum DCP_CURSOR_FORCE_MC_ON {
5462DCP_CURSOR_FORCE_MC_ON_FALSE             = 0x00000000,
5463DCP_CURSOR_FORCE_MC_ON_TRUE              = 0x00000001,
5464} DCP_CURSOR_FORCE_MC_ON;
5465
5466/*
5467 * DCP_CURSOR_URGENT_CONTROL enum
5468 */
5469
5470typedef enum DCP_CURSOR_URGENT_CONTROL {
5471DCP_CURSOR_URGENT_CONTROL_MODE_0         = 0x00000000,
5472DCP_CURSOR_URGENT_CONTROL_MODE_1         = 0x00000001,
5473DCP_CURSOR_URGENT_CONTROL_MODE_2         = 0x00000002,
5474DCP_CURSOR_URGENT_CONTROL_MODE_3         = 0x00000003,
5475DCP_CURSOR_URGENT_CONTROL_MODE_4         = 0x00000004,
5476} DCP_CURSOR_URGENT_CONTROL;
5477
5478/*
5479 * DCP_CURSOR_UPDATE_PENDING enum
5480 */
5481
5482typedef enum DCP_CURSOR_UPDATE_PENDING {
5483DCP_CURSOR_UPDATE_PENDING_FALSE          = 0x00000000,
5484DCP_CURSOR_UPDATE_PENDING_TRUE           = 0x00000001,
5485} DCP_CURSOR_UPDATE_PENDING;
5486
5487/*
5488 * DCP_CURSOR_UPDATE_TAKEN enum
5489 */
5490
5491typedef enum DCP_CURSOR_UPDATE_TAKEN {
5492DCP_CURSOR_UPDATE_TAKEN_FALSE            = 0x00000000,
5493DCP_CURSOR_UPDATE_TAKEN_TRUE             = 0x00000001,
5494} DCP_CURSOR_UPDATE_TAKEN;
5495
5496/*
5497 * DCP_CURSOR_UPDATE_LOCK enum
5498 */
5499
5500typedef enum DCP_CURSOR_UPDATE_LOCK {
5501DCP_CURSOR_UPDATE_LOCK_FALSE             = 0x00000000,
5502DCP_CURSOR_UPDATE_LOCK_TRUE              = 0x00000001,
5503} DCP_CURSOR_UPDATE_LOCK;
5504
5505/*
5506 * DCP_CURSOR_DISABLE_MULTIPLE_UPDATE enum
5507 */
5508
5509typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
5510DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE  = 0x00000000,
5511DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE  = 0x00000001,
5512} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
5513
5514/*
5515 * DCP_CURSOR_UPDATE_STEREO_MODE enum
5516 */
5517
5518typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
5519DCP_CURSOR_UPDATE_STEREO_MODE_BOTH       = 0x00000000,
5520DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY  = 0x00000001,
5521DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED  = 0x00000002,
5522DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY  = 0x00000003,
5523} DCP_CURSOR_UPDATE_STEREO_MODE;
5524
5525/*
5526 * DCP_CUR2_INV_TRANS_CLAMP enum
5527 */
5528
5529typedef enum DCP_CUR2_INV_TRANS_CLAMP {
5530DCP_CUR2_INV_TRANS_CLAMP_FALSE           = 0x00000000,
5531DCP_CUR2_INV_TRANS_CLAMP_TRUE            = 0x00000001,
5532} DCP_CUR2_INV_TRANS_CLAMP;
5533
5534/*
5535 * DCP_CUR_REQUEST_FILTER_DIS enum
5536 */
5537
5538typedef enum DCP_CUR_REQUEST_FILTER_DIS {
5539DCP_CUR_REQUEST_FILTER_DIS_FALSE         = 0x00000000,
5540DCP_CUR_REQUEST_FILTER_DIS_TRUE          = 0x00000001,
5541} DCP_CUR_REQUEST_FILTER_DIS;
5542
5543/*
5544 * DCP_CURSOR_STEREO_EN enum
5545 */
5546
5547typedef enum DCP_CURSOR_STEREO_EN {
5548DCP_CURSOR_STEREO_EN_FALSE               = 0x00000000,
5549DCP_CURSOR_STEREO_EN_TRUE                = 0x00000001,
5550} DCP_CURSOR_STEREO_EN;
5551
5552/*
5553 * DCP_CURSOR_STEREO_OFFSET_YNX enum
5554 */
5555
5556typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
5557DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION  = 0x00000000,
5558DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION  = 0x00000001,
5559} DCP_CURSOR_STEREO_OFFSET_YNX;
5560
5561/*
5562 * DCP_DC_LUT_RW_MODE enum
5563 */
5564
5565typedef enum DCP_DC_LUT_RW_MODE {
5566DCP_DC_LUT_RW_MODE_256_ENTRY             = 0x00000000,
5567DCP_DC_LUT_RW_MODE_PWL                   = 0x00000001,
5568} DCP_DC_LUT_RW_MODE;
5569
5570/*
5571 * DCP_DC_LUT_VGA_ACCESS_ENABLE enum
5572 */
5573
5574typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
5575DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE       = 0x00000000,
5576DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE        = 0x00000001,
5577} DCP_DC_LUT_VGA_ACCESS_ENABLE;
5578
5579/*
5580 * DCP_DC_LUT_AUTOFILL enum
5581 */
5582
5583typedef enum DCP_DC_LUT_AUTOFILL {
5584DCP_DC_LUT_AUTOFILL_FALSE                = 0x00000000,
5585DCP_DC_LUT_AUTOFILL_TRUE                 = 0x00000001,
5586} DCP_DC_LUT_AUTOFILL;
5587
5588/*
5589 * DCP_DC_LUT_AUTOFILL_DONE enum
5590 */
5591
5592typedef enum DCP_DC_LUT_AUTOFILL_DONE {
5593DCP_DC_LUT_AUTOFILL_DONE_FALSE           = 0x00000000,
5594DCP_DC_LUT_AUTOFILL_DONE_TRUE            = 0x00000001,
5595} DCP_DC_LUT_AUTOFILL_DONE;
5596
5597/*
5598 * DCP_DC_LUT_INC_B enum
5599 */
5600
5601typedef enum DCP_DC_LUT_INC_B {
5602DCP_DC_LUT_INC_B_NA                      = 0x00000000,
5603DCP_DC_LUT_INC_B_2                       = 0x00000001,
5604DCP_DC_LUT_INC_B_4                       = 0x00000002,
5605DCP_DC_LUT_INC_B_8                       = 0x00000003,
5606DCP_DC_LUT_INC_B_16                      = 0x00000004,
5607DCP_DC_LUT_INC_B_32                      = 0x00000005,
5608DCP_DC_LUT_INC_B_64                      = 0x00000006,
5609DCP_DC_LUT_INC_B_128                     = 0x00000007,
5610DCP_DC_LUT_INC_B_256                     = 0x00000008,
5611DCP_DC_LUT_INC_B_512                     = 0x00000009,
5612} DCP_DC_LUT_INC_B;
5613
5614/*
5615 * DCP_DC_LUT_DATA_B_SIGNED_EN enum
5616 */
5617
5618typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
5619DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE        = 0x00000000,
5620DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE         = 0x00000001,
5621} DCP_DC_LUT_DATA_B_SIGNED_EN;
5622
5623/*
5624 * DCP_DC_LUT_DATA_B_FLOAT_POINT_EN enum
5625 */
5626
5627typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
5628DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE   = 0x00000000,
5629DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE    = 0x00000001,
5630} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
5631
5632/*
5633 * DCP_DC_LUT_DATA_B_FORMAT enum
5634 */
5635
5636typedef enum DCP_DC_LUT_DATA_B_FORMAT {
5637DCP_DC_LUT_DATA_B_FORMAT_U0P10           = 0x00000000,
5638DCP_DC_LUT_DATA_B_FORMAT_S1P10           = 0x00000001,
5639DCP_DC_LUT_DATA_B_FORMAT_U1P11           = 0x00000002,
5640DCP_DC_LUT_DATA_B_FORMAT_U0P12           = 0x00000003,
5641} DCP_DC_LUT_DATA_B_FORMAT;
5642
5643/*
5644 * DCP_DC_LUT_INC_G enum
5645 */
5646
5647typedef enum DCP_DC_LUT_INC_G {
5648DCP_DC_LUT_INC_G_NA                      = 0x00000000,
5649DCP_DC_LUT_INC_G_2                       = 0x00000001,
5650DCP_DC_LUT_INC_G_4                       = 0x00000002,
5651DCP_DC_LUT_INC_G_8                       = 0x00000003,
5652DCP_DC_LUT_INC_G_16                      = 0x00000004,
5653DCP_DC_LUT_INC_G_32                      = 0x00000005,
5654DCP_DC_LUT_INC_G_64                      = 0x00000006,
5655DCP_DC_LUT_INC_G_128                     = 0x00000007,
5656DCP_DC_LUT_INC_G_256                     = 0x00000008,
5657DCP_DC_LUT_INC_G_512                     = 0x00000009,
5658} DCP_DC_LUT_INC_G;
5659
5660/*
5661 * DCP_DC_LUT_DATA_G_SIGNED_EN enum
5662 */
5663
5664typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
5665DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE        = 0x00000000,
5666DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE         = 0x00000001,
5667} DCP_DC_LUT_DATA_G_SIGNED_EN;
5668
5669/*
5670 * DCP_DC_LUT_DATA_G_FLOAT_POINT_EN enum
5671 */
5672
5673typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
5674DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE   = 0x00000000,
5675DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE    = 0x00000001,
5676} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
5677
5678/*
5679 * DCP_DC_LUT_DATA_G_FORMAT enum
5680 */
5681
5682typedef enum DCP_DC_LUT_DATA_G_FORMAT {
5683DCP_DC_LUT_DATA_G_FORMAT_U0P10           = 0x00000000,
5684DCP_DC_LUT_DATA_G_FORMAT_S1P10           = 0x00000001,
5685DCP_DC_LUT_DATA_G_FORMAT_U1P11           = 0x00000002,
5686DCP_DC_LUT_DATA_G_FORMAT_U0P12           = 0x00000003,
5687} DCP_DC_LUT_DATA_G_FORMAT;
5688
5689/*
5690 * DCP_DC_LUT_INC_R enum
5691 */
5692
5693typedef enum DCP_DC_LUT_INC_R {
5694DCP_DC_LUT_INC_R_NA                      = 0x00000000,
5695DCP_DC_LUT_INC_R_2                       = 0x00000001,
5696DCP_DC_LUT_INC_R_4                       = 0x00000002,
5697DCP_DC_LUT_INC_R_8                       = 0x00000003,
5698DCP_DC_LUT_INC_R_16                      = 0x00000004,
5699DCP_DC_LUT_INC_R_32                      = 0x00000005,
5700DCP_DC_LUT_INC_R_64                      = 0x00000006,
5701DCP_DC_LUT_INC_R_128                     = 0x00000007,
5702DCP_DC_LUT_INC_R_256                     = 0x00000008,
5703DCP_DC_LUT_INC_R_512                     = 0x00000009,
5704} DCP_DC_LUT_INC_R;
5705
5706/*
5707 * DCP_DC_LUT_DATA_R_SIGNED_EN enum
5708 */
5709
5710typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
5711DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE        = 0x00000000,
5712DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE         = 0x00000001,
5713} DCP_DC_LUT_DATA_R_SIGNED_EN;
5714
5715/*
5716 * DCP_DC_LUT_DATA_R_FLOAT_POINT_EN enum
5717 */
5718
5719typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
5720DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE   = 0x00000000,
5721DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE    = 0x00000001,
5722} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
5723
5724/*
5725 * DCP_DC_LUT_DATA_R_FORMAT enum
5726 */
5727
5728typedef enum DCP_DC_LUT_DATA_R_FORMAT {
5729DCP_DC_LUT_DATA_R_FORMAT_U0P10           = 0x00000000,
5730DCP_DC_LUT_DATA_R_FORMAT_S1P10           = 0x00000001,
5731DCP_DC_LUT_DATA_R_FORMAT_U1P11           = 0x00000002,
5732DCP_DC_LUT_DATA_R_FORMAT_U0P12           = 0x00000003,
5733} DCP_DC_LUT_DATA_R_FORMAT;
5734
5735/*
5736 * DCP_CRC_ENABLE enum
5737 */
5738
5739typedef enum DCP_CRC_ENABLE {
5740DCP_CRC_ENABLE_FALSE                     = 0x00000000,
5741DCP_CRC_ENABLE_TRUE                      = 0x00000001,
5742} DCP_CRC_ENABLE;
5743
5744/*
5745 * DCP_CRC_SOURCE_SEL enum
5746 */
5747
5748typedef enum DCP_CRC_SOURCE_SEL {
5749DCP_CRC_SOURCE_SEL_OUTPUT_PIX            = 0x00000000,
5750DCP_CRC_SOURCE_SEL_INPUT_L32             = 0x00000001,
5751DCP_CRC_SOURCE_SEL_INPUT_H32             = 0x00000002,
5752DCP_CRC_SOURCE_SEL_OUTPUT_CNTL           = 0x00000004,
5753} DCP_CRC_SOURCE_SEL;
5754
5755/*
5756 * DCP_CRC_LINE_SEL enum
5757 */
5758
5759typedef enum DCP_CRC_LINE_SEL {
5760DCP_CRC_LINE_SEL_RESERVED                = 0x00000000,
5761DCP_CRC_LINE_SEL_EVEN                    = 0x00000001,
5762DCP_CRC_LINE_SEL_ODD                     = 0x00000002,
5763DCP_CRC_LINE_SEL_BOTH                    = 0x00000003,
5764} DCP_CRC_LINE_SEL;
5765
5766/*
5767 * DCP_GRPH_FLIP_RATE enum
5768 */
5769
5770typedef enum DCP_GRPH_FLIP_RATE {
5771DCP_GRPH_FLIP_RATE_1FRAME                = 0x00000000,
5772DCP_GRPH_FLIP_RATE_2FRAME                = 0x00000001,
5773DCP_GRPH_FLIP_RATE_3FRAME                = 0x00000002,
5774DCP_GRPH_FLIP_RATE_4FRAME                = 0x00000003,
5775DCP_GRPH_FLIP_RATE_5FRAME                = 0x00000004,
5776DCP_GRPH_FLIP_RATE_6FRAME                = 0x00000005,
5777DCP_GRPH_FLIP_RATE_7FRAME                = 0x00000006,
5778DCP_GRPH_FLIP_RATE_8FRAME                = 0x00000007,
5779} DCP_GRPH_FLIP_RATE;
5780
5781/*
5782 * DCP_GRPH_FLIP_RATE_ENABLE enum
5783 */
5784
5785typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
5786DCP_GRPH_FLIP_RATE_ENABLE_FALSE          = 0x00000000,
5787DCP_GRPH_FLIP_RATE_ENABLE_TRUE           = 0x00000001,
5788} DCP_GRPH_FLIP_RATE_ENABLE;
5789
5790/*
5791 * DCP_GSL0_EN enum
5792 */
5793
5794typedef enum DCP_GSL0_EN {
5795DCP_GSL0_EN_FALSE                        = 0x00000000,
5796DCP_GSL0_EN_TRUE                         = 0x00000001,
5797} DCP_GSL0_EN;
5798
5799/*
5800 * DCP_GSL1_EN enum
5801 */
5802
5803typedef enum DCP_GSL1_EN {
5804DCP_GSL1_EN_FALSE                        = 0x00000000,
5805DCP_GSL1_EN_TRUE                         = 0x00000001,
5806} DCP_GSL1_EN;
5807
5808/*
5809 * DCP_GSL2_EN enum
5810 */
5811
5812typedef enum DCP_GSL2_EN {
5813DCP_GSL2_EN_FALSE                        = 0x00000000,
5814DCP_GSL2_EN_TRUE                         = 0x00000001,
5815} DCP_GSL2_EN;
5816
5817/*
5818 * DCP_GSL_MASTER_EN enum
5819 */
5820
5821typedef enum DCP_GSL_MASTER_EN {
5822DCP_GSL_MASTER_EN_FALSE                  = 0x00000000,
5823DCP_GSL_MASTER_EN_TRUE                   = 0x00000001,
5824} DCP_GSL_MASTER_EN;
5825
5826/*
5827 * DCP_GSL_XDMA_GROUP enum
5828 */
5829
5830typedef enum DCP_GSL_XDMA_GROUP {
5831DCP_GSL_XDMA_GROUP_VSYNC                 = 0x00000000,
5832DCP_GSL_XDMA_GROUP_HSYNC0                = 0x00000001,
5833DCP_GSL_XDMA_GROUP_HSYNC1                = 0x00000002,
5834DCP_GSL_XDMA_GROUP_HSYNC2                = 0x00000003,
5835} DCP_GSL_XDMA_GROUP;
5836
5837/*
5838 * DCP_GSL_XDMA_GROUP_UNDERFLOW_EN enum
5839 */
5840
5841typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
5842DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE    = 0x00000000,
5843DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE     = 0x00000001,
5844} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
5845
5846/*
5847 * DCP_GSL_SYNC_SOURCE enum
5848 */
5849
5850typedef enum DCP_GSL_SYNC_SOURCE {
5851DCP_GSL_SYNC_SOURCE_FLIP                 = 0x00000000,
5852DCP_GSL_SYNC_SOURCE_PHASE0               = 0x00000001,
5853DCP_GSL_SYNC_SOURCE_RESET                = 0x00000002,
5854DCP_GSL_SYNC_SOURCE_PHASE1               = 0x00000003,
5855} DCP_GSL_SYNC_SOURCE;
5856
5857/*
5858 * DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC enum
5859 */
5860
5861typedef enum DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC {
5862DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_DIS  = 0x00000000,
5863DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC_EN  = 0x00000001,
5864} DCP_GSL_USE_CHECKPOINT_WINDOW_IN_VSYNC;
5865
5866/*
5867 * DCP_GSL_DELAY_SURFACE_UPDATE_PENDING enum
5868 */
5869
5870typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
5871DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE  = 0x00000000,
5872DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE  = 0x00000001,
5873} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
5874
5875/*
5876 * DCP_TEST_DEBUG_WRITE_EN enum
5877 */
5878
5879typedef enum DCP_TEST_DEBUG_WRITE_EN {
5880DCP_TEST_DEBUG_WRITE_EN_FALSE            = 0x00000000,
5881DCP_TEST_DEBUG_WRITE_EN_TRUE             = 0x00000001,
5882} DCP_TEST_DEBUG_WRITE_EN;
5883
5884/*
5885 * DCP_GRPH_STEREOSYNC_FLIP_EN enum
5886 */
5887
5888typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
5889DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE        = 0x00000000,
5890DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE         = 0x00000001,
5891} DCP_GRPH_STEREOSYNC_FLIP_EN;
5892
5893/*
5894 * DCP_GRPH_STEREOSYNC_FLIP_MODE enum
5895 */
5896
5897typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
5898DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP       = 0x00000000,
5899DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0     = 0x00000001,
5900DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET      = 0x00000002,
5901DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1     = 0x00000003,
5902} DCP_GRPH_STEREOSYNC_FLIP_MODE;
5903
5904/*
5905 * DCP_GRPH_STEREOSYNC_SELECT_DISABLE enum
5906 */
5907
5908typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
5909DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE  = 0x00000000,
5910DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE  = 0x00000001,
5911} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
5912
5913/*
5914 * DCP_GRPH_ROTATION_ANGLE enum
5915 */
5916
5917typedef enum DCP_GRPH_ROTATION_ANGLE {
5918DCP_GRPH_ROTATION_ANGLE_0                = 0x00000000,
5919DCP_GRPH_ROTATION_ANGLE_90               = 0x00000001,
5920DCP_GRPH_ROTATION_ANGLE_180              = 0x00000002,
5921DCP_GRPH_ROTATION_ANGLE_270              = 0x00000003,
5922} DCP_GRPH_ROTATION_ANGLE;
5923
5924/*
5925 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN enum
5926 */
5927
5928typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
5929DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE  = 0x00000000,
5930DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE  = 0x00000001,
5931} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
5932
5933/*
5934 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE enum
5935 */
5936
5937typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
5938DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM  = 0x00000000,
5939DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE  = 0x00000001,
5940} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
5941
5942/*
5943 * DCP_GRPH_REGAMMA_MODE enum
5944 */
5945
5946typedef enum DCP_GRPH_REGAMMA_MODE {
5947DCP_GRPH_REGAMMA_MODE_BYPASS             = 0x00000000,
5948DCP_GRPH_REGAMMA_MODE_SRGB               = 0x00000001,
5949DCP_GRPH_REGAMMA_MODE_XVYCC              = 0x00000002,
5950DCP_GRPH_REGAMMA_MODE_PROGA              = 0x00000003,
5951DCP_GRPH_REGAMMA_MODE_PROGB              = 0x00000004,
5952} DCP_GRPH_REGAMMA_MODE;
5953
5954/*
5955 * DCP_ALPHA_ROUND_TRUNC_MODE enum
5956 */
5957
5958typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
5959DCP_ALPHA_ROUND_TRUNC_MODE_ROUND         = 0x00000000,
5960DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC         = 0x00000001,
5961} DCP_ALPHA_ROUND_TRUNC_MODE;
5962
5963/*
5964 * DCP_CURSOR_ALPHA_BLND_ENA enum
5965 */
5966
5967typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
5968DCP_CURSOR_ALPHA_BLND_ENA_FALSE          = 0x00000000,
5969DCP_CURSOR_ALPHA_BLND_ENA_TRUE           = 0x00000001,
5970} DCP_CURSOR_ALPHA_BLND_ENA;
5971
5972/*
5973 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK enum
5974 */
5975
5976typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
5977DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE  = 0x00000000,
5978DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE  = 0x00000001,
5979} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
5980
5981/*
5982 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK enum
5983 */
5984
5985typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
5986DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE = 0x00000000,
5987DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE  = 0x00000001,
5988} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
5989
5990/*
5991 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK enum
5992 */
5993
5994typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
5995DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE  = 0x00000000,
5996DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE  = 0x00000001,
5997} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
5998
5999/*
6000 * DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK enum

6001 */
6002
6003typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
6004DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6005DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE  = 0x00000001,
6006} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
6007
6008/*
6009 * DCP_GRPH_SURFACE_COUNTER_EN enum
6010 */
6011
6012typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
6013DCP_GRPH_SURFACE_COUNTER_EN_DISABLE      = 0x00000000,
6014DCP_GRPH_SURFACE_COUNTER_EN_ENABLE       = 0x00000001,
6015} DCP_GRPH_SURFACE_COUNTER_EN;
6016
6017/*
6018 * DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT enum
6019 */
6020
6021typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
6022DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0  = 0x00000000,
6023DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1  = 0x00000001,
6024DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2  = 0x00000002,
6025DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3  = 0x00000003,
6026DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4  = 0x00000004,
6027DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5  = 0x00000005,
6028DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6  = 0x00000006,
6029DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7  = 0x00000007,
6030DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8  = 0x00000008,
6031DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9  = 0x00000009,
6032DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10  = 0x0000000a,
6033DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11  = 0x0000000b,
6034} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
6035
6036/*
6037 * DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED enum
6038 */
6039
6040typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
6041DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO  = 0x00000000,
6042DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES  = 0x00000001,
6043} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
6044
6045/*
6046 * DCP_GRPH_XDMA_FLIP_TYPE_CLEAR enum
6047 */
6048
6049typedef enum DCP_GRPH_XDMA_FLIP_TYPE_CLEAR {
6050DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_DISABLE    = 0x00000000,
6051DCP_GRPH_XDMA_FLIP_TYPE_CLEAR_ENABLE     = 0x00000001,
6052} DCP_GRPH_XDMA_FLIP_TYPE_CLEAR;
6053
6054/*
6055 * DCP_GRPH_XDMA_DRR_MODE_ENABLE enum
6056 */
6057
6058typedef enum DCP_GRPH_XDMA_DRR_MODE_ENABLE {
6059DCP_GRPH_XDMA_DRR_MODE_ENABLE_DISABLE    = 0x00000000,
6060DCP_GRPH_XDMA_DRR_MODE_ENABLE_ENABLE     = 0x00000001,
6061} DCP_GRPH_XDMA_DRR_MODE_ENABLE;
6062
6063/*
6064 * DCP_GRPH_XDMA_MULTIFLIP_ENABLE enum
6065 */
6066
6067typedef enum DCP_GRPH_XDMA_MULTIFLIP_ENABLE {
6068DCP_GRPH_XDMA_MULTIFLIP_ENABLE_DISABLE   = 0x00000000,
6069DCP_GRPH_XDMA_MULTIFLIP_ENABLE_ENABLE    = 0x00000001,
6070} DCP_GRPH_XDMA_MULTIFLIP_ENABLE;
6071
6072/*
6073 * DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK enum
6074 */
6075
6076typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK {
6077DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_FALSE    = 0x00000000,
6078DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK_TRUE     = 0x00000001,
6079} DCP_GRPH_XDMA_FLIP_TIMEOUT_MASK;
6080
6081/*
6082 * DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK enum
6083 */
6084
6085typedef enum DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK {
6086DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_FALSE     = 0x00000000,
6087DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK_TRUE      = 0x00000001,
6088} DCP_GRPH_XDMA_FLIP_TIMEOUT_ACK;
6089
6090/*******************************************************
6091 * DC_PERFMON Enums
6092 *******************************************************/
6093
6094/*
6095 * PERFCOUNTER_CVALUE_SEL enum
6096 */
6097
6098typedef enum PERFCOUNTER_CVALUE_SEL {
6099PERFCOUNTER_CVALUE_SEL_47_0              = 0x00000000,
6100PERFCOUNTER_CVALUE_SEL_15_0              = 0x00000001,
6101PERFCOUNTER_CVALUE_SEL_31_16             = 0x00000002,
6102PERFCOUNTER_CVALUE_SEL_47_32             = 0x00000003,
6103PERFCOUNTER_CVALUE_SEL_11_0              = 0x00000004,
6104PERFCOUNTER_CVALUE_SEL_23_12             = 0x00000005,
6105PERFCOUNTER_CVALUE_SEL_35_24             = 0x00000006,
6106PERFCOUNTER_CVALUE_SEL_47_36             = 0x00000007,
6107} PERFCOUNTER_CVALUE_SEL;
6108
6109/*
6110 * PERFCOUNTER_INC_MODE enum
6111 */
6112
6113typedef enum PERFCOUNTER_INC_MODE {
6114PERFCOUNTER_INC_MODE_MULTI_BIT           = 0x00000000,
6115PERFCOUNTER_INC_MODE_BOTH_EDGE           = 0x00000001,
6116PERFCOUNTER_INC_MODE_LSB                 = 0x00000002,
6117PERFCOUNTER_INC_MODE_POS_EDGE            = 0x00000003,
6118PERFCOUNTER_INC_MODE_NEG_EDGE            = 0x00000004,
6119} PERFCOUNTER_INC_MODE;
6120
6121/*
6122 * PERFCOUNTER_HW_CNTL_SEL enum
6123 */
6124
6125typedef enum PERFCOUNTER_HW_CNTL_SEL {
6126PERFCOUNTER_HW_CNTL_SEL_RUNEN            = 0x00000000,
6127PERFCOUNTER_HW_CNTL_SEL_CNTOFF           = 0x00000001,
6128} PERFCOUNTER_HW_CNTL_SEL;
6129
6130/*
6131 * PERFCOUNTER_RUNEN_MODE enum
6132 */
6133
6134typedef enum PERFCOUNTER_RUNEN_MODE {
6135PERFCOUNTER_RUNEN_MODE_LEVEL             = 0x00000000,
6136PERFCOUNTER_RUNEN_MODE_EDGE              = 0x00000001,
6137} PERFCOUNTER_RUNEN_MODE;
6138
6139/*
6140 * PERFCOUNTER_CNTOFF_START_DIS enum
6141 */
6142
6143typedef enum PERFCOUNTER_CNTOFF_START_DIS {
6144PERFCOUNTER_CNTOFF_START_ENABLE          = 0x00000000,
6145PERFCOUNTER_CNTOFF_START_DISABLE         = 0x00000001,
6146} PERFCOUNTER_CNTOFF_START_DIS;
6147
6148/*
6149 * PERFCOUNTER_RESTART_EN enum
6150 */
6151
6152typedef enum PERFCOUNTER_RESTART_EN {
6153PERFCOUNTER_RESTART_DISABLE              = 0x00000000,
6154PERFCOUNTER_RESTART_ENABLE               = 0x00000001,
6155} PERFCOUNTER_RESTART_EN;
6156
6157/*
6158 * PERFCOUNTER_INT_EN enum
6159 */
6160
6161typedef enum PERFCOUNTER_INT_EN {
6162PERFCOUNTER_INT_DISABLE                  = 0x00000000,
6163PERFCOUNTER_INT_ENABLE                   = 0x00000001,
6164} PERFCOUNTER_INT_EN;
6165
6166/*
6167 * PERFCOUNTER_OFF_MASK enum
6168 */
6169
6170typedef enum PERFCOUNTER_OFF_MASK {
6171PERFCOUNTER_OFF_MASK_DISABLE             = 0x00000000,
6172PERFCOUNTER_OFF_MASK_ENABLE              = 0x00000001,
6173} PERFCOUNTER_OFF_MASK;
6174
6175/*
6176 * PERFCOUNTER_ACTIVE enum
6177 */
6178
6179typedef enum PERFCOUNTER_ACTIVE {
6180PERFCOUNTER_IS_IDLE                      = 0x00000000,
6181PERFCOUNTER_IS_ACTIVE                    = 0x00000001,
6182} PERFCOUNTER_ACTIVE;
6183
6184/*
6185 * PERFCOUNTER_INT_TYPE enum
6186 */
6187
6188typedef enum PERFCOUNTER_INT_TYPE {
6189PERFCOUNTER_INT_TYPE_LEVEL               = 0x00000000,
6190PERFCOUNTER_INT_TYPE_PULSE               = 0x00000001,
6191} PERFCOUNTER_INT_TYPE;
6192
6193/*
6194 * PERFCOUNTER_COUNTED_VALUE_TYPE enum
6195 */
6196
6197typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
6198PERFCOUNTER_COUNTED_VALUE_TYPE_ACC       = 0x00000000,
6199PERFCOUNTER_COUNTED_VALUE_TYPE_MAX       = 0x00000001,
6200PERFCOUNTER_COUNTED_VALUE_TYPE_MIN       = 0x00000002,
6201} PERFCOUNTER_COUNTED_VALUE_TYPE;
6202
6203/*
6204 * PERFCOUNTER_CNTL_SEL enum
6205 */
6206
6207typedef enum PERFCOUNTER_CNTL_SEL {
6208PERFCOUNTER_CNTL_SEL_0                   = 0x00000000,
6209PERFCOUNTER_CNTL_SEL_1                   = 0x00000001,
6210PERFCOUNTER_CNTL_SEL_2                   = 0x00000002,
6211PERFCOUNTER_CNTL_SEL_3                   = 0x00000003,
6212PERFCOUNTER_CNTL_SEL_4                   = 0x00000004,
6213PERFCOUNTER_CNTL_SEL_5                   = 0x00000005,
6214PERFCOUNTER_CNTL_SEL_6                   = 0x00000006,
6215PERFCOUNTER_CNTL_SEL_7                   = 0x00000007,
6216} PERFCOUNTER_CNTL_SEL;
6217
6218/*
6219 * PERFCOUNTER_CNT0_STATE enum
6220 */
6221
6222typedef enum PERFCOUNTER_CNT0_STATE {
6223PERFCOUNTER_CNT0_STATE_RESET             = 0x00000000,
6224PERFCOUNTER_CNT0_STATE_START             = 0x00000001,
6225PERFCOUNTER_CNT0_STATE_FREEZE            = 0x00000002,
6226PERFCOUNTER_CNT0_STATE_HW                = 0x00000003,
6227} PERFCOUNTER_CNT0_STATE;
6228
6229/*
6230 * PERFCOUNTER_STATE_SEL0 enum
6231 */
6232
6233typedef enum PERFCOUNTER_STATE_SEL0 {
6234PERFCOUNTER_STATE_SEL0_GLOBAL            = 0x00000000,
6235PERFCOUNTER_STATE_SEL0_LOCAL             = 0x00000001,
6236} PERFCOUNTER_STATE_SEL0;
6237
6238/*
6239 * PERFCOUNTER_CNT1_STATE enum
6240 */
6241
6242typedef enum PERFCOUNTER_CNT1_STATE {
6243PERFCOUNTER_CNT1_STATE_RESET             = 0x00000000,
6244PERFCOUNTER_CNT1_STATE_START             = 0x00000001,
6245PERFCOUNTER_CNT1_STATE_FREEZE            = 0x00000002,
6246PERFCOUNTER_CNT1_STATE_HW                = 0x00000003,
6247} PERFCOUNTER_CNT1_STATE;
6248
6249/*
6250 * PERFCOUNTER_STATE_SEL1 enum
6251 */
6252
6253typedef enum PERFCOUNTER_STATE_SEL1 {
6254PERFCOUNTER_STATE_SEL1_GLOBAL            = 0x00000000,
6255PERFCOUNTER_STATE_SEL1_LOCAL             = 0x00000001,
6256} PERFCOUNTER_STATE_SEL1;
6257
6258/*
6259 * PERFCOUNTER_CNT2_STATE enum
6260 */
6261
6262typedef enum PERFCOUNTER_CNT2_STATE {
6263PERFCOUNTER_CNT2_STATE_RESET             = 0x00000000,
6264PERFCOUNTER_CNT2_STATE_START             = 0x00000001,
6265PERFCOUNTER_CNT2_STATE_FREEZE            = 0x00000002,
6266PERFCOUNTER_CNT2_STATE_HW                = 0x00000003,
6267} PERFCOUNTER_CNT2_STATE;
6268
6269/*
6270 * PERFCOUNTER_STATE_SEL2 enum
6271 */
6272
6273typedef enum PERFCOUNTER_STATE_SEL2 {
6274PERFCOUNTER_STATE_SEL2_GLOBAL            = 0x00000000,
6275PERFCOUNTER_STATE_SEL2_LOCAL             = 0x00000001,
6276} PERFCOUNTER_STATE_SEL2;
6277
6278/*
6279 * PERFCOUNTER_CNT3_STATE enum
6280 */
6281
6282typedef enum PERFCOUNTER_CNT3_STATE {
6283PERFCOUNTER_CNT3_STATE_RESET             = 0x00000000,
6284PERFCOUNTER_CNT3_STATE_START             = 0x00000001,
6285PERFCOUNTER_CNT3_STATE_FREEZE            = 0x00000002,
6286PERFCOUNTER_CNT3_STATE_HW                = 0x00000003,
6287} PERFCOUNTER_CNT3_STATE;
6288
6289/*
6290 * PERFCOUNTER_STATE_SEL3 enum
6291 */
6292
6293typedef enum PERFCOUNTER_STATE_SEL3 {
6294PERFCOUNTER_STATE_SEL3_GLOBAL            = 0x00000000,
6295PERFCOUNTER_STATE_SEL3_LOCAL             = 0x00000001,
6296} PERFCOUNTER_STATE_SEL3;
6297
6298/*
6299 * PERFCOUNTER_CNT4_STATE enum
6300 */
6301
6302typedef enum PERFCOUNTER_CNT4_STATE {
6303PERFCOUNTER_CNT4_STATE_RESET             = 0x00000000,
6304PERFCOUNTER_CNT4_STATE_START             = 0x00000001,
6305PERFCOUNTER_CNT4_STATE_FREEZE            = 0x00000002,
6306PERFCOUNTER_CNT4_STATE_HW                = 0x00000003,
6307} PERFCOUNTER_CNT4_STATE;
6308
6309/*
6310 * PERFCOUNTER_STATE_SEL4 enum
6311 */
6312
6313typedef enum PERFCOUNTER_STATE_SEL4 {
6314PERFCOUNTER_STATE_SEL4_GLOBAL            = 0x00000000,
6315PERFCOUNTER_STATE_SEL4_LOCAL             = 0x00000001,
6316} PERFCOUNTER_STATE_SEL4;
6317
6318/*
6319 * PERFCOUNTER_CNT5_STATE enum
6320 */
6321
6322typedef enum PERFCOUNTER_CNT5_STATE {
6323PERFCOUNTER_CNT5_STATE_RESET             = 0x00000000,
6324PERFCOUNTER_CNT5_STATE_START             = 0x00000001,
6325PERFCOUNTER_CNT5_STATE_FREEZE            = 0x00000002,
6326PERFCOUNTER_CNT5_STATE_HW                = 0x00000003,
6327} PERFCOUNTER_CNT5_STATE;
6328
6329/*
6330 * PERFCOUNTER_STATE_SEL5 enum
6331 */
6332
6333typedef enum PERFCOUNTER_STATE_SEL5 {
6334PERFCOUNTER_STATE_SEL5_GLOBAL            = 0x00000000,
6335PERFCOUNTER_STATE_SEL5_LOCAL             = 0x00000001,
6336} PERFCOUNTER_STATE_SEL5;
6337
6338/*
6339 * PERFCOUNTER_CNT6_STATE enum
6340 */
6341
6342typedef enum PERFCOUNTER_CNT6_STATE {
6343PERFCOUNTER_CNT6_STATE_RESET             = 0x00000000,
6344PERFCOUNTER_CNT6_STATE_START             = 0x00000001,
6345PERFCOUNTER_CNT6_STATE_FREEZE            = 0x00000002,
6346PERFCOUNTER_CNT6_STATE_HW                = 0x00000003,
6347} PERFCOUNTER_CNT6_STATE;
6348
6349/*
6350 * PERFCOUNTER_STATE_SEL6 enum
6351 */
6352
6353typedef enum PERFCOUNTER_STATE_SEL6 {
6354PERFCOUNTER_STATE_SEL6_GLOBAL            = 0x00000000,
6355PERFCOUNTER_STATE_SEL6_LOCAL             = 0x00000001,
6356} PERFCOUNTER_STATE_SEL6;
6357
6358/*
6359 * PERFCOUNTER_CNT7_STATE enum
6360 */
6361
6362typedef enum PERFCOUNTER_CNT7_STATE {
6363PERFCOUNTER_CNT7_STATE_RESET             = 0x00000000,
6364PERFCOUNTER_CNT7_STATE_START             = 0x00000001,
6365PERFCOUNTER_CNT7_STATE_FREEZE            = 0x00000002,
6366PERFCOUNTER_CNT7_STATE_HW                = 0x00000003,
6367} PERFCOUNTER_CNT7_STATE;
6368
6369/*
6370 * PERFCOUNTER_STATE_SEL7 enum
6371 */
6372
6373typedef enum PERFCOUNTER_STATE_SEL7 {
6374PERFCOUNTER_STATE_SEL7_GLOBAL            = 0x00000000,
6375PERFCOUNTER_STATE_SEL7_LOCAL             = 0x00000001,
6376} PERFCOUNTER_STATE_SEL7;
6377
6378/*
6379 * PERFMON_STATE enum
6380 */
6381
6382typedef enum PERFMON_STATE {
6383PERFMON_STATE_RESET                      = 0x00000000,
6384PERFMON_STATE_START                      = 0x00000001,
6385PERFMON_STATE_FREEZE                     = 0x00000002,
6386PERFMON_STATE_HW                         = 0x00000003,
6387} PERFMON_STATE;
6388
6389/*
6390 * PERFMON_CNTOFF_AND_OR enum
6391 */
6392
6393typedef enum PERFMON_CNTOFF_AND_OR {
6394PERFMON_CNTOFF_OR                        = 0x00000000,
6395PERFMON_CNTOFF_AND                       = 0x00000001,
6396} PERFMON_CNTOFF_AND_OR;
6397
6398/*
6399 * PERFMON_CNTOFF_INT_EN enum
6400 */
6401
6402typedef enum PERFMON_CNTOFF_INT_EN {
6403PERFMON_CNTOFF_INT_DISABLE               = 0x00000000,
6404PERFMON_CNTOFF_INT_ENABLE                = 0x00000001,
6405} PERFMON_CNTOFF_INT_EN;
6406
6407/*
6408 * PERFMON_CNTOFF_INT_TYPE enum
6409 */
6410
6411typedef enum PERFMON_CNTOFF_INT_TYPE {
6412PERFMON_CNTOFF_INT_TYPE_LEVEL            = 0x00000000,
6413PERFMON_CNTOFF_INT_TYPE_PULSE            = 0x00000001,
6414} PERFMON_CNTOFF_INT_TYPE;
6415
6416/*******************************************************
6417 * SCL Enums
6418 *******************************************************/
6419
6420/*
6421 * SCL_C_RAM_TAP_PAIR_IDX enum
6422 */
6423
6424typedef enum SCL_C_RAM_TAP_PAIR_IDX {
6425SCL_C_RAM_TAP_PAIR_ID0                   = 0x00000000,
6426SCL_C_RAM_TAP_PAIR_ID1                   = 0x00000001,
6427SCL_C_RAM_TAP_PAIR_ID2                   = 0x00000002,
6428SCL_C_RAM_TAP_PAIR_ID3                   = 0x00000003,
6429SCL_C_RAM_TAP_PAIR_ID4                   = 0x00000004,
6430} SCL_C_RAM_TAP_PAIR_IDX;
6431
6432/*
6433 * SCL_C_RAM_PHASE enum
6434 */
6435
6436typedef enum SCL_C_RAM_PHASE {
6437SCL_C_RAM_PHASE_0                        = 0x00000000,
6438SCL_C_RAM_PHASE_1                        = 0x00000001,
6439SCL_C_RAM_PHASE_2                        = 0x00000002,
6440SCL_C_RAM_PHASE_3                        = 0x00000003,
6441SCL_C_RAM_PHASE_4                        = 0x00000004,
6442SCL_C_RAM_PHASE_5                        = 0x00000005,
6443SCL_C_RAM_PHASE_6                        = 0x00000006,
6444SCL_C_RAM_PHASE_7                        = 0x00000007,
6445SCL_C_RAM_PHASE_8                        = 0x00000008,
6446} SCL_C_RAM_PHASE;
6447
6448/*
6449 * SCL_C_RAM_FILTER_TYPE enum
6450 */
6451
6452typedef enum SCL_C_RAM_FILTER_TYPE {
6453SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT  = 0x00000000,
6454SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT    = 0x00000001,
6455SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT  = 0x00000002,
6456SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT    = 0x00000003,
6457} SCL_C_RAM_FILTER_TYPE;
6458
6459/*
6460 * SCL_MODE_SEL enum
6461 */
6462
6463typedef enum SCL_MODE_SEL {
6464SCL_MODE_RGB_BYPASS                      = 0x00000000,
6465SCL_MODE_RGB_SCALING                     = 0x00000001,
6466SCL_MODE_YCBCR_SCALING                   = 0x00000002,
6467SCL_MODE_YCBCR_BYPASS                    = 0x00000003,
6468} SCL_MODE_SEL;
6469
6470/*
6471 * SCL_PSCL_EN enum
6472 */
6473
6474typedef enum SCL_PSCL_EN {
6475SCL_PSCL_DISABLE                         = 0x00000000,
6476SCL_PSCL_ENANBLE                         = 0x00000001,
6477} SCL_PSCL_EN;
6478
6479/*
6480 * SCL_V_NUM_OF_TAPS enum
6481 */
6482
6483typedef enum SCL_V_NUM_OF_TAPS {
6484SCL_V_NUM_OF_TAPS_1                      = 0x00000000,
6485SCL_V_NUM_OF_TAPS_2                      = 0x00000001,
6486SCL_V_NUM_OF_TAPS_3                      = 0x00000002,
6487SCL_V_NUM_OF_TAPS_4                      = 0x00000003,
6488SCL_V_NUM_OF_TAPS_5                      = 0x00000004,
6489SCL_V_NUM_OF_TAPS_6                      = 0x00000005,
6490} SCL_V_NUM_OF_TAPS;
6491
6492/*
6493 * SCL_H_NUM_OF_TAPS enum
6494 */
6495
6496typedef enum SCL_H_NUM_OF_TAPS {
6497SCL_H_NUM_OF_TAPS_1                      = 0x00000000,
6498SCL_H_NUM_OF_TAPS_2                      = 0x00000001,
6499SCL_H_NUM_OF_TAPS_4                      = 0x00000003,
6500SCL_H_NUM_OF_TAPS_6                      = 0x00000005,
6501SCL_H_NUM_OF_TAPS_8                      = 0x00000007,
6502SCL_H_NUM_OF_TAPS_10                     = 0x00000009,
6503} SCL_H_NUM_OF_TAPS;
6504
6505/*
6506 * SCL_BOUNDARY_MODE enum
6507 */
6508
6509typedef enum SCL_BOUNDARY_MODE {
6510SCL_BOUNDARY_MODE_BLACK                  = 0x00000000,
6511SCL_BOUNDARY_MODE_EDGE                   = 0x00000001,
6512} SCL_BOUNDARY_MODE;
6513
6514/*
6515 * SCL_EARLY_EOL_MOD enum
6516 */
6517
6518typedef enum SCL_EARLY_EOL_MOD {
6519SCL_EARLY_EOL_MODE_CRTC                  = 0x00000000,
6520SCL_EARLY_EOL_MODE_INTERNAL              = 0x00000001,
6521} SCL_EARLY_EOL_MOD;
6522
6523/*
6524 * SCL_BYPASS_MODE enum
6525 */
6526
6527typedef enum SCL_BYPASS_MODE {
6528SCL_BYPASS_MODE_MC_MR                    = 0x00000000,
6529SCL_BYPASS_MODE_AC_NR                    = 0x00000001,
6530SCL_BYPASS_MODE_AC_AR                    = 0x00000002,
6531SCL_BYPASS_MODE_RESERVED                 = 0x00000003,
6532} SCL_BYPASS_MODE;
6533
6534/*
6535 * SCL_V_MANUAL_REPLICATE_FACTOR enum
6536 */
6537
6538typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
6539SCL_V_MANUAL_REPLICATE_FACTOR_1          = 0x00000000,
6540SCL_V_MANUAL_REPLICATE_FACTOR_2          = 0x00000001,
6541SCL_V_MANUAL_REPLICATE_FACTOR_3          = 0x00000002,
6542SCL_V_MANUAL_REPLICATE_FACTOR_4          = 0x00000003,
6543SCL_V_MANUAL_REPLICATE_FACTOR_5          = 0x00000004,
6544SCL_V_MANUAL_REPLICATE_FACTOR_6          = 0x00000005,
6545SCL_V_MANUAL_REPLICATE_FACTOR_7          = 0x00000006,
6546SCL_V_MANUAL_REPLICATE_FACTOR_8          = 0x00000007,
6547SCL_V_MANUAL_REPLICATE_FACTOR_9          = 0x00000008,
6548SCL_V_MANUAL_REPLICATE_FACTOR_10         = 0x00000009,
6549SCL_V_MANUAL_REPLICATE_FACTOR_11         = 0x0000000a,
6550SCL_V_MANUAL_REPLICATE_FACTOR_12         = 0x0000000b,
6551SCL_V_MANUAL_REPLICATE_FACTOR_13         = 0x0000000c,
6552SCL_V_MANUAL_REPLICATE_FACTOR_14         = 0x0000000d,
6553SCL_V_MANUAL_REPLICATE_FACTOR_15         = 0x0000000e,
6554SCL_V_MANUAL_REPLICATE_FACTOR_16         = 0x0000000f,
6555} SCL_V_MANUAL_REPLICATE_FACTOR;
6556
6557/*
6558 * SCL_H_MANUAL_REPLICATE_FACTOR enum
6559 */
6560
6561typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
6562SCL_H_MANUAL_REPLICATE_FACTOR_1          = 0x00000000,
6563SCL_H_MANUAL_REPLICATE_FACTOR_2          = 0x00000001,
6564SCL_H_MANUAL_REPLICATE_FACTOR_3          = 0x00000002,
6565SCL_H_MANUAL_REPLICATE_FACTOR_4          = 0x00000003,
6566SCL_H_MANUAL_REPLICATE_FACTOR_5          = 0x00000004,
6567SCL_H_MANUAL_REPLICATE_FACTOR_6          = 0x00000005,
6568SCL_H_MANUAL_REPLICATE_FACTOR_7          = 0x00000006,
6569SCL_H_MANUAL_REPLICATE_FACTOR_8          = 0x00000007,
6570SCL_H_MANUAL_REPLICATE_FACTOR_9          = 0x00000008,
6571SCL_H_MANUAL_REPLICATE_FACTOR_10         = 0x00000009,
6572SCL_H_MANUAL_REPLICATE_FACTOR_11         = 0x0000000a,
6573SCL_H_MANUAL_REPLICATE_FACTOR_12         = 0x0000000b,
6574SCL_H_MANUAL_REPLICATE_FACTOR_13         = 0x0000000c,
6575SCL_H_MANUAL_REPLICATE_FACTOR_14         = 0x0000000d,
6576SCL_H_MANUAL_REPLICATE_FACTOR_15         = 0x0000000e,
6577SCL_H_MANUAL_REPLICATE_FACTOR_16         = 0x0000000f,
6578} SCL_H_MANUAL_REPLICATE_FACTOR;
6579
6580/*
6581 * SCL_V_CALC_AUTO_RATIO_EN enum
6582 */
6583
6584typedef enum SCL_V_CALC_AUTO_RATIO_EN {
6585SCL_V_CALC_AUTO_RATIO_DISABLE            = 0x00000000,
6586SCL_V_CALC_AUTO_RATIO_ENABLE             = 0x00000001,
6587} SCL_V_CALC_AUTO_RATIO_EN;
6588
6589/*
6590 * SCL_H_CALC_AUTO_RATIO_EN enum
6591 */
6592
6593typedef enum SCL_H_CALC_AUTO_RATIO_EN {
6594SCL_H_CALC_AUTO_RATIO_DISABLE            = 0x00000000,
6595SCL_H_CALC_AUTO_RATIO_ENABLE             = 0x00000001,
6596} SCL_H_CALC_AUTO_RATIO_EN;
6597
6598/*
6599 * SCL_H_FILTER_PICK_NEAREST enum
6600 */
6601
6602typedef enum SCL_H_FILTER_PICK_NEAREST {
6603SCL_H_FILTER_PICK_NEAREST_DISABLE        = 0x00000000,
6604SCL_H_FILTER_PICK_NEAREST_ENABLE         = 0x00000001,
6605} SCL_H_FILTER_PICK_NEAREST;
6606
6607/*
6608 * SCL_H_2TAP_HARDCODE_COEF_EN enum
6609 */
6610
6611typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
6612SCL_H_2TAP_HARDCODE_COEF_DISABLE         = 0x00000000,
6613SCL_H_2TAP_HARDCODE_COEF_ENABLE          = 0x00000001,
6614} SCL_H_2TAP_HARDCODE_COEF_EN;
6615
6616/*
6617 * SCL_V_FILTER_PICK_NEAREST enum
6618 */
6619
6620typedef enum SCL_V_FILTER_PICK_NEAREST {
6621SCL_V_FILTER_PICK_NEAREST_DISABLE        = 0x00000000,
6622SCL_V_FILTER_PICK_NEAREST_ENABLE         = 0x00000001,
6623} SCL_V_FILTER_PICK_NEAREST;
6624
6625/*
6626 * SCL_V_2TAP_HARDCODE_COEF_EN enum
6627 */
6628
6629typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
6630SCL_V_2TAP_HARDCODE_COEF_DISABLE         = 0x00000000,
6631SCL_V_2TAP_HARDCODE_COEF_ENABLE          = 0x00000001,
6632} SCL_V_2TAP_HARDCODE_COEF_EN;
6633
6634/*
6635 * SCL_UPDATE_TAKEN enum
6636 */
6637
6638typedef enum SCL_UPDATE_TAKEN {
6639SCL_UPDATE_TAKEN_NO                      = 0x00000000,
6640SCL_UPDATE_TAKEN_YES                     = 0x00000001,
6641} SCL_UPDATE_TAKEN;
6642
6643/*
6644 * SCL_UPDATE_LOCK enum
6645 */
6646
6647typedef enum SCL_UPDATE_LOCK {
6648SCL_UPDATE_UNLOCKED                      = 0x00000000,
6649SCL_UPDATE_LOCKED                        = 0x00000001,
6650} SCL_UPDATE_LOCK;
6651
6652/*
6653 * SCL_COEF_UPDATE_COMPLETE enum
6654 */
6655
6656typedef enum SCL_COEF_UPDATE_COMPLETE {
6657SCL_COEF_UPDATE_NOT_COMPLETED            = 0x00000000,
6658SCL_COEF_UPDATE_COMPLETED                = 0x00000001,
6659} SCL_COEF_UPDATE_COMPLETE;
6660
6661/*
6662 * SCL_HF_SHARP_SCALE_FACTOR enum
6663 */
6664
6665typedef enum SCL_HF_SHARP_SCALE_FACTOR {
6666SCL_HF_SHARP_SCALE_FACTOR_0              = 0x00000000,
6667SCL_HF_SHARP_SCALE_FACTOR_1              = 0x00000001,
6668SCL_HF_SHARP_SCALE_FACTOR_2              = 0x00000002,
6669SCL_HF_SHARP_SCALE_FACTOR_3              = 0x00000003,
6670SCL_HF_SHARP_SCALE_FACTOR_4              = 0x00000004,
6671SCL_HF_SHARP_SCALE_FACTOR_5              = 0x00000005,
6672SCL_HF_SHARP_SCALE_FACTOR_6              = 0x00000006,
6673SCL_HF_SHARP_SCALE_FACTOR_7              = 0x00000007,
6674} SCL_HF_SHARP_SCALE_FACTOR;
6675
6676/*
6677 * SCL_HF_SHARP_EN enum
6678 */
6679
6680typedef enum SCL_HF_SHARP_EN {
6681SCL_HF_SHARP_DISABLE                     = 0x00000000,
6682SCL_HF_SHARP_ENABLE                      = 0x00000001,
6683} SCL_HF_SHARP_EN;
6684
6685/*
6686 * SCL_VF_SHARP_SCALE_FACTOR enum
6687 */
6688
6689typedef enum SCL_VF_SHARP_SCALE_FACTOR {
6690SCL_VF_SHARP_SCALE_FACTOR_0              = 0x00000000,
6691SCL_VF_SHARP_SCALE_FACTOR_1              = 0x00000001,
6692SCL_VF_SHARP_SCALE_FACTOR_2              = 0x00000002,
6693SCL_VF_SHARP_SCALE_FACTOR_3              = 0x00000003,
6694SCL_VF_SHARP_SCALE_FACTOR_4              = 0x00000004,
6695SCL_VF_SHARP_SCALE_FACTOR_5              = 0x00000005,
6696SCL_VF_SHARP_SCALE_FACTOR_6              = 0x00000006,
6697SCL_VF_SHARP_SCALE_FACTOR_7              = 0x00000007,
6698} SCL_VF_SHARP_SCALE_FACTOR;
6699
6700/*
6701 * SCL_VF_SHARP_EN enum
6702 */
6703
6704typedef enum SCL_VF_SHARP_EN {
6705SCL_VF_SHARP_DISABLE                     = 0x00000000,
6706SCL_VF_SHARP_ENABLE                      = 0x00000001,
6707} SCL_VF_SHARP_EN;
6708
6709/*
6710 * SCL_ALU_DISABLE enum
6711 */
6712
6713typedef enum SCL_ALU_DISABLE {
6714SCL_ALU_ENABLED                          = 0x00000000,
6715SCL_ALU_DISABLED                         = 0x00000001,
6716} SCL_ALU_DISABLE;
6717
6718/*
6719 * SCL_HOST_CONFLICT_MASK enum
6720 */
6721
6722typedef enum SCL_HOST_CONFLICT_MASK {
6723SCL_HOST_CONFLICT_DISABLE_INTERRUPT      = 0x00000000,
6724SCL_HOST_CONFLICT_ENABLE_INTERRUPT       = 0x00000001,
6725} SCL_HOST_CONFLICT_MASK;
6726
6727/*
6728 * SCL_SCL_MODE_CHANGE_MASK enum
6729 */
6730
6731typedef enum SCL_SCL_MODE_CHANGE_MASK {
6732SCL_MODE_CHANGE_DISABLE_INTERRUPT        = 0x00000000,
6733SCL_MODE_CHANGE_ENABLE_INTERRUPT         = 0x00000001,
6734} SCL_SCL_MODE_CHANGE_MASK;
6735
6736/*******************************************************
6737 * SCLV Enums
6738 *******************************************************/
6739
6740/*
6741 * SCLV_MODE_SEL enum
6742 */
6743
6744typedef enum SCLV_MODE_SEL {
6745SCLV_MODE_RGB_BYPASS                     = 0x00000000,
6746SCLV_MODE_RGB_SCALING                    = 0x00000001,
6747SCLV_MODE_YCBCR_SCALING                  = 0x00000002,
6748SCLV_MODE_YCBCR_BYPASS                   = 0x00000003,
6749} SCLV_MODE_SEL;
6750
6751/*
6752 * SCLV_INTERLACE_SOURCE enum
6753 */
6754
6755typedef enum SCLV_INTERLACE_SOURCE {
6756INTERLACE_SOURCE_PROGRESSIVE             = 0x00000000,
6757INTERLACE_SOURCE_INTERLEAVE              = 0x00000001,
6758INTERLACE_SOURCE_STACK                   = 0x00000002,
6759} SCLV_INTERLACE_SOURCE;
6760
6761/*
6762 * SCLV_UPDATE_LOCK enum
6763 */
6764
6765typedef enum SCLV_UPDATE_LOCK {
6766UPDATE_UNLOCKED                          = 0x00000000,
6767UPDATE_LOCKED                            = 0x00000001,
6768} SCLV_UPDATE_LOCK;
6769
6770/*
6771 * SCLV_COEF_UPDATE_COMPLETE enum
6772 */
6773
6774typedef enum SCLV_COEF_UPDATE_COMPLETE {
6775COEF_UPDATE_NOT_COMPLETE                 = 0x00000000,
6776COEF_UPDATE_COMPLETE                     = 0x00000001,
6777} SCLV_COEF_UPDATE_COMPLETE;
6778
6779/*******************************************************
6780 * DPRX_SD Enums
6781 *******************************************************/
6782
6783/*
6784 * DPRX_SD_PIXEL_ENCODING enum
6785 */
6786
6787typedef enum DPRX_SD_PIXEL_ENCODING {
6788PIXEL_FORMAT_RGB_444                     = 0x00000000,
6789PIXEL_FORMAT_YCBCR_444                   = 0x00000001,
6790PIXEL_FORMAT_YCBCR_422                   = 0x00000002,
6791PIXEL_FORMAT_Y_ONLY                      = 0x00000003,
6792} DPRX_SD_PIXEL_ENCODING;
6793
6794/*
6795 * DPRX_SD_COMPONENT_DEPTH enum
6796 */
6797
6798typedef enum DPRX_SD_COMPONENT_DEPTH {
6799COMPONENT_DEPTH_6BPC                     = 0x00000000,
6800COMPONENT_DEPTH_8BPC                     = 0x00000001,
6801COMPONENT_DEPTH_10BPC                    = 0x00000002,
6802COMPONENT_DEPTH_12BPC                    = 0x00000003,
6803COMPONENT_DEPTH_16BPC                    = 0x00000004,
6804} DPRX_SD_COMPONENT_DEPTH;
6805
6806/*******************************************************
6807 * AZF0STREAM Enums
6808 *******************************************************/
6809
6810/*
6811 * AZ_LATENCY_COUNTER_CONTROL enum
6812 */
6813
6814typedef enum AZ_LATENCY_COUNTER_CONTROL {
6815AZ_LATENCY_COUNTER_NO_RESET              = 0x00000000,
6816AZ_LATENCY_COUNTER_RESET_DONE            = 0x00000001,
6817} AZ_LATENCY_COUNTER_CONTROL;
6818
6819/*******************************************************
6820 * BLND Enums
6821 *******************************************************/
6822
6823/*
6824 * BLND_CONTROL_BLND_MODE enum
6825 */
6826
6827typedef enum BLND_CONTROL_BLND_MODE {
6828BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
6829BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY   = 0x00000001,
6830BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
6831BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
6832} BLND_CONTROL_BLND_MODE;
6833
6834/*
6835 * BLND_CONTROL_BLND_STEREO_TYPE enum
6836 */
6837
6838typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
6839BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
6840BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
6841BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
6842BLND_CONTROL_BLND_STEREO_TYPE_UNUSED     = 0x00000003,
6843} BLND_CONTROL_BLND_STEREO_TYPE;
6844
6845/*
6846 * BLND_CONTROL_BLND_STEREO_POLARITY enum
6847 */
6848
6849typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
6850BLND_CONTROL_BLND_STEREO_POLARITY_LOW    = 0x00000000,
6851BLND_CONTROL_BLND_STEREO_POLARITY_HIGH   = 0x00000001,
6852} BLND_CONTROL_BLND_STEREO_POLARITY;
6853
6854/*
6855 * BLND_CONTROL_BLND_FEEDTHROUGH_EN enum
6856 */
6857
6858typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
6859BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE   = 0x00000000,
6860BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE    = 0x00000001,
6861} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
6862
6863/*
6864 * BLND_CONTROL_BLND_ALPHA_MODE enum
6865 */
6866
6867typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
6868BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
6869BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
6870BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
6871BLND_CONTROL_BLND_ALPHA_MODE_UNUSED      = 0x00000003,
6872} BLND_CONTROL_BLND_ALPHA_MODE;
6873
6874/*
6875 * BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
6876 */
6877
6878typedef enum BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
6879BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_FALSE  = 0x00000000,
6880BLND_CONTROL_BLND_ACTIVE_OVERLAY_ONLY_TRUE  = 0x00000001,
6881} BLND_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;
6882
6883/*
6884 * BLND_CONTROL_BLND_MULTIPLIED_MODE enum
6885 */
6886
6887typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
6888BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE  = 0x00000000,
6889BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE   = 0x00000001,
6890} BLND_CONTROL_BLND_MULTIPLIED_MODE;
6891
6892/*
6893 * BLND_SM_CONTROL2_SM_MODE enum
6894 */
6895
6896typedef enum BLND_SM_CONTROL2_SM_MODE {
6897BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE    = 0x00000000,
6898BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
6899BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
6900BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
6901} BLND_SM_CONTROL2_SM_MODE;
6902
6903/*
6904 * BLND_SM_CONTROL2_SM_FRAME_ALTERNATE enum
6905 */
6906
6907typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
6908BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
6909BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
6910} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
6911
6912/*
6913 * BLND_SM_CONTROL2_SM_FIELD_ALTERNATE enum
6914 */
6915
6916typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
6917BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
6918BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
6919} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
6920
6921/*
6922 * BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
6923 */
6924
6925typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6926BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
6927BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
6928BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
6929BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
6930} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
6931
6932/*
6933 * BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
6934 */
6935
6936typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6937BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
6938BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
6939BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
6940BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
6941} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
6942
6943/*
6944 * BLND_CONTROL2_PTI_ENABLE enum
6945 */
6946
6947typedef enum BLND_CONTROL2_PTI_ENABLE {
6948BLND_CONTROL2_PTI_ENABLE_FALSE           = 0x00000000,
6949BLND_CONTROL2_PTI_ENABLE_TRUE            = 0x00000001,
6950} BLND_CONTROL2_PTI_ENABLE;
6951
6952/*
6953 * BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
6954 */
6955
6956typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6957BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
6958BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
6959} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
6960
6961/*
6962 * BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
6963 */
6964
6965typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6966BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
6967BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
6968} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
6969
6970/*
6971 * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
6972 */
6973
6974typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6975BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
6976BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
6977} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
6978
6979/*
6980 * BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
6981 */
6982
6983typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6984BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
6985BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
6986} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
6987
6988/*
6989 * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
6990 */
6991
6992typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6993BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
6994BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
6995} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
6996
6997/*
6998 * BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
6999 */
7000

7001typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
7002BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
7003BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
7004} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
7005
7006/*
7007 * BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
7008 */
7009
7010typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
7011BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
7012BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
7013} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
7014
7015/*
7016 * BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
7017 */
7018
7019typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
7020BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
7021BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
7022} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
7023
7024/*
7025 * BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
7026 */
7027
7028typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
7029BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
7030BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
7031} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
7032
7033/*
7034 * BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
7035 */
7036
7037typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
7038BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
7039BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
7040} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
7041
7042/*
7043 * BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
7044 */
7045
7046typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
7047BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
7048BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
7049} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
7050
7051/*
7052 * BLND_DEBUG_BLND_CNV_MUX_SELECT enum
7053 */
7054
7055typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
7056BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW       = 0x00000000,
7057BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH      = 0x00000001,
7058} BLND_DEBUG_BLND_CNV_MUX_SELECT;
7059
7060/*
7061 * BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
7062 */
7063
7064typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
7065BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
7066BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
7067} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
7068
7069/*******************************************************
7070 * AZF0ENDPOINT Enums
7071 *******************************************************/
7072
7073/*
7074 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7075 */
7076
7077typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7078AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7079AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7080AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7081AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7082AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7083AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7084AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7085AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7086AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
7087AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7088} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7089
7090/*
7091 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7092 */
7093
7094typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7095AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
7096AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
7097} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7098
7099/*
7100 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7101 */
7102
7103typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7104AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7105AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7106} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7107
7108/*
7109 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7110 */
7111
7112typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7113AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
7114AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
7115} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7116
7117/*
7118 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7119 */
7120
7121typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7122AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7123AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7124} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7125
7126/*
7127 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7128 */
7129
7130typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7131AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7132AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7133} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7134
7135/*
7136 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7137 */
7138
7139typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7140AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
7141AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
7142} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7143
7144/*
7145 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7146 */
7147
7148typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7149AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
7150AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7151} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7152
7153/*
7154 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7155 */
7156
7157typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7158AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
7159AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE  = 0x00000001,
7160} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7161
7162/*
7163 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7164 */
7165
7166typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7167AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7168AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
7169} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7170
7171/*
7172 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7173 */
7174
7175typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7176AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7177AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7178} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7179
7180/*
7181 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7182 */
7183
7184typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7185AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
7186AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7187} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7188
7189/*
7190 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7191 */
7192
7193typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7194AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
7195AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
7196} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7197
7198/*
7199 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7200 */
7201
7202typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7203AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7204AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7205AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7206AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7207AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7208AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7209AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7210AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7211AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED  = 0x00000008,
7212AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7213} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7214
7215/*
7216 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7217 */
7218
7219typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7220AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
7221AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
7222} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7223
7224/*
7225 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7226 */
7227
7228typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7229AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7230AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7231} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7232
7233/*
7234 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7235 */
7236
7237typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7238AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
7239AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
7240} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7241
7242/*
7243 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7244 */
7245
7246typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7247AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7248AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7249} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7250
7251/*
7252 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7253 */
7254
7255typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7256AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7257AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7258} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7259
7260/*
7261 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7262 */
7263
7264typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7265AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES  = 0x00000000,
7266AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
7267} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7268
7269/*
7270 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7271 */
7272
7273typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7274AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
7275AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7276} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7277
7278/*
7279 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7280 */
7281
7282typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7283AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7284AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
7285} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7286
7287/*
7288 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7289 */
7290
7291typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7292AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7293AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7294} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7295
7296/*
7297 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7298 */
7299
7300typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7301AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT  = 0x00000000,
7302AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7303} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7304
7305/*
7306 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7307 */
7308
7309typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7310AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN  = 0x00000000,
7311AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN  = 0x00000001,
7312} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7313
7314/*
7315 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7316 */
7317
7318typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7319AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED  = 0x00000000,
7320AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
7321} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7322
7323/*
7324 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7325 */
7326
7327typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7328AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
7329AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
7330} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7331
7332/*
7333 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7334 */
7335
7336typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7337AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
7338AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
7339} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7340
7341/*
7342 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7343 */
7344
7345typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7346AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
7347AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
7348} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7349
7350/*
7351 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7352 */
7353
7354typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7355AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY  = 0x00000000,
7356AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY  = 0x00000001,
7357} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7358
7359/*
7360 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7361 */
7362
7363typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7364AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
7365AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
7366} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7367
7368/*
7369 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7370 */
7371
7372typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7373AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
7374AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
7375} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7376
7377/*
7378 * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
7379 */
7380
7381typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
7382AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
7383AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
7384} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
7385
7386/*
7387 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7388 */
7389
7390typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7391AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY  = 0x00000000,
7392AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY  = 0x00000001,
7393} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7394
7395/*******************************************************
7396 * AZF0INPUTENDPOINT Enums
7397 *******************************************************/
7398
7399/*
7400 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7401 */
7402
7403typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7404AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7405AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7406AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7407AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7408AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7409AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7410AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7411AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7412AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
7413AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7414} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7415
7416/*
7417 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7418 */
7419
7420typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7421AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY  = 0x00000000,
7422AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY  = 0x00000001,
7423} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7424
7425/*
7426 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7427 */
7428
7429typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7430AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7431AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7432} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7433
7434/*
7435 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7436 */
7437
7438typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7439AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG  = 0x00000000,
7440AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL  = 0x00000001,
7441} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7442
7443/*
7444 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7445 */
7446
7447typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7448AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7449AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7450} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7451
7452/*
7453 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7454 */
7455
7456typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7457AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7458AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7459} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7460
7461/*
7462 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7463 */
7464
7465typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7466AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES  = 0x00000000,
7467AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES  = 0x00000001,
7468} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7469
7470/*
7471 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7472 */
7473
7474typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7475AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING  = 0x00000000,
7476AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7477} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7478
7479/*
7480 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
7481 */
7482
7483typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
7484AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE  = 0x00000000,
7485AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE  = 0x00000001,
7486} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
7487
7488/*
7489 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7490 */
7491
7492typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7493AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7494AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER  = 0x00000001,
7495} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7496
7497/*
7498 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7499 */
7500
7501typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7502AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7503AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7504} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7505
7506/*
7507 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7508 */
7509
7510typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7511AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
7512AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7513} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7514
7515/*
7516 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
7517 */
7518
7519typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
7520AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC  = 0x00000000,
7521AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO  = 0x00000001,
7522} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
7523
7524/*
7525 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
7526 */
7527
7528typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
7529AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED  = 0x00000000,
7530AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED  = 0x00000001,
7531AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED  = 0x00000002,
7532AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED  = 0x00000003,
7533AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED  = 0x00000004,
7534AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED  = 0x00000005,
7535AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED  = 0x00000006,
7536AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED  = 0x00000007,
7537AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED  = 0x00000008,
7538AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED  = 0x00000009,
7539} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
7540
7541/*
7542 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
7543 */
7544
7545typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
7546AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP  = 0x00000000,
7547AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP  = 0x00000001,
7548} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
7549
7550/*
7551 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
7552 */
7553
7554typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
7555AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY  = 0x00000000,
7556AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY  = 0x00000001,
7557} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
7558
7559/*
7560 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
7561 */
7562
7563typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
7564AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG  = 0x00000000,
7565AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL  = 0x00000001,
7566} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
7567
7568/*
7569 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
7570 */
7571
7572typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
7573AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST  = 0x00000000,
7574AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST  = 0x00000001,
7575} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
7576
7577/*
7578 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
7579 */
7580
7581typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
7582AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000000,
7583AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY  = 0x00000001,
7584} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
7585
7586/*
7587 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
7588 */
7589
7590typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
7591AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES  = 0x00000000,
7592AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES  = 0x00000001,
7593} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
7594
7595/*
7596 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
7597 */
7598
7599typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
7600AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING  = 0x00000000,
7601AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING  = 0x00000001,
7602} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
7603
7604/*
7605 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
7606 */
7607
7608typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
7609AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER  = 0x00000000,
7610AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE  = 0x00000001,
7611} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
7612
7613/*
7614 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
7615 */
7616
7617typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
7618AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER  = 0x00000000,
7619AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER  = 0x00000001,
7620} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
7621
7622/*
7623 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
7624 */
7625
7626typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
7627AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER  = 0x00000000,
7628AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER  = 0x00000001,
7629} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
7630
7631/*
7632 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
7633 */
7634
7635typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
7636AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED  = 0x00000000,
7637AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED  = 0x00000001,
7638} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
7639
7640/*
7641 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
7642 */
7643
7644typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
7645AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN  = 0x00000000,
7646AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN  = 0x00000001,
7647} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
7648
7649/*
7650 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
7651 */
7652
7653typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
7654AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED  = 0x00000000,
7655AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED  = 0x00000001,
7656} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
7657
7658/*
7659 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
7660 */
7661
7662typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
7663AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED  = 0x00000000,
7664AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED  = 0x00000001,
7665} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
7666
7667/*
7668 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
7669 */
7670
7671typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
7672AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN  = 0x00000000,
7673AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN  = 0x00000001,
7674} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
7675
7676/*
7677 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
7678 */
7679
7680typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
7681AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN  = 0x00000000,
7682AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN  = 0x00000001,
7683} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
7684
7685/*
7686 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
7687 */
7688
7689typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
7690AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY  = 0x00000000,
7691AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY  = 0x00000001,
7692} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
7693
7694/*
7695 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
7696 */
7697
7698typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
7699AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000000,
7700AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY  = 0x00000001,
7701} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
7702
7703/*
7704 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
7705 */
7706
7707typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
7708AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000000,
7709AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT  = 0x00000001,
7710} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
7711
7712/*
7713 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
7714 */
7715
7716typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
7717AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY  = 0x00000000,
7718AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY  = 0x00000001,
7719} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
7720
7721/*
7722 * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
7723 */
7724
7725typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
7726AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY  = 0x00000000,
7727AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY  = 0x00000001,
7728} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
7729
7730/*******************************************************
7731 * UNP Enums
7732 *******************************************************/
7733
7734/*
7735 * UNP_GRPH_EN enum
7736 */
7737
7738typedef enum UNP_GRPH_EN {
7739UNP_GRPH_DISABLED                        = 0x00000000,
7740UNP_GRPH_ENABLED                         = 0x00000001,
7741} UNP_GRPH_EN;
7742
7743/*
7744 * UNP_GRPH_DEPTH enum
7745 */
7746
7747typedef enum UNP_GRPH_DEPTH {
7748UNP_GRPH_8BPP                            = 0x00000000,
7749UNP_GRPH_16BPP                           = 0x00000001,
7750UNP_GRPH_32BPP                           = 0x00000002,
7751} UNP_GRPH_DEPTH;
7752
7753/*
7754 * UNP_GRPH_NUM_BANKS enum
7755 */
7756
7757typedef enum UNP_GRPH_NUM_BANKS {
7758UNP_GRPH_ADDR_SURF_2_BANK                = 0x00000000,
7759UNP_GRPH_ADDR_SURF_4_BANK                = 0x00000001,
7760UNP_GRPH_ADDR_SURF_8_BANK                = 0x00000002,
7761UNP_GRPH_ADDR_SURF_16_BANK               = 0x00000003,
7762} UNP_GRPH_NUM_BANKS;
7763
7764/*
7765 * UNP_GRPH_BANK_WIDTH enum
7766 */
7767
7768typedef enum UNP_GRPH_BANK_WIDTH {
7769UNP_GRPH_ADDR_SURF_BANK_WIDTH_1          = 0x00000000,
7770UNP_GRPH_ADDR_SURF_BANK_WIDTH_2          = 0x00000001,
7771UNP_GRPH_ADDR_SURF_BANK_WIDTH_4          = 0x00000002,
7772UNP_GRPH_ADDR_SURF_BANK_WIDTH_8          = 0x00000003,
7773} UNP_GRPH_BANK_WIDTH;
7774
7775/*
7776 * UNP_GRPH_BANK_HEIGHT enum
7777 */
7778
7779typedef enum UNP_GRPH_BANK_HEIGHT {
7780UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1         = 0x00000000,
7781UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2         = 0x00000001,
7782UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4         = 0x00000002,
7783UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8         = 0x00000003,
7784} UNP_GRPH_BANK_HEIGHT;
7785
7786/*
7787 * UNP_GRPH_TILE_SPLIT enum
7788 */
7789
7790typedef enum UNP_GRPH_TILE_SPLIT {
7791UNP_ADDR_SURF_TILE_SPLIT_64B             = 0x00000000,
7792UNP_ADDR_SURF_TILE_SPLIT_128B            = 0x00000001,
7793UNP_ADDR_SURF_TILE_SPLIT_256B            = 0x00000002,
7794UNP_ADDR_SURF_TILE_SPLIT_512B            = 0x00000003,
7795UNP_ADDR_SURF_TILE_SPLIT_1KB             = 0x00000004,
7796UNP_ADDR_SURF_TILE_SPLIT_2KB             = 0x00000005,
7797UNP_ADDR_SURF_TILE_SPLIT_4KB             = 0x00000006,
7798} UNP_GRPH_TILE_SPLIT;
7799
7800/*
7801 * UNP_GRPH_ADDRESS_TRANSLATION_ENABLE enum
7802 */
7803
7804typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
7805UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0     = 0x00000000,
7806UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1     = 0x00000001,
7807} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
7808
7809/*
7810 * UNP_GRPH_MACRO_TILE_ASPECT enum
7811 */
7812
7813typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
7814UNP_ADDR_SURF_MACRO_ASPECT_1             = 0x00000000,
7815UNP_ADDR_SURF_MACRO_ASPECT_2             = 0x00000001,
7816UNP_ADDR_SURF_MACRO_ASPECT_4             = 0x00000002,
7817UNP_ADDR_SURF_MACRO_ASPECT_8             = 0x00000003,
7818} UNP_GRPH_MACRO_TILE_ASPECT;
7819
7820/*
7821 * UNP_GRPH_COLOR_EXPANSION_MODE enum
7822 */
7823
7824typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
7825UNP_GRPH_DYNAMIC_EXPANSION               = 0x00000000,
7826UNP_GRPH_ZERO_EXPANSION                  = 0x00000001,
7827} UNP_GRPH_COLOR_EXPANSION_MODE;
7828
7829/*
7830 * UNP_VIDEO_FORMAT enum
7831 */
7832
7833typedef enum UNP_VIDEO_FORMAT {
7834UNP_VIDEO_FORMAT0                        = 0x00000000,
7835UNP_VIDEO_FORMAT1                        = 0x00000001,
7836UNP_VIDEO_FORMAT_YUV420_YCbCr            = 0x00000002,
7837UNP_VIDEO_FORMAT_YUV420_YCrCb            = 0x00000003,
7838UNP_VIDEO_FORMAT_YUV422_YCb              = 0x00000004,
7839UNP_VIDEO_FORMAT_YUV422_YCr              = 0x00000005,
7840UNP_VIDEO_FORMAT_YUV422_CbY              = 0x00000006,
7841UNP_VIDEO_FORMAT_YUV422_CrY              = 0x00000007,
7842} UNP_VIDEO_FORMAT;
7843
7844/*
7845 * UNP_GRPH_ENDIAN_SWAP enum
7846 */
7847
7848typedef enum UNP_GRPH_ENDIAN_SWAP {
7849UNP_GRPH_ENDIAN_SWAP_NONE                = 0x00000000,
7850UNP_GRPH_ENDIAN_SWAP_8IN16               = 0x00000001,
7851UNP_GRPH_ENDIAN_SWAP_8IN32               = 0x00000002,
7852UNP_GRPH_ENDIAN_SWAP_8IN43               = 0x00000003,
7853} UNP_GRPH_ENDIAN_SWAP;
7854
7855/*
7856 * UNP_GRPH_RED_CROSSBAR enum
7857 */
7858
7859typedef enum UNP_GRPH_RED_CROSSBAR {
7860UNP_GRPH_RED_CROSSBAR_R_Cr               = 0x00000000,
7861UNP_GRPH_RED_CROSSBAR_G_Y                = 0x00000001,
7862UNP_GRPH_RED_CROSSBAR_B_Cb               = 0x00000002,
7863UNP_GRPH_RED_CROSSBAR_A                  = 0x00000003,
7864} UNP_GRPH_RED_CROSSBAR;
7865
7866/*
7867 * UNP_GRPH_GREEN_CROSSBAR enum
7868 */
7869
7870typedef enum UNP_GRPH_GREEN_CROSSBAR {
7871UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y     = 0x00000000,
7872UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C   = 0x00000001,
7873UNP_UNP_GRPH_GREEN_CROSSBAR_A            = 0x00000002,
7874UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr         = 0x00000003,
7875} UNP_GRPH_GREEN_CROSSBAR;
7876
7877/*
7878 * UNP_GRPH_BLUE_CROSSBAR enum
7879 */
7880
7881typedef enum UNP_GRPH_BLUE_CROSSBAR {
7882UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C        = 0x00000000,
7883UNP_GRPH_BLUE_CROSSBAR_A                 = 0x00000001,
7884UNP_GRPH_BLUE_CROSSBAR_R_Cr              = 0x00000002,
7885UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y          = 0x00000003,
7886} UNP_GRPH_BLUE_CROSSBAR;
7887
7888/*
7889 * UNP_GRPH_MODE_UPDATE_LOCKG enum
7890 */
7891
7892typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
7893UNP_GRPH_UPDATE_LOCK_0                   = 0x00000000,
7894UNP_GRPH_UPDATE_LOCK_1                   = 0x00000001,
7895} UNP_GRPH_MODE_UPDATE_LOCKG;
7896
7897/*
7898 * UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK enum
7899 */
7900
7901typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
7902UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0    = 0x00000000,
7903UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1    = 0x00000001,
7904} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
7905
7906/*
7907 * UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE enum
7908 */
7909
7910typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
7911UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0  = 0x00000000,
7912UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1  = 0x00000001,
7913} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
7914
7915/*
7916 * UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE enum
7917 */
7918
7919typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
7920UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0  = 0x00000000,
7921UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1  = 0x00000001,
7922} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
7923
7924/*
7925 * UNP_GRPH_STEREOSYNC_FLIP_EN enum
7926 */
7927
7928typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
7929UNP_GRPH_STEREOSYNC_FLIP_DISABLE         = 0x00000000,
7930UNP_GRPH_STEREOSYNC_FLIP_ENABLE          = 0x00000001,
7931} UNP_GRPH_STEREOSYNC_FLIP_EN;
7932
7933/*
7934 * UNP_GRPH_STEREOSYNC_FLIP_MODE enum
7935 */
7936
7937typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
7938UNP_GRPH_STEREOSYNC_FLIP_MODE_0          = 0x00000000,
7939UNP_GRPH_STEREOSYNC_FLIP_MODE_1          = 0x00000001,
7940UNP_GRPH_STEREOSYNC_FLIP_MODE_2          = 0x00000002,
7941UNP_GRPH_STEREOSYNC_FLIP_MODE_3          = 0x00000003,
7942} UNP_GRPH_STEREOSYNC_FLIP_MODE;
7943
7944/*
7945 * UNP_GRPH_STACK_INTERLACE_FLIP_EN enum
7946 */
7947
7948typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
7949UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE    = 0x00000000,
7950UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE     = 0x00000001,
7951} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
7952
7953/*
7954 * UNP_GRPH_STACK_INTERLACE_FLIP_MODE enum
7955 */
7956
7957typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
7958UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0     = 0x00000000,
7959UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1     = 0x00000001,
7960UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2     = 0x00000002,
7961UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3     = 0x00000003,
7962} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
7963
7964/*
7965 * UNP_GRPH_STEREOSYNC_SELECT_DISABLE enum
7966 */
7967
7968typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
7969UNP_GRPH_STEREOSYNC_SELECT_EN            = 0x00000000,
7970UNP_GRPH_STEREOSYNC_SELECT_DIS           = 0x00000001,
7971} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
7972
7973/*
7974 * UNP_CRC_SOURCE_SEL enum
7975 */
7976
7977typedef enum UNP_CRC_SOURCE_SEL {
7978UNP_CRC_SOURCE_SEL_NP_TO_LBV             = 0x00000000,
7979UNP_CRC_SOURCE_SEL_LOWER32               = 0x00000001,
7980UNP_CRC_SOURCE_SEL_RESERVED              = 0x00000002,
7981UNP_CRC_SOURCE_SEL_LOWER16               = 0x00000003,
7982UNP_CRC_SOURCE_SEL_UNP_TO_LBV            = 0x00000004,
7983} UNP_CRC_SOURCE_SEL;
7984
7985/*
7986 * UNP_CRC_LINE_SEL enum
7987 */
7988
7989typedef enum UNP_CRC_LINE_SEL {
7990UNP_CRC_LINE_SEL_RESERVED                = 0x00000000,
7991UNP_CRC_LINE_SEL_EVEN_ONLY               = 0x00000001,
7992UNP_CRC_LINE_SEL_ODD_ONLY                = 0x00000002,
7993UNP_CRC_LINE_SEL_ODD_EVEN                = 0x00000003,
7994} UNP_CRC_LINE_SEL;
7995
7996/*
7997 * UNP_ROTATION_ANGLE enum
7998 */
7999
8000typedef enum UNP_ROTATION_ANGLE {

8001UNP_ROTATION_ANGLE_0                     = 0x00000000,
8002UNP_ROTATION_ANGLE_90                    = 0x00000001,
8003UNP_ROTATION_ANGLE_180                   = 0x00000002,
8004UNP_ROTATION_ANGLE_270                   = 0x00000003,
8005UNP_ROTATION_ANGLE_0m                    = 0x00000004,
8006UNP_ROTATION_ANGLE_90m                   = 0x00000005,
8007UNP_ROTATION_ANGLE_180m                  = 0x00000006,
8008UNP_ROTATION_ANGLE_270m                  = 0x00000007,
8009} UNP_ROTATION_ANGLE;
8010
8011/*
8012 * UNP_PIXEL_DROP enum
8013 */
8014
8015typedef enum UNP_PIXEL_DROP {
8016UNP_PIXEL_NO_DROP                        = 0x00000000,
8017UNP_PIXEL_DROPPING                       = 0x00000001,
8018} UNP_PIXEL_DROP;
8019
8020/*
8021 * UNP_BUFFER_MODE enum
8022 */
8023
8024typedef enum UNP_BUFFER_MODE {
8025UNP_BUFFER_MODE_LUMA                     = 0x00000000,
8026UNP_BUFFER_MODE_LUMA_CHROMA              = 0x00000001,
8027} UNP_BUFFER_MODE;
8028
8029/*******************************************************
8030 * DP Enums
8031 *******************************************************/
8032
8033/*
8034 * DP_LINK_TRAINING_COMPLETE enum
8035 */
8036
8037typedef enum DP_LINK_TRAINING_COMPLETE {
8038DP_LINK_TRAINING_NOT_COMPLETE            = 0x00000000,
8039DP_LINK_TRAINING_ALREADY_COMPLETE        = 0x00000001,
8040} DP_LINK_TRAINING_COMPLETE;
8041
8042/*
8043 * DP_EMBEDDED_PANEL_MODE enum
8044 */
8045
8046typedef enum DP_EMBEDDED_PANEL_MODE {
8047DP_EXTERNAL_PANEL                        = 0x00000000,
8048DP_EMBEDDED_PANEL                        = 0x00000001,
8049} DP_EMBEDDED_PANEL_MODE;
8050
8051/*
8052 * DP_PIXEL_ENCODING enum
8053 */
8054
8055typedef enum DP_PIXEL_ENCODING {
8056DP_PIXEL_ENCODING_RGB444                 = 0x00000000,
8057DP_PIXEL_ENCODING_YCBCR422               = 0x00000001,
8058DP_PIXEL_ENCODING_YCBCR444               = 0x00000002,
8059DP_PIXEL_ENCODING_RGB_WIDE_GAMUT         = 0x00000003,
8060DP_PIXEL_ENCODING_Y_ONLY                 = 0x00000004,
8061DP_PIXEL_ENCODING_YCBCR420               = 0x00000005,
8062DP_PIXEL_ENCODING_RESERVED               = 0x00000006,
8063} DP_PIXEL_ENCODING;
8064
8065/*
8066 * DP_DYN_RANGE enum
8067 */
8068
8069typedef enum DP_DYN_RANGE {
8070DP_DYN_VESA_RANGE                        = 0x00000000,
8071DP_DYN_CEA_RANGE                         = 0x00000001,
8072} DP_DYN_RANGE;
8073
8074/*
8075 * DP_YCBCR_RANGE enum
8076 */
8077
8078typedef enum DP_YCBCR_RANGE {
8079DP_YCBCR_RANGE_BT601_5                   = 0x00000000,
8080DP_YCBCR_RANGE_BT709_5                   = 0x00000001,
8081} DP_YCBCR_RANGE;
8082
8083/*
8084 * DP_COMPONENT_DEPTH enum
8085 */
8086
8087typedef enum DP_COMPONENT_DEPTH {
8088DP_COMPONENT_DEPTH_6BPC                  = 0x00000000,
8089DP_COMPONENT_DEPTH_8BPC                  = 0x00000001,
8090DP_COMPONENT_DEPTH_10BPC                 = 0x00000002,
8091DP_COMPONENT_DEPTH_12BPC                 = 0x00000003,
8092DP_COMPONENT_DEPTH_16BPC_RESERVED        = 0x00000004,
8093DP_COMPONENT_DEPTH_RESERVED              = 0x00000005,
8094} DP_COMPONENT_DEPTH;
8095
8096/*
8097 * DP_MSA_MISC0_OVERRIDE_ENABLE enum
8098 */
8099
8100typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
8101MSA_MISC0_OVERRIDE_DISABLE               = 0x00000000,
8102MSA_MISC0_OVERRIDE_ENABLE                = 0x00000001,
8103} DP_MSA_MISC0_OVERRIDE_ENABLE;
8104
8105/*
8106 * DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE enum
8107 */
8108
8109typedef enum DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE {
8110MSA_MISC1_BIT7_OVERRIDE_DISABLE          = 0x00000000,
8111MSA_MISC1_BIT7_OVERRIDE_ENABLE           = 0x00000001,
8112} DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE;
8113
8114/*
8115 * DP_UDI_LANES enum
8116 */
8117
8118typedef enum DP_UDI_LANES {
8119DP_UDI_1_LANE                            = 0x00000000,
8120DP_UDI_2_LANES                           = 0x00000001,
8121DP_UDI_LANES_RESERVED                    = 0x00000002,
8122DP_UDI_4_LANES                           = 0x00000003,
8123} DP_UDI_LANES;
8124
8125/*
8126 * DP_VID_STREAM_DIS_DEFER enum
8127 */
8128
8129typedef enum DP_VID_STREAM_DIS_DEFER {
8130DP_VID_STREAM_DIS_NO_DEFER               = 0x00000000,
8131DP_VID_STREAM_DIS_DEFER_TO_HBLANK        = 0x00000001,
8132DP_VID_STREAM_DIS_DEFER_TO_VBLANK        = 0x00000002,
8133} DP_VID_STREAM_DIS_DEFER;
8134
8135/*
8136 * DP_STEER_OVERFLOW_ACK enum
8137 */
8138
8139typedef enum DP_STEER_OVERFLOW_ACK {
8140DP_STEER_OVERFLOW_ACK_NO_EFFECT          = 0x00000000,
8141DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT      = 0x00000001,
8142} DP_STEER_OVERFLOW_ACK;
8143
8144/*
8145 * DP_STEER_OVERFLOW_MASK enum
8146 */
8147
8148typedef enum DP_STEER_OVERFLOW_MASK {
8149DP_STEER_OVERFLOW_MASKED                 = 0x00000000,
8150DP_STEER_OVERFLOW_UNMASK                 = 0x00000001,
8151} DP_STEER_OVERFLOW_MASK;
8152
8153/*
8154 * DP_TU_OVERFLOW_ACK enum
8155 */
8156
8157typedef enum DP_TU_OVERFLOW_ACK {
8158DP_TU_OVERFLOW_ACK_NO_EFFECT             = 0x00000000,
8159DP_TU_OVERFLOW_ACK_CLR_INTERRUPT         = 0x00000001,
8160} DP_TU_OVERFLOW_ACK;
8161
8162/*
8163 * DPHY_ALT_SCRAMBLER_RESET_EN enum
8164 */
8165
8166typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
8167DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE   = 0x00000000,
8168DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION  = 0x00000001,
8169} DPHY_ALT_SCRAMBLER_RESET_EN;
8170
8171/*
8172 * DPHY_ALT_SCRAMBLER_RESET_SEL enum
8173 */
8174
8175typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
8176DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE  = 0x00000000,
8177DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE  = 0x00000001,
8178} DPHY_ALT_SCRAMBLER_RESET_SEL;
8179
8180/*
8181 * DP_VID_TIMING_MODE enum
8182 */
8183
8184typedef enum DP_VID_TIMING_MODE {
8185DP_VID_TIMING_MODE_ASYNC                 = 0x00000000,
8186DP_VID_TIMING_MODE_SYNC                  = 0x00000001,
8187} DP_VID_TIMING_MODE;
8188
8189/*
8190 * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
8191 */
8192
8193typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
8194DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE  = 0x00000000,
8195DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START  = 0x00000001,
8196} DP_VID_M_N_DOUBLE_BUFFER_MODE;
8197
8198/*
8199 * DP_VID_M_N_GEN_EN enum
8200 */
8201
8202typedef enum DP_VID_M_N_GEN_EN {
8203DP_VID_M_N_PROGRAMMED_VIA_REG            = 0x00000000,
8204DP_VID_M_N_CALC_AUTO                     = 0x00000001,
8205} DP_VID_M_N_GEN_EN;
8206
8207/*
8208 * DP_VID_M_DOUBLE_VALUE_EN enum
8209 */
8210
8211typedef enum DP_VID_M_DOUBLE_VALUE_EN {
8212DP_VID_M_INPUT_PIXEL_RATE                = 0x00000000,
8213DP_VID_M_DOUBLE_INPUT_PIXEL_RATE         = 0x00000001,
8214} DP_VID_M_DOUBLE_VALUE_EN;
8215
8216/*
8217 * DP_VID_ENHANCED_FRAME_MODE enum
8218 */
8219
8220typedef enum DP_VID_ENHANCED_FRAME_MODE {
8221VID_NORMAL_FRAME_MODE                    = 0x00000000,
8222VID_ENHANCED_MODE                        = 0x00000001,
8223} DP_VID_ENHANCED_FRAME_MODE;
8224
8225/*
8226 * DP_VID_MSA_TOP_FIELD_MODE enum
8227 */
8228
8229typedef enum DP_VID_MSA_TOP_FIELD_MODE {
8230DP_TOP_FIELD_ONLY                        = 0x00000000,
8231DP_TOP_PLUS_BOTTOM_FIELD                 = 0x00000001,
8232} DP_VID_MSA_TOP_FIELD_MODE;
8233
8234/*
8235 * DP_VID_VBID_FIELD_POL enum
8236 */
8237
8238typedef enum DP_VID_VBID_FIELD_POL {
8239DP_VID_VBID_FIELD_POL_NORMAL             = 0x00000000,
8240DP_VID_VBID_FIELD_POL_INV                = 0x00000001,
8241} DP_VID_VBID_FIELD_POL;
8242
8243/*
8244 * DP_VID_STREAM_DISABLE_ACK enum
8245 */
8246
8247typedef enum DP_VID_STREAM_DISABLE_ACK {
8248ID_STREAM_DISABLE_NO_ACK                 = 0x00000000,
8249ID_STREAM_DISABLE_ACKED                  = 0x00000001,
8250} DP_VID_STREAM_DISABLE_ACK;
8251
8252/*
8253 * DP_VID_STREAM_DISABLE_MASK enum
8254 */
8255
8256typedef enum DP_VID_STREAM_DISABLE_MASK {
8257VID_STREAM_DISABLE_MASKED                = 0x00000000,
8258VID_STREAM_DISABLE_UNMASK                = 0x00000001,
8259} DP_VID_STREAM_DISABLE_MASK;
8260
8261/*
8262 * DPHY_ATEST_SEL_LANE0 enum
8263 */
8264
8265typedef enum DPHY_ATEST_SEL_LANE0 {
8266DPHY_ATEST_LANE0_PRBS_PATTERN            = 0x00000000,
8267DPHY_ATEST_LANE0_REG_PATTERN             = 0x00000001,
8268} DPHY_ATEST_SEL_LANE0;
8269
8270/*
8271 * DPHY_ATEST_SEL_LANE1 enum
8272 */
8273
8274typedef enum DPHY_ATEST_SEL_LANE1 {
8275DPHY_ATEST_LANE1_PRBS_PATTERN            = 0x00000000,
8276DPHY_ATEST_LANE1_REG_PATTERN             = 0x00000001,
8277} DPHY_ATEST_SEL_LANE1;
8278
8279/*
8280 * DPHY_ATEST_SEL_LANE2 enum
8281 */
8282
8283typedef enum DPHY_ATEST_SEL_LANE2 {
8284DPHY_ATEST_LANE2_PRBS_PATTERN            = 0x00000000,
8285DPHY_ATEST_LANE2_REG_PATTERN             = 0x00000001,
8286} DPHY_ATEST_SEL_LANE2;
8287
8288/*
8289 * DPHY_ATEST_SEL_LANE3 enum
8290 */
8291
8292typedef enum DPHY_ATEST_SEL_LANE3 {
8293DPHY_ATEST_LANE3_PRBS_PATTERN            = 0x00000000,
8294DPHY_ATEST_LANE3_REG_PATTERN             = 0x00000001,
8295} DPHY_ATEST_SEL_LANE3;
8296
8297/*
8298 * DPHY_SCRAMBLER_SEL enum
8299 */
8300
8301typedef enum DPHY_SCRAMBLER_SEL {
8302DPHY_SCRAMBLER_SEL_LANE_DATA             = 0x00000000,
8303DPHY_SCRAMBLER_SEL_DBG_DATA              = 0x00000001,
8304} DPHY_SCRAMBLER_SEL;
8305
8306/*
8307 * DPHY_BYPASS enum
8308 */
8309
8310typedef enum DPHY_BYPASS {
8311DPHY_8B10B_OUTPUT                        = 0x00000000,
8312DPHY_DBG_OUTPUT                          = 0x00000001,
8313} DPHY_BYPASS;
8314
8315/*
8316 * DPHY_SKEW_BYPASS enum
8317 */
8318
8319typedef enum DPHY_SKEW_BYPASS {
8320DPHY_WITH_SKEW                           = 0x00000000,
8321DPHY_NO_SKEW                             = 0x00000001,
8322} DPHY_SKEW_BYPASS;
8323
8324/*
8325 * DPHY_TRAINING_PATTERN_SEL enum
8326 */
8327
8328typedef enum DPHY_TRAINING_PATTERN_SEL {
8329DPHY_TRAINING_PATTERN_1                  = 0x00000000,
8330DPHY_TRAINING_PATTERN_2                  = 0x00000001,
8331DPHY_TRAINING_PATTERN_3                  = 0x00000002,
8332DPHY_TRAINING_PATTERN_4                  = 0x00000003,
8333} DPHY_TRAINING_PATTERN_SEL;
8334
8335/*
8336 * DPHY_8B10B_RESET enum
8337 */
8338
8339typedef enum DPHY_8B10B_RESET {
8340DPHY_8B10B_NOT_RESET                     = 0x00000000,
8341DPHY_8B10B_RESETET                       = 0x00000001,
8342} DPHY_8B10B_RESET;
8343
8344/*
8345 * DP_DPHY_8B10B_EXT_DISP enum
8346 */
8347
8348typedef enum DP_DPHY_8B10B_EXT_DISP {
8349DP_DPHY_8B10B_EXT_DISP_ZERO              = 0x00000000,
8350DP_DPHY_8B10B_EXT_DISP_ONE               = 0x00000001,
8351} DP_DPHY_8B10B_EXT_DISP;
8352
8353/*
8354 * DPHY_8B10B_CUR_DISP enum
8355 */
8356
8357typedef enum DPHY_8B10B_CUR_DISP {
8358DPHY_8B10B_CUR_DISP_ZERO                 = 0x00000000,
8359DPHY_8B10B_CUR_DISP_ONE                  = 0x00000001,
8360} DPHY_8B10B_CUR_DISP;
8361
8362/*
8363 * DPHY_PRBS_EN enum
8364 */
8365
8366typedef enum DPHY_PRBS_EN {
8367DPHY_PRBS_DISABLE                        = 0x00000000,
8368DPHY_PRBS_ENABLE                         = 0x00000001,
8369} DPHY_PRBS_EN;
8370
8371/*
8372 * DPHY_PRBS_SEL enum
8373 */
8374
8375typedef enum DPHY_PRBS_SEL {
8376DPHY_PRBS7_SELECTED                      = 0x00000000,
8377DPHY_PRBS23_SELECTED                     = 0x00000001,
8378DPHY_PRBS11_SELECTED                     = 0x00000002,
8379} DPHY_PRBS_SEL;
8380
8381/*
8382 * DPHY_SCRAMBLER_DIS enum
8383 */
8384
8385typedef enum DPHY_SCRAMBLER_DIS {
8386DPHY_SCR_ENABLED                         = 0x00000000,
8387DPHY_SCR_DISABLED                        = 0x00000001,
8388} DPHY_SCRAMBLER_DIS;
8389
8390/*
8391 * DPHY_SCRAMBLER_ADVANCE enum
8392 */
8393
8394typedef enum DPHY_SCRAMBLER_ADVANCE {
8395DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY  = 0x00000000,
8396DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL  = 0x00000001,
8397} DPHY_SCRAMBLER_ADVANCE;
8398
8399/*
8400 * DPHY_SCRAMBLER_KCODE enum
8401 */
8402
8403typedef enum DPHY_SCRAMBLER_KCODE {
8404DPHY_SCRAMBLER_KCODE_DISABLED            = 0x00000000,
8405DPHY_SCRAMBLER_KCODE_ENABLED             = 0x00000001,
8406} DPHY_SCRAMBLER_KCODE;
8407
8408/*
8409 * DPHY_LOAD_BS_COUNT_START enum
8410 */
8411
8412typedef enum DPHY_LOAD_BS_COUNT_START {
8413DPHY_LOAD_BS_COUNT_STARTED               = 0x00000000,
8414DPHY_LOAD_BS_COUNT_NOT_STARTED           = 0x00000001,
8415} DPHY_LOAD_BS_COUNT_START;
8416
8417/*
8418 * DPHY_CRC_EN enum
8419 */
8420
8421typedef enum DPHY_CRC_EN {
8422DPHY_CRC_DISABLED                        = 0x00000000,
8423DPHY_CRC_ENABLED                         = 0x00000001,
8424} DPHY_CRC_EN;
8425
8426/*
8427 * DPHY_CRC_CONT_EN enum
8428 */
8429
8430typedef enum DPHY_CRC_CONT_EN {
8431DPHY_CRC_ONE_SHOT                        = 0x00000000,
8432DPHY_CRC_CONTINUOUS                      = 0x00000001,
8433} DPHY_CRC_CONT_EN;
8434
8435/*
8436 * DPHY_CRC_FIELD enum
8437 */
8438
8439typedef enum DPHY_CRC_FIELD {
8440DPHY_CRC_START_FROM_TOP_FIELD            = 0x00000000,
8441DPHY_CRC_START_FROM_BOTTOM_FIELD         = 0x00000001,
8442} DPHY_CRC_FIELD;
8443
8444/*
8445 * DPHY_CRC_SEL enum
8446 */
8447
8448typedef enum DPHY_CRC_SEL {
8449DPHY_CRC_LANE0_SELECTED                  = 0x00000000,
8450DPHY_CRC_LANE1_SELECTED                  = 0x00000001,
8451DPHY_CRC_LANE2_SELECTED                  = 0x00000002,
8452DPHY_CRC_LANE3_SELECTED                  = 0x00000003,
8453} DPHY_CRC_SEL;
8454
8455/*
8456 * DPHY_RX_FAST_TRAINING_CAPABLE enum
8457 */
8458
8459typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
8460DPHY_FAST_TRAINING_NOT_CAPABLE_0         = 0x00000000,
8461DPHY_FAST_TRAINING_CAPABLE               = 0x00000001,
8462} DPHY_RX_FAST_TRAINING_CAPABLE;
8463
8464/*
8465 * DP_SEC_COLLISION_ACK enum
8466 */
8467
8468typedef enum DP_SEC_COLLISION_ACK {
8469DP_SEC_COLLISION_ACK_NO_EFFECT           = 0x00000000,
8470DP_SEC_COLLISION_ACK_CLR_FLAG            = 0x00000001,
8471} DP_SEC_COLLISION_ACK;
8472
8473/*
8474 * DP_SEC_AUDIO_MUTE enum
8475 */
8476
8477typedef enum DP_SEC_AUDIO_MUTE {
8478DP_SEC_AUDIO_MUTE_HW_CTRL                = 0x00000000,
8479DP_SEC_AUDIO_MUTE_SW_CTRL                = 0x00000001,
8480} DP_SEC_AUDIO_MUTE;
8481
8482/*
8483 * DP_SEC_TIMESTAMP_MODE enum
8484 */
8485
8486typedef enum DP_SEC_TIMESTAMP_MODE {
8487DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE       = 0x00000000,
8488DP_SEC_TIMESTAMP_AUTO_CALC_MODE          = 0x00000001,
8489} DP_SEC_TIMESTAMP_MODE;
8490
8491/*
8492 * DP_SEC_ASP_PRIORITY enum
8493 */
8494
8495typedef enum DP_SEC_ASP_PRIORITY {
8496DP_SEC_ASP_LOW_PRIORITY                  = 0x00000000,
8497DP_SEC_ASP_HIGH_PRIORITY                 = 0x00000001,
8498} DP_SEC_ASP_PRIORITY;
8499
8500/*
8501 * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
8502 */
8503
8504typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
8505DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ         = 0x00000000,
8506DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED  = 0x00000001,
8507} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
8508
8509/*
8510 * DP_MSE_SAT_UPDATE_ACT enum
8511 */
8512
8513typedef enum DP_MSE_SAT_UPDATE_ACT {
8514DP_MSE_SAT_UPDATE_NO_ACTION              = 0x00000000,
8515DP_MSE_SAT_UPDATE_WITH_TRIGGER           = 0x00000001,
8516DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER        = 0x00000002,
8517} DP_MSE_SAT_UPDATE_ACT;
8518
8519/*
8520 * DP_MSE_LINK_LINE enum
8521 */
8522
8523typedef enum DP_MSE_LINK_LINE {
8524DP_MSE_LINK_LINE_32_MTP_LONG             = 0x00000000,
8525DP_MSE_LINK_LINE_64_MTP_LONG             = 0x00000001,
8526DP_MSE_LINK_LINE_128_MTP_LONG            = 0x00000002,
8527DP_MSE_LINK_LINE_256_MTP_LONG            = 0x00000003,
8528} DP_MSE_LINK_LINE;
8529
8530/*
8531 * DP_MSE_BLANK_CODE enum
8532 */
8533
8534typedef enum DP_MSE_BLANK_CODE {
8535DP_MSE_BLANK_CODE_SF_FILLED              = 0x00000000,
8536DP_MSE_BLANK_CODE_ZERO_FILLED            = 0x00000001,
8537} DP_MSE_BLANK_CODE;
8538
8539/*
8540 * DP_MSE_TIMESTAMP_MODE enum
8541 */
8542
8543typedef enum DP_MSE_TIMESTAMP_MODE {
8544DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE  = 0x00000000,
8545DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE   = 0x00000001,
8546} DP_MSE_TIMESTAMP_MODE;
8547
8548/*
8549 * DP_MSE_ZERO_ENCODER enum
8550 */
8551
8552typedef enum DP_MSE_ZERO_ENCODER {
8553DP_MSE_NOT_ZERO_FE_ENCODER               = 0x00000000,
8554DP_MSE_ZERO_FE_ENCODER                   = 0x00000001,
8555} DP_MSE_ZERO_ENCODER;
8556
8557/*
8558 * DP_MSE_OUTPUT_DPDBG_DATA enum
8559 */
8560
8561typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
8562DP_MSE_OUTPUT_DPDBG_DATA_DIS             = 0x00000000,
8563DP_MSE_OUTPUT_DPDBG_DATA_EN              = 0x00000001,
8564} DP_MSE_OUTPUT_DPDBG_DATA;
8565
8566/*
8567 * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
8568 */
8569
8570typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
8571DP_DPHY_HBR2_PASS_THROUGH                = 0x00000000,
8572DP_DPHY_HBR2_PATTERN_1                   = 0x00000001,
8573DP_DPHY_HBR2_PATTERN_2_NEG               = 0x00000002,
8574DP_DPHY_HBR2_PATTERN_3                   = 0x00000003,
8575DP_DPHY_HBR2_PATTERN_2_POS               = 0x00000006,
8576} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
8577
8578/*
8579 * DPHY_CRC_MST_PHASE_ERROR_ACK enum
8580 */
8581
8582typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
8583DPHY_CRC_MST_PHASE_ERROR_NO_ACK          = 0x00000000,
8584DPHY_CRC_MST_PHASE_ERROR_ACKED           = 0x00000001,
8585} DPHY_CRC_MST_PHASE_ERROR_ACK;
8586
8587/*
8588 * DPHY_SW_FAST_TRAINING_START enum
8589 */
8590
8591typedef enum DPHY_SW_FAST_TRAINING_START {
8592DPHY_SW_FAST_TRAINING_NOT_STARTED        = 0x00000000,
8593DPHY_SW_FAST_TRAINING_STARTED            = 0x00000001,
8594} DPHY_SW_FAST_TRAINING_START;
8595
8596/*
8597 * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
8598 */
8599
8600typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
8601DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED  = 0x00000000,
8602DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED  = 0x00000001,
8603} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
8604
8605/*
8606 * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
8607 */
8608
8609typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
8610DP_DPHY_FAST_TRAINING_COMPLETE_MASKED    = 0x00000000,
8611DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED  = 0x00000001,
8612} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
8613
8614/*
8615 * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
8616 */
8617
8618typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
8619DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED  = 0x00000000,
8620DP_DPHY_FAST_TRAINING_COMPLETE_ACKED     = 0x00000001,
8621} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
8622
8623/*
8624 * DP_MSA_V_TIMING_OVERRIDE_EN enum
8625 */
8626
8627typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
8628MSA_V_TIMING_OVERRIDE_DISABLED           = 0x00000000,
8629MSA_V_TIMING_OVERRIDE_ENABLED            = 0x00000001,
8630} DP_MSA_V_TIMING_OVERRIDE_EN;
8631
8632/*
8633 * DP_SEC_GSP0_PRIORITY enum
8634 */
8635
8636typedef enum DP_SEC_GSP0_PRIORITY {
8637SEC_GSP0_PRIORITY_LOW                    = 0x00000000,
8638SEC_GSP0_PRIORITY_HIGH                   = 0x00000001,
8639} DP_SEC_GSP0_PRIORITY;
8640
8641/*
8642 * DP_SEC_GSP0_SEND enum
8643 */
8644
8645typedef enum DP_SEC_GSP0_SEND {
8646NOT_SENT                                 = 0x00000000,
8647FORCE_SENT                               = 0x00000001,
8648} DP_SEC_GSP0_SEND;
8649
8650/*******************************************************
8651 * COL_MAN Enums
8652 *******************************************************/
8653
8654/*
8655 * COL_MAN_UPDATE_LOCK enum
8656 */
8657
8658typedef enum COL_MAN_UPDATE_LOCK {
8659COL_MAN_UPDATE_UNLOCKED                  = 0x00000000,
8660COL_MAN_UPDATE_LOCKED                    = 0x00000001,
8661} COL_MAN_UPDATE_LOCK;
8662
8663/*
8664 * COL_MAN_DISABLE_MULTIPLE_UPDATE enum
8665 */
8666
8667typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
8668COL_MAN_MULTIPLE_UPDATE                  = 0x00000000,
8669COL_MAN_MULTIPLE_UPDAT_EDISABLE          = 0x00000001,
8670} COL_MAN_DISABLE_MULTIPLE_UPDATE;
8671
8672/*
8673 * COL_MAN_INPUTCSC_MODE enum
8674 */
8675
8676typedef enum COL_MAN_INPUTCSC_MODE {
8677INPUTCSC_MODE_BYPASS                     = 0x00000000,
8678INPUTCSC_MODE_A                          = 0x00000001,
8679INPUTCSC_MODE_B                          = 0x00000002,
8680INPUTCSC_MODE_UNITY                      = 0x00000003,
8681} COL_MAN_INPUTCSC_MODE;
8682
8683/*
8684 * COL_MAN_INPUTCSC_TYPE enum
8685 */
8686
8687typedef enum COL_MAN_INPUTCSC_TYPE {
8688INPUTCSC_TYPE_12_0                       = 0x00000000,
8689INPUTCSC_TYPE_10_2                       = 0x00000001,
8690INPUTCSC_TYPE_8_4                        = 0x00000002,
8691} COL_MAN_INPUTCSC_TYPE;
8692
8693/*
8694 * COL_MAN_INPUTCSC_CONVERT enum
8695 */
8696
8697typedef enum COL_MAN_INPUTCSC_CONVERT {
8698INPUTCSC_ROUND                           = 0x00000000,
8699INPUTCSC_TRUNCATE                        = 0x00000001,
8700} COL_MAN_INPUTCSC_CONVERT;
8701
8702/*
8703 * COL_MAN_PRESCALE_MODE enum
8704 */
8705
8706typedef enum COL_MAN_PRESCALE_MODE {
8707PRESCALE_MODE_BYPASS                     = 0x00000000,
8708PRESCALE_MODE_PROGRAM                    = 0x00000001,
8709PRESCALE_MODE_UNITY                      = 0x00000002,
8710} COL_MAN_PRESCALE_MODE;
8711
8712/*
8713 * COL_MAN_INPUT_GAMMA_MODE enum
8714 */
8715
8716typedef enum COL_MAN_INPUT_GAMMA_MODE {
8717INGAMMA_MODE_BYPASS                      = 0x00000000,
8718INGAMMA_MODE_FIX                         = 0x00000001,
8719INGAMMA_MODE_FLOAT                       = 0x00000002,
8720} COL_MAN_INPUT_GAMMA_MODE;
8721
8722/*
8723 * COL_MAN_OUTPUT_CSC_MODE enum
8724 */
8725
8726typedef enum COL_MAN_OUTPUT_CSC_MODE {
8727COL_MAN_OUTPUT_CSC_BYPASS                = 0x00000000,
8728COL_MAN_OUTPUT_CSC_RGB                   = 0x00000001,
8729COL_MAN_OUTPUT_CSC_YCrCb601              = 0x00000002,
8730COL_MAN_OUTPUT_CSC_YCrCb709              = 0x00000003,
8731COL_MAN_OUTPUT_CSC_A                     = 0x00000004,
8732COL_MAN_OUTPUT_CSC_B                     = 0x00000005,
8733COL_MAN_OUTPUT_CSC_UNITY                 = 0x00000006,
8734} COL_MAN_OUTPUT_CSC_MODE;
8735
8736/*
8737 * COL_MAN_DENORM_CLAMP_CONTROL enum
8738 */
8739
8740typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
8741DENORM_CLAMP_MODE_UNITY                  = 0x00000000,
8742DENORM_CLAMP_MODE_8                      = 0x00000001,
8743DENORM_CLAMP_MODE_10                     = 0x00000002,
8744DENORM_CLAMP_MODE_12                     = 0x00000003,
8745} COL_MAN_DENORM_CLAMP_CONTROL;
8746
8747/*
8748 * COL_MAN_REGAMMA_MODE_CONTROL enum
8749 */
8750
8751typedef enum COL_MAN_REGAMMA_MODE_CONTROL {
8752COL_MAN_REGAMMA_MODE_BYPASS              = 0x00000000,
8753COL_MAN_REGAMMA_MODE_ROM_A               = 0x00000001,
8754COL_MAN_REGAMMA_MODE_ROM_B               = 0x00000002,
8755COL_MAN_REGAMMA_MODE_A                   = 0x00000003,
8756COL_MAN_REGAMMA_MODE_B                   = 0x00000004,
8757} COL_MAN_REGAMMA_MODE_CONTROL;
8758
8759/*
8760 * COL_MAN_GLOBAL_PASSTHROUGH_ENABLE enum
8761 */
8762
8763typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
8764CM_GLOBAL_PASSTHROUGH_DISBALE            = 0x00000000,
8765CM_GLOBAL_PASSTHROUGH_ENABLE             = 0x00000001,
8766} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
8767
8768/*
8769 * COL_MAN_DEGAMMA_MODE enum
8770 */
8771
8772typedef enum COL_MAN_DEGAMMA_MODE {
8773DEGAMMA_MODE_BYPASS                      = 0x00000000,
8774DEGAMMA_MODE_A                           = 0x00000001,
8775DEGAMMA_MODE_B                           = 0x00000002,
8776} COL_MAN_DEGAMMA_MODE;
8777
8778/*
8779 * COL_MAN_GAMUT_REMAP_MODE enum
8780 */
8781
8782typedef enum COL_MAN_GAMUT_REMAP_MODE {
8783GAMUT_REMAP_MODE_BYPASS                  = 0x00000000,
8784GAMUT_REMAP_MODE_1                       = 0x00000001,
8785GAMUT_REMAP_MODE_2                       = 0x00000002,
8786GAMUT_REMAP_MODE_3                       = 0x00000003,
8787} COL_MAN_GAMUT_REMAP_MODE;
8788
8789/*******************************************************
8790 * MCIF_WB Enums
8791 *******************************************************/
8792
8793/*******************************************************
8794 * DP_AUX Enums
8795 *******************************************************/
8796
8797/*
8798 * DP_AUX_CONTROL_HPD_SEL enum
8799 */
8800
8801typedef enum DP_AUX_CONTROL_HPD_SEL {
8802DP_AUX_CONTROL_HPD1_SELECTED             = 0x00000000,
8803DP_AUX_CONTROL_HPD2_SELECTED             = 0x00000001,
8804DP_AUX_CONTROL_HPD3_SELECTED             = 0x00000002,
8805DP_AUX_CONTROL_HPD4_SELECTED             = 0x00000003,
8806DP_AUX_CONTROL_HPD5_SELECTED             = 0x00000004,
8807DP_AUX_CONTROL_HPD6_SELECTED             = 0x00000005,
8808} DP_AUX_CONTROL_HPD_SEL;
8809
8810/*
8811 * DP_AUX_CONTROL_TEST_MODE enum
8812 */
8813
8814typedef enum DP_AUX_CONTROL_TEST_MODE {
8815DP_AUX_CONTROL_TEST_MODE_DISABLE         = 0x00000000,
8816DP_AUX_CONTROL_TEST_MODE_ENABLE          = 0x00000001,
8817} DP_AUX_CONTROL_TEST_MODE;
8818
8819/*
8820 * DP_AUX_SW_CONTROL_SW_GO enum
8821 */
8822
8823typedef enum DP_AUX_SW_CONTROL_SW_GO {
8824DP_AUX_SW_CONTROL_SW__NOT_GO             = 0x00000000,
8825DP_AUX_SW_CONTROL_SW__GO                 = 0x00000001,
8826} DP_AUX_SW_CONTROL_SW_GO;
8827
8828/*
8829 * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
8830 */
8831
8832typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
8833DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG      = 0x00000000,
8834DP_AUX_SW_CONTROL_LS_READ__TRIG          = 0x00000001,
8835} DP_AUX_SW_CONTROL_LS_READ_TRIG;
8836
8837/*
8838 * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
8839 */
8840
8841typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
8842DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW  = 0x00000000,
8843DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW  = 0x00000001,
8844DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC  = 0x00000002,
8845DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS  = 0x00000003,
8846} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
8847
8848/*
8849 * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
8850 */
8851
8852typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
8853DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ  = 0x00000000,
8854DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ      = 0x00000001,
8855} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
8856
8857/*
8858 * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
8859 */
8860
8861typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
8862DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
8863DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG   = 0x00000001,
8864} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
8865
8866/*
8867 * DP_AUX_INT_ACK enum
8868 */
8869
8870typedef enum DP_AUX_INT_ACK {
8871DP_AUX_INT__NOT_ACK                      = 0x00000000,
8872DP_AUX_INT__ACK                          = 0x00000001,
8873} DP_AUX_INT_ACK;
8874
8875/*
8876 * DP_AUX_LS_UPDATE_ACK enum
8877 */
8878
8879typedef enum DP_AUX_LS_UPDATE_ACK {
8880DP_AUX_INT_LS_UPDATE_NOT_ACK             = 0x00000000,
8881DP_AUX_INT_LS_UPDATE_ACK                 = 0x00000001,
8882} DP_AUX_LS_UPDATE_ACK;
8883
8884/*
8885 * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
8886 */
8887
8888typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
8889DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK  = 0x00000000,
8890DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF  = 0x00000001,
8891} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
8892
8893/*
8894 * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
8895 */
8896
8897typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
8898DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
8899DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
8900DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
8901DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
8902} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
8903
8904/*
8905 * DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN enum
8906 */
8907
8908typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
8909DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US = 0x00000000,
8910DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US = 0x00000001,
8911DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US = 0x00000002,
8912DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US = 0x00000003,
8913DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US = 0x00000004,
8914DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US = 0x00000005,
8915DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US = 0x00000006,
8916DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US = 0x00000007,
8917} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
8918
8919/*
8920 * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
8921 */
8922
8923typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
8924DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
8925DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
8926DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
8927DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
8928DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
8929DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
8930} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
8931
8932/*
8933 * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
8934 */
8935
8936typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
8937DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD  = 0x00000000,
8938DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD  = 0x00000001,
8939DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD  = 0x00000002,
8940DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD  = 0x00000003,
8941DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD  = 0x00000004,
8942DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD  = 0x00000005,
8943DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD  = 0x00000006,
8944DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD  = 0x00000007,
8945} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
8946
8947/*
8948 * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
8949 */
8950
8951typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
8952DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD  = 0x00000000,
8953DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD  = 0x00000001,
8954DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD  = 0x00000002,
8955DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD  = 0x00000003,
8956DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD  = 0x00000004,
8957DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD  = 0x00000005,
8958DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD  = 0x00000006,
8959DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD  = 0x00000007,
8960} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
8961
8962/*
8963 * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
8964 */
8965
8966typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
8967DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
8968DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
8969DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
8970DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
8971} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
8972
8973/*
8974 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
8975 */
8976
8977typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
8978DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
8979DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
8980} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
8981
8982/*
8983 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
8984 */
8985
8986typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
8987DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
8988DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
8989} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
8990
8991/*
8992 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
8993 */
8994
8995typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
8996DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
8997DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
8998} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
8999
9000/*

9001 * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
9002 */
9003
9004typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
9005DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
9006DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
9007DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
9008DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
9009} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
9010
9011/*
9012 * DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN enum
9013 */
9014
9015typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
9016DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US = 0x00000000,
9017DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US = 0x00000001,
9018DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US = 0x00000002,
9019DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US = 0x00000003,
9020DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US = 0x00000004,
9021DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US = 0x00000005,
9022DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US = 0x00000006,
9023DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US = 0x00000007,
9024} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
9025
9026/*
9027 * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
9028 */
9029
9030typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
9031DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2  = 0x00000000,
9032DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4  = 0x00000001,
9033DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8  = 0x00000002,
9034DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16  = 0x00000003,
9035DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32  = 0x00000004,
9036DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64  = 0x00000005,
9037DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128  = 0x00000006,
9038DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256  = 0x00000007,
9039} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
9040
9041/*
9042 * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
9043 */
9044
9045typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
9046DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX  = 0x00000000,
9047DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX  = 0x00000001,
9048} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
9049
9050/*
9051 * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
9052 */
9053
9054typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
9055DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
9056DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
9057DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
9058DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
9059} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
9060
9061/*
9062 * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
9063 */
9064
9065typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
9066DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
9067DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
9068DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
9069DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
9070} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
9071
9072/*
9073 * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
9074 */
9075
9076typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
9077DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0  = 0x00000000,
9078DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64  = 0x00000001,
9079DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128  = 0x00000002,
9080DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256  = 0x00000003,
9081} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
9082
9083/*
9084 * DP_AUX_ERR_OCCURRED_ACK enum
9085 */
9086
9087typedef enum DP_AUX_ERR_OCCURRED_ACK {
9088DP_AUX_ERR_OCCURRED__NOT_ACK             = 0x00000000,
9089DP_AUX_ERR_OCCURRED__ACK                 = 0x00000001,
9090} DP_AUX_ERR_OCCURRED_ACK;
9091
9092/*
9093 * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
9094 */
9095
9096typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
9097DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK    = 0x00000000,
9098DP_AUX_POTENTIAL_ERR_REACHED__ACK        = 0x00000001,
9099} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
9100
9101/*
9102 * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
9103 */
9104
9105typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
9106ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
9107ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK    = 0x00000001,
9108} DP_AUX_DEFINITE_ERR_REACHED_ACK;
9109
9110/*
9111 * DP_AUX_RESET enum
9112 */
9113
9114typedef enum DP_AUX_RESET {
9115DP_AUX_RESET_DEASSERTED                  = 0x00000000,
9116DP_AUX_RESET_ASSERTED                    = 0x00000001,
9117} DP_AUX_RESET;
9118
9119/*
9120 * DP_AUX_RESET_DONE enum
9121 */
9122
9123typedef enum DP_AUX_RESET_DONE {
9124DP_AUX_RESET_SEQUENCE_NOT_DONE           = 0x00000000,
9125DP_AUX_RESET_SEQUENCE_DONE               = 0x00000001,
9126} DP_AUX_RESET_DONE;
9127
9128/*******************************************************
9129 * DSI Enums
9130 *******************************************************/
9131
9132/*
9133 * DSI_COMMAND_MODE_SRC_FORMAT enum
9134 */
9135
9136typedef enum DSI_COMMAND_MODE_SRC_FORMAT {
9137DSI_COMMAND_SRC_FORMAT_RGB8BIT           = 0x00000002,
9138DSI_COMMAND_SRC_FORMAT_RGB332            = 0x00000003,
9139DSI_COMMAND_SRC_FORMAT_RGB444            = 0x00000004,
9140DSI_COMMAND_SRC_FORMAT_RGB555            = 0x00000005,
9141DSI_COMMAND_SRC_FORMAT_RGB565            = 0x00000006,
9142DSI_COMMAND_SRC_FORMAT_RGB888            = 0x00000008,
9143} DSI_COMMAND_MODE_SRC_FORMAT;
9144
9145/*
9146 * DSI_COMMAND_MODE_DST_FORMAT enum
9147 */
9148
9149typedef enum DSI_COMMAND_MODE_DST_FORMAT {
9150DSI_COMMAND_DST_FORMAT_RGB111            = 0x00000000,
9151DSI_COMMAND_DST_FORMAT_RGB332            = 0x00000003,
9152DSI_COMMAND_DST_FORMAT_RGB444            = 0x00000004,
9153DSI_COMMAND_DST_FORMAT_RGB565            = 0x00000006,
9154DSI_COMMAND_DST_FORMAT_RGB666            = 0x00000007,
9155DSI_COMMAND_DST_FORMAT_RGB888            = 0x00000008,
9156} DSI_COMMAND_MODE_DST_FORMAT;
9157
9158/*
9159 * DSI_FLAG_CLR enum
9160 */
9161
9162typedef enum DSI_FLAG_CLR {
9163DSI_FLAG_NO_CLEAR                        = 0x00000000,
9164DSI_FLAG_CLEAR                           = 0x00000001,
9165} DSI_FLAG_CLR;
9166
9167/*
9168 * DSI_BIT_SWAP enum
9169 */
9170
9171typedef enum DSI_BIT_SWAP {
9172DSI_BIT_SWAP_DISABLE                     = 0x00000000,
9173DSI_BIT_SWAP_ENABLE                      = 0x00000001,
9174} DSI_BIT_SWAP;
9175
9176/*
9177 * DSI_CLK_GATING enum
9178 */
9179
9180typedef enum DSI_CLK_GATING {
9181DSI_CLK_GATING_ENABLE                    = 0x00000000,
9182DSI_CLK_GATING_DISABLE                   = 0x00000001,
9183} DSI_CLK_GATING;
9184
9185/*
9186 * DSI_LANE_ULPS_REQUEST enum
9187 */
9188
9189typedef enum DSI_LANE_ULPS_REQUEST {
9190DSI_LANE_ULPS_REQUEST_DEASSERT           = 0x00000000,
9191DSI_LANE_ULPS_REQUEST_ASSERT             = 0x00000001,
9192} DSI_LANE_ULPS_REQUEST;
9193
9194/*
9195 * DSI_LANE_ULPS_EXIT enum
9196 */
9197
9198typedef enum DSI_LANE_ULPS_EXIT {
9199DSI_LANE_ULPS_EXIT_DEASSERT              = 0x00000000,
9200DSI_LANE_ULPS_EXIT_ASSERT                = 0x00000001,
9201} DSI_LANE_ULPS_EXIT;
9202
9203/*
9204 * DSI_LANE_FORCE_TX_STOP enum
9205 */
9206
9207typedef enum DSI_LANE_FORCE_TX_STOP {
9208DSI_LANE_FORCE_TX_STOP_DEASSERT          = 0x00000000,
9209DSI_LANE_FORCE_TX_STOP_ASSERT            = 0x00000001,
9210} DSI_LANE_FORCE_TX_STOP;
9211
9212/*
9213 * DSI_CLOCK_LANE_HS_FORCE_REQUEST enum
9214 */
9215
9216typedef enum DSI_CLOCK_LANE_HS_FORCE_REQUEST {
9217DSI_CLOCK_LANE_HS_FORCE_REQUEST_DEASSERT  = 0x00000000,
9218DSI_CLOCK_LANE_HS_FORCE_REQUEST_ASSERT   = 0x00000001,
9219} DSI_CLOCK_LANE_HS_FORCE_REQUEST;
9220
9221/*
9222 * DSI_CONTROLLER_EN enum
9223 */
9224
9225typedef enum DSI_CONTROLLER_EN {
9226DSI_CONTROLLER_DISABLE                   = 0x00000000,
9227DSI_CONTROLLER_ENABLE                    = 0x00000001,
9228} DSI_CONTROLLER_EN;
9229
9230/*
9231 * DSI_VIDEO_MODE_EN enum
9232 */
9233
9234typedef enum DSI_VIDEO_MODE_EN {
9235DSI_VIDEO_MODE_DISABLE                   = 0x00000000,
9236DSI_VIDEO_MODE_ENABLE                    = 0x00000001,
9237} DSI_VIDEO_MODE_EN;
9238
9239/*
9240 * DSI_CMD_MODE_EN enum
9241 */
9242
9243typedef enum DSI_CMD_MODE_EN {
9244DSI_CMD_MODE_DISABLE                     = 0x00000000,
9245DSI_CMD_MODE_ENABLE                      = 0x00000001,
9246} DSI_CMD_MODE_EN;
9247
9248/*
9249 * DSI_DATA_LANE0_EN enum
9250 */
9251
9252typedef enum DSI_DATA_LANE0_EN {
9253DSI_DATA_LANE0_DISABLE                   = 0x00000000,
9254DSI_DATA_LANE0_ENABLE                    = 0x00000001,
9255} DSI_DATA_LANE0_EN;
9256
9257/*
9258 * DSI_DATA_LANE1_EN enum
9259 */
9260
9261typedef enum DSI_DATA_LANE1_EN {
9262DSI_DATA_LANE1_DISABLE                   = 0x00000000,
9263DSI_DATA_LANE1_ENABLE                    = 0x00000001,
9264} DSI_DATA_LANE1_EN;
9265
9266/*
9267 * DSI_DATA_LANE2_EN enum
9268 */
9269
9270typedef enum DSI_DATA_LANE2_EN {
9271DSI_DATA_LANE2_DISABLE                   = 0x00000000,
9272DSI_DATA_LANE2_ENABLE                    = 0x00000001,
9273} DSI_DATA_LANE2_EN;
9274
9275/*
9276 * DSI_DATA_LANE3_EN enum
9277 */
9278
9279typedef enum DSI_DATA_LANE3_EN {
9280DSI_DATA_LANE3_DISABLE                   = 0x00000000,
9281DSI_DATA_LANE3_ENABLE                    = 0x00000001,
9282} DSI_DATA_LANE3_EN;
9283
9284/*
9285 * DSI_CLOCK_LANE_EN enum
9286 */
9287
9288typedef enum DSI_CLOCK_LANE_EN {
9289DSI_CLOCK_LANE_DISABLE                   = 0x00000000,
9290DSI_CLOCK_LANE_ENABLE                    = 0x00000001,
9291} DSI_CLOCK_LANE_EN;
9292
9293/*
9294 * DSI_PHY_DATA_LANE0_EN enum
9295 */
9296
9297typedef enum DSI_PHY_DATA_LANE0_EN {
9298DSI_PHY_DATA_LANE0_DISABLE               = 0x00000000,
9299DSI_PHY_DATA_LANE0_ENABLE                = 0x00000001,
9300} DSI_PHY_DATA_LANE0_EN;
9301
9302/*
9303 * DSI_PHY_DATA_LANE1_EN enum
9304 */
9305
9306typedef enum DSI_PHY_DATA_LANE1_EN {
9307DSI_PHY_DATA_LANE1_DISABLE               = 0x00000000,
9308DSI_PHY_DATA_LANE1_ENABLE                = 0x00000001,
9309} DSI_PHY_DATA_LANE1_EN;
9310
9311/*
9312 * DSI_PHY_DATA_LANE2_EN enum
9313 */
9314
9315typedef enum DSI_PHY_DATA_LANE2_EN {
9316DSI_PHY_DATA_LANE2_DISABLE               = 0x00000000,
9317DSI_PHY_DATA_LANE2_ENABLE                = 0x00000001,
9318} DSI_PHY_DATA_LANE2_EN;
9319
9320/*
9321 * DSI_PHY_DATA_LANE3_EN enum
9322 */
9323
9324typedef enum DSI_PHY_DATA_LANE3_EN {
9325DSI_PHY_DATA_LANE3_DISABLE               = 0x00000000,
9326DSI_PHY_DATA_LANE3_ENABLE                = 0x00000001,
9327} DSI_PHY_DATA_LANE3_EN;
9328
9329/*
9330 * DSI_RESET_DISPCLK enum
9331 */
9332
9333typedef enum DSI_RESET_DISPCLK {
9334DSI_NO_RESET_ON_DISPCLK_DOMAIN_LOGIC     = 0x00000000,
9335DSI_RESET_ON_DISPCLK_DOMAIN_LOGIC        = 0x00000001,
9336} DSI_RESET_DISPCLK;
9337
9338/*
9339 * DSI_RESET_DSICLK enum
9340 */
9341
9342typedef enum DSI_RESET_DSICLK {
9343DSI_NO_RESET_ON_DSICLK_DOMAIN_LOGIC      = 0x00000000,
9344DSI_RESET_ON_DSICLK_DOMAIN_LOGIC         = 0x00000001,
9345} DSI_RESET_DSICLK;
9346
9347/*
9348 * DSI_RESET_BYTECLK enum
9349 */
9350
9351typedef enum DSI_RESET_BYTECLK {
9352DSI_NO_RESET_ON_BYTECLK_DOMAIN_LOGIC     = 0x00000000,
9353DSI_RESET_ON_BYTECLK_DOMAIN_LOGIC        = 0x00000001,
9354} DSI_RESET_BYTECLK;
9355
9356/*
9357 * DSI_RESET_ESCCLK enum
9358 */
9359
9360typedef enum DSI_RESET_ESCCLK {
9361DSI_NO_RESET_ON_ESCCLK_DOMAIN_LOGIC      = 0x00000000,
9362DSI_RESET_ON_ESCCLK_DOMAIN_LOGIC         = 0x00000001,
9363} DSI_RESET_ESCCLK;
9364
9365/*
9366 * DSI_CRTC_SEL enum
9367 */
9368
9369typedef enum DSI_CRTC_SEL {
9370DSI_GET_PIXEL_STREAM_FROM_FMT0           = 0x00000000,
9371DSI_GET_PIXEL_STREAM_FROM_FMT1           = 0x00000001,
9372DSI_GET_PIXEL_STREAM_FROM_FMT2           = 0x00000002,
9373DSI_GET_PIXEL_STREAM_FROM_FMT3           = 0x00000003,
9374DSI_GET_PIXEL_STREAM_FROM_FMT4           = 0x00000004,
9375DSI_GET_PIXEL_STREAM_FROM_FMT5           = 0x00000005,
9376} DSI_CRTC_SEL;
9377
9378/*
9379 * DSI_PACKET_BYTE_MSB_LSB_FLIP enum
9380 */
9381
9382typedef enum DSI_PACKET_BYTE_MSB_LSB_FLIP {
9383DSI_PACKET_BYTE_MSB_LSB_FLIP_NO_SWAP     = 0x00000000,
9384DSI_PACKET_BYTE_MSB_LSB_FLIP_SWAP        = 0x00000001,
9385} DSI_PACKET_BYTE_MSB_LSB_FLIP;
9386
9387/*
9388 * DSI_VIDEO_MODE_DST_FORMAT enum
9389 */
9390
9391typedef enum DSI_VIDEO_MODE_DST_FORMAT {
9392DSI_VIDEO_DST_FORMAT_RGB565              = 0x00000000,
9393DSI_VIDEO_DST_FORMAT_RGB666_PACKED       = 0x00000001,
9394DSI_VIDEO_DST_FORMAT_RGB666_LOOSELY_PACKED = 0x00000002,
9395DSI_VIDEO_DST_FORMAT_RGB888              = 0x00000003,
9396} DSI_VIDEO_MODE_DST_FORMAT;
9397
9398/*
9399 * DSI_VIDEO_TRAFFIC_MODE enum
9400 */
9401
9402typedef enum DSI_VIDEO_TRAFFIC_MODE {
9403DSI_TRAFFIC_MODE_SYNC_PULSES             = 0x00000000,
9404DSI_TRAFFIC_MODE_SYNC_EVENTS             = 0x00000001,
9405DSI_TRAFFIC_MODE_BURST                   = 0x00000002,
9406DSI_TRAFFIC_MODE_RESERVED                = 0x00000003,
9407} DSI_VIDEO_TRAFFIC_MODE;
9408
9409/*
9410 * DSI_VIDEO_BLLP_PWR_MODE enum
9411 */
9412
9413typedef enum DSI_VIDEO_BLLP_PWR_MODE {
9414DSI_VIDEO_BLLP_PWR_MODE_HS               = 0x00000000,
9415DSI_VIDEO_BLLP_PWR_MODE_LP               = 0x00000001,
9416} DSI_VIDEO_BLLP_PWR_MODE;
9417
9418/*
9419 * DSI_VIDEO_EOF_BLLP_PWR_MODE enum
9420 */
9421
9422typedef enum DSI_VIDEO_EOF_BLLP_PWR_MODE {
9423DSI_VIDEO_EOF_BLLP_PWR_MODE_HS           = 0x00000000,
9424DSI_VIDEO_EOF_BLLP_PWR_MODE_LP           = 0x00000001,
9425} DSI_VIDEO_EOF_BLLP_PWR_MODE;
9426
9427/*
9428 * DSI_VIDEO_PWR_MODE enum
9429 */
9430
9431typedef enum DSI_VIDEO_PWR_MODE {
9432DSI_VIDEO_PWR_MODE_HS                    = 0x00000000,
9433DSI_VIDEO_PWR_MODE_LP                    = 0x00000001,
9434} DSI_VIDEO_PWR_MODE;
9435
9436/*
9437 * DSI_VIDEO_PULSE_MODE_OPT enum
9438 */
9439
9440typedef enum DSI_VIDEO_PULSE_MODE_OPT {
9441PULSE_MODE_OPT_NO_HSA                    = 0x00000000,
9442PULSE_MODE_OPT_SEND                      = 0x00000001,
9443} DSI_VIDEO_PULSE_MODE_OPT;
9444
9445/*
9446 * DSI_RGB_SWAP enum
9447 */
9448
9449typedef enum DSI_RGB_SWAP {
9450DSI_SWAP_RGB                             = 0x00000000,
9451DSI_SWAP_RBG                             = 0x00000001,
9452DSI_SWAP_BGR                             = 0x00000002,
9453DSI_SWAP_BRG                             = 0x00000003,
9454DSI_SWAP_GRB                             = 0x00000004,
9455DSI_SWAP_GBR                             = 0x00000005,
9456} DSI_RGB_SWAP;
9457
9458/*
9459 * DSI_CMD_PACKET_TYPE enum
9460 */
9461
9462typedef enum DSI_CMD_PACKET_TYPE {
9463DSI_CMD_PACKET_TYPE_SHORT                = 0x00000000,
9464DSI_CMD_PACKET_TYPE_LONG                 = 0x00000001,
9465} DSI_CMD_PACKET_TYPE;
9466
9467/*
9468 * DSI_CMD_PWR_MODE enum
9469 */
9470
9471typedef enum DSI_CMD_PWR_MODE {
9472DSI_CMD_PWR_MODE_HS                      = 0x00000000,
9473DSI_CMD_PWR_MODE_LP                      = 0x00000001,
9474} DSI_CMD_PWR_MODE;
9475
9476/*
9477 * DSI_CMD_EMBEDDED_MODE enum
9478 */
9479
9480typedef enum DSI_CMD_EMBEDDED_MODE {
9481CMD_EMBEDDED_MODE_DISABLE                = 0x00000000,
9482CMD_EMBEDDED_MODE_ENABLE                 = 0x00000001,
9483} DSI_CMD_EMBEDDED_MODE;
9484
9485/*
9486 * DSI_CMD_ORDER enum
9487 */
9488
9489typedef enum DSI_CMD_ORDER {
9490DSI_CMD_ORDER_COMMAND_FIRST              = 0x00000000,
9491DSI_CMD_ORDER_DATA_FIRST                 = 0x00000001,
9492} DSI_CMD_ORDER;
9493
9494/*
9495 * DSI_DATA_BUFFER_ID enum
9496 */
9497
9498typedef enum DSI_DATA_BUFFER_ID {
9499DSI_DATA_BUFFER_OFFSET0                  = 0x00000000,
9500DSI_DATA_BUFFER_OFFSET1                  = 0x00000001,
9501} DSI_DATA_BUFFER_ID;
9502
9503/*
9504 * DSI_DWORD_BYTE_SWAP enum
9505 */
9506
9507typedef enum DSI_DWORD_BYTE_SWAP {
9508DWORD_BYTE_SWAP_NO_SWAP                  = 0x00000000,
9509DWORD_BYTE_SWAP_BYTE_SWAP                = 0x00000001,
9510DWORD_BYTE_SWAP_WORD_SWAP                = 0x00000002,
9511DWORD_BYTE_SWAP_BOTH_SWAP                = 0x00000003,
9512} DSI_DWORD_BYTE_SWAP;
9513
9514/*
9515 * DSI_INSERT_DCS_COMMAND enum
9516 */
9517
9518typedef enum DSI_INSERT_DCS_COMMAND {
9519DSI_INSERT_DCS_COMMAND_DISABLE           = 0x00000000,
9520DSI_INSERT_DCS_COMMAND_ENABLE            = 0x00000001,
9521} DSI_INSERT_DCS_COMMAND;
9522
9523/*
9524 * DSI_DMAFIFO_WRITE_WATERMARK enum
9525 */
9526
9527typedef enum DSI_DMAFIFO_WRITE_WATERMARK {
9528DSI_DMAFIFO_WRITE_WATERMARK_HALF         = 0x00000000,
9529DSI_DMAFIFO_WRITE_WATERMARK_FOURTH       = 0x00000001,
9530DSI_DMAFIFO_WRITE_WATERMARK_EIGHTH       = 0x00000002,
9531DSI_DMAFIFO_WRITE_WATERMARK_SIXTEENTH    = 0x00000003,
9532} DSI_DMAFIFO_WRITE_WATERMARK;
9533
9534/*
9535 * DSI_DMAFIFO_READ_WATERMARK enum
9536 */
9537
9538typedef enum DSI_DMAFIFO_READ_WATERMARK {
9539DSI_DMAFIFO_READ_WATERMARK_HALF          = 0x00000000,
9540DSI_DMAFIFO_READ_WATERMARK_FOURTH        = 0x00000001,
9541DSI_DMAFIFO_READ_WATERMARK_EIGHTH        = 0x00000002,
9542DSI_DMAFIFO_READ_WATERMARK_SIXTEENTH     = 0x00000003,
9543} DSI_DMAFIFO_READ_WATERMARK;
9544
9545/*
9546 * DSI_USE_DENG_LENGTH enum
9547 */
9548
9549typedef enum DSI_USE_DENG_LENGTH {
9550DSI_USE_DENG_LENGTH_DISABLE              = 0x00000000,
9551DSI_USE_DENG_LENGTH_ENABLE               = 0x00000001,
9552} DSI_USE_DENG_LENGTH;
9553
9554/*
9555 * DSI_COMMAND_TRIGGER_MODE enum
9556 */
9557
9558typedef enum DSI_COMMAND_TRIGGER_MODE {
9559DSI_COMMAND_TRIGGER_MODE_AUTO            = 0x00000000,
9560DSI_COMMAND_TRIGGER_MODE_MANUAL          = 0x00000001,
9561} DSI_COMMAND_TRIGGER_MODE;
9562
9563/*
9564 * DSI_COMMAND_TRIGGER_SEL enum
9565 */
9566
9567typedef enum DSI_COMMAND_TRIGGER_SEL {
9568DSI_COMMAND_TRIGGER_SEL_NONE             = 0x00000000,
9569DSI_COMMAND_TRIGGER_SEL_CRTC             = 0x00000001,
9570DSI_COMMAND_TRIGGER_SEL_TE               = 0x00000002,
9571DSI_COMMAND_TRIGGER_SEL_HW               = 0x00000003,
9572} DSI_COMMAND_TRIGGER_SEL;
9573
9574/*
9575 * DSI_HW_SOURCE_SEL enum
9576 */
9577
9578typedef enum DSI_HW_SOURCE_SEL {
9579HW_SOURCE_SEL_NONE                       = 0x00000000,
9580HW_SOURCE_SEL_DSC_VUP                    = 0x00000001,
9581HW_SOURCE_SEL_DSC_VLP                    = 0x00000002,
9582HW_SOURCE_SEL_DSC_JPEG                   = 0x00000003,
9583} DSI_HW_SOURCE_SEL;
9584
9585/*
9586 * DSI_COMMAND_TRIGGER_ORDER enum
9587 */
9588
9589typedef enum DSI_COMMAND_TRIGGER_ORDER {
9590DSI_COMMAND_TRIGGER_ORDER_DMA            = 0x00000000,
9591DSI_COMMAND_TRIGGER_ORDER_DENG           = 0x00000001,
9592} DSI_COMMAND_TRIGGER_ORDER;
9593
9594/*
9595 * DSI_TE_SRC_SEL enum
9596 */
9597
9598typedef enum DSI_TE_SRC_SEL {
9599DSI_TE_SEL_LINK                          = 0x00000000,
9600DSI_TE_SEL_PIN                           = 0x00000001,
9601} DSI_TE_SRC_SEL;
9602
9603/*
9604 * DSI_EXT_TE_MUX enum
9605 */
9606
9607typedef enum DSI_EXT_TE_MUX {
9608DSI_XT_TE_MUX_LCDD17                     = 0x00000000,
9609DSI_XT_TE_MUX_DCLK                       = 0x00000001,
9610DSI_XT_TE_MUX_SS                         = 0x00000002,
9611DSI_XT_TE_MUX_GCLK                       = 0x00000003,
9612DSI_XT_TE_MUX_GOE                        = 0x00000004,
9613DSI_XT_TE_MUX_DINV                       = 0x00000005,
9614DSI_XT_TE_MUX_FRAME                      = 0x00000006,
9615DSI_XT_TE_MUX_GPIO4                      = 0x00000007,
9616DSI_XT_TE_MUX_GPIO5                      = 0x00000008,
9617} DSI_EXT_TE_MUX;
9618
9619/*
9620 * DSI_EXT_TE_MODE enum
9621 */
9622
9623typedef enum DSI_EXT_TE_MODE {
9624DSI_EXT_TE_MODE_VSYNC_EDGE               = 0x00000000,
9625DSI_EXT_TE_MODE_VSYNC_WIDTH              = 0x00000001,
9626DSI_EXT_TE_MODE_HVSYNC_EDGE              = 0x00000002,
9627DSI_EXT_TE_MODE_HVSYNC_WIDTH             = 0x00000003,
9628} DSI_EXT_TE_MODE;
9629
9630/*
9631 * DSI_EXT_RESET_POL enum
9632 */
9633
9634typedef enum DSI_EXT_RESET_POL {
9635DSI_EXT_RESET_POL_HIGH                   = 0x00000000,
9636DSI_EXT_RESET_POL_LOW                    = 0x00000001,
9637} DSI_EXT_RESET_POL;
9638
9639/*
9640 * DSI_EXT_TE_POL enum
9641 */
9642
9643typedef enum DSI_EXT_TE_POL {
9644DSI_EXT_TE_POL_RISING                    = 0x00000000,
9645DSI_EXT_TE_POL_FALLING                   = 0x00000001,
9646} DSI_EXT_TE_POL;
9647
9648/*
9649 * DSI_RESET_PANEL enum
9650 */
9651
9652typedef enum DSI_RESET_PANEL {
9653DSI_RESET_PANEL_DEASSERT                 = 0x00000000,
9654DSI_RESET_PANEL_ASSERT                   = 0x00000001,
9655} DSI_RESET_PANEL;
9656
9657/*
9658 * DSI_CRC_ENABLE enum
9659 */
9660
9661typedef enum DSI_CRC_ENABLE {
9662DSI_CRC_CAL_DISABLE                      = 0x00000000,
9663DSI_CRC_CAL_ENABLE                       = 0x00000001,
9664} DSI_CRC_ENABLE;
9665
9666/*
9667 * DSI_TX_EOT_APPEND enum
9668 */
9669
9670typedef enum DSI_TX_EOT_APPEND {
9671DSI_TX_EOT_APPEND_DISABLE                = 0x00000000,
9672DSI_TX_EOT_APPEND_ENABLE                 = 0x00000001,
9673} DSI_TX_EOT_APPEND;
9674
9675/*
9676 * DSI_RX_EOT_IGNORE enum
9677 */
9678
9679typedef enum DSI_RX_EOT_IGNORE {
9680DSI_RX_EOT_IGNORE_DISABLE                = 0x00000000,
9681DSI_RX_EOT_IGNORE_ENABLE                 = 0x00000001,
9682} DSI_RX_EOT_IGNORE;
9683
9684/*
9685 * DSI_MIPI_BIST_RESET enum
9686 */
9687
9688typedef enum DSI_MIPI_BIST_RESET {
9689DSI_MIPI_BIST_RESET_DEASSERT             = 0x00000000,
9690DSI_MIPI_BIST_RESET_ASSERT               = 0x00000001,
9691} DSI_MIPI_BIST_RESET;
9692
9693/*
9694 * DSI_MIPI_BIST_VIDEO_FRMT enum
9695 */
9696
9697typedef enum DSI_MIPI_BIST_VIDEO_FRMT {
9698DSI_MIPI_BIST_VIDEO_FRMT_YUV422          = 0x00000000,
9699DSI_MIPI_BIST_VIDEO_FRMT_RAW8            = 0x00000001,
9700} DSI_MIPI_BIST_VIDEO_FRMT;
9701
9702/*
9703 * DSI_MIPI_BIST_START enum
9704 */
9705
9706typedef enum DSI_MIPI_BIST_START {
9707DSI_MIPI_BIST_START_DEASSERT             = 0x00000000,
9708DSI_MIPI_BIST_START_ASSERT               = 0x00000001,
9709} DSI_MIPI_BIST_START;
9710
9711/*
9712 * DSI_DBG_CLK_SEL enum
9713 */
9714
9715typedef enum DSI_DBG_CLK_SEL {
9716DSI_TEST_CLK_SEL_DISPCLK_P               = 0x00000000,
9717DSI_TEST_CLK_SEL_DISPCLK_G               = 0x00000001,
9718DSI_TEST_CLK_SEL_DISPCLK_R               = 0x00000002,
9719DSI_TEST_CLK_SEL_ESCCLK_G                = 0x00000003,
9720DSI_TEST_CLK_SEL_BYTECLK_G               = 0x00000004,
9721DSI_TEST_CLK_SEL_DSICLK_P                = 0x00000005,
9722DSI_TEST_CLK_SEL_DSICLK_R                = 0x00000006,
9723DSI_TEST_CLK_SEL_DSICLK_G                = 0x00000007,
9724DSI_TEST_CLK_SEL_DSICLK_TRN              = 0x00000008,
9725} DSI_DBG_CLK_SEL;
9726
9727/*
9728 * DSI_DENG_FIFO_USE_OVERWRITE_LEVEL enum
9729 */
9730
9731typedef enum DSI_DENG_FIFO_USE_OVERWRITE_LEVEL {
9732DSI_DENG_FIFO_LEVEL_OVERWRITE            = 0x00000000,
9733DSI_DENG_FIFO_LEVEL_CAL_AVERAGE          = 0x00000001,
9734} DSI_DENG_FIFO_USE_OVERWRITE_LEVEL;
9735
9736/*
9737 * DSI_DENG_FIFO_FORCE_RECAL_AVERAGE enum
9738 */
9739
9740typedef enum DSI_DENG_FIFO_FORCE_RECAL_AVERAGE {
9741DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_DEASSERT  = 0x00000000,
9742DSI_DENG_FIFO_FORCE_RECAL_AVERAGE_ASSERT  = 0x00000001,
9743} DSI_DENG_FIFO_FORCE_RECAL_AVERAGE;
9744
9745/*
9746 * DSI_DENG_FIFO_FORCE_RECOMP_MINMAX enum
9747 */
9748
9749typedef enum DSI_DENG_FIFO_FORCE_RECOMP_MINMAX {
9750DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_DEASSERT  = 0x00000000,
9751DSI_DENG_FIFO_FORCE_RECOMP_MINMAX_ASSERT  = 0x00000001,
9752} DSI_DENG_FIFO_FORCE_RECOMP_MINMAX;
9753
9754/*
9755 * DSI_DENG_FIFO_START enum
9756 */
9757
9758typedef enum DSI_DENG_FIFO_START {
9759DSI_DENG_FIFO_START_DEASSERT             = 0x00000000,
9760DSI_DENG_FIFO_START_ASSERT               = 0x00000001,
9761} DSI_DENG_FIFO_START;
9762
9763/*
9764 * DSI_USE_CMDFIFO enum
9765 */
9766
9767typedef enum DSI_USE_CMDFIFO {
9768DSI_CMD_USE_DMAFIFO                      = 0x00000000,
9769DSI_CMD_USE_CMDFIFO                      = 0x00000001,
9770} DSI_USE_CMDFIFO;
9771
9772/*
9773 * DSI_CRTC_FREEZE_TRIG enum
9774 */
9775
9776typedef enum DSI_CRTC_FREEZE_TRIG {
9777DSI_CRTC_FREEZE_TRIG_DEASSERT            = 0x00000000,
9778DSI_CRTC_FREEZE_TRIG_ASSERT              = 0x00000001,
9779} DSI_CRTC_FREEZE_TRIG;
9780
9781/*
9782 * DSI_PERF_LATENCY_SEL enum
9783 */
9784
9785typedef enum DSI_PERF_LATENCY_SEL {
9786DSI_PERF_LATENCY_SEL_DATA_LANE0          = 0x00000000,
9787DSI_PERF_LATENCY_SEL_DATA_LANE1          = 0x00000001,
9788DSI_PERF_LATENCY_SEL_DATA_LANE2          = 0x00000002,
9789DSI_PERF_LATENCY_SEL_DATA_LANE3          = 0x00000003,
9790} DSI_PERF_LATENCY_SEL;
9791
9792/*
9793 * DSI_DEBUG_DSICLK_SEL enum
9794 */
9795
9796typedef enum DSI_DEBUG_DSICLK_SEL {
9797DSI_DEBUG_DSICLK_SEL_VIDEO_ENGINE        = 0x00000000,
9798DSI_DEBUG_DSICLK_SEL_CMD_ENGINE          = 0x00000001,
9799DSI_DEBUG_DSICLK_SEL_RESYNC_FIFO         = 0x00000002,
9800DSI_DEBUG_DSICLK_SEL_CMDFIFO             = 0x00000003,
9801DSI_DEBUG_DSICLK_SEL_CMDBUFFER           = 0x00000004,
9802DSI_DEBUG_DSICLK_SEL_AFIFO               = 0x00000005,
9803DSI_DEBUG_DSICLK_SEL_LANECTRL            = 0x00000006,
9804} DSI_DEBUG_DSICLK_SEL;
9805
9806/*
9807 * DSI_DEBUG_BYTECLK_SEL enum
9808 */
9809
9810typedef enum DSI_DEBUG_BYTECLK_SEL {
9811DSI_DEBUG_BYTECLK_SEL_AFIFO              = 0x00000000,
9812DSI_DEBUG_BYTECLK_SEL_LANEFIFO0          = 0x00000001,
9813DSI_DEBUG_BYTECLK_SEL_LANEFIFO1          = 0x00000002,
9814DSI_DEBUG_BYTECLK_SEL_LANEFIFO2          = 0x00000003,
9815DSI_DEBUG_BYTECLK_SEL_LANEFIFO3          = 0x00000004,
9816DSI_DEBUG_BYTECLK_SEL_LANEBUF0           = 0x00000005,
9817DSI_DEBUG_BYTECLK_SEL_LANEBUF1           = 0x00000006,
9818DSI_DEBUG_BYTECLK_SEL_LANEBUF2           = 0x00000007,
9819DSI_DEBUG_BYTECLK_SEL_LANEBUF3           = 0x00000008,
9820DSI_DEBUG_BYTECLK_SEL_PINGPONG0          = 0x00000009,
9821DSI_DEBUG_BYTECLK_SEL_PINGPONG1          = 0x0000000a,
9822DSI_DEBUG_BYTECLK_SEL_PINGPING2          = 0x0000000b,
9823DSI_DEBUG_BYTECLK_SEL_PINGPING3          = 0x0000000c,
9824DSI_DEBUG_BYTECLK_SEL_EOT                = 0x0000000d,
9825DSI_DEBUG_BYTECLK_SEL_LANECTRL           = 0x0000000e,
9826} DSI_DEBUG_BYTECLK_SEL;
9827
9828/*******************************************************
9829 * DCIO_CHIP Enums
9830 *******************************************************/
9831
9832/*
9833 * DCIOCHIP_HPD_SEL enum
9834 */
9835
9836typedef enum DCIOCHIP_HPD_SEL {
9837DCIOCHIP_HPD_SEL_ASYNC                   = 0x00000000,
9838DCIOCHIP_HPD_SEL_CLOCKED                 = 0x00000001,
9839} DCIOCHIP_HPD_SEL;
9840
9841/*
9842 * DCIOCHIP_PAD_MODE enum
9843 */
9844
9845typedef enum DCIOCHIP_PAD_MODE {
9846DCIOCHIP_PAD_MODE_DDC                    = 0x00000000,
9847DCIOCHIP_PAD_MODE_DP                     = 0x00000001,
9848} DCIOCHIP_PAD_MODE;
9849
9850/*
9851 * DCIOCHIP_AUXSLAVE_PAD_MODE enum
9852 */
9853
9854typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
9855DCIOCHIP_AUXSLAVE_PAD_MODE_I2C           = 0x00000000,
9856DCIOCHIP_AUXSLAVE_PAD_MODE_AUX           = 0x00000001,
9857} DCIOCHIP_AUXSLAVE_PAD_MODE;
9858
9859/*
9860 * DCIOCHIP_INVERT enum
9861 */
9862
9863typedef enum DCIOCHIP_INVERT {
9864DCIOCHIP_POL_NON_INVERT                  = 0x00000000,
9865DCIOCHIP_POL_INVERT                      = 0x00000001,
9866} DCIOCHIP_INVERT;
9867
9868/*
9869 * DCIOCHIP_PD_EN enum
9870 */
9871
9872typedef enum DCIOCHIP_PD_EN {
9873DCIOCHIP_PD_EN_NOTALLOW                  = 0x00000000,
9874DCIOCHIP_PD_EN_ALLOW                     = 0x00000001,
9875} DCIOCHIP_PD_EN;
9876
9877/*
9878 * DCIOCHIP_GPIO_MASK_EN enum
9879 */
9880
9881typedef enum DCIOCHIP_GPIO_MASK_EN {
9882DCIOCHIP_GPIO_MASK_EN_HARDWARE           = 0x00000000,
9883DCIOCHIP_GPIO_MASK_EN_SOFTWARE           = 0x00000001,
9884} DCIOCHIP_GPIO_MASK_EN;
9885
9886/*
9887 * DCIOCHIP_MASK enum
9888 */
9889
9890typedef enum DCIOCHIP_MASK {
9891DCIOCHIP_MASK_DISABLE                    = 0x00000000,
9892DCIOCHIP_MASK_ENABLE                     = 0x00000001,
9893} DCIOCHIP_MASK;
9894
9895/*
9896 * DCIOCHIP_GPIO_I2C_MASK enum
9897 */
9898
9899typedef enum DCIOCHIP_GPIO_I2C_MASK {
9900DCIOCHIP_GPIO_I2C_MASK_DISABLE           = 0x00000000,
9901DCIOCHIP_GPIO_I2C_MASK_ENABLE            = 0x00000001,
9902} DCIOCHIP_GPIO_I2C_MASK;
9903
9904/*
9905 * DCIOCHIP_GPIO_I2C_DRIVE enum
9906 */
9907
9908typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
9909DCIOCHIP_GPIO_I2C_DRIVE_LOW              = 0x00000000,
9910DCIOCHIP_GPIO_I2C_DRIVE_HIGH             = 0x00000001,
9911} DCIOCHIP_GPIO_I2C_DRIVE;
9912
9913/*
9914 * DCIOCHIP_GPIO_I2C_EN enum
9915 */
9916
9917typedef enum DCIOCHIP_GPIO_I2C_EN {
9918DCIOCHIP_GPIO_I2C_DISABLE                = 0x00000000,
9919DCIOCHIP_GPIO_I2C_ENABLE                 = 0x00000001,
9920} DCIOCHIP_GPIO_I2C_EN;
9921
9922/*
9923 * DCIOCHIP_MASK_4BIT enum
9924 */
9925
9926typedef enum DCIOCHIP_MASK_4BIT {
9927DCIOCHIP_MASK_4BIT_DISABLE               = 0x00000000,
9928DCIOCHIP_MASK_4BIT_ENABLE                = 0x0000000f,
9929} DCIOCHIP_MASK_4BIT;
9930
9931/*
9932 * DCIOCHIP_ENABLE_4BIT enum
9933 */
9934
9935typedef enum DCIOCHIP_ENABLE_4BIT {
9936DCIOCHIP_4BIT_DISABLE                    = 0x00000000,
9937DCIOCHIP_4BIT_ENABLE                     = 0x0000000f,
9938} DCIOCHIP_ENABLE_4BIT;
9939
9940/*
9941 * DCIOCHIP_MASK_5BIT enum
9942 */
9943
9944typedef enum DCIOCHIP_MASK_5BIT {
9945DCIOCHIP_MASIK_5BIT_DISABLE              = 0x00000000,
9946DCIOCHIP_MASIK_5BIT_ENABLE               = 0x0000001f,
9947} DCIOCHIP_MASK_5BIT;
9948
9949/*
9950 * DCIOCHIP_ENABLE_5BIT enum
9951 */
9952
9953typedef enum DCIOCHIP_ENABLE_5BIT {
9954DCIOCHIP_5BIT_DISABLE                    = 0x00000000,
9955DCIOCHIP_5BIT_ENABLE                     = 0x0000001f,
9956} DCIOCHIP_ENABLE_5BIT;
9957
9958/*
9959 * DCIOCHIP_MASK_2BIT enum
9960 */
9961
9962typedef enum DCIOCHIP_MASK_2BIT {
9963DCIOCHIP_MASK_2BIT_DISABLE               = 0x00000000,
9964DCIOCHIP_MASK_2BIT_ENABLE                = 0x00000003,
9965} DCIOCHIP_MASK_2BIT;
9966
9967/*
9968 * DCIOCHIP_ENABLE_2BIT enum
9969 */
9970
9971typedef enum DCIOCHIP_ENABLE_2BIT {
9972DCIOCHIP_2BIT_DISABLE                    = 0x00000000,
9973DCIOCHIP_2BIT_ENABLE                     = 0x00000003,
9974} DCIOCHIP_ENABLE_2BIT;
9975
9976/*
9977 * DCIOCHIP_REF_27_SRC_SEL enum
9978 */
9979
9980typedef enum DCIOCHIP_REF_27_SRC_SEL {
9981DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER     = 0x00000000,
9982DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER  = 0x00000001,
9983DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS      = 0x00000002,
9984DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS  = 0x00000003,
9985} DCIOCHIP_REF_27_SRC_SEL;
9986
9987/*
9988 * DCIOCHIP_DVO_VREFPON enum
9989 */
9990
9991typedef enum DCIOCHIP_DVO_VREFPON {
9992DCIOCHIP_DVO_VREFPON_DISABLE             = 0x00000000,
9993DCIOCHIP_DVO_VREFPON_ENABLE              = 0x00000001,
9994} DCIOCHIP_DVO_VREFPON;
9995
9996/*
9997 * DCIOCHIP_DVO_VREFSEL enum
9998 */
9999
10000typedef enum DCIOCHIP_DVO_VREFSEL {

10001DCIOCHIP_DVO_VREFSEL_ONCHIP              = 0x00000000,
10002DCIOCHIP_DVO_VREFSEL_EXTERNAL            = 0x00000001,
10003} DCIOCHIP_DVO_VREFSEL;
10004
10005/*
10006 * DCIOCHIP_SPDIF1_IMODE enum
10007 */
10008
10009typedef enum DCIOCHIP_SPDIF1_IMODE {
10010DCIOCHIP_SPDIF1_IMODE_OE_A               = 0x00000000,
10011DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO          = 0x00000001,
10012} DCIOCHIP_SPDIF1_IMODE;
10013
10014/*
10015 * DCIOCHIP_AUX_FALLSLEWSEL enum
10016 */
10017
10018typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10019DCIOCHIP_AUX_FALLSLEWSEL_LOW             = 0x00000000,
10020DCIOCHIP_AUX_FALLSLEWSEL_HIGH0           = 0x00000001,
10021DCIOCHIP_AUX_FALLSLEWSEL_HIGH1           = 0x00000002,
10022DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH       = 0x00000003,
10023} DCIOCHIP_AUX_FALLSLEWSEL;
10024
10025/*
10026 * DCIOCHIP_AUX_SPIKESEL enum
10027 */
10028
10029typedef enum DCIOCHIP_AUX_SPIKESEL {
10030DCIOCHIP_AUX_SPIKESEL_50NS               = 0x00000000,
10031DCIOCHIP_AUX_SPIKESEL_10NS               = 0x00000001,
10032} DCIOCHIP_AUX_SPIKESEL;
10033
10034/*
10035 * DCIOCHIP_AUX_CSEL0P9 enum
10036 */
10037
10038typedef enum DCIOCHIP_AUX_CSEL0P9 {
10039DCIOCHIP_AUX_CSEL_DEC1P0                 = 0x00000000,
10040DCIOCHIP_AUX_CSEL_DEC0P9                 = 0x00000001,
10041} DCIOCHIP_AUX_CSEL0P9;
10042
10043/*
10044 * DCIOCHIP_AUX_CSEL1P1 enum
10045 */
10046
10047typedef enum DCIOCHIP_AUX_CSEL1P1 {
10048DCIOCHIP_AUX_CSEL_INC1P0                 = 0x00000000,
10049DCIOCHIP_AUX_CSEL_INC1P1                 = 0x00000001,
10050} DCIOCHIP_AUX_CSEL1P1;
10051
10052/*
10053 * DCIOCHIP_AUX_RSEL0P9 enum
10054 */
10055
10056typedef enum DCIOCHIP_AUX_RSEL0P9 {
10057DCIOCHIP_AUX_RSEL_DEC1P0                 = 0x00000000,
10058DCIOCHIP_AUX_RSEL_DEC0P9                 = 0x00000001,
10059} DCIOCHIP_AUX_RSEL0P9;
10060
10061/*
10062 * DCIOCHIP_AUX_RSEL1P1 enum
10063 */
10064
10065typedef enum DCIOCHIP_AUX_RSEL1P1 {
10066DCIOCHIP_AUX_RSEL_INC1P0                 = 0x00000000,
10067DCIOCHIP_AUX_RSEL_INC1P1                 = 0x00000001,
10068} DCIOCHIP_AUX_RSEL1P1;
10069
10070/*******************************************************
10071 * AZCONTROLLER Enums
10072 *******************************************************/
10073
10074/*
10075 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
10076 */
10077
10078typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10079GENERIC_AZ_CONTROLLER_REGISTER_DISABLE   = 0x00000000,
10080GENERIC_AZ_CONTROLLER_REGISTER_ENABLE    = 0x00000001,
10081} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
10082
10083/*
10084 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
10085 */
10086
10087typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10088GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED  = 0x00000000,
10089GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED  = 0x00000001,
10090} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
10091
10092/*
10093 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
10094 */
10095
10096typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10097GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET  = 0x00000000,
10098GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET  = 0x00000001,
10099} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
10100
10101/*
10102 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
10103 */
10104
10105typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10106GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED  = 0x00000000,
10107GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED  = 0x00000001,
10108} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
10109
10110/*
10111 * AZ_GLOBAL_CAPABILITIES enum
10112 */
10113
10114typedef enum AZ_GLOBAL_CAPABILITIES {
10115AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED  = 0x00000000,
10116AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED  = 0x00000001,
10117} AZ_GLOBAL_CAPABILITIES;
10118
10119/*
10120 * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
10121 */
10122
10123typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10124ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE   = 0x00000000,
10125ACCEPT_UNSOLICITED_RESPONSE_ENABLE       = 0x00000001,
10126} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
10127
10128/*
10129 * GLOBAL_CONTROL_FLUSH_CONTROL enum
10130 */
10131
10132typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10133FLUSH_CONTROL_FLUSH_NOT_STARTED          = 0x00000000,
10134FLUSH_CONTROL_FLUSH_STARTED              = 0x00000001,
10135} GLOBAL_CONTROL_FLUSH_CONTROL;
10136
10137/*
10138 * GLOBAL_CONTROL_CONTROLLER_RESET enum
10139 */
10140
10141typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10142CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET  = 0x00000000,
10143CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET  = 0x00000001,
10144} GLOBAL_CONTROL_CONTROLLER_RESET;
10145
10146/*
10147 * AZ_STATE_CHANGE_STATUS enum
10148 */
10149
10150typedef enum AZ_STATE_CHANGE_STATUS {
10151AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT  = 0x00000000,
10152AZ_STATE_CHANGE_STATUS_CODEC_PRESENT     = 0x00000001,
10153} AZ_STATE_CHANGE_STATUS;
10154
10155/*
10156 * GLOBAL_STATUS_FLUSH_STATUS enum
10157 */
10158
10159typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10160GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED  = 0x00000000,
10161GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED   = 0x00000001,
10162} GLOBAL_STATUS_FLUSH_STATUS;
10163
10164/*
10165 * STREAM_0_SYNCHRONIZATION enum
10166 */
10167
10168typedef enum STREAM_0_SYNCHRONIZATION {
10169STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10170STREAM_0_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10171} STREAM_0_SYNCHRONIZATION;
10172
10173/*
10174 * STREAM_1_SYNCHRONIZATION enum
10175 */
10176
10177typedef enum STREAM_1_SYNCHRONIZATION {
10178STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10179STREAM_1_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10180} STREAM_1_SYNCHRONIZATION;
10181
10182/*
10183 * STREAM_2_SYNCHRONIZATION enum
10184 */
10185
10186typedef enum STREAM_2_SYNCHRONIZATION {
10187STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10188STREAM_2_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10189} STREAM_2_SYNCHRONIZATION;
10190
10191/*
10192 * STREAM_3_SYNCHRONIZATION enum
10193 */
10194
10195typedef enum STREAM_3_SYNCHRONIZATION {
10196STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10197STREAM_3_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10198} STREAM_3_SYNCHRONIZATION;
10199
10200/*
10201 * STREAM_4_SYNCHRONIZATION enum
10202 */
10203
10204typedef enum STREAM_4_SYNCHRONIZATION {
10205STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10206STREAM_4_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10207} STREAM_4_SYNCHRONIZATION;
10208
10209/*
10210 * STREAM_5_SYNCHRONIZATION enum
10211 */
10212
10213typedef enum STREAM_5_SYNCHRONIZATION {
10214STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED  = 0x00000000,
10215STREAM_5_SYNCHRONIZATION_STEAM_STOPPED   = 0x00000001,
10216} STREAM_5_SYNCHRONIZATION;
10217
10218/*
10219 * STREAM_6_SYNCHRONIZATION enum
10220 */
10221
10222typedef enum STREAM_6_SYNCHRONIZATION {
10223STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10224STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10225} STREAM_6_SYNCHRONIZATION;
10226
10227/*
10228 * STREAM_7_SYNCHRONIZATION enum
10229 */
10230
10231typedef enum STREAM_7_SYNCHRONIZATION {
10232STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10233STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10234} STREAM_7_SYNCHRONIZATION;
10235
10236/*
10237 * STREAM_8_SYNCHRONIZATION enum
10238 */
10239
10240typedef enum STREAM_8_SYNCHRONIZATION {
10241STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10242STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10243} STREAM_8_SYNCHRONIZATION;
10244
10245/*
10246 * STREAM_9_SYNCHRONIZATION enum
10247 */
10248
10249typedef enum STREAM_9_SYNCHRONIZATION {
10250STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10251STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10252} STREAM_9_SYNCHRONIZATION;
10253
10254/*
10255 * STREAM_10_SYNCHRONIZATION enum
10256 */
10257
10258typedef enum STREAM_10_SYNCHRONIZATION {
10259STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10260STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10261} STREAM_10_SYNCHRONIZATION;
10262
10263/*
10264 * STREAM_11_SYNCHRONIZATION enum
10265 */
10266
10267typedef enum STREAM_11_SYNCHRONIZATION {
10268STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10269STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10270} STREAM_11_SYNCHRONIZATION;
10271
10272/*
10273 * STREAM_12_SYNCHRONIZATION enum
10274 */
10275
10276typedef enum STREAM_12_SYNCHRONIZATION {
10277STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10278STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10279} STREAM_12_SYNCHRONIZATION;
10280
10281/*
10282 * STREAM_13_SYNCHRONIZATION enum
10283 */
10284
10285typedef enum STREAM_13_SYNCHRONIZATION {
10286STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10287STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10288} STREAM_13_SYNCHRONIZATION;
10289
10290/*
10291 * STREAM_14_SYNCHRONIZATION enum
10292 */
10293
10294typedef enum STREAM_14_SYNCHRONIZATION {
10295STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10296STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10297} STREAM_14_SYNCHRONIZATION;
10298
10299/*
10300 * STREAM_15_SYNCHRONIZATION enum
10301 */
10302
10303typedef enum STREAM_15_SYNCHRONIZATION {
10304STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED  = 0x00000000,
10305STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x00000001,
10306} STREAM_15_SYNCHRONIZATION;
10307
10308/*
10309 * CORB_READ_POINTER_RESET enum
10310 */
10311
10312typedef enum CORB_READ_POINTER_RESET {
10313CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET  = 0x00000000,
10314CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET  = 0x00000001,
10315} CORB_READ_POINTER_RESET;
10316
10317/*
10318 * AZ_CORB_SIZE enum
10319 */
10320
10321typedef enum AZ_CORB_SIZE {
10322AZ_CORB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
10323AZ_CORB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
10324AZ_CORB_SIZE_256ENTRIES                  = 0x00000002,
10325AZ_CORB_SIZE_RESERVED                    = 0x00000003,
10326} AZ_CORB_SIZE;
10327
10328/*
10329 * AZ_RIRB_WRITE_POINTER_RESET enum
10330 */
10331
10332typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10333AZ_RIRB_WRITE_POINTER_NOT_RESET          = 0x00000000,
10334AZ_RIRB_WRITE_POINTER_DO_RESET           = 0x00000001,
10335} AZ_RIRB_WRITE_POINTER_RESET;
10336
10337/*
10338 * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
10339 */
10340
10341typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10342RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
10343RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
10344} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
10345
10346/*
10347 * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
10348 */
10349
10350typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10351RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED  = 0x00000000,
10352RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED  = 0x00000001,
10353} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
10354
10355/*
10356 * AZ_RIRB_SIZE enum
10357 */
10358
10359typedef enum AZ_RIRB_SIZE {
10360AZ_RIRB_SIZE_2ENTRIES_RESERVED           = 0x00000000,
10361AZ_RIRB_SIZE_16ENTRIES_RESERVED          = 0x00000001,
10362AZ_RIRB_SIZE_256ENTRIES                  = 0x00000002,
10363AZ_RIRB_SIZE_UNDEFINED                   = 0x00000003,
10364} AZ_RIRB_SIZE;
10365
10366/*
10367 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
10368 */
10369
10370typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10371IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID  = 0x00000000,
10372IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID  = 0x00000001,
10373} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
10374
10375/*
10376 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
10377 */
10378
10379typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10380IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY  = 0x00000000,
10381IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY  = 0x00000001,
10382} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
10383
10384/*
10385 * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
10386 */
10387
10388typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10389DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE  = 0x00000000,
10390DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE  = 0x00000001,
10391} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
10392
10393/*******************************************************
10394 * AZENDPOINT Enums
10395 *******************************************************/
10396
10397/*
10398 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10399 */
10400
10401typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10402AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
10403AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
10404} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10405
10406/*
10407 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10408 */
10409
10410typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10411AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
10412AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
10413} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10414
10415/*
10416 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10417 */
10418
10419typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10420AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
10421AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
10422AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
10423AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
10424AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
10425} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10426
10427/*
10428 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10429 */
10430
10431typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10432AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
10433AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
10434AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
10435AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
10436AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
10437AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
10438AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
10439AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
10440} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10441
10442/*
10443 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10444 */
10445
10446typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10447AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
10448AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
10449AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
10450AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
10451AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
10452AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
10453} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10454
10455/*
10456 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10457 */
10458
10459typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10460AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
10461AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
10462AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
10463AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
10464AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
10465AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
10466AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
10467AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
10468AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
10469} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10470
10471/*
10472 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10473 */
10474
10475typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10476AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET  = 0x00000000,
10477AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET  = 0x00000001,
10478} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
10479
10480/*
10481 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10482 */
10483
10484typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10485AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET  = 0x00000000,
10486AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET  = 0x00000001,
10487} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
10488
10489/*
10490 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10491 */
10492
10493typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10494AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET  = 0x00000000,
10495AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET  = 0x00000001,
10496} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
10497
10498/*
10499 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10500 */
10501
10502typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10503AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET  = 0x00000000,
10504AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET  = 0x00000001,
10505} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
10506
10507/*
10508 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10509 */
10510
10511typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10512AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET  = 0x00000000,
10513AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET  = 0x00000001,
10514} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
10515
10516/*
10517 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10518 */
10519
10520typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10521AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON  = 0x00000000,
10522AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON  = 0x00000001,
10523} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
10524
10525/*
10526 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10527 */
10528
10529typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10530AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO  = 0x00000000,
10531AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE  = 0x00000001,
10532} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
10533
10534/*
10535 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10536 */
10537
10538typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10539AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
10540AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
10541} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10542
10543/*
10544 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10545 */
10546
10547typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10548AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE  = 0x00000000,
10549AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE  = 0x00000001,
10550} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
10551
10552/*
10553 * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10554 */
10555
10556typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10557AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF  = 0x00000000,
10558AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN  = 0x00000001,
10559} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
10560
10561/*
10562 * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10563 */
10564
10565typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10566AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
10567AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
10568} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10569
10570/*
10571 * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10572 */
10573
10574typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10575AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED  = 0x00000000,
10576AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN  = 0x00000001,
10577} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
10578
10579/*
10580 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10581 */
10582
10583typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10584AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED  = 0x00000000,
10585AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED  = 0x00000001,
10586} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
10587
10588/*
10589 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10590 */
10591
10592typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10593AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED  = 0x00000000,
10594AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED  = 0x00000001,
10595} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
10596
10597/*
10598 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10599 */
10600
10601typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10602AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED  = 0x00000000,
10603AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED  = 0x00000001,
10604} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
10605
10606/*
10607 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10608 */
10609
10610typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10611AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED  = 0x00000000,
10612AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED  = 0x00000001,
10613} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
10614
10615/*
10616 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10617 */
10618
10619typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10620AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
10621AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
10622} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10623
10624/*
10625 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10626 */
10627
10628typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10629AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
10630AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
10631} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10632
10633/*
10634 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10635 */
10636
10637typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10638AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
10639AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
10640} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10641
10642/*
10643 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10644 */
10645
10646typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10647AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
10648AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
10649} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10650
10651/*
10652 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10653 */
10654
10655typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10656AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE  = 0x00000000,
10657AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE  = 0x00000001,
10658} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10659
10660/*******************************************************
10661 * AZF0CONTROLLER Enums
10662 *******************************************************/
10663
10664/*
10665 * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10666 */
10667
10668typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10669AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET  = 0x00000000,
10670AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC  = 0x00000001,
10671} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
10672
10673/*******************************************************
10674 * AZF0ROOT Enums
10675 *******************************************************/
10676
10677/*
10678 * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
10679 */
10680
10681typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
10682CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL  = 0x00000000,
10683CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6  = 0x00000001,
10684CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5  = 0x00000002,
10685CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4  = 0x00000003,
10686CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3  = 0x00000004,
10687CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2  = 0x00000005,
10688CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1  = 0x00000006,
10689CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0  = 0x00000007,
10690} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
10691
10692/*
10693 * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
10694 */
10695
10696typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
10697CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL  = 0x00000000,
10698CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6  = 0x00000001,
10699CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5  = 0x00000002,
10700CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4  = 0x00000003,
10701CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3  = 0x00000004,
10702CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2  = 0x00000005,
10703CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1  = 0x00000006,
10704CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0  = 0x00000007,
10705} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
10706
10707/*******************************************************
10708 * AZINPUTENDPOINT Enums
10709 *******************************************************/
10710
10711/*
10712 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10713 */
10714
10715typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10716AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM  = 0x00000000,
10717AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM  = 0x00000001,
10718} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10719
10720/*
10721 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10722 */
10723
10724typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10725AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
10726AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
10727} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10728
10729/*
10730 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10731 */
10732
10733typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10734AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
10735AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
10736AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
10737AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
10738AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
10739} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10740
10741/*
10742 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10743 */
10744
10745typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10746AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
10747AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
10748AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
10749AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
10750AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
10751AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
10752AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
10753AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
10754} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10755
10756/*
10757 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10758 */
10759
10760typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10761AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
10762AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
10763AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
10764AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
10765AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
10766AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
10767} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10768
10769/*
10770 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10771 */
10772
10773typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10774AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
10775AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
10776AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
10777AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
10778AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
10779AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
10780AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
10781AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
10782AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED  = 0x00000008,
10783} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10784
10785/*
10786 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10787 */
10788
10789typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10790AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED  = 0x00000000,
10791AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED  = 0x00000001,
10792} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10793
10794/*
10795 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
10796 */
10797
10798typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
10799AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF  = 0x00000000,
10800AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN  = 0x00000001,
10801} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
10802
10803/*
10804 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10805 */
10806
10807typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10808AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED  = 0x00000000,
10809AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED  = 0x00000001,
10810} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10811
10812/*
10813 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
10814 */
10815
10816typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
10817AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED  = 0x00000000,
10818AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED  = 0x00000001,
10819} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
10820
10821/*
10822 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10823 */
10824
10825typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10826AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED  = 0x00000000,
10827AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED  = 0x00000001,
10828} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10829
10830/*
10831 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
10832 */
10833
10834typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
10835AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED  = 0x00000000,
10836AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED  = 0x00000001,
10837} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
10838
10839/*
10840 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10841 */
10842
10843typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10844AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED  = 0x00000000,
10845AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED  = 0x00000001,
10846} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10847
10848/*
10849 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
10850 */
10851
10852typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
10853AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED  = 0x00000000,
10854AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED  = 0x00000001,
10855} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
10856
10857/*
10858 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10859 */
10860
10861typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10862AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED  = 0x00000000,
10863AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED  = 0x00000001,
10864} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10865
10866/*
10867 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
10868 */
10869
10870typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
10871AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED  = 0x00000000,
10872AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED  = 0x00000001,
10873} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
10874
10875/*
10876 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10877 */
10878
10879typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10880AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED  = 0x00000000,
10881AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED  = 0x00000001,
10882} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10883
10884/*******************************************************
10885 * AZROOT Enums
10886 *******************************************************/
10887
10888/*
10889 * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
10890 */
10891
10892typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
10893AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET  = 0x00000000,
10894AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET  = 0x00000001,
10895} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
10896
10897/*******************************************************
10898 * DCCG Enums
10899 *******************************************************/
10900
10901/*
10902 * ENABLE enum
10903 */
10904
10905typedef enum ENABLE {
10906DISABLE_THE_FEATURE                      = 0x00000000,
10907ENABLE_THE_FEATURE                       = 0x00000001,
10908} ENABLE;
10909
10910/*
10911 * ENABLE_CLOCK enum
10912 */
10913
10914typedef enum ENABLE_CLOCK {
10915DISABLE_THE_CLOCK                        = 0x00000000,
10916ENABLE_THE_CLOCK                         = 0x00000001,
10917} ENABLE_CLOCK;
10918
10919/*
10920 * FORCE_VBI enum
10921 */
10922
10923typedef enum FORCE_VBI {
10924FORCE_VBI_LOW                            = 0x00000000,
10925FORCE_VBI_HIGH                           = 0x00000001,
10926} FORCE_VBI;
10927
10928/*
10929 * OVERRIDE_CGTT_SCLK enum
10930 */
10931
10932typedef enum OVERRIDE_CGTT_SCLK {
10933OVERRIDE_CGTT_SCLK_NOOP                  = 0x00000000,
10934SET_OVERRIDE_CGTT_SCLK                   = 0x00000001,
10935} OVERRIDE_CGTT_SCLK;
10936
10937/*
10938 * CLEAR_SMU_INTR enum
10939 */
10940
10941typedef enum CLEAR_SMU_INTR {
10942SMU_INTR_STATUS_NOOP                     = 0x00000000,
10943SMU_INTR_STATUS_CLEAR                    = 0x00000001,
10944} CLEAR_SMU_INTR;
10945
10946/*
10947 * STATIC_SCREEN_SMU_INTR enum
10948 */
10949
10950typedef enum STATIC_SCREEN_SMU_INTR {
10951STATIC_SCREEN_SMU_INTR_NOOP              = 0x00000000,
10952SET_STATIC_SCREEN_SMU_INTR               = 0x00000001,
10953} STATIC_SCREEN_SMU_INTR;
10954
10955/*
10956 * JITTER_REMOVE_DISABLE enum
10957 */
10958
10959typedef enum JITTER_REMOVE_DISABLE {
10960ENABLE_JITTER_REMOVAL                    = 0x00000000,
10961DISABLE_JITTER_REMOVAL                   = 0x00000001,
10962} JITTER_REMOVE_DISABLE;
10963
10964/*
10965 * DS_REF_SRC enum
10966 */
10967
10968typedef enum DS_REF_SRC {
10969DS_REF_IS_XTALIN                         = 0x00000000,
10970DS_REF_IS_EXT_GENLOCK                    = 0x00000001,
10971DS_REF_IS_PCIE                           = 0x00000002,
10972} DS_REF_SRC;
10973
10974/*
10975 * DISABLE_CLOCK_GATING enum
10976 */
10977
10978typedef enum DISABLE_CLOCK_GATING {
10979CLOCK_GATING_ENABLED                     = 0x00000000,
10980CLOCK_GATING_DISABLED                    = 0x00000001,
10981} DISABLE_CLOCK_GATING;
10982
10983/*
10984 * DISABLE_CLOCK_GATING_IN_DCO enum
10985 */
10986
10987typedef enum DISABLE_CLOCK_GATING_IN_DCO {
10988CLOCK_GATING_ENABLED_IN_DCO              = 0x00000000,
10989CLOCK_GATING_DISABLED_IN_DCO             = 0x00000001,
10990} DISABLE_CLOCK_GATING_IN_DCO;
10991
10992/*
10993 * DCCG_DEEP_COLOR_CNTL enum
10994 */
10995
10996typedef enum DCCG_DEEP_COLOR_CNTL {
10997DCCG_DEEP_COLOR_DTO_DISABLE              = 0x00000000,
10998DCCG_DEEP_COLOR_DTO_5_4_RATIO            = 0x00000001,
10999DCCG_DEEP_COLOR_DTO_3_2_RATIO            = 0x00000002,
11000DCCG_DEEP_COLOR_DTO_2_1_RATIO            = 0x00000003,

11001} DCCG_DEEP_COLOR_CNTL;
11002
11003/*
11004 * REFCLK_CLOCK_EN enum
11005 */
11006
11007typedef enum REFCLK_CLOCK_EN {
11008REFCLK_CLOCK_EN_XTALIN_CLK               = 0x00000000,
11009REFCLK_CLOCK_EN_ALLOW_SRC_SEL            = 0x00000001,
11010} REFCLK_CLOCK_EN;
11011
11012/*
11013 * REFCLK_SRC_SEL enum
11014 */
11015
11016typedef enum REFCLK_SRC_SEL {
11017REFCLK_SRC_SEL_PCIE_REFCLK               = 0x00000000,
11018REFCLK_SRC_SEL_CPL_REFCLK                = 0x00000001,
11019} REFCLK_SRC_SEL;
11020
11021/*
11022 * DPREFCLK_SRC_SEL enum
11023 */
11024
11025typedef enum DPREFCLK_SRC_SEL {
11026DPREFCLK_SRC_SEL_CK                      = 0x00000000,
11027DPREFCLK_SRC_SEL_P0PLL                   = 0x00000001,
11028DPREFCLK_SRC_SEL_P1PLL                   = 0x00000002,
11029DPREFCLK_SRC_SEL_P2PLL                   = 0x00000003,
11030DPREFCLK_SRC_SEL_P3PLL                   = 0x00000004,
11031} DPREFCLK_SRC_SEL;
11032
11033/*
11034 * XTAL_REF_SEL enum
11035 */
11036
11037typedef enum XTAL_REF_SEL {
11038XTAL_REF_SEL_1X                          = 0x00000000,
11039XTAL_REF_SEL_2X                          = 0x00000001,
11040} XTAL_REF_SEL;
11041
11042/*
11043 * XTAL_REF_CLOCK_SOURCE_SEL enum
11044 */
11045
11046typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
11047XTAL_REF_CLOCK_SOURCE_SEL_XTALIN         = 0x00000000,
11048XTAL_REF_CLOCK_SOURCE_SEL_PPLL           = 0x00000001,
11049} XTAL_REF_CLOCK_SOURCE_SEL;
11050
11051/*
11052 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11053 */
11054
11055typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11056MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
11057MICROSECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK  = 0x00000001,
11058} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11059
11060/*
11061 * ALLOW_SR_ON_TRANS_REQ enum
11062 */
11063
11064typedef enum ALLOW_SR_ON_TRANS_REQ {
11065ALLOW_SR_ON_TRANS_REQ_ENABLE             = 0x00000000,
11066ALLOW_SR_ON_TRANS_REQ_DISABLE            = 0x00000001,
11067} ALLOW_SR_ON_TRANS_REQ;
11068
11069/*
11070 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
11071 */
11072
11073typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
11074MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN    = 0x00000000,
11075MILLISECOND_TIME_BASE_CLOCK_IS_PPLL_REFCLK  = 0x00000001,
11076} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
11077
11078/*
11079 * PIPE_PIXEL_RATE_SOURCE enum
11080 */
11081
11082typedef enum PIPE_PIXEL_RATE_SOURCE {
11083PIPE_PIXEL_RATE_SOURCE_P0PLL             = 0x00000000,
11084PIPE_PIXEL_RATE_SOURCE_P1PLL             = 0x00000001,
11085PIPE_PIXEL_RATE_SOURCE_P2PLL             = 0x00000002,
11086} PIPE_PIXEL_RATE_SOURCE;
11087
11088/*
11089 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
11090 */
11091
11092typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
11093PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA    = 0x00000000,
11094PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB    = 0x00000001,
11095PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC    = 0x00000002,
11096PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD    = 0x00000003,
11097PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE    = 0x00000004,
11098PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF    = 0x00000005,
11099PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYG    = 0x00000006,
11100} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
11101
11102/*
11103 * PIPE_PIXEL_RATE_PLL_SOURCE enum
11104 */
11105
11106typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
11107PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL        = 0x00000000,
11108PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL       = 0x00000001,
11109} PIPE_PIXEL_RATE_PLL_SOURCE;
11110
11111/*
11112 * DP_DTO_DS_DISABLE enum
11113 */
11114
11115typedef enum DP_DTO_DS_DISABLE {
11116DP_DTO_DESPREAD_DISABLE                  = 0x00000000,
11117DP_DTO_DESPREAD_ENABLE                   = 0x00000001,
11118} DP_DTO_DS_DISABLE;
11119
11120/*
11121 * CRTC_ADD_PIXEL enum
11122 */
11123
11124typedef enum CRTC_ADD_PIXEL {
11125CRTC_ADD_PIXEL_NOOP                      = 0x00000000,
11126CRTC_ADD_PIXEL_FORCE                     = 0x00000001,
11127} CRTC_ADD_PIXEL;
11128
11129/*
11130 * CRTC_DROP_PIXEL enum
11131 */
11132
11133typedef enum CRTC_DROP_PIXEL {
11134CRTC_DROP_PIXEL_NOOP                     = 0x00000000,
11135CRTC_DROP_PIXEL_FORCE                    = 0x00000001,
11136} CRTC_DROP_PIXEL;
11137
11138/*
11139 * SYMCLK_FE_FORCE_EN enum
11140 */
11141
11142typedef enum SYMCLK_FE_FORCE_EN {
11143SYMCLK_FE_FORCE_EN_DISABLE               = 0x00000000,
11144SYMCLK_FE_FORCE_EN_ENABLE                = 0x00000001,
11145} SYMCLK_FE_FORCE_EN;
11146
11147/*
11148 * SYMCLK_FE_FORCE_SRC enum
11149 */
11150
11151typedef enum SYMCLK_FE_FORCE_SRC {
11152SYMCLK_FE_FORCE_SRC_UNIPHYA              = 0x00000000,
11153SYMCLK_FE_FORCE_SRC_UNIPHYB              = 0x00000001,
11154SYMCLK_FE_FORCE_SRC_UNIPHYC              = 0x00000002,
11155SYMCLK_FE_FORCE_SRC_UNIPHYD              = 0x00000003,
11156SYMCLK_FE_FORCE_SRC_UNIPHYE              = 0x00000004,
11157SYMCLK_FE_FORCE_SRC_UNIPHYF              = 0x00000005,
11158SYMCLK_FE_FORCE_SRC_UNIPHYG              = 0x00000006,
11159} SYMCLK_FE_FORCE_SRC;
11160
11161/*
11162 * DPDBG_CLK_FORCE_EN enum
11163 */
11164
11165typedef enum DPDBG_CLK_FORCE_EN {
11166DPDBG_CLK_FORCE_EN_DISABLE               = 0x00000000,
11167DPDBG_CLK_FORCE_EN_ENABLE                = 0x00000001,
11168} DPDBG_CLK_FORCE_EN;
11169
11170/*
11171 * DVOACLK_COARSE_SKEW_CNTL enum
11172 */
11173
11174typedef enum DVOACLK_COARSE_SKEW_CNTL {
11175DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT   = 0x00000000,
11176DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP    = 0x00000001,
11177DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS   = 0x00000002,
11178DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS   = 0x00000003,
11179DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS   = 0x00000004,
11180DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS   = 0x00000005,
11181DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS   = 0x00000006,
11182DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS   = 0x00000007,
11183DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS   = 0x00000008,
11184DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS   = 0x00000009,
11185DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS  = 0x0000000a,
11186DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS  = 0x0000000b,
11187DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS  = 0x0000000c,
11188DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS  = 0x0000000d,
11189DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS  = 0x0000000e,
11190DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS  = 0x0000000f,
11191DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP    = 0x00000010,
11192DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS   = 0x00000011,
11193DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS   = 0x00000012,
11194DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS   = 0x00000013,
11195DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS   = 0x00000014,
11196DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS   = 0x00000015,
11197DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS   = 0x00000016,
11198DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS   = 0x00000017,
11199DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS   = 0x00000018,
11200DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS  = 0x00000019,
11201DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS  = 0x0000001a,
11202DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS  = 0x0000001b,
11203DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS  = 0x0000001c,
11204DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS  = 0x0000001d,
11205DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS  = 0x0000001e,
11206} DVOACLK_COARSE_SKEW_CNTL;
11207
11208/*
11209 * DVOACLK_FINE_SKEW_CNTL enum
11210 */
11211
11212typedef enum DVOACLK_FINE_SKEW_CNTL {
11213DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT     = 0x00000000,
11214DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP      = 0x00000001,
11215DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS     = 0x00000002,
11216DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS     = 0x00000003,
11217DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP      = 0x00000004,
11218DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS     = 0x00000005,
11219DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS     = 0x00000006,
11220DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS     = 0x00000007,
11221} DVOACLK_FINE_SKEW_CNTL;
11222
11223/*
11224 * DVOACLKD_IN_PHASE enum
11225 */
11226
11227typedef enum DVOACLKD_IN_PHASE {
11228DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
11229DVOACLKD_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
11230} DVOACLKD_IN_PHASE;
11231
11232/*
11233 * DVOACLKC_IN_PHASE enum
11234 */
11235
11236typedef enum DVOACLKC_IN_PHASE {
11237DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
11238DVOACLKC_IN_PHASE_WITH_PCLK_DVO          = 0x00000001,
11239} DVOACLKC_IN_PHASE;
11240
11241/*
11242 * DVOACLKC_MVP_IN_PHASE enum
11243 */
11244
11245typedef enum DVOACLKC_MVP_IN_PHASE {
11246DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO  = 0x00000000,
11247DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO      = 0x00000001,
11248} DVOACLKC_MVP_IN_PHASE;
11249
11250/*
11251 * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
11252 */
11253
11254typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
11255DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE  = 0x00000000,
11256DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE  = 0x00000001,
11257} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
11258
11259/*
11260 * MVP_CLK_SRC_SEL enum
11261 */
11262
11263typedef enum MVP_CLK_SRC_SEL {
11264MVP_CLK_SRC_SEL_RSRV                     = 0x00000000,
11265MVP_CLK_SRC_SEL_IO_1                     = 0x00000001,
11266MVP_CLK_SRC_SEL_IO_2                     = 0x00000002,
11267MVP_CLK_SRC_SEL_REFCLK                   = 0x00000003,
11268} MVP_CLK_SRC_SEL;
11269
11270/*
11271 * DCCG_AUDIO_DTO0_SOURCE_SEL enum
11272 */
11273
11274typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
11275DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC0         = 0x00000000,
11276DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC1         = 0x00000001,
11277DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC2         = 0x00000002,
11278DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC3         = 0x00000003,
11279DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC4         = 0x00000004,
11280DCCG_AUDIO_DTO0_SOURCE_SEL_CRTC5         = 0x00000005,
11281DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED      = 0x00000006,
11282} DCCG_AUDIO_DTO0_SOURCE_SEL;
11283
11284/*
11285 * DCCG_AUDIO_DTO_SEL enum
11286 */
11287
11288typedef enum DCCG_AUDIO_DTO_SEL {
11289DCCG_AUDIO_DTO_SEL_AUDIO_DTO0            = 0x00000000,
11290DCCG_AUDIO_DTO_SEL_AUDIO_DTO1            = 0x00000001,
11291DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO          = 0x00000002,
11292} DCCG_AUDIO_DTO_SEL;
11293
11294/*
11295 * DCCG_AUDIO_DTO2_SOURCE_SEL enum
11296 */
11297
11298typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
11299DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0        = 0x00000000,
11300DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1        = 0x00000001,
11301} DCCG_AUDIO_DTO2_SOURCE_SEL;
11302
11303/*
11304 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
11305 */
11306
11307typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
11308DCCG_AUDIO_DTO_USE_128FBR_FOR_DP         = 0x00000000,
11309DCCG_AUDIO_DTO_USE_512FBR_FOR_DP         = 0x00000001,
11310} DCCG_AUDIO_DTO_USE_512FBR_DTO;
11311
11312/*
11313 * DCCG_DBG_EN enum
11314 */
11315
11316typedef enum DCCG_DBG_EN {
11317DCCG_DBG_EN_DISABLE                      = 0x00000000,
11318DCCG_DBG_EN_ENABLE                       = 0x00000001,
11319} DCCG_DBG_EN;
11320
11321/*
11322 * DCCG_DBG_BLOCK_SEL enum
11323 */
11324
11325typedef enum DCCG_DBG_BLOCK_SEL {
11326DCCG_DBG_BLOCK_SEL_DCCG                  = 0x00000000,
11327DCCG_DBG_BLOCK_SEL_PMON                  = 0x00000001,
11328DCCG_DBG_BLOCK_SEL_PMON2                 = 0x00000002,
11329} DCCG_DBG_BLOCK_SEL;
11330
11331/*
11332 * DISPCLK_FREQ_RAMP_DONE enum
11333 */
11334
11335typedef enum DISPCLK_FREQ_RAMP_DONE {
11336DISPCLK_FREQ_RAMP_IN_PROGRESS            = 0x00000000,
11337DISPCLK_FREQ_RAMP_COMPLETED              = 0x00000001,
11338} DISPCLK_FREQ_RAMP_DONE;
11339
11340/*
11341 * DCCG_FIFO_ERRDET_RESET enum
11342 */
11343
11344typedef enum DCCG_FIFO_ERRDET_RESET {
11345DCCG_FIFO_ERRDET_RESET_NOOP              = 0x00000000,
11346DCCG_FIFO_ERRDET_RESET_FORCE             = 0x00000001,
11347} DCCG_FIFO_ERRDET_RESET;
11348
11349/*
11350 * DCCG_FIFO_ERRDET_STATE enum
11351 */
11352
11353typedef enum DCCG_FIFO_ERRDET_STATE {
11354DCCG_FIFO_ERRDET_STATE_DETECTION         = 0x00000000,
11355DCCG_FIFO_ERRDET_STATE_CALIBRATION       = 0x00000001,
11356} DCCG_FIFO_ERRDET_STATE;
11357
11358/*
11359 * DCCG_FIFO_ERRDET_OVR_EN enum
11360 */
11361
11362typedef enum DCCG_FIFO_ERRDET_OVR_EN {
11363DCCG_FIFO_ERRDET_OVR_DISABLE             = 0x00000000,
11364DCCG_FIFO_ERRDET_OVR_ENABLE              = 0x00000001,
11365} DCCG_FIFO_ERRDET_OVR_EN;
11366
11367/*
11368 * DISPCLK_CHG_FWD_CORR_DISABLE enum
11369 */
11370
11371typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
11372DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING  = 0x00000000,
11373DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING  = 0x00000001,
11374} DISPCLK_CHG_FWD_CORR_DISABLE;
11375
11376/*
11377 * DC_MEM_GLOBAL_PWR_REQ_DIS enum
11378 */
11379
11380typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
11381DC_MEM_GLOBAL_PWR_REQ_ENABLE             = 0x00000000,
11382DC_MEM_GLOBAL_PWR_REQ_DISABLE            = 0x00000001,
11383} DC_MEM_GLOBAL_PWR_REQ_DIS;
11384
11385/*
11386 * DCCG_PERF_RUN enum
11387 */
11388
11389typedef enum DCCG_PERF_RUN {
11390DCCG_PERF_RUN_NOOP                       = 0x00000000,
11391DCCG_PERF_RUN_START                      = 0x00000001,
11392} DCCG_PERF_RUN;
11393
11394/*
11395 * DCCG_PERF_MODE_VSYNC enum
11396 */
11397
11398typedef enum DCCG_PERF_MODE_VSYNC {
11399DCCG_PERF_MODE_VSYNC_NOOP                = 0x00000000,
11400DCCG_PERF_MODE_VSYNC_START               = 0x00000001,
11401} DCCG_PERF_MODE_VSYNC;
11402
11403/*
11404 * DCCG_PERF_MODE_HSYNC enum
11405 */
11406
11407typedef enum DCCG_PERF_MODE_HSYNC {
11408DCCG_PERF_MODE_HSYNC_NOOP                = 0x00000000,
11409DCCG_PERF_MODE_HSYNC_START               = 0x00000001,
11410} DCCG_PERF_MODE_HSYNC;
11411
11412/*
11413 * DCCG_PERF_CRTC_SELECT enum
11414 */
11415
11416typedef enum DCCG_PERF_CRTC_SELECT {
11417DCCG_PERF_SEL_CRTC0                      = 0x00000000,
11418DCCG_PERF_SEL_CRTC1                      = 0x00000001,
11419DCCG_PERF_SEL_CRTC2                      = 0x00000002,
11420DCCG_PERF_SEL_CRTC3                      = 0x00000003,
11421DCCG_PERF_SEL_CRTC4                      = 0x00000004,
11422DCCG_PERF_SEL_CRTC5                      = 0x00000005,
11423} DCCG_PERF_CRTC_SELECT;
11424
11425/*
11426 * CLOCK_BRANCH_SOFT_RESET enum
11427 */
11428
11429typedef enum CLOCK_BRANCH_SOFT_RESET {
11430CLOCK_BRANCH_SOFT_RESET_NOOP             = 0x00000000,
11431CLOCK_BRANCH_SOFT_RESET_FORCE            = 0x00000001,
11432} CLOCK_BRANCH_SOFT_RESET;
11433
11434/*
11435 * PLL_CFG_IF_SOFT_RESET enum
11436 */
11437
11438typedef enum PLL_CFG_IF_SOFT_RESET {
11439PLL_CFG_IF_SOFT_RESET_NOOP               = 0x00000000,
11440PLL_CFG_IF_SOFT_RESET_FORCE              = 0x00000001,
11441} PLL_CFG_IF_SOFT_RESET;
11442
11443/*
11444 * DVO_ENABLE_RST enum
11445 */
11446
11447typedef enum DVO_ENABLE_RST {
11448DVO_ENABLE_RST_DISABLE                   = 0x00000000,
11449DVO_ENABLE_RST_ENABLE                    = 0x00000001,
11450} DVO_ENABLE_RST;
11451
11452/*******************************************************
11453 * DCI Enums
11454 *******************************************************/
11455
11456/*
11457 * LptNumPipes enum
11458 */
11459
11460typedef enum LptNumPipes {
11461LPT_NUM_PIPES_1CH                        = 0x00000000,
11462LPT_NUM_PIPES_2CH                        = 0x00000001,
11463LPT_NUM_PIPES_4CH                        = 0x00000002,
11464LPT_NUM_PIPES_8CH                        = 0x00000003,
11465} LptNumPipes;
11466
11467/*
11468 * LptNumBanks enum
11469 */
11470
11471typedef enum LptNumBanks {
11472LPT_NUM_BANKS_2BANK                      = 0x00000000,
11473LPT_NUM_BANKS_4BANK                      = 0x00000001,
11474LPT_NUM_BANKS_8BANK                      = 0x00000002,
11475LPT_NUM_BANKS_16BANK                     = 0x00000003,
11476LPT_NUM_BANKS_32BANK                     = 0x00000004,
11477} LptNumBanks;
11478
11479/*
11480 * OVERRIDE_CGTT_DCEFCLK enum
11481 */
11482
11483typedef enum OVERRIDE_CGTT_DCEFCLK {
11484OVERRIDE_CGTT_DCEFCLK_NOOP               = 0x00000000,
11485SET_OVERRIDE_CGTT_DCEFCLK                = 0x00000001,
11486} OVERRIDE_CGTT_DCEFCLK;
11487
11488/*******************************************************
11489 * DCIO Enums
11490 *******************************************************/
11491
11492/*
11493 * DCIO_DC_GENERICA_SEL enum
11494 */
11495
11496typedef enum DCIO_DC_GENERICA_SEL {
11497DCIO_GENERICA_SEL_DACA_STEREOSYNC        = 0x00000000,
11498DCIO_GENERICA_SEL_STEREOSYNC             = 0x00000001,
11499DCIO_GENERICA_SEL_DACA_PIXCLK            = 0x00000002,
11500DCIO_GENERICA_SEL_DACB_PIXCLK            = 0x00000003,
11501DCIO_GENERICA_SEL_DVOA_CTL3              = 0x00000004,
11502DCIO_GENERICA_SEL_P1_PLLCLK              = 0x00000005,
11503DCIO_GENERICA_SEL_P2_PLLCLK              = 0x00000006,
11504DCIO_GENERICA_SEL_DVOA_STEREOSYNC        = 0x00000007,
11505DCIO_GENERICA_SEL_DACA_FIELD_NUMBER      = 0x00000008,
11506DCIO_GENERICA_SEL_DACB_FIELD_NUMBER      = 0x00000009,
11507DCIO_GENERICA_SEL_GENERICA_DCCG          = 0x0000000a,
11508DCIO_GENERICA_SEL_SYNCEN                 = 0x0000000b,
11509DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
11510DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
11511DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
11512DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
11513DCIO_GENERICA_SEL_GENERICA_DPRX          = 0x00000010,
11514DCIO_GENERICA_SEL_GENERICB_DPRX          = 0x00000011,
11515} DCIO_DC_GENERICA_SEL;
11516
11517/*
11518 * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
11519 */
11520
11521typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
11522DCIO_UNIPHYA_TEST_REFDIV_CLK             = 0x00000000,
11523DCIO_UNIPHYB_TEST_REFDIV_CLK             = 0x00000001,
11524DCIO_UNIPHYC_TEST_REFDIV_CLK             = 0x00000002,
11525DCIO_UNIPHYD_TEST_REFDIV_CLK             = 0x00000003,
11526DCIO_UNIPHYE_TEST_REFDIV_CLK             = 0x00000004,
11527DCIO_UNIPHYF_TEST_REFDIV_CLK             = 0x00000005,
11528DCIO_UNIPHYG_TEST_REFDIV_CLK             = 0x00000006,
11529DCIO_UNIPHYLPA_TEST_REFDIV_CLK           = 0x00000007,
11530DCIO_UNIPHYLPB_TEST_REFDIV_CLK           = 0x00000008,
11531} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
11532
11533/*
11534 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
11535 */
11536
11537typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
11538DCIO_UNIPHYA_FBDIV_CLK                   = 0x00000000,
11539DCIO_UNIPHYB_FBDIV_CLK                   = 0x00000001,
11540DCIO_UNIPHYC_FBDIV_CLK                   = 0x00000002,
11541DCIO_UNIPHYD_FBDIV_CLK                   = 0x00000003,
11542DCIO_UNIPHYE_FBDIV_CLK                   = 0x00000004,
11543DCIO_UNIPHYF_FBDIV_CLK                   = 0x00000005,
11544DCIO_UNIPHYG_FBDIV_CLK                   = 0x00000006,
11545DCIO_UNIPHYLPA_FBDIV_CLK                 = 0x00000007,
11546DCIO_UNIPHYLPB_FBDIV_CLK                 = 0x00000008,
11547} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
11548
11549/*
11550 * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
11551 */
11552
11553typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
11554DCIO_UNIPHYA_FBDIV_SSC_CLK               = 0x00000000,
11555DCIO_UNIPHYB_FBDIV_SSC_CLK               = 0x00000001,
11556DCIO_UNIPHYC_FBDIV_SSC_CLK               = 0x00000002,
11557DCIO_UNIPHYD_FBDIV_SSC_CLK               = 0x00000003,
11558DCIO_UNIPHYE_FBDIV_SSC_CLK               = 0x00000004,
11559DCIO_UNIPHYF_FBDIV_SSC_CLK               = 0x00000005,
11560DCIO_UNIPHYG_FBDIV_SSC_CLK               = 0x00000006,
11561DCIO_UNIPHYLPA_FBDIV_SSC_CLK             = 0x00000007,
11562DCIO_UNIPHYLPB_FBDIV_SSC_CLK             = 0x00000008,
11563} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
11564
11565/*
11566 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
11567 */
11568
11569typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
11570DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2         = 0x00000000,
11571DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2         = 0x00000001,
11572DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2         = 0x00000002,
11573DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2         = 0x00000003,
11574DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2         = 0x00000004,
11575DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2         = 0x00000005,
11576DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2         = 0x00000006,
11577DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2       = 0x00000007,
11578DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2       = 0x00000008,
11579} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
11580
11581/*
11582 * DCIO_DC_GENERICB_SEL enum
11583 */
11584
11585typedef enum DCIO_DC_GENERICB_SEL {
11586DCIO_GENERICB_SEL_DACA_STEREOSYNC        = 0x00000000,
11587DCIO_GENERICB_SEL_STEREOSYNC             = 0x00000001,
11588DCIO_GENERICB_SEL_DACA_PIXCLK            = 0x00000002,
11589DCIO_GENERICB_SEL_DACB_PIXCLK            = 0x00000003,
11590DCIO_GENERICB_SEL_DVOA_CTL3              = 0x00000004,
11591DCIO_GENERICB_SEL_P1_PLLCLK              = 0x00000005,
11592DCIO_GENERICB_SEL_P2_PLLCLK              = 0x00000006,
11593DCIO_GENERICB_SEL_DVOA_STEREOSYNC        = 0x00000007,
11594DCIO_GENERICB_SEL_DACA_FIELD_NUMBER      = 0x00000008,
11595DCIO_GENERICB_SEL_DACB_FIELD_NUMBER      = 0x00000009,
11596DCIO_GENERICB_SEL_GENERICB_DCCG          = 0x0000000a,
11597DCIO_GENERICB_SEL_SYNCEN                 = 0x0000000b,
11598DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK      = 0x0000000c,
11599DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK       = 0x0000000d,
11600DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK   = 0x0000000e,
11601DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2  = 0x0000000f,
11602} DCIO_DC_GENERICB_SEL;
11603
11604/*
11605 * DCIO_DC_PAD_EXTERN_SIG_SEL enum
11606 */
11607
11608typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
11609DCIO_DC_PAD_EXTERN_SIG_SEL_MVP           = 0x00000000,
11610DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA        = 0x00000001,
11611DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK     = 0x00000002,
11612DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC   = 0x00000003,
11613DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA      = 0x00000004,
11614DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB      = 0x00000005,
11615DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC      = 0x00000006,
11616DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1          = 0x00000007,
11617DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2          = 0x00000008,
11618DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK       = 0x00000009,
11619DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA      = 0x0000000a,
11620DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK       = 0x0000000b,
11621DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA      = 0x0000000c,
11622DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1         = 0x0000000d,
11623DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0         = 0x0000000e,
11624DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL        = 0x0000000f,
11625} DCIO_DC_PAD_EXTERN_SIG_SEL;
11626
11627/*
11628 * DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS enum
11629 */
11630
11631typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
11632DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA         = 0x00000000,
11633DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE  = 0x00000001,
11634DCIO_MVP_PIXEL_SRC_STATUS_CRTC           = 0x00000002,
11635DCIO_MVP_PIXEL_SRC_STATUS_LB             = 0x00000003,
11636} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
11637
11638/*
11639 * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
11640 */
11641
11642typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
11643DCIO_HSYNCA_OUTPUT_SEL_DISABLE           = 0x00000000,
11644DCIO_HSYNCA_OUTPUT_SEL_PPLL1             = 0x00000001,
11645DCIO_HSYNCA_OUTPUT_SEL_PPLL2             = 0x00000002,
11646DCIO_HSYNCA_OUTPUT_SEL_RESERVED          = 0x00000003,
11647} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
11648
11649/*
11650 * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
11651 */
11652
11653typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
11654DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE        = 0x00000000,
11655DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1          = 0x00000001,
11656DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2          = 0x00000002,
11657DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3  = 0x00000003,
11658} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
11659
11660/*
11661 * DCIO_DC_GPIO_VIP_DEBUG enum
11662 */
11663
11664typedef enum DCIO_DC_GPIO_VIP_DEBUG {
11665DCIO_DC_GPIO_VIP_DEBUG_NORMAL            = 0x00000000,
11666DCIO_DC_GPIO_VIP_DEBUG_CG_BIG            = 0x00000001,
11667} DCIO_DC_GPIO_VIP_DEBUG;
11668
11669/*
11670 * DCIO_DC_GPIO_MACRO_DEBUG enum
11671 */
11672
11673typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
11674DCIO_DC_GPIO_MACRO_DEBUG_NORMAL          = 0x00000000,
11675DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF        = 0x00000001,
11676DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2  = 0x00000002,
11677DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3  = 0x00000003,
11678} DCIO_DC_GPIO_MACRO_DEBUG;
11679
11680/*
11681 * DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL enum
11682 */
11683
11684typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
11685DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL  = 0x00000000,
11686DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP  = 0x00000001,
11687} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
11688
11689/*
11690 * DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN enum
11691 */
11692
11693typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
11694DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS    = 0x00000000,
11695DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE    = 0x00000001,
11696} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
11697
11698/*
11699 * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
11700 */
11701
11702typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
11703DCIO_DPRX_LOOPBACK_ENABLE_NORMAL         = 0x00000000,
11704DCIO_DPRX_LOOPBACK_ENABLE_LOOP           = 0x00000001,
11705} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
11706
11707/*
11708 * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
11709 */
11710
11711typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
11712DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
11713DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
11714DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002,
11715DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003,
11716DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004,
11717DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005,
11718DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006,
11719DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007,
11720} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
11721
11722/*
11723 * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
11724 */
11725
11726typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
11727DCIO_UNIPHY_CHANNEL_NO_INVERSION         = 0x00000000,
11728DCIO_UNIPHY_CHANNEL_INVERTED             = 0x00000001,
11729} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
11730
11731/*
11732 * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
11733 */
11734
11735typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
11736DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW  = 0x00000000,
11737DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW   = 0x00000001,
11738DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED  = 0x00000002,
11739DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED  = 0x00000003,
11740} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
11741
11742/*
11743 * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
11744 */
11745
11746typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
11747DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0      = 0x00000000,
11748DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1      = 0x00000001,
11749DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2      = 0x00000002,
11750DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3      = 0x00000003,
11751} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
11752
11753/*
11754 * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
11755 */
11756
11757typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
11758DCIO_VIP_MUX_EN_DVO                      = 0x00000000,
11759DCIO_VIP_MUX_EN_VIP                      = 0x00000001,
11760} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
11761
11762/*
11763 * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
11764 */
11765
11766typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
11767DCIO_VIP_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
11768DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
11769} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
11770
11771/*
11772 * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
11773 */
11774
11775typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
11776DCIO_DVO_ALTER_MAPPING_EN_DEFAULT        = 0x00000000,
11777DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE    = 0x00000001,
11778} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
11779
11780/*
11781 * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
11782 */
11783
11784typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
11785DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE  = 0x00000000,
11786DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE  = 0x00000001,
11787} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
11788
11789/*
11790 * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
11791 */
11792
11793typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
11794DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF   = 0x00000000,
11795DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON    = 0x00000001,
11796} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
11797
11798/*
11799 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
11800 */
11801
11802typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
11803DCIO_LVTMA_SYNCEN_POL_NON_INVERT         = 0x00000000,
11804DCIO_LVTMA_SYNCEN_POL_INVERT             = 0x00000001,
11805} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
11806
11807/*
11808 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
11809 */
11810
11811typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
11812DCIO_LVTMA_DIGON_OFF                     = 0x00000000,
11813DCIO_LVTMA_DIGON_ON                      = 0x00000001,
11814} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
11815
11816/*
11817 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
11818 */
11819
11820typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
11821DCIO_LVTMA_DIGON_POL_NON_INVERT          = 0x00000000,
11822DCIO_LVTMA_DIGON_POL_INVERT              = 0x00000001,
11823} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
11824
11825/*
11826 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
11827 */
11828
11829typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
11830DCIO_LVTMA_BLON_OFF                      = 0x00000000,
11831DCIO_LVTMA_BLON_ON                       = 0x00000001,
11832} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
11833
11834/*
11835 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
11836 */
11837
11838typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
11839DCIO_LVTMA_BLON_POL_NON_INVERT           = 0x00000000,
11840DCIO_LVTMA_BLON_POL_INVERT               = 0x00000001,
11841} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
11842
11843/*
11844 * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
11845 */
11846
11847typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
11848DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON      = 0x00000000,
11849DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE  = 0x00000001,
11850} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
11851
11852/*
11853 * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
11854 */
11855
11856typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
11857DCIO_BL_PWM_FRACTIONAL_DISABLE           = 0x00000000,
11858DCIO_BL_PWM_FRACTIONAL_ENABLE            = 0x00000001,
11859} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
11860
11861/*
11862 * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
11863 */
11864
11865typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
11866DCIO_BL_PWM_DISABLE                      = 0x00000000,
11867DCIO_BL_PWM_ENABLE                       = 0x00000001,
11868} DCIO_BL_PWM_CNTL_BL_PWM_EN;
11869
11870/*
11871 * DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
11872 */
11873
11874typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
11875DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL  = 0x00000000,
11876DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1  = 0x00000001,
11877DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2  = 0x00000002,
11878DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3  = 0x00000003,
11879} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
11880
11881/*
11882 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
11883 */
11884
11885typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
11886DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE      = 0x00000000,
11887DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE       = 0x00000001,
11888} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
11889
11890/*
11891 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
11892 */
11893
11894typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
11895DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL  = 0x00000000,
11896DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM  = 0x00000001,
11897} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
11898
11899/*
11900 * DCIO_BL_PWM_GRP1_REG_LOCK enum
11901 */
11902
11903typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
11904DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE        = 0x00000000,
11905DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE         = 0x00000001,
11906} DCIO_BL_PWM_GRP1_REG_LOCK;
11907
11908/*
11909 * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
11910 */
11911
11912typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
11913DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE  = 0x00000000,
11914DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE  = 0x00000001,
11915} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
11916
11917/*
11918 * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
11919 */
11920
11921typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
11922DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1  = 0x00000000,
11923DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2  = 0x00000001,
11924DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3  = 0x00000002,
11925DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4  = 0x00000003,
11926DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5  = 0x00000004,
11927DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6  = 0x00000005,
11928} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
11929
11930/*
11931 * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
11932 */
11933
11934typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
11935DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM  = 0x00000000,
11936DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM  = 0x00000001,
11937} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
11938
11939/*
11940 * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
11941 */
11942
11943typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
11944DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE  = 0x00000000,
11945DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE  = 0x00000001,
11946} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
11947
11948/*
11949 * DCIO_GSL_SEL enum
11950 */
11951
11952typedef enum DCIO_GSL_SEL {
11953DCIO_GSL_SEL_GROUP_0                     = 0x00000000,
11954DCIO_GSL_SEL_GROUP_1                     = 0x00000001,
11955DCIO_GSL_SEL_GROUP_2                     = 0x00000002,
11956} DCIO_GSL_SEL;
11957
11958/*
11959 * DCIO_GENLK_CLK_GSL_MASK enum
11960 */
11961
11962typedef enum DCIO_GENLK_CLK_GSL_MASK {
11963DCIO_GENLK_CLK_GSL_MASK_NO               = 0x00000000,
11964DCIO_GENLK_CLK_GSL_MASK_TIMING           = 0x00000001,
11965DCIO_GENLK_CLK_GSL_MASK_STEREO           = 0x00000002,
11966} DCIO_GENLK_CLK_GSL_MASK;
11967
11968/*
11969 * DCIO_GENLK_VSYNC_GSL_MASK enum
11970 */
11971
11972typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
11973DCIO_GENLK_VSYNC_GSL_MASK_NO             = 0x00000000,
11974DCIO_GENLK_VSYNC_GSL_MASK_TIMING         = 0x00000001,
11975DCIO_GENLK_VSYNC_GSL_MASK_STEREO         = 0x00000002,
11976} DCIO_GENLK_VSYNC_GSL_MASK;
11977
11978/*
11979 * DCIO_SWAPLOCK_A_GSL_MASK enum
11980 */
11981
11982typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
11983DCIO_SWAPLOCK_A_GSL_MASK_NO              = 0x00000000,
11984DCIO_SWAPLOCK_A_GSL_MASK_TIMING          = 0x00000001,
11985DCIO_SWAPLOCK_A_GSL_MASK_STEREO          = 0x00000002,
11986} DCIO_SWAPLOCK_A_GSL_MASK;
11987
11988/*
11989 * DCIO_SWAPLOCK_B_GSL_MASK enum
11990 */
11991
11992typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
11993DCIO_SWAPLOCK_B_GSL_MASK_NO              = 0x00000000,
11994DCIO_SWAPLOCK_B_GSL_MASK_TIMING          = 0x00000001,
11995DCIO_SWAPLOCK_B_GSL_MASK_STEREO          = 0x00000002,
11996} DCIO_SWAPLOCK_B_GSL_MASK;
11997
11998/*
11999 * DCIO_GSL_VSYNC_SEL enum
12000 */

12001
12002typedef enum DCIO_GSL_VSYNC_SEL {
12003DCIO_GSL_VSYNC_SEL_PIPE0                 = 0x00000000,
12004DCIO_GSL_VSYNC_SEL_PIPE1                 = 0x00000001,
12005DCIO_GSL_VSYNC_SEL_PIPE2                 = 0x00000002,
12006DCIO_GSL_VSYNC_SEL_PIPE3                 = 0x00000003,
12007DCIO_GSL_VSYNC_SEL_PIPE4                 = 0x00000004,
12008DCIO_GSL_VSYNC_SEL_PIPE5                 = 0x00000005,
12009} DCIO_GSL_VSYNC_SEL;
12010
12011/*
12012 * DCIO_GSL0_TIMING_SYNC_SEL enum
12013 */
12014
12015typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
12016DCIO_GSL0_TIMING_SYNC_SEL_PIPE           = 0x00000000,
12017DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
12018DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
12019DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
12020DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
12021} DCIO_GSL0_TIMING_SYNC_SEL;
12022
12023/*
12024 * DCIO_GSL0_GLOBAL_UNLOCK_SEL enum
12025 */
12026
12027typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
12028DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
12029DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC  = 0x00000001,
12030DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
12031DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
12032DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
12033} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
12034
12035/*
12036 * DCIO_GSL1_TIMING_SYNC_SEL enum
12037 */
12038
12039typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
12040DCIO_GSL1_TIMING_SYNC_SEL_PIPE           = 0x00000000,
12041DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
12042DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
12043DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
12044DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
12045} DCIO_GSL1_TIMING_SYNC_SEL;
12046
12047/*
12048 * DCIO_GSL1_GLOBAL_UNLOCK_SEL enum
12049 */
12050
12051typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
12052DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
12053DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC  = 0x00000001,
12054DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
12055DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
12056DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
12057} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
12058
12059/*
12060 * DCIO_GSL2_TIMING_SYNC_SEL enum
12061 */
12062
12063typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
12064DCIO_GSL2_TIMING_SYNC_SEL_PIPE           = 0x00000000,
12065DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC   = 0x00000001,
12066DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK     = 0x00000002,
12067DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A     = 0x00000003,
12068DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B     = 0x00000004,
12069} DCIO_GSL2_TIMING_SYNC_SEL;
12070
12071/*
12072 * DCIO_GSL2_GLOBAL_UNLOCK_SEL enum
12073 */
12074
12075typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
12076DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION    = 0x00000000,
12077DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC  = 0x00000001,
12078DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK    = 0x00000002,
12079DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A   = 0x00000003,
12080DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B   = 0x00000004,
12081} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
12082
12083/*
12084 * DCIO_DC_GPU_TIMER_START_POSITION enum
12085 */
12086
12087typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
12088DCIO_GPU_TIMER_START_0_END_27            = 0x00000000,
12089DCIO_GPU_TIMER_START_1_END_28            = 0x00000001,
12090DCIO_GPU_TIMER_START_2_END_29            = 0x00000002,
12091DCIO_GPU_TIMER_START_3_END_30            = 0x00000003,
12092DCIO_GPU_TIMER_START_4_END_31            = 0x00000004,
12093DCIO_GPU_TIMER_START_6_END_33            = 0x00000005,
12094DCIO_GPU_TIMER_START_8_END_35            = 0x00000006,
12095DCIO_GPU_TIMER_START_10_END_37           = 0x00000007,
12096} DCIO_DC_GPU_TIMER_START_POSITION;
12097
12098/*
12099 * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
12100 */
12101
12102typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
12103DCIO_TEST_CLK_SEL_DISPCLK                = 0x00000000,
12104DCIO_TEST_CLK_SEL_GATED_DISPCLK          = 0x00000001,
12105DCIO_TEST_CLK_SEL_SCLK                   = 0x00000002,
12106} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
12107
12108/*
12109 * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
12110 */
12111
12112typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
12113DCIO_DISPCLK_R_DCIO_GATE_DISABLE         = 0x00000000,
12114DCIO_DISPCLK_R_DCIO_GATE_ENABLE          = 0x00000001,
12115} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
12116
12117/*
12118 * DCIO_DCO_DCFE_EXT_VSYNC_MUX enum
12119 */
12120
12121typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
12122DCIO_EXT_VSYNC_MUX_SWAPLOCKB             = 0x00000000,
12123DCIO_EXT_VSYNC_MUX_CRTC0                 = 0x00000001,
12124DCIO_EXT_VSYNC_MUX_CRTC1                 = 0x00000002,
12125DCIO_EXT_VSYNC_MUX_CRTC2                 = 0x00000003,
12126DCIO_EXT_VSYNC_MUX_CRTC3                 = 0x00000004,
12127DCIO_EXT_VSYNC_MUX_CRTC4                 = 0x00000005,
12128DCIO_EXT_VSYNC_MUX_CRTC5                 = 0x00000006,
12129DCIO_EXT_VSYNC_MUX_GENERICB              = 0x00000007,
12130} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
12131
12132/*
12133 * DCIO_DCO_EXT_VSYNC_MASK enum
12134 */
12135
12136typedef enum DCIO_DCO_EXT_VSYNC_MASK {
12137DCIO_EXT_VSYNC_MASK_NONE                 = 0x00000000,
12138DCIO_EXT_VSYNC_MASK_PIPE0                = 0x00000001,
12139DCIO_EXT_VSYNC_MASK_PIPE1                = 0x00000002,
12140DCIO_EXT_VSYNC_MASK_PIPE2                = 0x00000003,
12141DCIO_EXT_VSYNC_MASK_PIPE3                = 0x00000004,
12142DCIO_EXT_VSYNC_MASK_PIPE4                = 0x00000005,
12143DCIO_EXT_VSYNC_MASK_PIPE5                = 0x00000006,
12144DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE       = 0x00000007,
12145} DCIO_DCO_EXT_VSYNC_MASK;
12146
12147/*
12148 * DCIO_DSYNC_SOFT_RESET enum
12149 */
12150
12151typedef enum DCIO_DSYNC_SOFT_RESET {
12152DCIO_DSYNC_SOFT_RESET_DEASSERT           = 0x00000000,
12153DCIO_DSYNC_SOFT_RESET_ASSERT             = 0x00000001,
12154} DCIO_DSYNC_SOFT_RESET;
12155
12156/*
12157 * DCIO_DACA_SOFT_RESET enum
12158 */
12159
12160typedef enum DCIO_DACA_SOFT_RESET {
12161DCIO_DACA_SOFT_RESET_DEASSERT            = 0x00000000,
12162DCIO_DACA_SOFT_RESET_ASSERT              = 0x00000001,
12163} DCIO_DACA_SOFT_RESET;
12164
12165/*
12166 * DCIO_DCRXPHY_SOFT_RESET enum
12167 */
12168
12169typedef enum DCIO_DCRXPHY_SOFT_RESET {
12170DCIO_DCRXPHY_SOFT_RESET_DEASSERT         = 0x00000000,
12171DCIO_DCRXPHY_SOFT_RESET_ASSERT           = 0x00000001,
12172} DCIO_DCRXPHY_SOFT_RESET;
12173
12174/*
12175 * DCIO_DPHY_LANE_SEL enum
12176 */
12177
12178typedef enum DCIO_DPHY_LANE_SEL {
12179DCIO_DPHY_LANE_SEL_LANE0                 = 0x00000000,
12180DCIO_DPHY_LANE_SEL_LANE1                 = 0x00000001,
12181DCIO_DPHY_LANE_SEL_LANE2                 = 0x00000002,
12182DCIO_DPHY_LANE_SEL_LANE3                 = 0x00000003,
12183} DCIO_DPHY_LANE_SEL;
12184
12185/*
12186 * DCIO_DPCS_INTERRUPT_TYPE enum
12187 */
12188
12189typedef enum DCIO_DPCS_INTERRUPT_TYPE {
12190DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED     = 0x00000000,
12191DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED     = 0x00000001,
12192} DCIO_DPCS_INTERRUPT_TYPE;
12193
12194/*
12195 * DCIO_DPCS_INTERRUPT_MASK enum
12196 */
12197
12198typedef enum DCIO_DPCS_INTERRUPT_MASK {
12199DCIO_DPCS_INTERRUPT_DISABLE              = 0x00000000,
12200DCIO_DPCS_INTERRUPT_ENABLE               = 0x00000001,
12201} DCIO_DPCS_INTERRUPT_MASK;
12202
12203/*
12204 * DCIO_DC_GPU_TIMER_READ_SELECT enum
12205 */
12206
12207typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
12208DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE  = 0x00000000,
12209DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE  = 0x00000001,
12210DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE  = 0x00000002,
12211DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE  = 0x00000003,
12212DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE  = 0x00000004,
12213DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE  = 0x00000005,
12214DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE  = 0x00000006,
12215DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE  = 0x00000007,
12216DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE  = 0x00000008,
12217DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE  = 0x00000009,
12218DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE  = 0x0000000a,
12219DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE  = 0x0000000b,
12220DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP  = 0x0000000c,
12221DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP  = 0x0000000d,
12222DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP  = 0x0000000e,
12223DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP  = 0x0000000f,
12224DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP  = 0x00000010,
12225DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP  = 0x00000011,
12226DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP  = 0x00000012,
12227DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP  = 0x00000013,
12228DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP  = 0x00000014,
12229DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP  = 0x00000015,
12230DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP  = 0x00000016,
12231DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP  = 0x00000017,
12232DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM  = 0x00000018,
12233DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM  = 0x00000019,
12234DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM  = 0x0000001a,
12235DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM  = 0x0000001b,
12236DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM  = 0x0000001c,
12237DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM  = 0x0000001d,
12238DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM  = 0x0000001e,
12239DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM  = 0x0000001f,
12240DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM  = 0x00000020,
12241DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM  = 0x00000021,
12242DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM  = 0x00000022,
12243DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM  = 0x00000023,
12244} DCIO_DC_GPU_TIMER_READ_SELECT;
12245
12246/*
12247 * DCIO_IMPCAL_STEP_DELAY enum
12248 */
12249
12250typedef enum DCIO_IMPCAL_STEP_DELAY {
12251DCIO_IMPCAL_STEP_DELAY_1us               = 0x00000000,
12252DCIO_IMPCAL_STEP_DELAY_2us               = 0x00000001,
12253DCIO_IMPCAL_STEP_DELAY_3us               = 0x00000002,
12254DCIO_IMPCAL_STEP_DELAY_4us               = 0x00000003,
12255DCIO_IMPCAL_STEP_DELAY_5us               = 0x00000004,
12256DCIO_IMPCAL_STEP_DELAY_6us               = 0x00000005,
12257DCIO_IMPCAL_STEP_DELAY_7us               = 0x00000006,
12258DCIO_IMPCAL_STEP_DELAY_8us               = 0x00000007,
12259DCIO_IMPCAL_STEP_DELAY_9us               = 0x00000008,
12260DCIO_IMPCAL_STEP_DELAY_10us              = 0x00000009,
12261DCIO_IMPCAL_STEP_DELAY_11us              = 0x0000000a,
12262DCIO_IMPCAL_STEP_DELAY_12us              = 0x0000000b,
12263DCIO_IMPCAL_STEP_DELAY_13us              = 0x0000000c,
12264DCIO_IMPCAL_STEP_DELAY_14us              = 0x0000000d,
12265DCIO_IMPCAL_STEP_DELAY_15us              = 0x0000000e,
12266DCIO_IMPCAL_STEP_DELAY_16us              = 0x0000000f,
12267} DCIO_IMPCAL_STEP_DELAY;
12268
12269/*
12270 * DCIO_UNIPHY_IMPCAL_SEL enum
12271 */
12272
12273typedef enum DCIO_UNIPHY_IMPCAL_SEL {
12274DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE       = 0x00000000,
12275DCIO_UNIPHY_IMPCAL_SEL_BINARY            = 0x00000001,
12276} DCIO_UNIPHY_IMPCAL_SEL;
12277
12278/*
12279 * DCIO_DBG_ASYNC_BLOCK_SEL enum
12280 */
12281
12282typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
12283DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE        = 0x00000000,
12284DCIO_DBG_ASYNC_BLOCK_SEL_DCCG            = 0x00000001,
12285DCIO_DBG_ASYNC_BLOCK_SEL_DCIO            = 0x00000002,
12286DCIO_DBG_ASYNC_BLOCK_SEL_DCO             = 0x00000003,
12287} DCIO_DBG_ASYNC_BLOCK_SEL;
12288
12289/*
12290 * DCIO_DBG_ASYNC_4BIT_SEL enum
12291 */
12292
12293typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
12294DCIO_DBG_ASYNC_4BIT_SEL_3TO0             = 0x00000000,
12295DCIO_DBG_ASYNC_4BIT_SEL_7TO4             = 0x00000001,
12296DCIO_DBG_ASYNC_4BIT_SEL_11TO8            = 0x00000002,
12297DCIO_DBG_ASYNC_4BIT_SEL_15TO12           = 0x00000003,
12298DCIO_DBG_ASYNC_4BIT_SEL_19TO16           = 0x00000004,
12299DCIO_DBG_ASYNC_4BIT_SEL_23TO20           = 0x00000005,
12300DCIO_DBG_ASYNC_4BIT_SEL_27TO24           = 0x00000006,
12301DCIO_DBG_ASYNC_4BIT_SEL_31TO28           = 0x00000007,
12302} DCIO_DBG_ASYNC_4BIT_SEL;
12303
12304/*******************************************************
12305 * AOUT Enums
12306 *******************************************************/
12307
12308/*
12309 * AOUT_EN enum
12310 */
12311
12312typedef enum AOUT_EN {
12313AOUT_DISABLE                             = 0x00000000,
12314AOUT_ENABLE                              = 0x00000001,
12315} AOUT_EN;
12316
12317/*
12318 * AOUT_FIFO_START_ADDR enum
12319 */
12320
12321typedef enum AOUT_FIFO_START_ADDR {
12322AOUT_FIFO_START_ADDR_2                   = 0x00000000,
12323AOUT_FIFO_START_ADDR_3                   = 0x00000001,
12324} AOUT_FIFO_START_ADDR;
12325
12326/*
12327 * AOUT_CRC_TEST_EN enum
12328 */
12329
12330typedef enum AOUT_CRC_TEST_EN {
12331AOUT_CRC_DISABLE                         = 0x00000000,
12332AOUT_CRC_ENABLE                          = 0x00000001,
12333} AOUT_CRC_TEST_EN;
12334
12335/*
12336 * AOUT_CRC_SOFT_RESET enum
12337 */
12338
12339typedef enum AOUT_CRC_SOFT_RESET {
12340AOUT_CRC_NO_RESET                        = 0x00000000,
12341AOUT_CRC_RESET                           = 0x00000001,
12342} AOUT_CRC_SOFT_RESET;
12343
12344/*
12345 * AOUT_CRC_CONT_EN enum
12346 */
12347
12348typedef enum AOUT_CRC_CONT_EN {
12349AOUT_CRC_ONE_SHOT                        = 0x00000000,
12350AOUT_CRC_CONT                            = 0x00000001,
12351} AOUT_CRC_CONT_EN;
12352
12353/*
12354 * I2S_WORD_SIZE enum
12355 */
12356
12357typedef enum I2S_WORD_SIZE {
12358I2S_WORD_SIZE_32                         = 0x00000000,
12359I2S_WORD_SIZE_16                         = 0x00000001,
12360} I2S_WORD_SIZE;
12361
12362/*
12363 * I2S_SAMPLE_ALIGNMENT enum
12364 */
12365
12366typedef enum I2S_SAMPLE_ALIGNMENT {
12367I2S_SAMPLE_LEFT_ALIGNED                  = 0x00000000,
12368I2S_SAMPLE_RIGHT_ALIGNED                 = 0x00000001,
12369} I2S_SAMPLE_ALIGNMENT;
12370
12371/*
12372 * I2S_SAMPLE_BIT_ORDER enum
12373 */
12374
12375typedef enum I2S_SAMPLE_BIT_ORDER {
12376I2S_SAMPLE_BIT_ORDER_MSB                 = 0x00000000,
12377I2S_SAMPLE_BIT_ORDER_LSB                 = 0x00000001,
12378} I2S_SAMPLE_BIT_ORDER;
12379
12380/*
12381 * I2S_LRCLK_POLARITY enum
12382 */
12383
12384typedef enum I2S_LRCLK_POLARITY {
12385I2S_LRCLK_LOW_LEFT                       = 0x00000000,
12386I2S_LRCLK_HIGH_LEFT                      = 0x00000001,
12387} I2S_LRCLK_POLARITY;
12388
12389/*
12390 * I2S_WORD_ALIGNMENT enum
12391 */
12392
12393typedef enum I2S_WORD_ALIGNMENT {
12394I2S_WORD_ALTERNATE_ALIGNMENT             = 0x00000000,
12395I2S_WORD_I2S_ALIGNMENT                   = 0x00000001,
12396} I2S_WORD_ALIGNMENT;
12397
12398/*
12399 * SPDIF_INVERT_EN enum
12400 */
12401
12402typedef enum SPDIF_INVERT_EN {
12403SPDIF_INVERT_DISABLE                     = 0x00000000,
12404SPDIF_INVERT_ENABLE                      = 0x00000001,
12405} SPDIF_INVERT_EN;
12406
12407/*******************************************************
12408 * DCO Enums
12409 *******************************************************/
12410
12411/*
12412 * DPDBG_EN enum
12413 */
12414
12415typedef enum DPDBG_EN {
12416DPDBG_DISABLE                            = 0x00000000,
12417DPDBG_ENABLE                             = 0x00000001,
12418} DPDBG_EN;
12419
12420/*
12421 * DPDBG_INPUT_EN enum
12422 */
12423
12424typedef enum DPDBG_INPUT_EN {
12425DPDBG_INPUT_DISABLE                      = 0x00000000,
12426DPDBG_INPUT_ENABLE                       = 0x00000001,
12427} DPDBG_INPUT_EN;
12428
12429/*
12430 * DPDBG_ERROR_DETECTION_MODE enum
12431 */
12432
12433typedef enum DPDBG_ERROR_DETECTION_MODE {
12434DPDBG_ERROR_DETECTION_MODE_CSC           = 0x00000000,
12435DPDBG_ERROR_DETECTION_MODE_RS_ENCODING   = 0x00000001,
12436} DPDBG_ERROR_DETECTION_MODE;
12437
12438/*
12439 * DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK enum
12440 */
12441
12442typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
12443DPDBG_FIFO_OVERFLOW_INT_DISABLE          = 0x00000000,
12444DPDBG_FIFO_OVERFLOW_INT_ENABLE           = 0x00000001,
12445} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
12446
12447/*
12448 * DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE enum
12449 */
12450
12451typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
12452DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED      = 0x00000000,
12453DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED      = 0x00000001,
12454} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
12455
12456/*
12457 * DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK enum
12458 */
12459
12460typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
12461DPDBG_FIFO_OVERFLOW_INT_NO_ACK           = 0x00000000,
12462DPDBG_FIFO_OVERFLOW_INT_CLEAR            = 0x00000001,
12463} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
12464
12465/*
12466 * PM_ASSERT_RESET enum
12467 */
12468
12469typedef enum PM_ASSERT_RESET {
12470PM_ASSERT_RESET_0                        = 0x00000000,
12471PM_ASSERT_RESET_1                        = 0x00000001,
12472} PM_ASSERT_RESET;
12473
12474/*
12475 * DAC_MUX_SELECT enum
12476 */
12477
12478typedef enum DAC_MUX_SELECT {
12479DAC_MUX_SELECT_DACA                      = 0x00000000,
12480DAC_MUX_SELECT_DACB                      = 0x00000001,
12481} DAC_MUX_SELECT;
12482
12483/*
12484 * TMDS_DVO_MUX_SELECT enum
12485 */
12486
12487typedef enum TMDS_DVO_MUX_SELECT {
12488TMDS_DVO_MUX_SELECT_B                    = 0x00000000,
12489TMDS_DVO_MUX_SELECT_G                    = 0x00000001,
12490TMDS_DVO_MUX_SELECT_R                    = 0x00000002,
12491TMDS_DVO_MUX_SELECT_RESERVED             = 0x00000003,
12492} TMDS_DVO_MUX_SELECT;
12493
12494/*
12495 * DACA_SOFT_RESET enum
12496 */
12497
12498typedef enum DACA_SOFT_RESET {
12499DACA_SOFT_RESET_0                        = 0x00000000,
12500DACA_SOFT_RESET_1                        = 0x00000001,
12501} DACA_SOFT_RESET;
12502
12503/*
12504 * I2S0_SPDIF0_SOFT_RESET enum
12505 */
12506
12507typedef enum I2S0_SPDIF0_SOFT_RESET {
12508I2S0_SPDIF0_SOFT_RESET_0                 = 0x00000000,
12509I2S0_SPDIF0_SOFT_RESET_1                 = 0x00000001,
12510} I2S0_SPDIF0_SOFT_RESET;
12511
12512/*
12513 * I2S1_SOFT_RESET enum
12514 */
12515
12516typedef enum I2S1_SOFT_RESET {
12517I2S1_SOFT_RESET_0                        = 0x00000000,
12518I2S1_SOFT_RESET_1                        = 0x00000001,
12519} I2S1_SOFT_RESET;
12520
12521/*
12522 * SPDIF1_SOFT_RESET enum
12523 */
12524
12525typedef enum SPDIF1_SOFT_RESET {
12526SPDIF1_SOFT_RESET_0                      = 0x00000000,
12527SPDIF1_SOFT_RESET_1                      = 0x00000001,
12528} SPDIF1_SOFT_RESET;
12529
12530/*
12531 * DB_CLK_SOFT_RESET enum
12532 */
12533
12534typedef enum DB_CLK_SOFT_RESET {
12535DB_CLK_SOFT_RESET_0                      = 0x00000000,
12536DB_CLK_SOFT_RESET_1                      = 0x00000001,
12537} DB_CLK_SOFT_RESET;
12538
12539/*
12540 * FMT0_SOFT_RESET enum
12541 */
12542
12543typedef enum FMT0_SOFT_RESET {
12544FMT0_SOFT_RESET_0                        = 0x00000000,
12545FMT0_SOFT_RESET_1                        = 0x00000001,
12546} FMT0_SOFT_RESET;
12547
12548/*
12549 * FMT1_SOFT_RESET enum
12550 */
12551
12552typedef enum FMT1_SOFT_RESET {
12553FMT1_SOFT_RESET_0                        = 0x00000000,
12554FMT1_SOFT_RESET_1                        = 0x00000001,
12555} FMT1_SOFT_RESET;
12556
12557/*
12558 * FMT2_SOFT_RESET enum
12559 */
12560
12561typedef enum FMT2_SOFT_RESET {
12562FMT2_SOFT_RESET_0                        = 0x00000000,
12563FMT2_SOFT_RESET_1                        = 0x00000001,
12564} FMT2_SOFT_RESET;
12565
12566/*
12567 * FMT3_SOFT_RESET enum
12568 */
12569
12570typedef enum FMT3_SOFT_RESET {
12571FMT3_SOFT_RESET_0                        = 0x00000000,
12572FMT3_SOFT_RESET_1                        = 0x00000001,
12573} FMT3_SOFT_RESET;
12574
12575/*
12576 * FMT4_SOFT_RESET enum
12577 */
12578
12579typedef enum FMT4_SOFT_RESET {
12580FMT4_SOFT_RESET_0                        = 0x00000000,
12581FMT4_SOFT_RESET_1                        = 0x00000001,
12582} FMT4_SOFT_RESET;
12583
12584/*
12585 * FMT5_SOFT_RESET enum
12586 */
12587
12588typedef enum FMT5_SOFT_RESET {
12589FMT5_SOFT_RESET_0                        = 0x00000000,
12590FMT5_SOFT_RESET_1                        = 0x00000001,
12591} FMT5_SOFT_RESET;
12592
12593/*
12594 * MVP_SOFT_RESET enum
12595 */
12596
12597typedef enum MVP_SOFT_RESET {
12598MVP_SOFT_RESET_0                         = 0x00000000,
12599MVP_SOFT_RESET_1                         = 0x00000001,
12600} MVP_SOFT_RESET;
12601
12602/*
12603 * ABM_SOFT_RESET enum
12604 */
12605
12606typedef enum ABM_SOFT_RESET {
12607ABM_SOFT_RESET_0                         = 0x00000000,
12608ABM_SOFT_RESET_1                         = 0x00000001,
12609} ABM_SOFT_RESET;
12610
12611/*
12612 * DVO_SOFT_RESET enum
12613 */
12614
12615typedef enum DVO_SOFT_RESET {
12616DVO_SOFT_RESET_0                         = 0x00000000,
12617DVO_SOFT_RESET_1                         = 0x00000001,
12618} DVO_SOFT_RESET;
12619
12620/*
12621 * DIGA_FE_SOFT_RESET enum
12622 */
12623
12624typedef enum DIGA_FE_SOFT_RESET {
12625DIGA_FE_SOFT_RESET_0                     = 0x00000000,
12626DIGA_FE_SOFT_RESET_1                     = 0x00000001,
12627} DIGA_FE_SOFT_RESET;
12628
12629/*
12630 * DIGA_BE_SOFT_RESET enum
12631 */
12632
12633typedef enum DIGA_BE_SOFT_RESET {
12634DIGA_BE_SOFT_RESET_0                     = 0x00000000,
12635DIGA_BE_SOFT_RESET_1                     = 0x00000001,
12636} DIGA_BE_SOFT_RESET;
12637
12638/*
12639 * DIGB_FE_SOFT_RESET enum
12640 */
12641
12642typedef enum DIGB_FE_SOFT_RESET {
12643DIGB_FE_SOFT_RESET_0                     = 0x00000000,
12644DIGB_FE_SOFT_RESET_1                     = 0x00000001,
12645} DIGB_FE_SOFT_RESET;
12646
12647/*
12648 * DIGB_BE_SOFT_RESET enum
12649 */
12650
12651typedef enum DIGB_BE_SOFT_RESET {
12652DIGB_BE_SOFT_RESET_0                     = 0x00000000,
12653DIGB_BE_SOFT_RESET_1                     = 0x00000001,
12654} DIGB_BE_SOFT_RESET;
12655
12656/*
12657 * DIGC_FE_SOFT_RESET enum
12658 */
12659
12660typedef enum DIGC_FE_SOFT_RESET {
12661DIGC_FE_SOFT_RESET_0                     = 0x00000000,
12662DIGC_FE_SOFT_RESET_1                     = 0x00000001,
12663} DIGC_FE_SOFT_RESET;
12664
12665/*
12666 * DIGC_BE_SOFT_RESET enum
12667 */
12668
12669typedef enum DIGC_BE_SOFT_RESET {
12670DIGC_BE_SOFT_RESET_0                     = 0x00000000,
12671DIGC_BE_SOFT_RESET_1                     = 0x00000001,
12672} DIGC_BE_SOFT_RESET;
12673
12674/*
12675 * DIGD_FE_SOFT_RESET enum
12676 */
12677
12678typedef enum DIGD_FE_SOFT_RESET {
12679DIGD_FE_SOFT_RESET_0                     = 0x00000000,
12680DIGD_FE_SOFT_RESET_1                     = 0x00000001,
12681} DIGD_FE_SOFT_RESET;
12682
12683/*
12684 * DIGD_BE_SOFT_RESET enum
12685 */
12686
12687typedef enum DIGD_BE_SOFT_RESET {
12688DIGD_BE_SOFT_RESET_0                     = 0x00000000,
12689DIGD_BE_SOFT_RESET_1                     = 0x00000001,
12690} DIGD_BE_SOFT_RESET;
12691
12692/*
12693 * DIGE_FE_SOFT_RESET enum
12694 */
12695
12696typedef enum DIGE_FE_SOFT_RESET {
12697DIGE_FE_SOFT_RESET_0                     = 0x00000000,
12698DIGE_FE_SOFT_RESET_1                     = 0x00000001,
12699} DIGE_FE_SOFT_RESET;
12700
12701/*
12702 * DIGE_BE_SOFT_RESET enum
12703 */
12704
12705typedef enum DIGE_BE_SOFT_RESET {
12706DIGE_BE_SOFT_RESET_0                     = 0x00000000,
12707DIGE_BE_SOFT_RESET_1                     = 0x00000001,
12708} DIGE_BE_SOFT_RESET;
12709
12710/*
12711 * DIGF_FE_SOFT_RESET enum
12712 */
12713
12714typedef enum DIGF_FE_SOFT_RESET {
12715DIGF_FE_SOFT_RESET_0                     = 0x00000000,
12716DIGF_FE_SOFT_RESET_1                     = 0x00000001,
12717} DIGF_FE_SOFT_RESET;
12718
12719/*
12720 * DIGF_BE_SOFT_RESET enum
12721 */
12722
12723typedef enum DIGF_BE_SOFT_RESET {
12724DIGF_BE_SOFT_RESET_0                     = 0x00000000,
12725DIGF_BE_SOFT_RESET_1                     = 0x00000001,
12726} DIGF_BE_SOFT_RESET;
12727
12728/*
12729 * DIGG_FE_SOFT_RESET enum
12730 */
12731
12732typedef enum DIGG_FE_SOFT_RESET {
12733DIGG_FE_SOFT_RESET_0                     = 0x00000000,
12734DIGG_FE_SOFT_RESET_1                     = 0x00000001,
12735} DIGG_FE_SOFT_RESET;
12736
12737/*
12738 * DIGG_BE_SOFT_RESET enum
12739 */
12740
12741typedef enum DIGG_BE_SOFT_RESET {
12742DIGG_BE_SOFT_RESET_0                     = 0x00000000,
12743DIGG_BE_SOFT_RESET_1                     = 0x00000001,
12744} DIGG_BE_SOFT_RESET;
12745
12746/*
12747 * DPDBG_SOFT_RESET enum
12748 */
12749
12750typedef enum DPDBG_SOFT_RESET {
12751DPDBG_SOFT_RESET_0                       = 0x00000000,
12752DPDBG_SOFT_RESET_1                       = 0x00000001,
12753} DPDBG_SOFT_RESET;
12754
12755/*
12756 * DIGLPA_FE_SOFT_RESET enum
12757 */
12758
12759typedef enum DIGLPA_FE_SOFT_RESET {
12760DIGLPA_FE_SOFT_RESET_0                   = 0x00000000,
12761DIGLPA_FE_SOFT_RESET_1                   = 0x00000001,
12762} DIGLPA_FE_SOFT_RESET;
12763
12764/*
12765 * DIGLPA_BE_SOFT_RESET enum
12766 */
12767
12768typedef enum DIGLPA_BE_SOFT_RESET {
12769DIGLPA_BE_SOFT_RESET_0                   = 0x00000000,
12770DIGLPA_BE_SOFT_RESET_1                   = 0x00000001,
12771} DIGLPA_BE_SOFT_RESET;
12772
12773/*
12774 * DIGLPB_FE_SOFT_RESET enum
12775 */
12776
12777typedef enum DIGLPB_FE_SOFT_RESET {
12778DIGLPB_FE_SOFT_RESET_0                   = 0x00000000,
12779DIGLPB_FE_SOFT_RESET_1                   = 0x00000001,
12780} DIGLPB_FE_SOFT_RESET;
12781
12782/*
12783 * DIGLPB_BE_SOFT_RESET enum
12784 */
12785
12786typedef enum DIGLPB_BE_SOFT_RESET {
12787DIGLPB_BE_SOFT_RESET_0                   = 0x00000000,
12788DIGLPB_BE_SOFT_RESET_1                   = 0x00000001,
12789} DIGLPB_BE_SOFT_RESET;
12790
12791/*
12792 * GENERICA_STEREOSYNC_SEL enum
12793 */
12794
12795typedef enum GENERICA_STEREOSYNC_SEL {
12796GENERICA_STEREOSYNC_SEL_D1               = 0x00000000,
12797GENERICA_STEREOSYNC_SEL_D2               = 0x00000001,
12798GENERICA_STEREOSYNC_SEL_D3               = 0x00000002,
12799GENERICA_STEREOSYNC_SEL_D4               = 0x00000003,
12800GENERICA_STEREOSYNC_SEL_D5               = 0x00000004,
12801GENERICA_STEREOSYNC_SEL_D6               = 0x00000005,
12802GENERICA_STEREOSYNC_SEL_RESERVED         = 0x00000006,
12803} GENERICA_STEREOSYNC_SEL;
12804
12805/*
12806 * GENERICB_STEREOSYNC_SEL enum
12807 */
12808
12809typedef enum GENERICB_STEREOSYNC_SEL {
12810GENERICB_STEREOSYNC_SEL_D1               = 0x00000000,
12811GENERICB_STEREOSYNC_SEL_D2               = 0x00000001,
12812GENERICB_STEREOSYNC_SEL_D3               = 0x00000002,
12813GENERICB_STEREOSYNC_SEL_D4               = 0x00000003,
12814GENERICB_STEREOSYNC_SEL_D5               = 0x00000004,
12815GENERICB_STEREOSYNC_SEL_D6               = 0x00000005,
12816GENERICB_STEREOSYNC_SEL_RESERVED         = 0x00000006,
12817} GENERICB_STEREOSYNC_SEL;
12818
12819/*
12820 * DCO_DBG_BLOCK_SEL enum
12821 */
12822
12823typedef enum DCO_DBG_BLOCK_SEL {
12824DCO_DBG_BLOCK_SEL_DCO                    = 0x00000000,
12825DCO_DBG_BLOCK_SEL_ABM                    = 0x00000001,
12826DCO_DBG_BLOCK_SEL_DVO                    = 0x00000002,
12827DCO_DBG_BLOCK_SEL_DAC                    = 0x00000003,
12828DCO_DBG_BLOCK_SEL_MVP                    = 0x00000004,
12829DCO_DBG_BLOCK_SEL_FMT0                   = 0x00000005,
12830DCO_DBG_BLOCK_SEL_FMT1                   = 0x00000006,
12831DCO_DBG_BLOCK_SEL_FMT2                   = 0x00000007,
12832DCO_DBG_BLOCK_SEL_FMT3                   = 0x00000008,
12833DCO_DBG_BLOCK_SEL_FMT4                   = 0x00000009,
12834DCO_DBG_BLOCK_SEL_FMT5                   = 0x0000000a,
12835DCO_DBG_BLOCK_SEL_DIGFE_A                = 0x0000000b,
12836DCO_DBG_BLOCK_SEL_DIGFE_B                = 0x0000000c,
12837DCO_DBG_BLOCK_SEL_DIGFE_C                = 0x0000000d,
12838DCO_DBG_BLOCK_SEL_DIGFE_D                = 0x0000000e,
12839DCO_DBG_BLOCK_SEL_DIGFE_E                = 0x0000000f,
12840DCO_DBG_BLOCK_SEL_DIGFE_F                = 0x00000010,
12841DCO_DBG_BLOCK_SEL_DIGFE_G                = 0x00000011,
12842DCO_DBG_BLOCK_SEL_DIGA                   = 0x00000012,
12843DCO_DBG_BLOCK_SEL_DIGB                   = 0x00000013,
12844DCO_DBG_BLOCK_SEL_DIGC                   = 0x00000014,
12845DCO_DBG_BLOCK_SEL_DIGD                   = 0x00000015,
12846DCO_DBG_BLOCK_SEL_DIGE                   = 0x00000016,
12847DCO_DBG_BLOCK_SEL_DIGF                   = 0x00000017,
12848DCO_DBG_BLOCK_SEL_DIGG                   = 0x00000018,
12849DCO_DBG_BLOCK_SEL_DPFE_A                 = 0x00000019,
12850DCO_DBG_BLOCK_SEL_DPFE_B                 = 0x0000001a,
12851DCO_DBG_BLOCK_SEL_DPFE_C                 = 0x0000001b,
12852DCO_DBG_BLOCK_SEL_DPFE_D                 = 0x0000001c,
12853DCO_DBG_BLOCK_SEL_DPFE_E                 = 0x0000001d,
12854DCO_DBG_BLOCK_SEL_DPFE_F                 = 0x0000001e,
12855DCO_DBG_BLOCK_SEL_DPFE_G                 = 0x0000001f,
12856DCO_DBG_BLOCK_SEL_DPA                    = 0x00000020,
12857DCO_DBG_BLOCK_SEL_DPB                    = 0x00000021,
12858DCO_DBG_BLOCK_SEL_DPC                    = 0x00000022,
12859DCO_DBG_BLOCK_SEL_DPD                    = 0x00000023,
12860DCO_DBG_BLOCK_SEL_DPE                    = 0x00000024,
12861DCO_DBG_BLOCK_SEL_DPF                    = 0x00000025,
12862DCO_DBG_BLOCK_SEL_DPG                    = 0x00000026,
12863DCO_DBG_BLOCK_SEL_AUX0                   = 0x00000027,
12864DCO_DBG_BLOCK_SEL_AUX1                   = 0x00000028,
12865DCO_DBG_BLOCK_SEL_AUX2                   = 0x00000029,
12866DCO_DBG_BLOCK_SEL_AUX3                   = 0x0000002a,
12867DCO_DBG_BLOCK_SEL_AUX4                   = 0x0000002b,
12868DCO_DBG_BLOCK_SEL_AUX5                   = 0x0000002c,
12869DCO_DBG_BLOCK_SEL_PERFMON_DCO            = 0x0000002d,
12870DCO_DBG_BLOCK_SEL_AUDIO_OUT              = 0x0000002e,
12871DCO_DBG_BLOCK_SEL_DIGLPFEA               = 0x0000002f,
12872DCO_DBG_BLOCK_SEL_DIGLPFEB               = 0x00000030,
12873DCO_DBG_BLOCK_SEL_DIGLPA                 = 0x00000031,
12874DCO_DBG_BLOCK_SEL_DIGLPB                 = 0x00000032,
12875DCO_DBG_BLOCK_SEL_DPLPFEA                = 0x00000033,
12876DCO_DBG_BLOCK_SEL_DPLPFEB                = 0x00000034,
12877DCO_DBG_BLOCK_SEL_DPLPA                  = 0x00000035,
12878DCO_DBG_BLOCK_SEL_DPLPB                  = 0x00000036,
12879} DCO_DBG_BLOCK_SEL;
12880
12881/*
12882 * DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE enum
12883 */
12884
12885typedef enum DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE {
12886DCO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL       = 0x00000000,
12887DCO_HDMI_RXSTATUS_TIMER_TYPE_PULSE       = 0x00000001,
12888} DCO_HDMI_RXSTATUS_TIMER_CONTROL_DCO_HDMI_RXSTATUS_TIMER_TYPE;
12889
12890/*
12891 * FMT420_MEMORY_SOURCE_SEL enum
12892 */
12893
12894typedef enum FMT420_MEMORY_SOURCE_SEL {
12895FMT420_MEMORY_SOURCE_SEL_FMT0            = 0x00000000,
12896FMT420_MEMORY_SOURCE_SEL_FMT1            = 0x00000001,
12897FMT420_MEMORY_SOURCE_SEL_FMT2            = 0x00000002,
12898FMT420_MEMORY_SOURCE_SEL_FMT3            = 0x00000003,
12899FMT420_MEMORY_SOURCE_SEL_FMT4            = 0x00000004,
12900FMT420_MEMORY_SOURCE_SEL_FMT5            = 0x00000005,
12901FMT420_MEMORY_SOURCE_SEL_FMT_RESERVED    = 0x00000006,
12902} FMT420_MEMORY_SOURCE_SEL;
12903
12904/*******************************************************
12905 * DOUT_I2C Enums
12906 *******************************************************/
12907
12908/*
12909 * DOUT_I2C_CONTROL_GO enum
12910 */
12911
12912typedef enum DOUT_I2C_CONTROL_GO {
12913DOUT_I2C_CONTROL_STOP_TRANSFER           = 0x00000000,
12914DOUT_I2C_CONTROL_START_TRANSFER          = 0x00000001,
12915} DOUT_I2C_CONTROL_GO;
12916
12917/*
12918 * DOUT_I2C_CONTROL_SOFT_RESET enum
12919 */
12920
12921typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
12922DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
12923DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER    = 0x00000001,
12924} DOUT_I2C_CONTROL_SOFT_RESET;
12925
12926/*
12927 * DOUT_I2C_CONTROL_SEND_RESET enum
12928 */
12929
12930typedef enum DOUT_I2C_CONTROL_SEND_RESET {
12931DOUT_I2C_CONTROL__NOT_SEND_RESET         = 0x00000000,
12932DOUT_I2C_CONTROL__SEND_RESET             = 0x00000001,
12933} DOUT_I2C_CONTROL_SEND_RESET;
12934
12935/*
12936 * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
12937 */
12938
12939typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
12940DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS     = 0x00000000,
12941DOUT_I2C_CONTROL_RESET_SW_STATUS         = 0x00000001,
12942} DOUT_I2C_CONTROL_SW_STATUS_RESET;
12943
12944/*
12945 * DOUT_I2C_CONTROL_DDC_SELECT enum
12946 */
12947
12948typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
12949DOUT_I2C_CONTROL_SELECT_DDC1             = 0x00000000,
12950DOUT_I2C_CONTROL_SELECT_DDC2             = 0x00000001,
12951DOUT_I2C_CONTROL_SELECT_DDC3             = 0x00000002,
12952DOUT_I2C_CONTROL_SELECT_DDC4             = 0x00000003,
12953DOUT_I2C_CONTROL_SELECT_DDC5             = 0x00000004,
12954DOUT_I2C_CONTROL_SELECT_DDC6             = 0x00000005,
12955DOUT_I2C_CONTROL_SELECT_DDCVGA           = 0x00000006,
12956} DOUT_I2C_CONTROL_DDC_SELECT;
12957
12958/*
12959 * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
12960 */
12961
12962typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
12963DOUT_I2C_CONTROL_TRANS0                  = 0x00000000,
12964DOUT_I2C_CONTROL_TRANS0_TRANS1           = 0x00000001,
12965DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2    = 0x00000002,
12966DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3  = 0x00000003,
12967} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
12968
12969/*
12970 * DOUT_I2C_CONTROL_DBG_REF_SEL enum
12971 */
12972
12973typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
12974DOUT_I2C_CONTROL_NORMAL_DEBUG            = 0x00000000,
12975DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG    = 0x00000001,
12976} DOUT_I2C_CONTROL_DBG_REF_SEL;
12977
12978/*
12979 * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
12980 */
12981
12982typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
12983DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL  = 0x00000000,
12984DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH    = 0x00000001,
12985DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
12986DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
12987} DOUT_I2C_ARBITRATION_SW_PRIORITY;
12988
12989/*
12990 * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
12991 */
12992
12993typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
12994DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED    = 0x00000000,
12995DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED   = 0x00000001,
12996} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
12997
12998/*
12999 * DOUT_I2C_ARBITRATION_ABORT_XFER enum
13000 */

13001
13002typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
13003DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
13004DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER  = 0x00000001,
13005} DOUT_I2C_ARBITRATION_ABORT_XFER;
13006
13007/*
13008 * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
13009 */
13010
13011typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
13012DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
13013DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ    = 0x00000001,
13014} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
13015
13016/*
13017 * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
13018 */
13019
13020typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
13021DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
13022DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG  = 0x00000001,
13023} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
13024
13025/*
13026 * DOUT_I2C_ACK enum
13027 */
13028
13029typedef enum DOUT_I2C_ACK {
13030DOUT_I2C_NO_ACK                          = 0x00000000,
13031DOUT_I2C_ACK_TO_CLEAN                    = 0x00000001,
13032} DOUT_I2C_ACK;
13033
13034/*
13035 * DOUT_I2C_DDC_SPEED_THRESHOLD enum
13036 */
13037
13038typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
13039DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO  = 0x00000000,
13040DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE  = 0x00000001,
13041DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE  = 0x00000002,
13042DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE  = 0x00000003,
13043} DOUT_I2C_DDC_SPEED_THRESHOLD;
13044
13045/*
13046 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
13047 */
13048
13049typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
13050DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
13051DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA     = 0x00000001,
13052} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
13053
13054/*
13055 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
13056 */
13057
13058typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
13059DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS  = 0x00000000,
13060DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS  = 0x00000001,
13061} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
13062
13063/*
13064 * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
13065 */
13066
13067typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
13068DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT   = 0x00000000,
13069DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT  = 0x00000001,
13070} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
13071
13072/*
13073 * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
13074 */
13075
13076typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
13077DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR  = 0x00000000,
13078DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL     = 0x00000001,
13079} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
13080
13081/*
13082 * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
13083 */
13084
13085typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
13086DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS  = 0x00000000,
13087DOUT_I2C_TRANSACTION_STOP_ALL_TRANS      = 0x00000001,
13088} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
13089
13090/*
13091 * DOUT_I2C_DATA_INDEX_WRITE enum
13092 */
13093
13094typedef enum DOUT_I2C_DATA_INDEX_WRITE {
13095DOUT_I2C_DATA__NOT_INDEX_WRITE           = 0x00000000,
13096DOUT_I2C_DATA__INDEX_WRITE               = 0x00000001,
13097} DOUT_I2C_DATA_INDEX_WRITE;
13098
13099/*
13100 * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
13101 */
13102
13103typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
13104DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
13105DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION  = 0x00000001,
13106} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
13107
13108/*
13109 * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
13110 */
13111
13112typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
13113DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL  = 0x00000000,
13114DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE  = 0x00000001,
13115} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
13116
13117/*******************************************************
13118 * FBC Enums
13119 *******************************************************/
13120
13121/*
13122 * FBC_IDLE_MASK_MASK_BITS enum
13123 */
13124
13125typedef enum FBC_IDLE_MASK_MASK_BITS {
13126FBC_IDLE_MASK_DISP_REG_UPDATE            = 0x00000000,
13127FBC_IDLE_MASK_RESERVED1                  = 0x00000001,
13128FBC_IDLE_MASK_FBC_GRPH_COMP_EN           = 0x00000002,
13129FBC_IDLE_MASK_FBC_MIN_COMPRESSION        = 0x00000003,
13130FBC_IDLE_MASK_FBC_ALPHA_COMP_EN          = 0x00000004,
13131FBC_IDLE_MASK_FBC_ZERO_ALPHA_CHUNK_SKIP_EN  = 0x00000005,
13132FBC_IDLE_MASK_FBC_FORCE_COPY_TO_COMP_BUF  = 0x00000006,
13133FBC_IDLE_MASK_RESERVED7                  = 0x00000007,
13134FBC_IDLE_MASK_RESERVED8                  = 0x00000008,
13135FBC_IDLE_MASK_RESERVED9                  = 0x00000009,
13136FBC_IDLE_MASK_RESERVED10                 = 0x0000000a,
13137FBC_IDLE_MASK_RESERVED11                 = 0x0000000b,
13138FBC_IDLE_MASK_RESERVED12                 = 0x0000000c,
13139FBC_IDLE_MASK_RESERVED13                 = 0x0000000d,
13140FBC_IDLE_MASK_RESERVED14                 = 0x0000000e,
13141FBC_IDLE_MASK_RESERVED15                 = 0x0000000f,
13142FBC_IDLE_MASK_RESERVED16                 = 0x00000010,
13143FBC_IDLE_MASK_RESERVED17                 = 0x00000011,
13144FBC_IDLE_MASK_RESERVED18                 = 0x00000012,
13145FBC_IDLE_MASK_RESERVED19                 = 0x00000013,
13146FBC_IDLE_MASK_RESERVED20                 = 0x00000014,
13147FBC_IDLE_MASK_RESERVED21                 = 0x00000015,
13148FBC_IDLE_MASK_RESERVED22                 = 0x00000016,
13149FBC_IDLE_MASK_RESERVED23                 = 0x00000017,
13150FBC_IDLE_MASK_MC_HIT_REGION_0            = 0x00000018,
13151FBC_IDLE_MASK_MC_HIT_REGION_1            = 0x00000019,
13152FBC_IDLE_MASK_MC_HIT_REGION_2            = 0x0000001a,
13153FBC_IDLE_MASK_MC_HIT_REGION_3            = 0x0000001b,
13154FBC_IDLE_MASK_MC_WRITE                   = 0x0000001c,
13155FBC_IDLE_MASK_RESERVED29                 = 0x0000001d,
13156FBC_IDLE_MASK_RESERVED30                 = 0x0000001e,
13157FBC_IDLE_MASK_RESERVED31                 = 0x0000001f,
13158} FBC_IDLE_MASK_MASK_BITS;
13159
13160/*******************************************************
13161 * DPCSRX Enums
13162 *******************************************************/
13163
13164/*
13165 * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
13166 */
13167
13168typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
13169DPCSRX_BPHY_PCS_RX0_CLK                  = 0x00000000,
13170DPCSRX_BPHY_PCS_RX1_CLK                  = 0x00000001,
13171DPCSRX_BPHY_PCS_RX2_CLK                  = 0x00000002,
13172DPCSRX_BPHY_PCS_RX3_CLK                  = 0x00000003,
13173} DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL;
13174
13175/*
13176 * DPCSRX_DBG_CFGCLK_SEL enum
13177 */
13178
13179typedef enum DPCSRX_DBG_CFGCLK_SEL {
13180DPCSRX_DBG_CFGCLK_SEL_DC_DPCS_INF        = 0x00000000,
13181DPCSRX_DBG_CFGCLK_SEL_DPCS_BPHY_INF      = 0x00000001,
13182DPCSRX_DBG_CFGCLK_SEL_CBUS_SLAVE         = 0x00000002,
13183DPCSRX_DBG_CFGCLK_SEL_CBUS_MASTER        = 0x00000003,
13184} DPCSRX_DBG_CFGCLK_SEL;
13185
13186/*
13187 * DPCSRX_RX_SYMCLK_SEL enum
13188 */
13189
13190typedef enum DPCSRX_RX_SYMCLK_SEL {
13191DPCSRX_DBG_RX_SYMCLK_SEL_OUT0            = 0x00000000,
13192DPCSRX_DBG_RX_SYMCLK_SEL_OUT1            = 0x00000001,
13193DPCSRX_DBG_RX_SYMCLK_SEL_INT             = 0x00000002,
13194} DPCSRX_RX_SYMCLK_SEL;
13195
13196/*******************************************************
13197 * DPCSTX Enums
13198 *******************************************************/
13199
13200/*
13201 * DPCSTX_DBG_CFGCLK_SEL enum
13202 */
13203
13204typedef enum DPCSTX_DBG_CFGCLK_SEL {
13205DPCSTX_DBG_CFGCLK_SEL_DC_DPCS_INF        = 0x00000000,
13206DPCSTX_DBG_CFGCLK_SEL_DPCS_BPHY_INF      = 0x00000001,
13207DPCSTX_DBG_CFGCLK_SEL_CBUS_SLAVE         = 0x00000002,
13208DPCSTX_DBG_CFGCLK_SEL_CBUS_MASTER        = 0x00000003,
13209} DPCSTX_DBG_CFGCLK_SEL;
13210
13211/*
13212 * DPCSTX_TX_SYMCLK_SEL enum
13213 */
13214
13215typedef enum DPCSTX_TX_SYMCLK_SEL {
13216DPCSTX_DBG_TX_SYMCLK_SEL_IN0             = 0x00000000,
13217DPCSTX_DBG_TX_SYMCLK_SEL_IN1             = 0x00000001,
13218DPCSTX_DBG_TX_SYMCLK_SEL_FIFO_WR         = 0x00000002,
13219} DPCSTX_TX_SYMCLK_SEL;
13220
13221/*
13222 * DPCSTX_TX_SYMCLK_DIV2_SEL enum
13223 */
13224
13225typedef enum DPCSTX_TX_SYMCLK_DIV2_SEL {
13226DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT0       = 0x00000000,
13227DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT1       = 0x00000001,
13228DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT2       = 0x00000002,
13229DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_OUT3       = 0x00000003,
13230DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_FIFO_RD    = 0x00000004,
13231DPCSTX_DBG_TX_SYMCLK_DIV2_SEL_INT        = 0x00000005,
13232} DPCSTX_TX_SYMCLK_DIV2_SEL;
13233
13234/*******************************************************
13235 * CB Enums
13236 *******************************************************/
13237
13238/*
13239 * SurfaceNumber enum
13240 */
13241
13242typedef enum SurfaceNumber {
13243NUMBER_UNORM                             = 0x00000000,
13244NUMBER_SNORM                             = 0x00000001,
13245NUMBER_USCALED                           = 0x00000002,
13246NUMBER_SSCALED                           = 0x00000003,
13247NUMBER_UINT                              = 0x00000004,
13248NUMBER_SINT                              = 0x00000005,
13249NUMBER_SRGB                              = 0x00000006,
13250NUMBER_FLOAT                             = 0x00000007,
13251} SurfaceNumber;
13252
13253/*
13254 * SurfaceSwap enum
13255 */
13256
13257typedef enum SurfaceSwap {
13258SWAP_STD                                 = 0x00000000,
13259SWAP_ALT                                 = 0x00000001,
13260SWAP_STD_REV                             = 0x00000002,
13261SWAP_ALT_REV                             = 0x00000003,
13262} SurfaceSwap;
13263
13264/*
13265 * CBMode enum
13266 */
13267
13268typedef enum CBMode {
13269CB_DISABLE                               = 0x00000000,
13270CB_NORMAL                                = 0x00000001,
13271CB_ELIMINATE_FAST_CLEAR                  = 0x00000002,
13272CB_RESOLVE                               = 0x00000003,
13273CB_DECOMPRESS                            = 0x00000004,
13274CB_FMASK_DECOMPRESS                      = 0x00000005,
13275CB_DCC_DECOMPRESS                        = 0x00000006,
13276} CBMode;
13277
13278/*
13279 * RoundMode enum
13280 */
13281
13282typedef enum RoundMode {
13283ROUND_BY_HALF                            = 0x00000000,
13284ROUND_TRUNCATE                           = 0x00000001,
13285} RoundMode;
13286
13287/*
13288 * SourceFormat enum
13289 */
13290
13291typedef enum SourceFormat {
13292EXPORT_4C_32BPC                          = 0x00000000,
13293EXPORT_4C_16BPC                          = 0x00000001,
13294EXPORT_2C_32BPC_GR                       = 0x00000002,
13295EXPORT_2C_32BPC_AR                       = 0x00000003,
13296} SourceFormat;
13297
13298/*
13299 * BlendOp enum
13300 */
13301
13302typedef enum BlendOp {
13303BLEND_ZERO                               = 0x00000000,
13304BLEND_ONE                                = 0x00000001,
13305BLEND_SRC_COLOR                          = 0x00000002,
13306BLEND_ONE_MINUS_SRC_COLOR                = 0x00000003,
13307BLEND_SRC_ALPHA                          = 0x00000004,
13308BLEND_ONE_MINUS_SRC_ALPHA                = 0x00000005,
13309BLEND_DST_ALPHA                          = 0x00000006,
13310BLEND_ONE_MINUS_DST_ALPHA                = 0x00000007,
13311BLEND_DST_COLOR                          = 0x00000008,
13312BLEND_ONE_MINUS_DST_COLOR                = 0x00000009,
13313BLEND_SRC_ALPHA_SATURATE                 = 0x0000000a,
13314BLEND_BOTH_SRC_ALPHA                     = 0x0000000b,
13315BLEND_BOTH_INV_SRC_ALPHA                 = 0x0000000c,
13316BLEND_CONSTANT_COLOR                     = 0x0000000d,
13317BLEND_ONE_MINUS_CONSTANT_COLOR           = 0x0000000e,
13318BLEND_SRC1_COLOR                         = 0x0000000f,
13319BLEND_INV_SRC1_COLOR                     = 0x00000010,
13320BLEND_SRC1_ALPHA                         = 0x00000011,
13321BLEND_INV_SRC1_ALPHA                     = 0x00000012,
13322BLEND_CONSTANT_ALPHA                     = 0x00000013,
13323BLEND_ONE_MINUS_CONSTANT_ALPHA           = 0x00000014,
13324} BlendOp;
13325
13326/*
13327 * CombFunc enum
13328 */
13329
13330typedef enum CombFunc {
13331COMB_DST_PLUS_SRC                        = 0x00000000,
13332COMB_SRC_MINUS_DST                       = 0x00000001,
13333COMB_MIN_DST_SRC                         = 0x00000002,
13334COMB_MAX_DST_SRC                         = 0x00000003,
13335COMB_DST_MINUS_SRC                       = 0x00000004,
13336} CombFunc;
13337
13338/*
13339 * BlendOpt enum
13340 */
13341
13342typedef enum BlendOpt {
13343FORCE_OPT_AUTO                           = 0x00000000,
13344FORCE_OPT_DISABLE                        = 0x00000001,
13345FORCE_OPT_ENABLE_IF_SRC_A_0              = 0x00000002,
13346FORCE_OPT_ENABLE_IF_SRC_RGB_0            = 0x00000003,
13347FORCE_OPT_ENABLE_IF_SRC_ARGB_0           = 0x00000004,
13348FORCE_OPT_ENABLE_IF_SRC_A_1              = 0x00000005,
13349FORCE_OPT_ENABLE_IF_SRC_RGB_1            = 0x00000006,
13350FORCE_OPT_ENABLE_IF_SRC_ARGB_1           = 0x00000007,
13351} BlendOpt;
13352
13353/*
13354 * CmaskCode enum
13355 */
13356
13357typedef enum CmaskCode {
13358CMASK_CLR00_F0                           = 0x00000000,
13359CMASK_CLR00_F1                           = 0x00000001,
13360CMASK_CLR00_F2                           = 0x00000002,
13361CMASK_CLR00_FX                           = 0x00000003,
13362CMASK_CLR01_F0                           = 0x00000004,
13363CMASK_CLR01_F1                           = 0x00000005,
13364CMASK_CLR01_F2                           = 0x00000006,
13365CMASK_CLR01_FX                           = 0x00000007,
13366CMASK_CLR10_F0                           = 0x00000008,
13367CMASK_CLR10_F1                           = 0x00000009,
13368CMASK_CLR10_F2                           = 0x0000000a,
13369CMASK_CLR10_FX                           = 0x0000000b,
13370CMASK_CLR11_F0                           = 0x0000000c,
13371CMASK_CLR11_F1                           = 0x0000000d,
13372CMASK_CLR11_F2                           = 0x0000000e,
13373CMASK_CLR11_FX                           = 0x0000000f,
13374} CmaskCode;
13375
13376/*
13377 * CmaskAddr enum
13378 */
13379
13380typedef enum CmaskAddr {
13381CMASK_ADDR_TILED                         = 0x00000000,
13382CMASK_ADDR_LINEAR                        = 0x00000001,
13383CMASK_ADDR_COMPATIBLE                    = 0x00000002,
13384} CmaskAddr;
13385
13386/*
13387 * MemArbMode enum
13388 */
13389
13390typedef enum MemArbMode {
13391MEM_ARB_MODE_FIXED                       = 0x00000000,
13392MEM_ARB_MODE_AGE                         = 0x00000001,
13393MEM_ARB_MODE_WEIGHT                      = 0x00000002,
13394MEM_ARB_MODE_BOTH                        = 0x00000003,
13395} MemArbMode;
13396
13397/*
13398 * CBPerfSel enum
13399 */
13400
13401typedef enum CBPerfSel {
13402CB_PERF_SEL_NONE                         = 0x00000000,
13403CB_PERF_SEL_BUSY                         = 0x00000001,
13404CB_PERF_SEL_CORE_SCLK_VLD                = 0x00000002,
13405CB_PERF_SEL_REG_SCLK0_VLD                = 0x00000003,
13406CB_PERF_SEL_REG_SCLK1_VLD                = 0x00000004,
13407CB_PERF_SEL_DRAWN_QUAD                   = 0x00000005,
13408CB_PERF_SEL_DRAWN_PIXEL                  = 0x00000006,
13409CB_PERF_SEL_DRAWN_QUAD_FRAGMENT          = 0x00000007,
13410CB_PERF_SEL_DRAWN_TILE                   = 0x00000008,
13411CB_PERF_SEL_DB_CB_TILE_VALID_READY       = 0x00000009,
13412CB_PERF_SEL_DB_CB_TILE_VALID_READYB      = 0x0000000a,
13413CB_PERF_SEL_DB_CB_TILE_VALIDB_READY      = 0x0000000b,
13414CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB     = 0x0000000c,
13415CB_PERF_SEL_CM_FC_TILE_VALID_READY       = 0x0000000d,
13416CB_PERF_SEL_CM_FC_TILE_VALID_READYB      = 0x0000000e,
13417CB_PERF_SEL_CM_FC_TILE_VALIDB_READY      = 0x0000000f,
13418CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB     = 0x00000010,
13419CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY  = 0x00000011,
13420CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB  = 0x00000012,
13421CB_PERF_SEL_DB_CB_LQUAD_VALID_READY      = 0x00000013,
13422CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB     = 0x00000014,
13423CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY     = 0x00000015,
13424CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB    = 0x00000016,
13425CB_PERF_SEL_LQUAD_NO_TILE                = 0x00000017,
13426CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R  = 0x00000018,
13427CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR  = 0x00000019,
13428CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR  = 0x0000001a,
13429CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR  = 0x0000001b,
13430CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR  = 0x0000001c,
13431CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR  = 0x0000001d,
13432CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR  = 0x0000001e,
13433CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT  = 0x0000001f,
13434CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID  = 0x00000020,
13435CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK  = 0x00000021,
13436CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK  = 0x00000022,
13437CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL  = 0x00000023,
13438CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY    = 0x00000024,
13439CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB   = 0x00000025,
13440CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY   = 0x00000026,
13441CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB  = 0x00000027,
13442CB_PERF_SEL_FOP_IN_VALID_READY           = 0x00000028,
13443CB_PERF_SEL_FOP_IN_VALID_READYB          = 0x00000029,
13444CB_PERF_SEL_FOP_IN_VALIDB_READY          = 0x0000002a,
13445CB_PERF_SEL_FOP_IN_VALIDB_READYB         = 0x0000002b,
13446CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY   = 0x0000002c,
13447CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB  = 0x0000002d,
13448CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY  = 0x0000002e,
13449CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB  = 0x0000002f,
13450CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY    = 0x00000030,
13451CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB   = 0x00000031,
13452CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY   = 0x00000032,
13453CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB  = 0x00000033,
13454CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY    = 0x00000034,
13455CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB   = 0x00000035,
13456CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY   = 0x00000036,
13457CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB  = 0x00000037,
13458CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY  = 0x00000038,
13459CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB  = 0x00000039,
13460CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY  = 0x0000003a,
13461CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB  = 0x0000003b,
13462CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY  = 0x0000003c,
13463CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB  = 0x0000003d,
13464CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY  = 0x0000003e,
13465CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB  = 0x0000003f,
13466CB_PERF_SEL_CC_BC_CS_FRAG_VALID          = 0x00000040,
13467CB_PERF_SEL_CM_CACHE_HIT                 = 0x00000041,
13468CB_PERF_SEL_CM_CACHE_TAG_MISS            = 0x00000042,
13469CB_PERF_SEL_CM_CACHE_SECTOR_MISS         = 0x00000043,
13470CB_PERF_SEL_CM_CACHE_REEVICTION_STALL    = 0x00000044,
13471CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000045,
13472CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000046,
13473CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000047,
13474CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL   = 0x00000048,
13475CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL  = 0x00000049,
13476CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL    = 0x0000004a,
13477CB_PERF_SEL_CM_CACHE_STALL               = 0x0000004b,
13478CB_PERF_SEL_CM_CACHE_FLUSH               = 0x0000004c,
13479CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED        = 0x0000004d,
13480CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED     = 0x0000004e,
13481CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000004f,
13482CB_PERF_SEL_FC_CACHE_HIT                 = 0x00000050,
13483CB_PERF_SEL_FC_CACHE_TAG_MISS            = 0x00000051,
13484CB_PERF_SEL_FC_CACHE_SECTOR_MISS         = 0x00000052,
13485CB_PERF_SEL_FC_CACHE_REEVICTION_STALL    = 0x00000053,
13486CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000054,
13487CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000055,
13488CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000056,
13489CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL   = 0x00000057,
13490CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL  = 0x00000058,
13491CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL    = 0x00000059,
13492CB_PERF_SEL_FC_CACHE_STALL               = 0x0000005a,
13493CB_PERF_SEL_FC_CACHE_FLUSH               = 0x0000005b,
13494CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED        = 0x0000005c,
13495CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED     = 0x0000005d,
13496CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000005e,
13497CB_PERF_SEL_CC_CACHE_HIT                 = 0x0000005f,
13498CB_PERF_SEL_CC_CACHE_TAG_MISS            = 0x00000060,
13499CB_PERF_SEL_CC_CACHE_SECTOR_MISS         = 0x00000061,
13500CB_PERF_SEL_CC_CACHE_REEVICTION_STALL    = 0x00000062,
13501CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x00000063,
13502CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x00000064,
13503CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x00000065,
13504CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL   = 0x00000066,
13505CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL  = 0x00000067,
13506CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL    = 0x00000068,
13507CB_PERF_SEL_CC_CACHE_STALL               = 0x00000069,
13508CB_PERF_SEL_CC_CACHE_FLUSH               = 0x0000006a,
13509CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED        = 0x0000006b,
13510CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED     = 0x0000006c,
13511CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x0000006d,
13512CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION  = 0x0000006e,
13513CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC  = 0x0000006f,
13514CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY     = 0x00000070,
13515CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB    = 0x00000071,
13516CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY    = 0x00000072,
13517CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB   = 0x00000073,
13518CB_PERF_SEL_CM_MC_WRITE_REQUEST          = 0x00000074,
13519CB_PERF_SEL_FC_MC_WRITE_REQUEST          = 0x00000075,
13520CB_PERF_SEL_CC_MC_WRITE_REQUEST          = 0x00000076,
13521CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000077,
13522CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000078,
13523CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000079,
13524CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY     = 0x0000007a,
13525CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB    = 0x0000007b,
13526CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY    = 0x0000007c,
13527CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB   = 0x0000007d,
13528CB_PERF_SEL_CM_MC_READ_REQUEST           = 0x0000007e,
13529CB_PERF_SEL_FC_MC_READ_REQUEST           = 0x0000007f,
13530CB_PERF_SEL_CC_MC_READ_REQUEST           = 0x00000080,
13531CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000081,
13532CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000082,
13533CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT  = 0x00000083,
13534CB_PERF_SEL_CM_TQ_FULL                   = 0x00000084,
13535CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL  = 0x00000085,
13536CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL      = 0x00000086,
13537CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL      = 0x00000087,
13538CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL  = 0x00000088,
13539CB_PERF_SEL_FOP_FMASK_RAW_STALL          = 0x00000089,
13540CB_PERF_SEL_FOP_FMASK_BYPASS_STALL       = 0x0000008a,
13541CB_PERF_SEL_CC_SF_FULL                   = 0x0000008b,
13542CB_PERF_SEL_CC_RB_FULL                   = 0x0000008c,
13543CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL  = 0x0000008d,
13544CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL  = 0x0000008e,
13545CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL     = 0x0000008f,
13546CB_PERF_SEL_EVENT                        = 0x00000090,
13547CB_PERF_SEL_EVENT_CACHE_FLUSH_TS         = 0x00000091,
13548CB_PERF_SEL_EVENT_CONTEXT_DONE           = 0x00000092,
13549CB_PERF_SEL_EVENT_CACHE_FLUSH            = 0x00000093,
13550CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT  = 0x00000094,
13551CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT  = 0x00000095,
13552CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS  = 0x00000096,
13553CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META  = 0x00000097,
13554CB_PERF_SEL_CC_SURFACE_SYNC              = 0x00000098,
13555CB_PERF_SEL_CMASK_READ_DATA_0xC          = 0x00000099,
13556CB_PERF_SEL_CMASK_READ_DATA_0xD          = 0x0000009a,
13557CB_PERF_SEL_CMASK_READ_DATA_0xE          = 0x0000009b,
13558CB_PERF_SEL_CMASK_READ_DATA_0xF          = 0x0000009c,
13559CB_PERF_SEL_CMASK_WRITE_DATA_0xC         = 0x0000009d,
13560CB_PERF_SEL_CMASK_WRITE_DATA_0xD         = 0x0000009e,
13561CB_PERF_SEL_CMASK_WRITE_DATA_0xE         = 0x0000009f,
13562CB_PERF_SEL_CMASK_WRITE_DATA_0xF         = 0x000000a0,
13563CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT      = 0x000000a1,
13564CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT  = 0x000000a2,
13565CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT  = 0x000000a3,
13566CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE  = 0x000000a4,
13567CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE  = 0x000000a5,
13568CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE  = 0x000000a6,
13569CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE  = 0x000000a7,
13570CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE  = 0x000000a8,
13571CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE  = 0x000000a9,
13572CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE  = 0x000000aa,
13573CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE  = 0x000000ab,
13574CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE  = 0x000000ac,
13575CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE  = 0x000000ad,
13576CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE  = 0x000000ae,
13577CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE  = 0x000000af,
13578CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE  = 0x000000b0,
13579CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE  = 0x000000b1,
13580CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE  = 0x000000b2,
13581CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE  = 0x000000b3,
13582CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT        = 0x000000b4,
13583CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS       = 0x000000b5,
13584CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS       = 0x000000b6,
13585CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS       = 0x000000b7,
13586CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS       = 0x000000b8,
13587CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS       = 0x000000b9,
13588CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS       = 0x000000ba,
13589CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT      = 0x000000bb,
13590CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS     = 0x000000bc,
13591CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS     = 0x000000bd,
13592CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS     = 0x000000be,
13593CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS     = 0x000000bf,
13594CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS     = 0x000000c0,
13595CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS     = 0x000000c1,
13596CB_PERF_SEL_QUAD_READS_FRAGMENT_0        = 0x000000c2,
13597CB_PERF_SEL_QUAD_READS_FRAGMENT_1        = 0x000000c3,
13598CB_PERF_SEL_QUAD_READS_FRAGMENT_2        = 0x000000c4,
13599CB_PERF_SEL_QUAD_READS_FRAGMENT_3        = 0x000000c5,
13600CB_PERF_SEL_QUAD_READS_FRAGMENT_4        = 0x000000c6,
13601CB_PERF_SEL_QUAD_READS_FRAGMENT_5        = 0x000000c7,
13602CB_PERF_SEL_QUAD_READS_FRAGMENT_6        = 0x000000c8,
13603CB_PERF_SEL_QUAD_READS_FRAGMENT_7        = 0x000000c9,
13604CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0       = 0x000000ca,
13605CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1       = 0x000000cb,
13606CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2       = 0x000000cc,
13607CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3       = 0x000000cd,
13608CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4       = 0x000000ce,
13609CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5       = 0x000000cf,
13610CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6       = 0x000000d0,
13611CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7       = 0x000000d1,
13612CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST  = 0x000000d2,
13613CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS  = 0x000000d3,
13614CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS  = 0x000000d4,
13615CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED  = 0x000000d5,
13616CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED  = 0x000000d6,
13617CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED  = 0x000000d7,
13618CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST  = 0x000000d8,
13619CB_PERF_SEL_DRAWN_BUSY                   = 0x000000d9,
13620CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY      = 0x000000da,
13621CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY       = 0x000000db,
13622CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY       = 0x000000dc,
13623CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY       = 0x000000dd,
13624CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED  = 0x000000de,
13625CB_PERF_SEL_FC_SEQUENCER_CLEAR           = 0x000000df,
13626CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR  = 0x000000e0,
13627CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS  = 0x000000e1,
13628CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE  = 0x000000e2,
13629CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL     = 0x000000e3,
13630CB_PERF_SEL_FC_DOC_IS_STALLED            = 0x000000e4,
13631CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED     = 0x000000e5,
13632CB_PERF_SEL_FC_DOC_MRTS_COMBINED         = 0x000000e6,
13633CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS        = 0x000000e7,
13634CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT         = 0x000000e8,
13635CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS        = 0x000000e9,
13636CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT         = 0x000000ea,
13637CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL  = 0x000000eb,
13638CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR    = 0x000000ec,
13639CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS   = 0x000000ed,
13640CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS   = 0x000000ee,
13641CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS   = 0x000000ef,
13642CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS  = 0x000000f0,
13643CB_PERF_SEL_FC_DCC_CACHE_HIT             = 0x000000f1,
13644CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS        = 0x000000f2,
13645CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS     = 0x000000f3,
13646CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL  = 0x000000f4,
13647CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL  = 0x000000f5,
13648CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL  = 0x000000f6,
13649CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL  = 0x000000f7,
13650CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL  = 0x000000f8,
13651CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL  = 0x000000f9,
13652CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL  = 0x000000fa,
13653CB_PERF_SEL_FC_DCC_CACHE_STALL           = 0x000000fb,
13654CB_PERF_SEL_FC_DCC_CACHE_FLUSH           = 0x000000fc,
13655CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED    = 0x000000fd,
13656CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED  = 0x000000fe,
13657CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED  = 0x000000ff,
13658CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT     = 0x00000100,
13659CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST      = 0x00000101,
13660CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT  = 0x00000102,
13661CB_PERF_SEL_FC_MC_DCC_READ_REQUEST       = 0x00000103,
13662CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT  = 0x00000104,
13663CB_PERF_SEL_CC_DCC_RDREQ_STALL           = 0x00000105,
13664CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN    = 0x00000106,
13665CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT   = 0x00000107,
13666CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN      = 0x00000108,
13667CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT     = 0x00000109,
13668CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR      = 0x0000010a,
13669CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1  = 0x0000010b,
13670CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2  = 0x0000010c,
13671CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x0000010d,
13672CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1  = 0x0000010e,
13673CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1  = 0x0000010f,
13674CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2  = 0x00000110,
13675CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1  = 0x00000111,
13676CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000112,
13677CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000113,
13678CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1  = 0x00000114,
13679CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2  = 0x00000115,
13680CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2  = 0x00000116,
13681CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2  = 0x00000117,
13682CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000118,
13683CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1  = 0x00000119,
13684CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1  = 0x0000011a,
13685CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2  = 0x0000011b,
13686CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3  = 0x0000011c,
13687CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4  = 0x0000011d,
13688CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1  = 0x0000011e,
13689CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2  = 0x0000011f,
13690CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3  = 0x00000120,
13691CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4  = 0x00000121,
13692CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1  = 0x00000122,
13693CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2  = 0x00000123,
13694CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3  = 0x00000124,
13695CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4  = 0x00000125,
13696CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1  = 0x00000126,
13697CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2  = 0x00000127,
13698CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3  = 0x00000128,
13699CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1  = 0x00000129,
13700CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2  = 0x0000012a,
13701CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3  = 0x0000012b,
13702CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4  = 0x0000012c,
13703CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1  = 0x0000012d,
13704CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2  = 0x0000012e,
13705CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3  = 0x0000012f,
13706CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4  = 0x00000130,
13707CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1  = 0x00000131,
13708CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2  = 0x00000132,
13709CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3  = 0x00000133,
13710CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4  = 0x00000134,
13711CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1  = 0x00000135,
13712CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2  = 0x00000136,
13713CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3  = 0x00000137,
13714CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1  = 0x00000138,
13715CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1  = 0x00000139,
13716CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1  = 0x0000013a,
13717CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1  = 0x0000013b,
13718CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1  = 0x0000013c,
13719CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1  = 0x0000013d,
13720CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1  = 0x0000013e,
13721CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1  = 0x0000013f,
13722CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2  = 0x00000140,
13723CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2  = 0x00000141,
13724CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2  = 0x00000142,
13725CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2  = 0x00000143,
13726CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2  = 0x00000144,
13727CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2  = 0x00000145,
13728CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2  = 0x00000146,
13729CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1  = 0x00000147,
13730CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1  = 0x00000148,
13731CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1  = 0x00000149,
13732CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1  = 0x0000014a,
13733CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2  = 0x0000014b,
13734CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2  = 0x0000014c,
13735CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2  = 0x0000014d,
13736CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2  = 0x0000014e,
13737CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2  = 0x0000014f,
13738CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000150,
13739CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2  = 0x00000151,
13740CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000152,
13741CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000153,
13742CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000154,
13743CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1  = 0x00000155,
13744CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1  = 0x00000156,
13745CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2  = 0x00000157,
13746CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3  = 0x00000158,
13747CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4  = 0x00000159,
13748CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5  = 0x0000015a,
13749CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6  = 0x0000015b,
13750CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0  = 0x0000015c,
13751CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1  = 0x0000015d,
13752CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1  = 0x0000015e,
13753CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2  = 0x0000015f,
13754CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3  = 0x00000160,
13755CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4  = 0x00000161,
13756CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5  = 0x00000162,
13757CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0  = 0x00000163,
13758CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1  = 0x00000164,
13759CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1  = 0x00000165,
13760CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1  = 0x00000166,
13761CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1  = 0x00000167,
13762CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1  = 0x00000168,
13763CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1  = 0x00000169,
13764CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1  = 0x0000016a,
13765CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1  = 0x0000016b,
13766CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1  = 0x0000016c,
13767CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2  = 0x0000016d,
13768CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2  = 0x0000016e,
13769CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2  = 0x0000016f,
13770CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2  = 0x00000170,
13771CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2  = 0x00000171,
13772CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2  = 0x00000172,
13773CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2  = 0x00000173,
13774CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1  = 0x00000174,
13775CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2  = 0x00000175,
13776CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3  = 0x00000176,
13777CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4  = 0x00000177,
13778CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5  = 0x00000178,
13779CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6  = 0x00000179,
13780CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7  = 0x0000017a,
13781CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED  = 0x0000017b,
13782CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1   = 0x0000017c,
13783CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1   = 0x0000017d,
13784CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2   = 0x0000017e,
13785CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3   = 0x0000017f,
13786CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1   = 0x00000180,
13787CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2   = 0x00000181,
13788CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3   = 0x00000182,
13789CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4   = 0x00000183,
13790CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5   = 0x00000184,
13791CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1   = 0x00000185,
13792CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2   = 0x00000186,
13793CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3   = 0x00000187,
13794CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4   = 0x00000188,
13795CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5   = 0x00000189,
13796CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6   = 0x0000018a,
13797CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7   = 0x0000018b,
13798CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH     = 0x0000018c,
13799CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT     = 0x0000018d,
13800CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT    = 0x0000018e,
13801CB_PERF_SEL_RBP_SPLIT_MICROTILE          = 0x0000018f,
13802CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK     = 0x00000190,
13803CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK  = 0x00000191,
13804CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING  = 0x00000192,
13805CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS  = 0x00000193,
13806CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD  = 0x00000194,
13807} CBPerfSel;
13808
13809/*
13810 * CBPerfOpFilterSel enum
13811 */
13812
13813typedef enum CBPerfOpFilterSel {
13814CB_PERF_OP_FILTER_SEL_WRITE_ONLY         = 0x00000000,
13815CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION  = 0x00000001,
13816CB_PERF_OP_FILTER_SEL_RESOLVE            = 0x00000002,
13817CB_PERF_OP_FILTER_SEL_DECOMPRESS         = 0x00000003,
13818CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS   = 0x00000004,
13819CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR  = 0x00000005,
13820} CBPerfOpFilterSel;
13821
13822/*
13823 * CBPerfClearFilterSel enum
13824 */
13825
13826typedef enum CBPerfClearFilterSel {
13827CB_PERF_CLEAR_FILTER_SEL_NONCLEAR        = 0x00000000,
13828CB_PERF_CLEAR_FILTER_SEL_CLEAR           = 0x00000001,
13829} CBPerfClearFilterSel;
13830
13831/*******************************************************
13832 * TC Enums
13833 *******************************************************/
13834
13835/*
13836 * TC_OP_MASKS enum
13837 */
13838
13839typedef enum TC_OP_MASKS {
13840TC_OP_MASK_FLUSH_DENROM                  = 0x00000008,
13841TC_OP_MASK_64                            = 0x00000020,
13842TC_OP_MASK_NO_RTN                        = 0x00000040,
13843} TC_OP_MASKS;
13844
13845/*
13846 * TC_OP enum
13847 */
13848
13849typedef enum TC_OP {
13850TC_OP_READ                               = 0x00000000,
13851TC_OP_ATOMIC_FCMPSWAP_RTN_32             = 0x00000001,
13852TC_OP_ATOMIC_FMIN_RTN_32                 = 0x00000002,
13853TC_OP_ATOMIC_FMAX_RTN_32                 = 0x00000003,
13854TC_OP_RESERVED_FOP_RTN_32_0              = 0x00000004,
13855TC_OP_RESERVED_FOP_RTN_32_1              = 0x00000005,
13856TC_OP_RESERVED_FOP_RTN_32_2              = 0x00000006,
13857TC_OP_ATOMIC_SWAP_RTN_32                 = 0x00000007,
13858TC_OP_ATOMIC_CMPSWAP_RTN_32              = 0x00000008,
13859TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32  = 0x00000009,
13860TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32    = 0x0000000a,
13861TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32    = 0x0000000b,
13862TC_OP_PROBE_FILTER                       = 0x0000000c,
13863TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1  = 0x0000000d,
13864TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2  = 0x0000000e,
13865TC_OP_ATOMIC_ADD_RTN_32                  = 0x0000000f,
13866TC_OP_ATOMIC_SUB_RTN_32                  = 0x00000010,
13867TC_OP_ATOMIC_SMIN_RTN_32                 = 0x00000011,
13868TC_OP_ATOMIC_UMIN_RTN_32                 = 0x00000012,
13869TC_OP_ATOMIC_SMAX_RTN_32                 = 0x00000013,
13870TC_OP_ATOMIC_UMAX_RTN_32                 = 0x00000014,
13871TC_OP_ATOMIC_AND_RTN_32                  = 0x00000015,
13872TC_OP_ATOMIC_OR_RTN_32                   = 0x00000016,
13873TC_OP_ATOMIC_XOR_RTN_32                  = 0x00000017,
13874TC_OP_ATOMIC_INC_RTN_32                  = 0x00000018,
13875TC_OP_ATOMIC_DEC_RTN_32                  = 0x00000019,
13876TC_OP_WBINVL1_VOL                        = 0x0000001a,
13877TC_OP_WBINVL1_SD                         = 0x0000001b,
13878TC_OP_RESERVED_NON_FLOAT_RTN_32_0        = 0x0000001c,
13879TC_OP_RESERVED_NON_FLOAT_RTN_32_1        = 0x0000001d,
13880TC_OP_RESERVED_NON_FLOAT_RTN_32_2        = 0x0000001e,
13881TC_OP_RESERVED_NON_FLOAT_RTN_32_3        = 0x0000001f,
13882TC_OP_WRITE                              = 0x00000020,
13883TC_OP_ATOMIC_FCMPSWAP_RTN_64             = 0x00000021,
13884TC_OP_ATOMIC_FMIN_RTN_64                 = 0x00000022,
13885TC_OP_ATOMIC_FMAX_RTN_64                 = 0x00000023,
13886TC_OP_RESERVED_FOP_RTN_64_0              = 0x00000024,
13887TC_OP_RESERVED_FOP_RTN_64_1              = 0x00000025,
13888TC_OP_RESERVED_FOP_RTN_64_2              = 0x00000026,
13889TC_OP_ATOMIC_SWAP_RTN_64                 = 0x00000027,
13890TC_OP_ATOMIC_CMPSWAP_RTN_64              = 0x00000028,
13891TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64  = 0x00000029,
13892TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64    = 0x0000002a,
13893TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64    = 0x0000002b,
13894TC_OP_WBINVL2_SD                         = 0x0000002c,
13895TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0  = 0x0000002d,
13896TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1  = 0x0000002e,
13897TC_OP_ATOMIC_ADD_RTN_64                  = 0x0000002f,
13898TC_OP_ATOMIC_SUB_RTN_64                  = 0x00000030,
13899TC_OP_ATOMIC_SMIN_RTN_64                 = 0x00000031,
13900TC_OP_ATOMIC_UMIN_RTN_64                 = 0x00000032,
13901TC_OP_ATOMIC_SMAX_RTN_64                 = 0x00000033,
13902TC_OP_ATOMIC_UMAX_RTN_64                 = 0x00000034,
13903TC_OP_ATOMIC_AND_RTN_64                  = 0x00000035,
13904TC_OP_ATOMIC_OR_RTN_64                   = 0x00000036,
13905TC_OP_ATOMIC_XOR_RTN_64                  = 0x00000037,
13906TC_OP_ATOMIC_INC_RTN_64                  = 0x00000038,
13907TC_OP_ATOMIC_DEC_RTN_64                  = 0x00000039,
13908TC_OP_WBL2_NC                            = 0x0000003a,
13909TC_OP_WBL2_WC                            = 0x0000003b,
13910TC_OP_RESERVED_NON_FLOAT_RTN_64_1        = 0x0000003c,
13911TC_OP_RESERVED_NON_FLOAT_RTN_64_2        = 0x0000003d,
13912TC_OP_RESERVED_NON_FLOAT_RTN_64_3        = 0x0000003e,
13913TC_OP_RESERVED_NON_FLOAT_RTN_64_4        = 0x0000003f,
13914TC_OP_WBINVL1                            = 0x00000040,
13915TC_OP_ATOMIC_FCMPSWAP_32                 = 0x00000041,
13916TC_OP_ATOMIC_FMIN_32                     = 0x00000042,
13917TC_OP_ATOMIC_FMAX_32                     = 0x00000043,
13918TC_OP_RESERVED_FOP_32_0                  = 0x00000044,
13919TC_OP_RESERVED_FOP_32_1                  = 0x00000045,
13920TC_OP_RESERVED_FOP_32_2                  = 0x00000046,
13921TC_OP_ATOMIC_SWAP_32                     = 0x00000047,
13922TC_OP_ATOMIC_CMPSWAP_32                  = 0x00000048,
13923TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32    = 0x00000049,
13924TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32        = 0x0000004a,
13925TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32        = 0x0000004b,
13926TC_OP_INV_METADATA                       = 0x0000004c,
13927TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1     = 0x0000004d,
13928TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2     = 0x0000004e,
13929TC_OP_ATOMIC_ADD_32                      = 0x0000004f,
13930TC_OP_ATOMIC_SUB_32                      = 0x00000050,
13931TC_OP_ATOMIC_SMIN_32                     = 0x00000051,
13932TC_OP_ATOMIC_UMIN_32                     = 0x00000052,
13933TC_OP_ATOMIC_SMAX_32                     = 0x00000053,
13934TC_OP_ATOMIC_UMAX_32                     = 0x00000054,
13935TC_OP_ATOMIC_AND_32                      = 0x00000055,
13936TC_OP_ATOMIC_OR_32                       = 0x00000056,
13937TC_OP_ATOMIC_XOR_32                      = 0x00000057,
13938TC_OP_ATOMIC_INC_32                      = 0x00000058,
13939TC_OP_ATOMIC_DEC_32                      = 0x00000059,
13940TC_OP_INVL2_NC                           = 0x0000005a,
13941TC_OP_NOP_RTN0                           = 0x0000005b,
13942TC_OP_RESERVED_NON_FLOAT_32_1            = 0x0000005c,
13943TC_OP_RESERVED_NON_FLOAT_32_2            = 0x0000005d,
13944TC_OP_RESERVED_NON_FLOAT_32_3            = 0x0000005e,
13945TC_OP_RESERVED_NON_FLOAT_32_4            = 0x0000005f,
13946TC_OP_WBINVL2                            = 0x00000060,
13947TC_OP_ATOMIC_FCMPSWAP_64                 = 0x00000061,
13948TC_OP_ATOMIC_FMIN_64                     = 0x00000062,
13949TC_OP_ATOMIC_FMAX_64                     = 0x00000063,
13950TC_OP_RESERVED_FOP_64_0                  = 0x00000064,
13951TC_OP_RESERVED_FOP_64_1                  = 0x00000065,
13952TC_OP_RESERVED_FOP_64_2                  = 0x00000066,
13953TC_OP_ATOMIC_SWAP_64                     = 0x00000067,
13954TC_OP_ATOMIC_CMPSWAP_64                  = 0x00000068,
13955TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64    = 0x00000069,
13956TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64        = 0x0000006a,
13957TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64        = 0x0000006b,
13958TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0     = 0x0000006c,
13959TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1     = 0x0000006d,
13960TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2     = 0x0000006e,
13961TC_OP_ATOMIC_ADD_64                      = 0x0000006f,
13962TC_OP_ATOMIC_SUB_64                      = 0x00000070,
13963TC_OP_ATOMIC_SMIN_64                     = 0x00000071,
13964TC_OP_ATOMIC_UMIN_64                     = 0x00000072,
13965TC_OP_ATOMIC_SMAX_64                     = 0x00000073,
13966TC_OP_ATOMIC_UMAX_64                     = 0x00000074,
13967TC_OP_ATOMIC_AND_64                      = 0x00000075,
13968TC_OP_ATOMIC_OR_64                       = 0x00000076,
13969TC_OP_ATOMIC_XOR_64                      = 0x00000077,
13970TC_OP_ATOMIC_INC_64                      = 0x00000078,
13971TC_OP_ATOMIC_DEC_64                      = 0x00000079,
13972TC_OP_WBINVL2_NC                         = 0x0000007a,
13973TC_OP_NOP_ACK                            = 0x0000007b,
13974TC_OP_RESERVED_NON_FLOAT_64_1            = 0x0000007c,
13975TC_OP_RESERVED_NON_FLOAT_64_2            = 0x0000007d,
13976TC_OP_RESERVED_NON_FLOAT_64_3            = 0x0000007e,
13977TC_OP_RESERVED_NON_FLOAT_64_4            = 0x0000007f,
13978} TC_OP;
13979
13980/*
13981 * TC_CHUB_REQ_CREDITS_ENUM enum
13982 */
13983
13984typedef enum TC_CHUB_REQ_CREDITS_ENUM {
13985TC_CHUB_REQ_CREDITS                      = 0x00000010,
13986} TC_CHUB_REQ_CREDITS_ENUM;
13987
13988/*
13989 * CHUB_TC_RET_CREDITS_ENUM enum
13990 */
13991
13992typedef enum CHUB_TC_RET_CREDITS_ENUM {
13993CHUB_TC_RET_CREDITS                      = 0x00000020,
13994} CHUB_TC_RET_CREDITS_ENUM;
13995
13996/*
13997 * TC_NACKS enum
13998 */
13999
14000typedef enum TC_NACKS {

14001TC_NACK_NO_FAULT                         = 0x00000000,
14002TC_NACK_PAGE_FAULT                       = 0x00000001,
14003TC_NACK_PROTECTION_FAULT                 = 0x00000002,
14004TC_NACK_DATA_ERROR                       = 0x00000003,
14005} TC_NACKS;
14006
14007/*
14008 * TC_EA_CID enum
14009 */
14010
14011typedef enum TC_EA_CID {
14012TC_EA_CID_RT                             = 0x00000000,
14013TC_EA_CID_FMASK                          = 0x00000001,
14014TC_EA_CID_DCC                            = 0x00000002,
14015TC_EA_CID_TCPMETA                        = 0x00000003,
14016TC_EA_CID_Z                              = 0x00000004,
14017TC_EA_CID_STENCIL                        = 0x00000005,
14018TC_EA_CID_HTILE                          = 0x00000006,
14019TC_EA_CID_MISC                           = 0x00000007,
14020TC_EA_CID_TCP                            = 0x00000008,
14021TC_EA_CID_SQC                            = 0x00000009,
14022TC_EA_CID_CPF                            = 0x0000000a,
14023TC_EA_CID_CPG                            = 0x0000000b,
14024TC_EA_CID_IA                             = 0x0000000c,
14025TC_EA_CID_WD                             = 0x0000000d,
14026TC_EA_CID_PA                             = 0x0000000e,
14027TC_EA_CID_UTCL2_TPI                      = 0x0000000f,
14028} TC_EA_CID;
14029
14030/*******************************************************
14031 * SPI Enums
14032 *******************************************************/
14033
14034/*
14035 * SPI_SAMPLE_CNTL enum
14036 */
14037
14038typedef enum SPI_SAMPLE_CNTL {
14039CENTROIDS_ONLY                           = 0x00000000,
14040CENTERS_ONLY                             = 0x00000001,
14041CENTROIDS_AND_CENTERS                    = 0x00000002,
14042UNDEF                                    = 0x00000003,
14043} SPI_SAMPLE_CNTL;
14044
14045/*
14046 * SPI_FOG_MODE enum
14047 */
14048
14049typedef enum SPI_FOG_MODE {
14050SPI_FOG_NONE                             = 0x00000000,
14051SPI_FOG_EXP                              = 0x00000001,
14052SPI_FOG_EXP2                             = 0x00000002,
14053SPI_FOG_LINEAR                           = 0x00000003,
14054} SPI_FOG_MODE;
14055
14056/*
14057 * SPI_PNT_SPRITE_OVERRIDE enum
14058 */
14059
14060typedef enum SPI_PNT_SPRITE_OVERRIDE {
14061SPI_PNT_SPRITE_SEL_0                     = 0x00000000,
14062SPI_PNT_SPRITE_SEL_1                     = 0x00000001,
14063SPI_PNT_SPRITE_SEL_S                     = 0x00000002,
14064SPI_PNT_SPRITE_SEL_T                     = 0x00000003,
14065SPI_PNT_SPRITE_SEL_NONE                  = 0x00000004,
14066} SPI_PNT_SPRITE_OVERRIDE;
14067
14068/*
14069 * SPI_PERFCNT_SEL enum
14070 */
14071
14072typedef enum SPI_PERFCNT_SEL {
14073SPI_PERF_VS_WINDOW_VALID                 = 0x00000000,
14074SPI_PERF_VS_BUSY                         = 0x00000001,
14075SPI_PERF_VS_FIRST_WAVE                   = 0x00000002,
14076SPI_PERF_VS_LAST_WAVE                    = 0x00000003,
14077SPI_PERF_VS_LSHS_DEALLOC                 = 0x00000004,
14078SPI_PERF_VS_PC_STALL                     = 0x00000005,
14079SPI_PERF_VS_POS0_STALL                   = 0x00000006,
14080SPI_PERF_VS_POS1_STALL                   = 0x00000007,
14081SPI_PERF_VS_CRAWLER_STALL                = 0x00000008,
14082SPI_PERF_VS_EVENT_WAVE                   = 0x00000009,
14083SPI_PERF_VS_WAVE                         = 0x0000000a,
14084SPI_PERF_VS_PERS_UPD_FULL0               = 0x0000000b,
14085SPI_PERF_VS_PERS_UPD_FULL1               = 0x0000000c,
14086SPI_PERF_VS_LATE_ALLOC_FULL              = 0x0000000d,
14087SPI_PERF_VS_FIRST_SUBGRP                 = 0x0000000e,
14088SPI_PERF_VS_LAST_SUBGRP                  = 0x0000000f,
14089SPI_PERF_GS_WINDOW_VALID                 = 0x00000010,
14090SPI_PERF_GS_BUSY                         = 0x00000011,
14091SPI_PERF_GS_CRAWLER_STALL                = 0x00000012,
14092SPI_PERF_GS_EVENT_WAVE                   = 0x00000013,
14093SPI_PERF_GS_WAVE                         = 0x00000014,
14094SPI_PERF_GS_PERS_UPD_FULL0               = 0x00000015,
14095SPI_PERF_GS_PERS_UPD_FULL1               = 0x00000016,
14096SPI_PERF_GS_FIRST_SUBGRP                 = 0x00000017,
14097SPI_PERF_GS_LAST_SUBGRP                  = 0x00000018,
14098SPI_PERF_ES_WINDOW_VALID                 = 0x00000019,
14099SPI_PERF_ES_BUSY                         = 0x0000001a,
14100SPI_PERF_ES_CRAWLER_STALL                = 0x0000001b,
14101SPI_PERF_ES_FIRST_WAVE                   = 0x0000001c,
14102SPI_PERF_ES_LAST_WAVE                    = 0x0000001d,
14103SPI_PERF_ES_LSHS_DEALLOC                 = 0x0000001e,
14104SPI_PERF_ES_EVENT_WAVE                   = 0x0000001f,
14105SPI_PERF_ES_WAVE                         = 0x00000020,
14106SPI_PERF_ES_PERS_UPD_FULL0               = 0x00000021,
14107SPI_PERF_ES_PERS_UPD_FULL1               = 0x00000022,
14108SPI_PERF_ES_FIRST_SUBGRP                 = 0x00000023,
14109SPI_PERF_ES_LAST_SUBGRP                  = 0x00000024,
14110SPI_PERF_HS_WINDOW_VALID                 = 0x00000025,
14111SPI_PERF_HS_BUSY                         = 0x00000026,
14112SPI_PERF_HS_CRAWLER_STALL                = 0x00000027,
14113SPI_PERF_HS_FIRST_WAVE                   = 0x00000028,
14114SPI_PERF_HS_LAST_WAVE                    = 0x00000029,
14115SPI_PERF_HS_LSHS_DEALLOC                 = 0x0000002a,
14116SPI_PERF_HS_EVENT_WAVE                   = 0x0000002b,
14117SPI_PERF_HS_WAVE                         = 0x0000002c,
14118SPI_PERF_HS_PERS_UPD_FULL0               = 0x0000002d,
14119SPI_PERF_HS_PERS_UPD_FULL1               = 0x0000002e,
14120SPI_PERF_LS_WINDOW_VALID                 = 0x0000002f,
14121SPI_PERF_LS_BUSY                         = 0x00000030,
14122SPI_PERF_LS_CRAWLER_STALL                = 0x00000031,
14123SPI_PERF_LS_FIRST_WAVE                   = 0x00000032,
14124SPI_PERF_LS_LAST_WAVE                    = 0x00000033,
14125SPI_PERF_OFFCHIP_LDS_STALL_LS            = 0x00000034,
14126SPI_PERF_LS_EVENT_WAVE                   = 0x00000035,
14127SPI_PERF_LS_WAVE                         = 0x00000036,
14128SPI_PERF_LS_PERS_UPD_FULL0               = 0x00000037,
14129SPI_PERF_LS_PERS_UPD_FULL1               = 0x00000038,
14130SPI_PERF_CSG_WINDOW_VALID                = 0x00000039,
14131SPI_PERF_CSG_BUSY                        = 0x0000003a,
14132SPI_PERF_CSG_NUM_THREADGROUPS            = 0x0000003b,
14133SPI_PERF_CSG_CRAWLER_STALL               = 0x0000003c,
14134SPI_PERF_CSG_EVENT_WAVE                  = 0x0000003d,
14135SPI_PERF_CSG_WAVE                        = 0x0000003e,
14136SPI_PERF_CSN_WINDOW_VALID                = 0x0000003f,
14137SPI_PERF_CSN_BUSY                        = 0x00000040,
14138SPI_PERF_CSN_NUM_THREADGROUPS            = 0x00000041,
14139SPI_PERF_CSN_CRAWLER_STALL               = 0x00000042,
14140SPI_PERF_CSN_EVENT_WAVE                  = 0x00000043,
14141SPI_PERF_CSN_WAVE                        = 0x00000044,
14142SPI_PERF_PS_CTL_WINDOW_VALID             = 0x00000045,
14143SPI_PERF_PS_CTL_BUSY                     = 0x00000046,
14144SPI_PERF_PS_CTL_ACTIVE                   = 0x00000047,
14145SPI_PERF_PS_CTL_DEALLOC_BIN0             = 0x00000048,
14146SPI_PERF_PS_CTL_FPOS_BIN1_STALL          = 0x00000049,
14147SPI_PERF_PS_CTL_EVENT_WAVE               = 0x0000004a,
14148SPI_PERF_PS_CTL_WAVE                     = 0x0000004b,
14149SPI_PERF_PS_CTL_OPT_WAVE                 = 0x0000004c,
14150SPI_PERF_PS_CTL_PASS_BIN0                = 0x0000004d,
14151SPI_PERF_PS_CTL_PASS_BIN1                = 0x0000004e,
14152SPI_PERF_PS_CTL_FPOS_BIN2                = 0x0000004f,
14153SPI_PERF_PS_CTL_PRIM_BIN0                = 0x00000050,
14154SPI_PERF_PS_CTL_PRIM_BIN1                = 0x00000051,
14155SPI_PERF_PS_CTL_CNF_BIN2                 = 0x00000052,
14156SPI_PERF_PS_CTL_CNF_BIN3                 = 0x00000053,
14157SPI_PERF_PS_CTL_CRAWLER_STALL            = 0x00000054,
14158SPI_PERF_PS_CTL_LDS_RES_FULL             = 0x00000055,
14159SPI_PERF_PS_PERS_UPD_FULL0               = 0x00000056,
14160SPI_PERF_PS_PERS_UPD_FULL1               = 0x00000057,
14161SPI_PERF_PIX_ALLOC_PEND_CNT              = 0x00000058,
14162SPI_PERF_PIX_ALLOC_SCB_STALL             = 0x00000059,
14163SPI_PERF_PIX_ALLOC_DB0_STALL             = 0x0000005a,
14164SPI_PERF_PIX_ALLOC_DB1_STALL             = 0x0000005b,
14165SPI_PERF_PIX_ALLOC_DB2_STALL             = 0x0000005c,
14166SPI_PERF_PIX_ALLOC_DB3_STALL             = 0x0000005d,
14167SPI_PERF_LDS0_PC_VALID                   = 0x0000005e,
14168SPI_PERF_LDS1_PC_VALID                   = 0x0000005f,
14169SPI_PERF_RA_PIPE_REQ_BIN2                = 0x00000060,
14170SPI_PERF_RA_TASK_REQ_BIN3                = 0x00000061,
14171SPI_PERF_RA_WR_CTL_FULL                  = 0x00000062,
14172SPI_PERF_RA_REQ_NO_ALLOC                 = 0x00000063,
14173SPI_PERF_RA_REQ_NO_ALLOC_PS              = 0x00000064,
14174SPI_PERF_RA_REQ_NO_ALLOC_VS              = 0x00000065,
14175SPI_PERF_RA_REQ_NO_ALLOC_GS              = 0x00000066,
14176SPI_PERF_RA_REQ_NO_ALLOC_ES              = 0x00000067,
14177SPI_PERF_RA_REQ_NO_ALLOC_HS              = 0x00000068,
14178SPI_PERF_RA_REQ_NO_ALLOC_LS              = 0x00000069,
14179SPI_PERF_RA_REQ_NO_ALLOC_CSG             = 0x0000006a,
14180SPI_PERF_RA_REQ_NO_ALLOC_CSN             = 0x0000006b,
14181SPI_PERF_RA_RES_STALL_PS                 = 0x0000006c,
14182SPI_PERF_RA_RES_STALL_VS                 = 0x0000006d,
14183SPI_PERF_RA_RES_STALL_GS                 = 0x0000006e,
14184SPI_PERF_RA_RES_STALL_ES                 = 0x0000006f,
14185SPI_PERF_RA_RES_STALL_HS                 = 0x00000070,
14186SPI_PERF_RA_RES_STALL_LS                 = 0x00000071,
14187SPI_PERF_RA_RES_STALL_CSG                = 0x00000072,
14188SPI_PERF_RA_RES_STALL_CSN                = 0x00000073,
14189SPI_PERF_RA_TMP_STALL_PS                 = 0x00000074,
14190SPI_PERF_RA_TMP_STALL_VS                 = 0x00000075,
14191SPI_PERF_RA_TMP_STALL_GS                 = 0x00000076,
14192SPI_PERF_RA_TMP_STALL_ES                 = 0x00000077,
14193SPI_PERF_RA_TMP_STALL_HS                 = 0x00000078,
14194SPI_PERF_RA_TMP_STALL_LS                 = 0x00000079,
14195SPI_PERF_RA_TMP_STALL_CSG                = 0x0000007a,
14196SPI_PERF_RA_TMP_STALL_CSN                = 0x0000007b,
14197SPI_PERF_RA_WAVE_SIMD_FULL_PS            = 0x0000007c,
14198SPI_PERF_RA_WAVE_SIMD_FULL_VS            = 0x0000007d,
14199SPI_PERF_RA_WAVE_SIMD_FULL_GS            = 0x0000007e,
14200SPI_PERF_RA_WAVE_SIMD_FULL_ES            = 0x0000007f,
14201SPI_PERF_RA_WAVE_SIMD_FULL_HS            = 0x00000080,
14202SPI_PERF_RA_WAVE_SIMD_FULL_LS            = 0x00000081,
14203SPI_PERF_RA_WAVE_SIMD_FULL_CSG           = 0x00000082,
14204SPI_PERF_RA_WAVE_SIMD_FULL_CSN           = 0x00000083,
14205SPI_PERF_RA_VGPR_SIMD_FULL_PS            = 0x00000084,
14206SPI_PERF_RA_VGPR_SIMD_FULL_VS            = 0x00000085,
14207SPI_PERF_RA_VGPR_SIMD_FULL_GS            = 0x00000086,
14208SPI_PERF_RA_VGPR_SIMD_FULL_ES            = 0x00000087,
14209SPI_PERF_RA_VGPR_SIMD_FULL_HS            = 0x00000088,
14210SPI_PERF_RA_VGPR_SIMD_FULL_LS            = 0x00000089,
14211SPI_PERF_RA_VGPR_SIMD_FULL_CSG           = 0x0000008a,
14212SPI_PERF_RA_VGPR_SIMD_FULL_CSN           = 0x0000008b,
14213SPI_PERF_RA_SGPR_SIMD_FULL_PS            = 0x0000008c,
14214SPI_PERF_RA_SGPR_SIMD_FULL_VS            = 0x0000008d,
14215SPI_PERF_RA_SGPR_SIMD_FULL_GS            = 0x0000008e,
14216SPI_PERF_RA_SGPR_SIMD_FULL_ES            = 0x0000008f,
14217SPI_PERF_RA_SGPR_SIMD_FULL_HS            = 0x00000090,
14218SPI_PERF_RA_SGPR_SIMD_FULL_LS            = 0x00000091,
14219SPI_PERF_RA_SGPR_SIMD_FULL_CSG           = 0x00000092,
14220SPI_PERF_RA_SGPR_SIMD_FULL_CSN           = 0x00000093,
14221SPI_PERF_RA_LDS_CU_FULL_PS               = 0x00000094,
14222SPI_PERF_RA_LDS_CU_FULL_LS               = 0x00000095,
14223SPI_PERF_RA_LDS_CU_FULL_ES               = 0x00000096,
14224SPI_PERF_RA_LDS_CU_FULL_CSG              = 0x00000097,
14225SPI_PERF_RA_LDS_CU_FULL_CSN              = 0x00000098,
14226SPI_PERF_RA_BAR_CU_FULL_HS               = 0x00000099,
14227SPI_PERF_RA_BAR_CU_FULL_CSG              = 0x0000009a,
14228SPI_PERF_RA_BAR_CU_FULL_CSN              = 0x0000009b,
14229SPI_PERF_RA_BULKY_CU_FULL_CSG            = 0x0000009c,
14230SPI_PERF_RA_BULKY_CU_FULL_CSN            = 0x0000009d,
14231SPI_PERF_RA_TGLIM_CU_FULL_CSG            = 0x0000009e,
14232SPI_PERF_RA_TGLIM_CU_FULL_CSN            = 0x0000009f,
14233SPI_PERF_RA_WVLIM_STALL_PS               = 0x000000a0,
14234SPI_PERF_RA_WVLIM_STALL_VS               = 0x000000a1,
14235SPI_PERF_RA_WVLIM_STALL_GS               = 0x000000a2,
14236SPI_PERF_RA_WVLIM_STALL_ES               = 0x000000a3,
14237SPI_PERF_RA_WVLIM_STALL_HS               = 0x000000a4,
14238SPI_PERF_RA_WVLIM_STALL_LS               = 0x000000a5,
14239SPI_PERF_RA_WVLIM_STALL_CSG              = 0x000000a6,
14240SPI_PERF_RA_WVLIM_STALL_CSN              = 0x000000a7,
14241SPI_PERF_RA_PS_LOCK_NA                   = 0x000000a8,
14242SPI_PERF_RA_VS_LOCK                      = 0x000000a9,
14243SPI_PERF_RA_GS_LOCK                      = 0x000000aa,
14244SPI_PERF_RA_ES_LOCK                      = 0x000000ab,
14245SPI_PERF_RA_HS_LOCK                      = 0x000000ac,
14246SPI_PERF_RA_LS_LOCK                      = 0x000000ad,
14247SPI_PERF_RA_CSG_LOCK                     = 0x000000ae,
14248SPI_PERF_RA_CSN_LOCK                     = 0x000000af,
14249SPI_PERF_RA_RSV_UPD                      = 0x000000b0,
14250SPI_PERF_EXP_ARB_COL_CNT                 = 0x000000b1,
14251SPI_PERF_EXP_ARB_PAR_CNT                 = 0x000000b2,
14252SPI_PERF_EXP_ARB_POS_CNT                 = 0x000000b3,
14253SPI_PERF_EXP_ARB_GDS_CNT                 = 0x000000b4,
14254SPI_PERF_CLKGATE_BUSY_STALL              = 0x000000b5,
14255SPI_PERF_CLKGATE_ACTIVE_STALL            = 0x000000b6,
14256SPI_PERF_CLKGATE_ALL_CLOCKS_ON           = 0x000000b7,
14257SPI_PERF_CLKGATE_CGTT_DYN_ON             = 0x000000b8,
14258SPI_PERF_CLKGATE_CGTT_REG_ON             = 0x000000b9,
14259SPI_PERF_NUM_VS_POS_EXPORTS              = 0x000000ba,
14260SPI_PERF_NUM_VS_PARAM_EXPORTS            = 0x000000bb,
14261SPI_PERF_NUM_PS_COL_EXPORTS              = 0x000000bc,
14262SPI_PERF_ES_GRP_FIFO_FULL                = 0x000000bd,
14263SPI_PERF_GS_GRP_FIFO_FULL                = 0x000000be,
14264SPI_PERF_HS_GRP_FIFO_FULL                = 0x000000bf,
14265SPI_PERF_LS_GRP_FIFO_FULL                = 0x000000c0,
14266SPI_PERF_VS_ALLOC_CNT                    = 0x000000c1,
14267SPI_PERF_VS_LATE_ALLOC_ACCUM             = 0x000000c2,
14268SPI_PERF_PC_ALLOC_CNT                    = 0x000000c3,
14269SPI_PERF_PC_ALLOC_ACCUM                  = 0x000000c4,
14270} SPI_PERFCNT_SEL;
14271
14272/*
14273 * SPI_SHADER_FORMAT enum
14274 */
14275
14276typedef enum SPI_SHADER_FORMAT {
14277SPI_SHADER_NONE                          = 0x00000000,
14278SPI_SHADER_1COMP                         = 0x00000001,
14279SPI_SHADER_2COMP                         = 0x00000002,
14280SPI_SHADER_4COMPRESS                     = 0x00000003,
14281SPI_SHADER_4COMP                         = 0x00000004,
14282} SPI_SHADER_FORMAT;
14283
14284/*
14285 * SPI_SHADER_EX_FORMAT enum
14286 */
14287
14288typedef enum SPI_SHADER_EX_FORMAT {
14289SPI_SHADER_ZERO                          = 0x00000000,
14290SPI_SHADER_32_R                          = 0x00000001,
14291SPI_SHADER_32_GR                         = 0x00000002,
14292SPI_SHADER_32_AR                         = 0x00000003,
14293SPI_SHADER_FP16_ABGR                     = 0x00000004,
14294SPI_SHADER_UNORM16_ABGR                  = 0x00000005,
14295SPI_SHADER_SNORM16_ABGR                  = 0x00000006,
14296SPI_SHADER_UINT16_ABGR                   = 0x00000007,
14297SPI_SHADER_SINT16_ABGR                   = 0x00000008,
14298SPI_SHADER_32_ABGR                       = 0x00000009,
14299} SPI_SHADER_EX_FORMAT;
14300
14301/*
14302 * CLKGATE_SM_MODE enum
14303 */
14304
14305typedef enum CLKGATE_SM_MODE {
14306ON_SEQ                                   = 0x00000000,
14307OFF_SEQ                                  = 0x00000001,
14308PROG_SEQ                                 = 0x00000002,
14309READ_SEQ                                 = 0x00000003,
14310SM_MODE_RESERVED                         = 0x00000004,
14311} CLKGATE_SM_MODE;
14312
14313/*
14314 * CLKGATE_BASE_MODE enum
14315 */
14316
14317typedef enum CLKGATE_BASE_MODE {
14318MULT_8                                   = 0x00000000,
14319MULT_16                                  = 0x00000001,
14320} CLKGATE_BASE_MODE;
14321
14322/*******************************************************
14323 * SQ Enums
14324 *******************************************************/
14325
14326/*
14327 * SQ_TEX_CLAMP enum
14328 */
14329
14330typedef enum SQ_TEX_CLAMP {
14331SQ_TEX_WRAP                              = 0x00000000,
14332SQ_TEX_MIRROR                            = 0x00000001,
14333SQ_TEX_CLAMP_LAST_TEXEL                  = 0x00000002,
14334SQ_TEX_MIRROR_ONCE_LAST_TEXEL            = 0x00000003,
14335SQ_TEX_CLAMP_HALF_BORDER                 = 0x00000004,
14336SQ_TEX_MIRROR_ONCE_HALF_BORDER           = 0x00000005,
14337SQ_TEX_CLAMP_BORDER                      = 0x00000006,
14338SQ_TEX_MIRROR_ONCE_BORDER                = 0x00000007,
14339} SQ_TEX_CLAMP;
14340
14341/*
14342 * SQ_TEX_XY_FILTER enum
14343 */
14344
14345typedef enum SQ_TEX_XY_FILTER {
14346SQ_TEX_XY_FILTER_POINT                   = 0x00000000,
14347SQ_TEX_XY_FILTER_BILINEAR                = 0x00000001,
14348SQ_TEX_XY_FILTER_ANISO_POINT             = 0x00000002,
14349SQ_TEX_XY_FILTER_ANISO_BILINEAR          = 0x00000003,
14350} SQ_TEX_XY_FILTER;
14351
14352/*
14353 * SQ_TEX_Z_FILTER enum
14354 */
14355
14356typedef enum SQ_TEX_Z_FILTER {
14357SQ_TEX_Z_FILTER_NONE                     = 0x00000000,
14358SQ_TEX_Z_FILTER_POINT                    = 0x00000001,
14359SQ_TEX_Z_FILTER_LINEAR                   = 0x00000002,
14360} SQ_TEX_Z_FILTER;
14361
14362/*
14363 * SQ_TEX_MIP_FILTER enum
14364 */
14365
14366typedef enum SQ_TEX_MIP_FILTER {
14367SQ_TEX_MIP_FILTER_NONE                   = 0x00000000,
14368SQ_TEX_MIP_FILTER_POINT                  = 0x00000001,
14369SQ_TEX_MIP_FILTER_LINEAR                 = 0x00000002,
14370SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ        = 0x00000003,
14371} SQ_TEX_MIP_FILTER;
14372
14373/*
14374 * SQ_TEX_ANISO_RATIO enum
14375 */
14376
14377typedef enum SQ_TEX_ANISO_RATIO {
14378SQ_TEX_ANISO_RATIO_1                     = 0x00000000,
14379SQ_TEX_ANISO_RATIO_2                     = 0x00000001,
14380SQ_TEX_ANISO_RATIO_4                     = 0x00000002,
14381SQ_TEX_ANISO_RATIO_8                     = 0x00000003,
14382SQ_TEX_ANISO_RATIO_16                    = 0x00000004,
14383} SQ_TEX_ANISO_RATIO;
14384
14385/*
14386 * SQ_TEX_DEPTH_COMPARE enum
14387 */
14388
14389typedef enum SQ_TEX_DEPTH_COMPARE {
14390SQ_TEX_DEPTH_COMPARE_NEVER               = 0x00000000,
14391SQ_TEX_DEPTH_COMPARE_LESS                = 0x00000001,
14392SQ_TEX_DEPTH_COMPARE_EQUAL               = 0x00000002,
14393SQ_TEX_DEPTH_COMPARE_LESSEQUAL           = 0x00000003,
14394SQ_TEX_DEPTH_COMPARE_GREATER             = 0x00000004,
14395SQ_TEX_DEPTH_COMPARE_NOTEQUAL            = 0x00000005,
14396SQ_TEX_DEPTH_COMPARE_GREATEREQUAL        = 0x00000006,
14397SQ_TEX_DEPTH_COMPARE_ALWAYS              = 0x00000007,
14398} SQ_TEX_DEPTH_COMPARE;
14399
14400/*
14401 * SQ_TEX_BORDER_COLOR enum
14402 */
14403
14404typedef enum SQ_TEX_BORDER_COLOR {
14405SQ_TEX_BORDER_COLOR_TRANS_BLACK          = 0x00000000,
14406SQ_TEX_BORDER_COLOR_OPAQUE_BLACK         = 0x00000001,
14407SQ_TEX_BORDER_COLOR_OPAQUE_WHITE         = 0x00000002,
14408SQ_TEX_BORDER_COLOR_REGISTER             = 0x00000003,
14409} SQ_TEX_BORDER_COLOR;
14410
14411/*
14412 * SQ_RSRC_BUF_TYPE enum
14413 */
14414
14415typedef enum SQ_RSRC_BUF_TYPE {
14416SQ_RSRC_BUF                              = 0x00000000,
14417SQ_RSRC_BUF_RSVD_1                       = 0x00000001,
14418SQ_RSRC_BUF_RSVD_2                       = 0x00000002,
14419SQ_RSRC_BUF_RSVD_3                       = 0x00000003,
14420} SQ_RSRC_BUF_TYPE;
14421
14422/*
14423 * SQ_RSRC_IMG_TYPE enum
14424 */
14425
14426typedef enum SQ_RSRC_IMG_TYPE {
14427SQ_RSRC_IMG_RSVD_0                       = 0x00000000,
14428SQ_RSRC_IMG_RSVD_1                       = 0x00000001,
14429SQ_RSRC_IMG_RSVD_2                       = 0x00000002,
14430SQ_RSRC_IMG_RSVD_3                       = 0x00000003,
14431SQ_RSRC_IMG_RSVD_4                       = 0x00000004,
14432SQ_RSRC_IMG_RSVD_5                       = 0x00000005,
14433SQ_RSRC_IMG_RSVD_6                       = 0x00000006,
14434SQ_RSRC_IMG_RSVD_7                       = 0x00000007,
14435SQ_RSRC_IMG_1D                           = 0x00000008,
14436SQ_RSRC_IMG_2D                           = 0x00000009,
14437SQ_RSRC_IMG_3D                           = 0x0000000a,
14438SQ_RSRC_IMG_CUBE                         = 0x0000000b,
14439SQ_RSRC_IMG_1D_ARRAY                     = 0x0000000c,
14440SQ_RSRC_IMG_2D_ARRAY                     = 0x0000000d,
14441SQ_RSRC_IMG_2D_MSAA                      = 0x0000000e,
14442SQ_RSRC_IMG_2D_MSAA_ARRAY                = 0x0000000f,
14443} SQ_RSRC_IMG_TYPE;
14444
14445/*
14446 * SQ_RSRC_FLAT_TYPE enum
14447 */
14448
14449typedef enum SQ_RSRC_FLAT_TYPE {
14450SQ_RSRC_FLAT_RSVD_0                      = 0x00000000,
14451SQ_RSRC_FLAT                             = 0x00000001,
14452SQ_RSRC_FLAT_RSVD_2                      = 0x00000002,
14453SQ_RSRC_FLAT_RSVD_3                      = 0x00000003,
14454} SQ_RSRC_FLAT_TYPE;
14455
14456/*
14457 * SQ_IMG_FILTER_TYPE enum
14458 */
14459
14460typedef enum SQ_IMG_FILTER_TYPE {
14461SQ_IMG_FILTER_MODE_BLEND                 = 0x00000000,
14462SQ_IMG_FILTER_MODE_MIN                   = 0x00000001,
14463SQ_IMG_FILTER_MODE_MAX                   = 0x00000002,
14464} SQ_IMG_FILTER_TYPE;
14465
14466/*
14467 * SQ_SEL_XYZW01 enum
14468 */
14469
14470typedef enum SQ_SEL_XYZW01 {
14471SQ_SEL_0                                 = 0x00000000,
14472SQ_SEL_1                                 = 0x00000001,
14473SQ_SEL_RESERVED_0                        = 0x00000002,
14474SQ_SEL_RESERVED_1                        = 0x00000003,
14475SQ_SEL_X                                 = 0x00000004,
14476SQ_SEL_Y                                 = 0x00000005,
14477SQ_SEL_Z                                 = 0x00000006,
14478SQ_SEL_W                                 = 0x00000007,
14479} SQ_SEL_XYZW01;
14480
14481/*
14482 * SQ_WAVE_TYPE enum
14483 */
14484
14485typedef enum SQ_WAVE_TYPE {
14486SQ_WAVE_TYPE_PS                          = 0x00000000,
14487SQ_WAVE_TYPE_VS                          = 0x00000001,
14488SQ_WAVE_TYPE_GS                          = 0x00000002,
14489SQ_WAVE_TYPE_ES                          = 0x00000003,
14490SQ_WAVE_TYPE_HS                          = 0x00000004,
14491SQ_WAVE_TYPE_LS                          = 0x00000005,
14492SQ_WAVE_TYPE_CS                          = 0x00000006,
14493SQ_WAVE_TYPE_PS1                         = 0x00000007,
14494} SQ_WAVE_TYPE;
14495
14496/*
14497 * SQ_THREAD_TRACE_TOKEN_TYPE enum
14498 */
14499
14500typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
14501SQ_THREAD_TRACE_TOKEN_MISC               = 0x00000000,
14502SQ_THREAD_TRACE_TOKEN_TIMESTAMP          = 0x00000001,
14503SQ_THREAD_TRACE_TOKEN_REG                = 0x00000002,
14504SQ_THREAD_TRACE_TOKEN_WAVE_START         = 0x00000003,
14505SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC         = 0x00000004,
14506SQ_THREAD_TRACE_TOKEN_REG_CSPRIV         = 0x00000005,
14507SQ_THREAD_TRACE_TOKEN_WAVE_END           = 0x00000006,
14508SQ_THREAD_TRACE_TOKEN_EVENT              = 0x00000007,
14509SQ_THREAD_TRACE_TOKEN_EVENT_CS           = 0x00000008,
14510SQ_THREAD_TRACE_TOKEN_EVENT_GFX1         = 0x00000009,
14511SQ_THREAD_TRACE_TOKEN_INST               = 0x0000000a,
14512SQ_THREAD_TRACE_TOKEN_INST_PC            = 0x0000000b,
14513SQ_THREAD_TRACE_TOKEN_INST_USERDATA      = 0x0000000c,
14514SQ_THREAD_TRACE_TOKEN_ISSUE              = 0x0000000d,
14515SQ_THREAD_TRACE_TOKEN_PERF               = 0x0000000e,
14516SQ_THREAD_TRACE_TOKEN_REG_CS             = 0x0000000f,
14517} SQ_THREAD_TRACE_TOKEN_TYPE;
14518
14519/*
14520 * SQ_THREAD_TRACE_MISC_TOKEN_TYPE enum
14521 */
14522
14523typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
14524SQ_THREAD_TRACE_MISC_TOKEN_TIME          = 0x00000000,
14525SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET    = 0x00000001,
14526SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST   = 0x00000002,
14527SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC     = 0x00000003,
14528SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN  = 0x00000004,
14529SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END  = 0x00000005,
14530SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX       = 0x00000006,
14531SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN    = 0x00000007,
14532} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
14533
14534/*
14535 * SQ_THREAD_TRACE_INST_TYPE enum
14536 */
14537
14538typedef enum SQ_THREAD_TRACE_INST_TYPE {
14539SQ_THREAD_TRACE_INST_TYPE_SMEM_RD        = 0x00000000,
14540SQ_THREAD_TRACE_INST_TYPE_SALU_32        = 0x00000001,
14541SQ_THREAD_TRACE_INST_TYPE_VMEM_RD        = 0x00000002,
14542SQ_THREAD_TRACE_INST_TYPE_VMEM_WR        = 0x00000003,
14543SQ_THREAD_TRACE_INST_TYPE_FLAT_WR        = 0x00000004,
14544SQ_THREAD_TRACE_INST_TYPE_VALU_32        = 0x00000005,
14545SQ_THREAD_TRACE_INST_TYPE_LDS            = 0x00000006,
14546SQ_THREAD_TRACE_INST_TYPE_PC             = 0x00000007,
14547SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS     = 0x00000008,
14548SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX     = 0x00000009,
14549SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL  = 0x0000000a,
14550SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS  = 0x0000000b,
14551SQ_THREAD_TRACE_INST_TYPE_JUMP           = 0x0000000c,
14552SQ_THREAD_TRACE_INST_TYPE_NEXT           = 0x0000000d,
14553SQ_THREAD_TRACE_INST_TYPE_FLAT_RD        = 0x0000000e,
14554SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG      = 0x0000000f,
14555SQ_THREAD_TRACE_INST_TYPE_SMEM_WR        = 0x00000010,
14556SQ_THREAD_TRACE_INST_TYPE_SALU_64        = 0x00000011,
14557SQ_THREAD_TRACE_INST_TYPE_VALU_64        = 0x00000012,
14558SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY  = 0x00000013,
14559SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY  = 0x00000014,
14560SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY  = 0x00000015,
14561SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY  = 0x00000016,
14562SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY  = 0x00000017,
14563SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY  = 0x00000018,
14564SQ_THREAD_TRACE_INST_TYPE_FATAL_HALT     = 0x00000019,
14565} SQ_THREAD_TRACE_INST_TYPE;
14566
14567/*
14568 * SQ_THREAD_TRACE_REG_TYPE enum
14569 */
14570
14571typedef enum SQ_THREAD_TRACE_REG_TYPE {
14572SQ_THREAD_TRACE_REG_TYPE_EVENT           = 0x00000000,
14573SQ_THREAD_TRACE_REG_TYPE_DRAW            = 0x00000001,
14574SQ_THREAD_TRACE_REG_TYPE_DISPATCH        = 0x00000002,
14575SQ_THREAD_TRACE_REG_TYPE_USERDATA        = 0x00000003,
14576SQ_THREAD_TRACE_REG_TYPE_MARKER          = 0x00000004,
14577SQ_THREAD_TRACE_REG_TYPE_GFXDEC          = 0x00000005,
14578SQ_THREAD_TRACE_REG_TYPE_SHDEC           = 0x00000006,
14579SQ_THREAD_TRACE_REG_TYPE_OTHER           = 0x00000007,
14580} SQ_THREAD_TRACE_REG_TYPE;
14581
14582/*
14583 * SQ_THREAD_TRACE_REG_OP enum
14584 */
14585
14586typedef enum SQ_THREAD_TRACE_REG_OP {
14587SQ_THREAD_TRACE_REG_OP_READ              = 0x00000000,
14588SQ_THREAD_TRACE_REG_OP_WRITE             = 0x00000001,
14589} SQ_THREAD_TRACE_REG_OP;
14590
14591/*
14592 * SQ_THREAD_TRACE_MODE_SEL enum
14593 */
14594
14595typedef enum SQ_THREAD_TRACE_MODE_SEL {
14596SQ_THREAD_TRACE_MODE_OFF                 = 0x00000000,
14597SQ_THREAD_TRACE_MODE_ON                  = 0x00000001,
14598} SQ_THREAD_TRACE_MODE_SEL;
14599
14600/*
14601 * SQ_THREAD_TRACE_CAPTURE_MODE enum
14602 */
14603
14604typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
14605SQ_THREAD_TRACE_CAPTURE_MODE_ALL         = 0x00000000,
14606SQ_THREAD_TRACE_CAPTURE_MODE_SELECT      = 0x00000001,
14607SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL  = 0x00000002,
14608} SQ_THREAD_TRACE_CAPTURE_MODE;
14609
14610/*
14611 * SQ_THREAD_TRACE_VM_ID_MASK enum
14612 */
14613
14614typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
14615SQ_THREAD_TRACE_VM_ID_MASK_SINGLE        = 0x00000000,
14616SQ_THREAD_TRACE_VM_ID_MASK_ALL           = 0x00000001,
14617SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL  = 0x00000002,
14618} SQ_THREAD_TRACE_VM_ID_MASK;
14619
14620/*
14621 * SQ_THREAD_TRACE_WAVE_MASK enum
14622 */
14623
14624typedef enum SQ_THREAD_TRACE_WAVE_MASK {
14625SQ_THREAD_TRACE_WAVE_MASK_NONE           = 0x00000000,
14626SQ_THREAD_TRACE_WAVE_MASK_ALL            = 0x00000001,
14627} SQ_THREAD_TRACE_WAVE_MASK;
14628
14629/*
14630 * SQ_THREAD_TRACE_ISSUE enum
14631 */
14632
14633typedef enum SQ_THREAD_TRACE_ISSUE {
14634SQ_THREAD_TRACE_ISSUE_NULL               = 0x00000000,
14635SQ_THREAD_TRACE_ISSUE_STALL              = 0x00000001,
14636SQ_THREAD_TRACE_ISSUE_INST               = 0x00000002,
14637SQ_THREAD_TRACE_ISSUE_IMMED              = 0x00000003,
14638} SQ_THREAD_TRACE_ISSUE;
14639
14640/*
14641 * SQ_THREAD_TRACE_ISSUE_MASK enum
14642 */
14643
14644typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
14645SQ_THREAD_TRACE_ISSUE_MASK_ALL           = 0x00000000,
14646SQ_THREAD_TRACE_ISSUE_MASK_STALLED       = 0x00000001,
14647SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED  = 0x00000002,
14648SQ_THREAD_TRACE_ISSUE_MASK_IMMED         = 0x00000003,
14649} SQ_THREAD_TRACE_ISSUE_MASK;
14650
14651/*
14652 * SQ_PERF_SEL enum
14653 */
14654
14655typedef enum SQ_PERF_SEL {
14656SQ_PERF_SEL_NONE                         = 0x00000000,
14657SQ_PERF_SEL_ACCUM_PREV                   = 0x00000001,
14658SQ_PERF_SEL_CYCLES                       = 0x00000002,
14659SQ_PERF_SEL_BUSY_CYCLES                  = 0x00000003,
14660SQ_PERF_SEL_WAVES                        = 0x00000004,
14661SQ_PERF_SEL_LEVEL_WAVES                  = 0x00000005,
14662SQ_PERF_SEL_WAVES_EQ_64                  = 0x00000006,
14663SQ_PERF_SEL_WAVES_LT_64                  = 0x00000007,
14664SQ_PERF_SEL_WAVES_LT_48                  = 0x00000008,
14665SQ_PERF_SEL_WAVES_LT_32                  = 0x00000009,
14666SQ_PERF_SEL_WAVES_LT_16                  = 0x0000000a,
14667SQ_PERF_SEL_WAVES_CU                     = 0x0000000b,
14668SQ_PERF_SEL_LEVEL_WAVES_CU               = 0x0000000c,
14669SQ_PERF_SEL_BUSY_CU_CYCLES               = 0x0000000d,
14670SQ_PERF_SEL_ITEMS                        = 0x0000000e,
14671SQ_PERF_SEL_QUADS                        = 0x0000000f,
14672SQ_PERF_SEL_EVENTS                       = 0x00000010,
14673SQ_PERF_SEL_SURF_SYNCS                   = 0x00000011,
14674SQ_PERF_SEL_TTRACE_REQS                  = 0x00000012,
14675SQ_PERF_SEL_TTRACE_INFLIGHT_REQS         = 0x00000013,
14676SQ_PERF_SEL_TTRACE_STALL                 = 0x00000014,
14677SQ_PERF_SEL_MSG_CNTR                     = 0x00000015,
14678SQ_PERF_SEL_MSG_PERF                     = 0x00000016,
14679SQ_PERF_SEL_MSG_GSCNT                    = 0x00000017,
14680SQ_PERF_SEL_MSG_INTERRUPT                = 0x00000018,
14681SQ_PERF_SEL_INSTS                        = 0x00000019,
14682SQ_PERF_SEL_INSTS_VALU                   = 0x0000001a,
14683SQ_PERF_SEL_INSTS_VMEM_WR                = 0x0000001b,
14684SQ_PERF_SEL_INSTS_VMEM_RD                = 0x0000001c,
14685SQ_PERF_SEL_INSTS_VMEM                   = 0x0000001d,
14686SQ_PERF_SEL_INSTS_SALU                   = 0x0000001e,
14687SQ_PERF_SEL_INSTS_SMEM                   = 0x0000001f,
14688SQ_PERF_SEL_INSTS_FLAT                   = 0x00000020,
14689SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY          = 0x00000021,
14690SQ_PERF_SEL_INSTS_LDS                    = 0x00000022,
14691SQ_PERF_SEL_INSTS_GDS                    = 0x00000023,
14692SQ_PERF_SEL_INSTS_EXP                    = 0x00000024,
14693SQ_PERF_SEL_INSTS_EXP_GDS                = 0x00000025,
14694SQ_PERF_SEL_INSTS_BRANCH                 = 0x00000026,
14695SQ_PERF_SEL_INSTS_SENDMSG                = 0x00000027,
14696SQ_PERF_SEL_INSTS_VSKIPPED               = 0x00000028,
14697SQ_PERF_SEL_INST_LEVEL_VMEM              = 0x00000029,
14698SQ_PERF_SEL_INST_LEVEL_SMEM              = 0x0000002a,
14699SQ_PERF_SEL_INST_LEVEL_LDS               = 0x0000002b,
14700SQ_PERF_SEL_INST_LEVEL_GDS               = 0x0000002c,
14701SQ_PERF_SEL_INST_LEVEL_EXP               = 0x0000002d,
14702SQ_PERF_SEL_WAVE_CYCLES                  = 0x0000002e,
14703SQ_PERF_SEL_WAVE_READY                   = 0x0000002f,
14704SQ_PERF_SEL_WAIT_CNT_VM                  = 0x00000030,
14705SQ_PERF_SEL_WAIT_CNT_LGKM                = 0x00000031,
14706SQ_PERF_SEL_WAIT_CNT_EXP                 = 0x00000032,
14707SQ_PERF_SEL_WAIT_CNT_ANY                 = 0x00000033,
14708SQ_PERF_SEL_WAIT_BARRIER                 = 0x00000034,
14709SQ_PERF_SEL_WAIT_EXP_ALLOC               = 0x00000035,
14710SQ_PERF_SEL_WAIT_SLEEP                   = 0x00000036,
14711SQ_PERF_SEL_WAIT_SLEEP_XNACK             = 0x00000037,
14712SQ_PERF_SEL_WAIT_OTHER                   = 0x00000038,
14713SQ_PERF_SEL_WAIT_ANY                     = 0x00000039,
14714SQ_PERF_SEL_WAIT_TTRACE                  = 0x0000003a,
14715SQ_PERF_SEL_WAIT_IFETCH                  = 0x0000003b,
14716SQ_PERF_SEL_WAIT_INST_ANY                = 0x0000003c,
14717SQ_PERF_SEL_WAIT_INST_VMEM               = 0x0000003d,
14718SQ_PERF_SEL_WAIT_INST_SCA                = 0x0000003e,
14719SQ_PERF_SEL_WAIT_INST_LDS                = 0x0000003f,
14720SQ_PERF_SEL_WAIT_INST_VALU               = 0x00000040,
14721SQ_PERF_SEL_WAIT_INST_EXP_GDS            = 0x00000041,
14722SQ_PERF_SEL_WAIT_INST_MISC               = 0x00000042,
14723SQ_PERF_SEL_WAIT_INST_FLAT               = 0x00000043,
14724SQ_PERF_SEL_ACTIVE_INST_ANY              = 0x00000044,
14725SQ_PERF_SEL_ACTIVE_INST_VMEM             = 0x00000045,
14726SQ_PERF_SEL_ACTIVE_INST_LDS              = 0x00000046,
14727SQ_PERF_SEL_ACTIVE_INST_VALU             = 0x00000047,
14728SQ_PERF_SEL_ACTIVE_INST_SCA              = 0x00000048,
14729SQ_PERF_SEL_ACTIVE_INST_EXP_GDS          = 0x00000049,
14730SQ_PERF_SEL_ACTIVE_INST_MISC             = 0x0000004a,
14731SQ_PERF_SEL_ACTIVE_INST_FLAT             = 0x0000004b,
14732SQ_PERF_SEL_INST_CYCLES_VMEM_WR          = 0x0000004c,
14733SQ_PERF_SEL_INST_CYCLES_VMEM_RD          = 0x0000004d,
14734SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR        = 0x0000004e,
14735SQ_PERF_SEL_INST_CYCLES_VMEM_DATA        = 0x0000004f,
14736SQ_PERF_SEL_INST_CYCLES_VMEM_CMD         = 0x00000050,
14737SQ_PERF_SEL_INST_CYCLES_EXP              = 0x00000051,
14738SQ_PERF_SEL_INST_CYCLES_GDS              = 0x00000052,
14739SQ_PERF_SEL_INST_CYCLES_SMEM             = 0x00000053,
14740SQ_PERF_SEL_INST_CYCLES_SALU             = 0x00000054,
14741SQ_PERF_SEL_THREAD_CYCLES_VALU           = 0x00000055,
14742SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX       = 0x00000056,
14743SQ_PERF_SEL_IFETCH                       = 0x00000057,
14744SQ_PERF_SEL_IFETCH_LEVEL                 = 0x00000058,
14745SQ_PERF_SEL_CBRANCH_FORK                 = 0x00000059,
14746SQ_PERF_SEL_CBRANCH_FORK_SPLIT           = 0x0000005a,
14747SQ_PERF_SEL_VALU_LDS_DIRECT_RD           = 0x0000005b,
14748SQ_PERF_SEL_VALU_LDS_INTERP_OP           = 0x0000005c,
14749SQ_PERF_SEL_LDS_BANK_CONFLICT            = 0x0000005d,
14750SQ_PERF_SEL_LDS_ADDR_CONFLICT            = 0x0000005e,
14751SQ_PERF_SEL_LDS_UNALIGNED_STALL          = 0x0000005f,
14752SQ_PERF_SEL_LDS_MEM_VIOLATIONS           = 0x00000060,
14753SQ_PERF_SEL_LDS_ATOMIC_RETURN            = 0x00000061,
14754SQ_PERF_SEL_LDS_IDX_ACTIVE               = 0x00000062,
14755SQ_PERF_SEL_VALU_DEP_STALL               = 0x00000063,
14756SQ_PERF_SEL_VALU_STARVE                  = 0x00000064,
14757SQ_PERF_SEL_EXP_REQ_FIFO_FULL            = 0x00000065,
14758SQ_PERF_SEL_LDS_DATA_FIFO_FULL           = 0x00000066,
14759SQ_PERF_SEL_LDS_CMD_FIFO_FULL            = 0x00000067,
14760SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL       = 0x00000068,
14761SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL        = 0x00000069,
14762SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY        = 0x0000006a,
14763SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL    = 0x0000006b,
14764SQ_PERF_SEL_VALU_SRC_C_CONFLICT          = 0x0000006c,
14765SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT      = 0x0000006d,
14766SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT      = 0x0000006e,
14767SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT         = 0x0000006f,
14768SQ_PERF_SEL_LDS_SRC_CD_CONFLICT          = 0x00000070,
14769SQ_PERF_SEL_SRC_CD_BUSY                  = 0x00000071,
14770SQ_PERF_SEL_PT_POWER_STALL               = 0x00000072,
14771SQ_PERF_SEL_USER0                        = 0x00000073,
14772SQ_PERF_SEL_USER1                        = 0x00000074,
14773SQ_PERF_SEL_USER2                        = 0x00000075,
14774SQ_PERF_SEL_USER3                        = 0x00000076,
14775SQ_PERF_SEL_USER4                        = 0x00000077,
14776SQ_PERF_SEL_USER5                        = 0x00000078,
14777SQ_PERF_SEL_USER6                        = 0x00000079,
14778SQ_PERF_SEL_USER7                        = 0x0000007a,
14779SQ_PERF_SEL_USER8                        = 0x0000007b,
14780SQ_PERF_SEL_USER9                        = 0x0000007c,
14781SQ_PERF_SEL_USER10                       = 0x0000007d,
14782SQ_PERF_SEL_USER11                       = 0x0000007e,
14783SQ_PERF_SEL_USER12                       = 0x0000007f,
14784SQ_PERF_SEL_USER13                       = 0x00000080,
14785SQ_PERF_SEL_USER14                       = 0x00000081,
14786SQ_PERF_SEL_USER15                       = 0x00000082,
14787SQ_PERF_SEL_USER_LEVEL0                  = 0x00000083,
14788SQ_PERF_SEL_USER_LEVEL1                  = 0x00000084,
14789SQ_PERF_SEL_USER_LEVEL2                  = 0x00000085,
14790SQ_PERF_SEL_USER_LEVEL3                  = 0x00000086,
14791SQ_PERF_SEL_USER_LEVEL4                  = 0x00000087,
14792SQ_PERF_SEL_USER_LEVEL5                  = 0x00000088,
14793SQ_PERF_SEL_USER_LEVEL6                  = 0x00000089,
14794SQ_PERF_SEL_USER_LEVEL7                  = 0x0000008a,
14795SQ_PERF_SEL_USER_LEVEL8                  = 0x0000008b,
14796SQ_PERF_SEL_USER_LEVEL9                  = 0x0000008c,
14797SQ_PERF_SEL_USER_LEVEL10                 = 0x0000008d,
14798SQ_PERF_SEL_USER_LEVEL11                 = 0x0000008e,
14799SQ_PERF_SEL_USER_LEVEL12                 = 0x0000008f,
14800SQ_PERF_SEL_USER_LEVEL13                 = 0x00000090,
14801SQ_PERF_SEL_USER_LEVEL14                 = 0x00000091,
14802SQ_PERF_SEL_USER_LEVEL15                 = 0x00000092,
14803SQ_PERF_SEL_POWER_VALU                   = 0x00000093,
14804SQ_PERF_SEL_POWER_VALU0                  = 0x00000094,
14805SQ_PERF_SEL_POWER_VALU1                  = 0x00000095,
14806SQ_PERF_SEL_POWER_VALU2                  = 0x00000096,
14807SQ_PERF_SEL_POWER_GPR_RD                 = 0x00000097,
14808SQ_PERF_SEL_POWER_GPR_WR                 = 0x00000098,
14809SQ_PERF_SEL_POWER_LDS_BUSY               = 0x00000099,
14810SQ_PERF_SEL_POWER_ALU_BUSY               = 0x0000009a,
14811SQ_PERF_SEL_POWER_TEX_BUSY               = 0x0000009b,
14812SQ_PERF_SEL_ACCUM_PREV_HIRES             = 0x0000009c,
14813SQ_PERF_SEL_WAVES_RESTORED               = 0x0000009d,
14814SQ_PERF_SEL_WAVES_SAVED                  = 0x0000009e,
14815SQ_PERF_SEL_INSTS_SMEM_NORM              = 0x0000009f,
14816SQ_PERF_SEL_ATC_INSTS_VMEM               = 0x000000a0,
14817SQ_PERF_SEL_ATC_INST_LEVEL_VMEM          = 0x000000a1,
14818SQ_PERF_SEL_ATC_XNACK_FIRST              = 0x000000a2,
14819SQ_PERF_SEL_ATC_XNACK_ALL                = 0x000000a3,
14820SQ_PERF_SEL_ATC_XNACK_FIFO_FULL          = 0x000000a4,
14821SQ_PERF_SEL_ATC_INSTS_SMEM               = 0x000000a5,
14822SQ_PERF_SEL_ATC_INST_LEVEL_SMEM          = 0x000000a6,
14823SQ_PERF_SEL_IFETCH_XNACK                 = 0x000000a7,
14824SQ_PERF_SEL_TLB_SHOOTDOWN                = 0x000000a8,
14825SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES         = 0x000000a9,
14826SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY         = 0x000000aa,
14827SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY         = 0x000000ab,
14828SQ_PERF_SEL_INSTS_VMEM_REPLAY            = 0x000000ac,
14829SQ_PERF_SEL_INSTS_SMEM_REPLAY            = 0x000000ad,
14830SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY       = 0x000000ae,
14831SQ_PERF_SEL_INSTS_FLAT_REPLAY            = 0x000000af,
14832SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY        = 0x000000b0,
14833SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY        = 0x000000b1,
14834SQ_PERF_SEL_UTCL1_TRANSLATION_MISS       = 0x000000b2,
14835SQ_PERF_SEL_UTCL1_PERMISSION_MISS        = 0x000000b3,
14836SQ_PERF_SEL_UTCL1_REQUEST                = 0x000000b4,
14837SQ_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL    = 0x000000b5,
14838SQ_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX     = 0x000000b6,
14839SQ_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT     = 0x000000b7,
14840SQ_PERF_SEL_UTCL1_LFIFO_FULL             = 0x000000b8,
14841SQ_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES    = 0x000000b9,
14842SQ_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x000000ba,
14843SQ_PERF_SEL_DUMMY_END                    = 0x000000bb,
14844SQ_PERF_SEL_DUMMY_LAST                   = 0x000000ff,
14845SQC_PERF_SEL_ICACHE_INPUT_VALID_READY    = 0x00000100,
14846SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB   = 0x00000101,
14847SQC_PERF_SEL_ICACHE_INPUT_VALIDB         = 0x00000102,
14848SQC_PERF_SEL_DCACHE_INPUT_VALID_READY    = 0x00000103,
14849SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB   = 0x00000104,
14850SQC_PERF_SEL_DCACHE_INPUT_VALIDB         = 0x00000105,
14851SQC_PERF_SEL_TC_REQ                      = 0x00000106,
14852SQC_PERF_SEL_TC_INST_REQ                 = 0x00000107,
14853SQC_PERF_SEL_TC_DATA_READ_REQ            = 0x00000108,
14854SQC_PERF_SEL_TC_DATA_WRITE_REQ           = 0x00000109,
14855SQC_PERF_SEL_TC_DATA_ATOMIC_REQ          = 0x0000010a,
14856SQC_PERF_SEL_TC_STALL                    = 0x0000010b,
14857SQC_PERF_SEL_TC_STARVE                   = 0x0000010c,
14858SQC_PERF_SEL_ICACHE_BUSY_CYCLES          = 0x0000010d,
14859SQC_PERF_SEL_ICACHE_REQ                  = 0x0000010e,
14860SQC_PERF_SEL_ICACHE_HITS                 = 0x0000010f,
14861SQC_PERF_SEL_ICACHE_MISSES               = 0x00000110,
14862SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE     = 0x00000111,
14863SQC_PERF_SEL_ICACHE_INVAL_INST           = 0x00000112,
14864SQC_PERF_SEL_ICACHE_INVAL_ASYNC          = 0x00000113,
14865SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT  = 0x00000114,
14866SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB  = 0x00000115,
14867SQC_PERF_SEL_ICACHE_CACHE_STALLED        = 0x00000116,
14868SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO  = 0x00000117,
14869SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX  = 0x00000118,
14870SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT   = 0x00000119,
14871SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO  = 0x0000011a,
14872SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0x0000011b,
14873SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF  = 0x0000011c,
14874SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT  = 0x0000011d,
14875SQC_PERF_SEL_ICACHE_PREFETCH_1           = 0x0000011e,
14876SQC_PERF_SEL_ICACHE_PREFETCH_2           = 0x0000011f,
14877SQC_PERF_SEL_ICACHE_PREFETCH_FILTERED    = 0x00000120,
14878SQC_PERF_SEL_DCACHE_BUSY_CYCLES          = 0x00000121,
14879SQC_PERF_SEL_DCACHE_REQ                  = 0x00000122,
14880SQC_PERF_SEL_DCACHE_HITS                 = 0x00000123,
14881SQC_PERF_SEL_DCACHE_MISSES               = 0x00000124,
14882SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE     = 0x00000125,
14883SQC_PERF_SEL_DCACHE_HIT_LRU_READ         = 0x00000126,
14884SQC_PERF_SEL_DCACHE_MISS_EVICT_READ      = 0x00000127,
14885SQC_PERF_SEL_DCACHE_WC_LRU_WRITE         = 0x00000128,
14886SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE       = 0x00000129,
14887SQC_PERF_SEL_DCACHE_ATOMIC               = 0x0000012a,
14888SQC_PERF_SEL_DCACHE_VOLATILE             = 0x0000012b,
14889SQC_PERF_SEL_DCACHE_INVAL_INST           = 0x0000012c,
14890SQC_PERF_SEL_DCACHE_INVAL_ASYNC          = 0x0000012d,
14891SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST  = 0x0000012e,
14892SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC  = 0x0000012f,
14893SQC_PERF_SEL_DCACHE_WB_INST              = 0x00000130,
14894SQC_PERF_SEL_DCACHE_WB_ASYNC             = 0x00000131,
14895SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST     = 0x00000132,
14896SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC    = 0x00000133,
14897SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT  = 0x00000134,
14898SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB  = 0x00000135,
14899SQC_PERF_SEL_DCACHE_CACHE_STALLED        = 0x00000136,
14900SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX  = 0x00000137,
14901SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT   = 0x00000138,
14902SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT    = 0x00000139,
14903SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED  = 0x0000013a,
14904SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE  = 0x0000013b,
14905SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT  = 0x0000013c,
14906SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH  = 0x0000013d,
14907SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE  = 0x0000013e,
14908SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO  = 0x0000013f,
14909SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0x00000140,
14910SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF  = 0x00000141,
14911SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT  = 0x00000142,
14912SQC_PERF_SEL_DCACHE_REQ_READ_1           = 0x00000143,
14913SQC_PERF_SEL_DCACHE_REQ_READ_2           = 0x00000144,
14914SQC_PERF_SEL_DCACHE_REQ_READ_4           = 0x00000145,
14915SQC_PERF_SEL_DCACHE_REQ_READ_8           = 0x00000146,
14916SQC_PERF_SEL_DCACHE_REQ_READ_16          = 0x00000147,
14917SQC_PERF_SEL_DCACHE_REQ_TIME             = 0x00000148,
14918SQC_PERF_SEL_DCACHE_REQ_WRITE_1          = 0x00000149,
14919SQC_PERF_SEL_DCACHE_REQ_WRITE_2          = 0x0000014a,
14920SQC_PERF_SEL_DCACHE_REQ_WRITE_4          = 0x0000014b,
14921SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE        = 0x0000014c,
14922SQC_PERF_SEL_SQ_DCACHE_REQS              = 0x0000014d,
14923SQC_PERF_SEL_DCACHE_FLAT_REQ             = 0x0000014e,
14924SQC_PERF_SEL_DCACHE_NONFLAT_REQ          = 0x0000014f,
14925SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL       = 0x00000150,
14926SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL       = 0x00000151,
14927SQC_PERF_SEL_TC_INFLIGHT_LEVEL           = 0x00000152,
14928SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL    = 0x00000153,
14929SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL    = 0x00000154,
14930SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS  = 0x00000155,
14931SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS  = 0x00000156,
14932SQC_PERF_SEL_ICACHE_GATCL1_REQUEST       = 0x00000157,
14933SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX  = 0x00000158,
14934SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT  = 0x00000159,
14935SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL    = 0x0000015a,
14936SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES  = 0x0000015b,
14937SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS  = 0x0000015c,
14938SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT  = 0x0000015d,
14939SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL  = 0x0000015e,
14940SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS  = 0x0000015f,
14941SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS  = 0x00000160,
14942SQC_PERF_SEL_DCACHE_GATCL1_REQUEST       = 0x00000161,
14943SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX  = 0x00000162,
14944SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT  = 0x00000163,
14945SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL    = 0x00000164,
14946SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES  = 0x00000165,
14947SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS  = 0x00000166,
14948SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT  = 0x00000167,
14949SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL  = 0x00000168,
14950SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS  = 0x00000169,
14951SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL  = 0x0000016a,
14952SQC_PERF_SEL_DUMMY_LAST                  = 0x0000016b,
14953} SQ_PERF_SEL;
14954
14955/*
14956 * SQ_CAC_POWER_SEL enum
14957 */
14958
14959typedef enum SQ_CAC_POWER_SEL {
14960SQ_CAC_POWER_VALU                        = 0x00000000,
14961SQ_CAC_POWER_VALU0                       = 0x00000001,
14962SQ_CAC_POWER_VALU1                       = 0x00000002,
14963SQ_CAC_POWER_VALU2                       = 0x00000003,
14964SQ_CAC_POWER_GPR_RD                      = 0x00000004,
14965SQ_CAC_POWER_GPR_WR                      = 0x00000005,
14966SQ_CAC_POWER_LDS_BUSY                    = 0x00000006,
14967SQ_CAC_POWER_ALU_BUSY                    = 0x00000007,
14968SQ_CAC_POWER_TEX_BUSY                    = 0x00000008,
14969} SQ_CAC_POWER_SEL;
14970
14971/*
14972 * SQ_IND_CMD_CMD enum
14973 */
14974
14975typedef enum SQ_IND_CMD_CMD {
14976SQ_IND_CMD_CMD_NULL                      = 0x00000000,
14977SQ_IND_CMD_CMD_SETHALT                   = 0x00000001,
14978SQ_IND_CMD_CMD_SAVECTX                   = 0x00000002,
14979SQ_IND_CMD_CMD_KILL                      = 0x00000003,
14980SQ_IND_CMD_CMD_DEBUG                     = 0x00000004,
14981SQ_IND_CMD_CMD_TRAP                      = 0x00000005,
14982SQ_IND_CMD_CMD_SET_SPI_PRIO              = 0x00000006,
14983SQ_IND_CMD_CMD_SETFATALHALT              = 0x00000007,
14984} SQ_IND_CMD_CMD;
14985
14986/*
14987 * SQ_IND_CMD_MODE enum
14988 */
14989
14990typedef enum SQ_IND_CMD_MODE {
14991SQ_IND_CMD_MODE_SINGLE                   = 0x00000000,
14992SQ_IND_CMD_MODE_BROADCAST                = 0x00000001,
14993SQ_IND_CMD_MODE_BROADCAST_QUEUE          = 0x00000002,
14994SQ_IND_CMD_MODE_BROADCAST_PIPE           = 0x00000003,
14995SQ_IND_CMD_MODE_BROADCAST_ME             = 0x00000004,
14996} SQ_IND_CMD_MODE;
14997
14998/*
14999 * SQ_EDC_INFO_SOURCE enum
15000 */

15001
15002typedef enum SQ_EDC_INFO_SOURCE {
15003SQ_EDC_INFO_SOURCE_INVALID               = 0x00000000,
15004SQ_EDC_INFO_SOURCE_INST                  = 0x00000001,
15005SQ_EDC_INFO_SOURCE_SGPR                  = 0x00000002,
15006SQ_EDC_INFO_SOURCE_VGPR                  = 0x00000003,
15007SQ_EDC_INFO_SOURCE_LDS                   = 0x00000004,
15008SQ_EDC_INFO_SOURCE_GDS                   = 0x00000005,
15009SQ_EDC_INFO_SOURCE_TA                    = 0x00000006,
15010} SQ_EDC_INFO_SOURCE;
15011
15012/*
15013 * SQ_ROUND_MODE enum
15014 */
15015
15016typedef enum SQ_ROUND_MODE {
15017SQ_ROUND_NEAREST_EVEN                    = 0x00000000,
15018SQ_ROUND_PLUS_INFINITY                   = 0x00000001,
15019SQ_ROUND_MINUS_INFINITY                  = 0x00000002,
15020SQ_ROUND_TO_ZERO                         = 0x00000003,
15021} SQ_ROUND_MODE;
15022
15023/*
15024 * SQ_INTERRUPT_WORD_ENCODING enum
15025 */
15026
15027typedef enum SQ_INTERRUPT_WORD_ENCODING {
15028SQ_INTERRUPT_WORD_ENCODING_AUTO          = 0x00000000,
15029SQ_INTERRUPT_WORD_ENCODING_INST          = 0x00000001,
15030SQ_INTERRUPT_WORD_ENCODING_ERROR         = 0x00000002,
15031} SQ_INTERRUPT_WORD_ENCODING;
15032
15033/*
15034 * ENUM_SQ_EXPORT_RAT_INST enum
15035 */
15036
15037typedef enum ENUM_SQ_EXPORT_RAT_INST {
15038SQ_EXPORT_RAT_INST_NOP                   = 0x00000000,
15039SQ_EXPORT_RAT_INST_STORE_TYPED           = 0x00000001,
15040SQ_EXPORT_RAT_INST_STORE_RAW             = 0x00000002,
15041SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM     = 0x00000003,
15042SQ_EXPORT_RAT_INST_CMPXCHG_INT           = 0x00000004,
15043SQ_EXPORT_RAT_INST_CMPXCHG_FLT           = 0x00000005,
15044SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM       = 0x00000006,
15045SQ_EXPORT_RAT_INST_ADD                   = 0x00000007,
15046SQ_EXPORT_RAT_INST_SUB                   = 0x00000008,
15047SQ_EXPORT_RAT_INST_RSUB                  = 0x00000009,
15048SQ_EXPORT_RAT_INST_MIN_INT               = 0x0000000a,
15049SQ_EXPORT_RAT_INST_MIN_UINT              = 0x0000000b,
15050SQ_EXPORT_RAT_INST_MAX_INT               = 0x0000000c,
15051SQ_EXPORT_RAT_INST_MAX_UINT              = 0x0000000d,
15052SQ_EXPORT_RAT_INST_AND                   = 0x0000000e,
15053SQ_EXPORT_RAT_INST_OR                    = 0x0000000f,
15054SQ_EXPORT_RAT_INST_XOR                   = 0x00000010,
15055SQ_EXPORT_RAT_INST_MSKOR                 = 0x00000011,
15056SQ_EXPORT_RAT_INST_INC_UINT              = 0x00000012,
15057SQ_EXPORT_RAT_INST_DEC_UINT              = 0x00000013,
15058SQ_EXPORT_RAT_INST_STORE_DWORD           = 0x00000014,
15059SQ_EXPORT_RAT_INST_STORE_SHORT           = 0x00000015,
15060SQ_EXPORT_RAT_INST_STORE_BYTE            = 0x00000016,
15061SQ_EXPORT_RAT_INST_NOP_RTN               = 0x00000020,
15062SQ_EXPORT_RAT_INST_XCHG_RTN              = 0x00000022,
15063SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN      = 0x00000023,
15064SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN       = 0x00000024,
15065SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN       = 0x00000025,
15066SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN   = 0x00000026,
15067SQ_EXPORT_RAT_INST_ADD_RTN               = 0x00000027,
15068SQ_EXPORT_RAT_INST_SUB_RTN               = 0x00000028,
15069SQ_EXPORT_RAT_INST_RSUB_RTN              = 0x00000029,
15070SQ_EXPORT_RAT_INST_MIN_INT_RTN           = 0x0000002a,
15071SQ_EXPORT_RAT_INST_MIN_UINT_RTN          = 0x0000002b,
15072SQ_EXPORT_RAT_INST_MAX_INT_RTN           = 0x0000002c,
15073SQ_EXPORT_RAT_INST_MAX_UINT_RTN          = 0x0000002d,
15074SQ_EXPORT_RAT_INST_AND_RTN               = 0x0000002e,
15075SQ_EXPORT_RAT_INST_OR_RTN                = 0x0000002f,
15076SQ_EXPORT_RAT_INST_XOR_RTN               = 0x00000030,
15077SQ_EXPORT_RAT_INST_MSKOR_RTN             = 0x00000031,
15078SQ_EXPORT_RAT_INST_INC_UINT_RTN          = 0x00000032,
15079SQ_EXPORT_RAT_INST_DEC_UINT_RTN          = 0x00000033,
15080} ENUM_SQ_EXPORT_RAT_INST;
15081
15082/*
15083 * SQ_IBUF_ST enum
15084 */
15085
15086typedef enum SQ_IBUF_ST {
15087SQ_IBUF_IB_IDLE                          = 0x00000000,
15088SQ_IBUF_IB_INI_WAIT_GNT                  = 0x00000001,
15089SQ_IBUF_IB_INI_WAIT_DRET                 = 0x00000002,
15090SQ_IBUF_IB_LE_4DW                        = 0x00000003,
15091SQ_IBUF_IB_WAIT_DRET                     = 0x00000004,
15092SQ_IBUF_IB_EMPTY_WAIT_DRET               = 0x00000005,
15093SQ_IBUF_IB_DRET                          = 0x00000006,
15094SQ_IBUF_IB_EMPTY_WAIT_GNT                = 0x00000007,
15095} SQ_IBUF_ST;
15096
15097/*
15098 * SQ_INST_STR_ST enum
15099 */
15100
15101typedef enum SQ_INST_STR_ST {
15102SQ_INST_STR_IB_WAVE_NORML                = 0x00000000,
15103SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV    = 0x00000001,
15104SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV     = 0x00000002,
15105SQ_INST_STR_IB_WAVE_INST_SKIP_AV         = 0x00000003,
15106SQ_INST_STR_IB_WAVE_SETVSKIP_ST0         = 0x00000004,
15107SQ_INST_STR_IB_WAVE_SETVSKIP_ST1         = 0x00000005,
15108SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT       = 0x00000006,
15109SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT  = 0x00000007,
15110} SQ_INST_STR_ST;
15111
15112/*
15113 * SQ_WAVE_IB_ECC_ST enum
15114 */
15115
15116typedef enum SQ_WAVE_IB_ECC_ST {
15117SQ_WAVE_IB_ECC_CLEAN                     = 0x00000000,
15118SQ_WAVE_IB_ECC_ERR_CONTINUE              = 0x00000001,
15119SQ_WAVE_IB_ECC_ERR_HALT                  = 0x00000002,
15120SQ_WAVE_IB_ECC_WITH_ERR_MSG              = 0x00000003,
15121} SQ_WAVE_IB_ECC_ST;
15122
15123/*
15124 * SH_MEM_ADDRESS_MODE enum
15125 */
15126
15127typedef enum SH_MEM_ADDRESS_MODE {
15128SH_MEM_ADDRESS_MODE_64                   = 0x00000000,
15129SH_MEM_ADDRESS_MODE_32                   = 0x00000001,
15130} SH_MEM_ADDRESS_MODE;
15131
15132/*
15133 * SH_MEM_ALIGNMENT_MODE enum
15134 */
15135
15136typedef enum SH_MEM_ALIGNMENT_MODE {
15137SH_MEM_ALIGNMENT_MODE_DWORD              = 0x00000000,
15138SH_MEM_ALIGNMENT_MODE_DWORD_STRICT       = 0x00000001,
15139SH_MEM_ALIGNMENT_MODE_STRICT             = 0x00000002,
15140SH_MEM_ALIGNMENT_MODE_UNALIGNED          = 0x00000003,
15141} SH_MEM_ALIGNMENT_MODE;
15142
15143/*
15144 * SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX enum
15145 */
15146
15147typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
15148SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC  = 0x00000018,
15149SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE  = 0x00000019,
15150} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;
15151
15152/*
15153 * SQ_LB_CTR_SEL_VALUES enum
15154 */
15155
15156typedef enum SQ_LB_CTR_SEL_VALUES {
15157SQ_LB_CTR_SEL_ALU_CYCLES                 = 0x00000000,
15158SQ_LB_CTR_SEL_ALU_STALLS                 = 0x00000001,
15159SQ_LB_CTR_SEL_TEX_CYCLES                 = 0x00000002,
15160SQ_LB_CTR_SEL_TEX_STALLS                 = 0x00000003,
15161SQ_LB_CTR_SEL_SALU_CYCLES                = 0x00000004,
15162SQ_LB_CTR_SEL_SCALAR_STALLS              = 0x00000005,
15163SQ_LB_CTR_SEL_SMEM_CYCLES                = 0x00000006,
15164SQ_LB_CTR_SEL_ICACHE_STALLS              = 0x00000007,
15165SQ_LB_CTR_SEL_DCACHE_STALLS              = 0x00000008,
15166SQ_LB_CTR_SEL_RESERVED0                  = 0x00000009,
15167SQ_LB_CTR_SEL_RESERVED1                  = 0x0000000a,
15168SQ_LB_CTR_SEL_RESERVED2                  = 0x0000000b,
15169SQ_LB_CTR_SEL_RESERVED3                  = 0x0000000c,
15170SQ_LB_CTR_SEL_RESERVED4                  = 0x0000000d,
15171SQ_LB_CTR_SEL_RESERVED5                  = 0x0000000e,
15172SQ_LB_CTR_SEL_RESERVED6                  = 0x0000000f,
15173} SQ_LB_CTR_SEL_VALUES;
15174
15175/*
15176 * SQ_WAVE_TYPE value
15177 */
15178
15179#define SQ_WAVE_TYPE_PS0               0x00000000
15180
15181/*
15182 * SQIND_PARTITIONS value
15183 */
15184
15185#define SQIND_GLOBAL_REGS_OFFSET       0x00000000
15186#define SQIND_GLOBAL_REGS_SIZE         0x00000008
15187#define SQIND_LOCAL_REGS_OFFSET        0x00000008
15188#define SQIND_LOCAL_REGS_SIZE          0x00000008
15189#define SQIND_WAVE_HWREGS_OFFSET       0x00000010
15190#define SQIND_WAVE_HWREGS_SIZE         0x000001f0
15191#define SQIND_WAVE_SGPRS_OFFSET        0x00000200
15192#define SQIND_WAVE_SGPRS_SIZE          0x00000200
15193#define SQIND_WAVE_VGPRS_OFFSET        0x00000400
15194#define SQIND_WAVE_VGPRS_SIZE          0x00000100
15195
15196/*
15197 * SQ_GFXDEC value
15198 */
15199
15200#define SQ_GFXDEC_BEGIN                0x0000a000
15201#define SQ_GFXDEC_END                  0x0000c000
15202#define SQ_GFXDEC_STATE_ID_SHIFT       0x0000000a
15203
15204/*
15205 * SQDEC value
15206 */
15207
15208#define SQDEC_BEGIN                    0x00002300
15209#define SQDEC_END                      0x000023ff
15210
15211/*
15212 * SQPERFSDEC value
15213 */
15214
15215#define SQPERFSDEC_BEGIN               0x0000d9c0
15216#define SQPERFSDEC_END                 0x0000da40
15217
15218/*
15219 * SQPERFDDEC value
15220 */
15221
15222#define SQPERFDDEC_BEGIN               0x0000d1c0
15223#define SQPERFDDEC_END                 0x0000d240
15224
15225/*
15226 * SQGFXUDEC value
15227 */
15228
15229#define SQGFXUDEC_BEGIN                0x0000c330
15230#define SQGFXUDEC_END                  0x0000c380
15231
15232/*
15233 * SQPWRDEC value
15234 */
15235
15236#define SQPWRDEC_BEGIN                 0x0000f08c
15237#define SQPWRDEC_END                   0x0000f094
15238
15239/*
15240 * SQ_DISPATCHER value
15241 */
15242
15243#define SQ_DISPATCHER_GFX_MIN          0x00000010
15244#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
15245
15246/*
15247 * SQ_MAX value
15248 */
15249
15250#define SQ_MAX_PGM_SGPRS               0x00000068
15251#define SQ_MAX_PGM_VGPRS               0x00000100
15252
15253/*
15254 * SQ_THREAD_TRACE_TIME_UNIT value
15255 */
15256
15257#define SQ_THREAD_TRACE_TIME_UNIT      0x00000004
15258
15259/*
15260 * SQ_EXCP_BITS value
15261 */
15262
15263#define SQ_EX_MODE_EXCP_VALU_BASE      0x00000000
15264#define SQ_EX_MODE_EXCP_VALU_SIZE      0x00000007
15265#define SQ_EX_MODE_EXCP_INVALID        0x00000000
15266#define SQ_EX_MODE_EXCP_INPUT_DENORM   0x00000001
15267#define SQ_EX_MODE_EXCP_DIV0           0x00000002
15268#define SQ_EX_MODE_EXCP_OVERFLOW       0x00000003
15269#define SQ_EX_MODE_EXCP_UNDERFLOW      0x00000004
15270#define SQ_EX_MODE_EXCP_INEXACT        0x00000005
15271#define SQ_EX_MODE_EXCP_INT_DIV0       0x00000006
15272#define SQ_EX_MODE_EXCP_ADDR_WATCH0    0x00000007
15273#define SQ_EX_MODE_EXCP_MEM_VIOL       0x00000008
15274
15275/*
15276 * SQ_EXCP_HI_BITS value
15277 */
15278
15279#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
15280#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
15281#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
15282
15283/*
15284 * HW_INSERTED_INST_ID value
15285 */
15286
15287#define INST_ID_PRIV_START             0x80000000
15288#define INST_ID_ECC_INTERRUPT_MSG      0xfffffff0
15289#define INST_ID_TTRACE_NEW_PC_MSG      0xfffffff1
15290#define INST_ID_HW_TRAP                0xfffffff2
15291#define INST_ID_KILL_SEQ               0xfffffff3
15292#define INST_ID_SPI_WREXEC             0xfffffff4
15293#define INST_ID_HOST_REG_TRAP_MSG      0xfffffffe
15294
15295/*
15296 * SIMM16_WAITCNT_PARTITIONS value
15297 */
15298
15299#define SIMM16_WAITCNT_VM_CNT_START    0x00000000
15300#define SIMM16_WAITCNT_VM_CNT_SIZE     0x00000004
15301#define SIMM16_WAITCNT_EXP_CNT_START   0x00000004
15302#define SIMM16_WAITCNT_EXP_CNT_SIZE    0x00000003
15303#define SIMM16_WAITCNT_LGKM_CNT_START  0x00000008
15304#define SIMM16_WAITCNT_LGKM_CNT_SIZE   0x00000004
15305#define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e
15306#define SIMM16_WAITCNT_VM_CNT_HI_SIZE  0x00000002
15307
15308/*
15309 * SQ_EDC_FUE_CNTL_BITS value
15310 */
15311
15312#define SQ_EDC_FUE_CNTL_SQ             0x00000000
15313#define SQ_EDC_FUE_CNTL_LDS            0x00000001
15314#define SQ_EDC_FUE_CNTL_SIMD0          0x00000002
15315#define SQ_EDC_FUE_CNTL_SIMD1          0x00000003
15316#define SQ_EDC_FUE_CNTL_SIMD2          0x00000004
15317#define SQ_EDC_FUE_CNTL_SIMD3          0x00000005
15318#define SQ_EDC_FUE_CNTL_TA             0x00000006
15319#define SQ_EDC_FUE_CNTL_TD             0x00000007
15320#define SQ_EDC_FUE_CNTL_TCP            0x00000008
15321
15322/*******************************************************
15323 * COMP Enums
15324 *******************************************************/
15325
15326/*
15327 * CSDATA_TYPE enum
15328 */
15329
15330typedef enum CSDATA_TYPE {
15331CSDATA_TYPE_TG                           = 0x00000000,
15332CSDATA_TYPE_STATE                        = 0x00000001,
15333CSDATA_TYPE_EVENT                        = 0x00000002,
15334CSDATA_TYPE_PRIVATE                      = 0x00000003,
15335} CSDATA_TYPE;
15336
15337/*
15338 * CSDATA_TYPE_WIDTH value
15339 */
15340
15341#define CSDATA_TYPE_WIDTH              0x00000002
15342
15343/*
15344 * CSDATA_ADDR_WIDTH value
15345 */
15346
15347#define CSDATA_ADDR_WIDTH              0x00000007
15348
15349/*
15350 * CSDATA_DATA_WIDTH value
15351 */
15352
15353#define CSDATA_DATA_WIDTH              0x00000020
15354
15355/*******************************************************
15356 * VGT Enums
15357 *******************************************************/
15358
15359/*
15360 * VGT_OUT_PRIM_TYPE enum
15361 */
15362
15363typedef enum VGT_OUT_PRIM_TYPE {
15364VGT_OUT_POINT                            = 0x00000000,
15365VGT_OUT_LINE                             = 0x00000001,
15366VGT_OUT_TRI                              = 0x00000002,
15367VGT_OUT_RECT_V0                          = 0x00000003,
15368VGT_OUT_RECT_V1                          = 0x00000004,
15369VGT_OUT_RECT_V2                          = 0x00000005,
15370VGT_OUT_RECT_V3                          = 0x00000006,
15371VGT_OUT_2D_RECT                          = 0x00000007,
15372VGT_TE_QUAD                              = 0x00000008,
15373VGT_TE_PRIM_INDEX_LINE                   = 0x00000009,
15374VGT_TE_PRIM_INDEX_TRI                    = 0x0000000a,
15375VGT_TE_PRIM_INDEX_QUAD                   = 0x0000000b,
15376VGT_OUT_LINE_ADJ                         = 0x0000000c,
15377VGT_OUT_TRI_ADJ                          = 0x0000000d,
15378VGT_OUT_PATCH                            = 0x0000000e,
15379} VGT_OUT_PRIM_TYPE;
15380
15381/*
15382 * VGT_DI_PRIM_TYPE enum
15383 */
15384
15385typedef enum VGT_DI_PRIM_TYPE {
15386DI_PT_NONE                               = 0x00000000,
15387DI_PT_POINTLIST                          = 0x00000001,
15388DI_PT_LINELIST                           = 0x00000002,
15389DI_PT_LINESTRIP                          = 0x00000003,
15390DI_PT_TRILIST                            = 0x00000004,
15391DI_PT_TRIFAN                             = 0x00000005,
15392DI_PT_TRISTRIP                           = 0x00000006,
15393DI_PT_2D_RECTANGLE                       = 0x00000007,
15394DI_PT_UNUSED_1                           = 0x00000008,
15395DI_PT_PATCH                              = 0x00000009,
15396DI_PT_LINELIST_ADJ                       = 0x0000000a,
15397DI_PT_LINESTRIP_ADJ                      = 0x0000000b,
15398DI_PT_TRILIST_ADJ                        = 0x0000000c,
15399DI_PT_TRISTRIP_ADJ                       = 0x0000000d,
15400DI_PT_UNUSED_3                           = 0x0000000e,
15401DI_PT_UNUSED_4                           = 0x0000000f,
15402DI_PT_TRI_WITH_WFLAGS                    = 0x00000010,
15403DI_PT_RECTLIST                           = 0x00000011,
15404DI_PT_LINELOOP                           = 0x00000012,
15405DI_PT_QUADLIST                           = 0x00000013,
15406DI_PT_QUADSTRIP                          = 0x00000014,
15407DI_PT_POLYGON                            = 0x00000015,
15408} VGT_DI_PRIM_TYPE;
15409
15410/*
15411 * VGT_DI_SOURCE_SELECT enum
15412 */
15413
15414typedef enum VGT_DI_SOURCE_SELECT {
15415DI_SRC_SEL_DMA                           = 0x00000000,
15416DI_SRC_SEL_IMMEDIATE                     = 0x00000001,
15417DI_SRC_SEL_AUTO_INDEX                    = 0x00000002,
15418DI_SRC_SEL_RESERVED                      = 0x00000003,
15419} VGT_DI_SOURCE_SELECT;
15420
15421/*
15422 * VGT_DI_MAJOR_MODE_SELECT enum
15423 */
15424
15425typedef enum VGT_DI_MAJOR_MODE_SELECT {
15426DI_MAJOR_MODE_0                          = 0x00000000,
15427DI_MAJOR_MODE_1                          = 0x00000001,
15428} VGT_DI_MAJOR_MODE_SELECT;
15429
15430/*
15431 * VGT_DI_INDEX_SIZE enum
15432 */
15433
15434typedef enum VGT_DI_INDEX_SIZE {
15435DI_INDEX_SIZE_16_BIT                     = 0x00000000,
15436DI_INDEX_SIZE_32_BIT                     = 0x00000001,
15437DI_INDEX_SIZE_8_BIT                      = 0x00000002,
15438} VGT_DI_INDEX_SIZE;
15439
15440/*
15441 * VGT_EVENT_TYPE enum
15442 */
15443
15444typedef enum VGT_EVENT_TYPE {
15445Reserved_0x00                            = 0x00000000,
15446SAMPLE_STREAMOUTSTATS1                   = 0x00000001,
15447SAMPLE_STREAMOUTSTATS2                   = 0x00000002,
15448SAMPLE_STREAMOUTSTATS3                   = 0x00000003,
15449CACHE_FLUSH_TS                           = 0x00000004,
15450CONTEXT_DONE                             = 0x00000005,
15451CACHE_FLUSH                              = 0x00000006,
15452CS_PARTIAL_FLUSH                         = 0x00000007,
15453VGT_STREAMOUT_SYNC                       = 0x00000008,
15454Reserved_0x09                            = 0x00000009,
15455VGT_STREAMOUT_RESET                      = 0x0000000a,
15456END_OF_PIPE_INCR_DE                      = 0x0000000b,
15457END_OF_PIPE_IB_END                       = 0x0000000c,
15458RST_PIX_CNT                              = 0x0000000d,
15459BREAK_BATCH                              = 0x0000000e,
15460VS_PARTIAL_FLUSH                         = 0x0000000f,
15461PS_PARTIAL_FLUSH                         = 0x00000010,
15462FLUSH_HS_OUTPUT                          = 0x00000011,
15463FLUSH_DFSM                               = 0x00000012,
15464RESET_TO_LOWEST_VGT                      = 0x00000013,
15465CACHE_FLUSH_AND_INV_TS_EVENT             = 0x00000014,
15466ZPASS_DONE                               = 0x00000015,
15467CACHE_FLUSH_AND_INV_EVENT                = 0x00000016,
15468PERFCOUNTER_START                        = 0x00000017,
15469PERFCOUNTER_STOP                         = 0x00000018,
15470PIPELINESTAT_START                       = 0x00000019,
15471PIPELINESTAT_STOP                        = 0x0000001a,
15472PERFCOUNTER_SAMPLE                       = 0x0000001b,
15473Available_0x1c                           = 0x0000001c,
15474Available_0x1d                           = 0x0000001d,
15475SAMPLE_PIPELINESTAT                      = 0x0000001e,
15476SO_VGTSTREAMOUT_FLUSH                    = 0x0000001f,
15477SAMPLE_STREAMOUTSTATS                    = 0x00000020,
15478RESET_VTX_CNT                            = 0x00000021,
15479BLOCK_CONTEXT_DONE                       = 0x00000022,
15480CS_CONTEXT_DONE                          = 0x00000023,
15481VGT_FLUSH                                = 0x00000024,
15482TGID_ROLLOVER                            = 0x00000025,
15483SQ_NON_EVENT                             = 0x00000026,
15484SC_SEND_DB_VPZ                           = 0x00000027,
15485BOTTOM_OF_PIPE_TS                        = 0x00000028,
15486FLUSH_SX_TS                              = 0x00000029,
15487DB_CACHE_FLUSH_AND_INV                   = 0x0000002a,
15488FLUSH_AND_INV_DB_DATA_TS                 = 0x0000002b,
15489FLUSH_AND_INV_DB_META                    = 0x0000002c,
15490FLUSH_AND_INV_CB_DATA_TS                 = 0x0000002d,
15491FLUSH_AND_INV_CB_META                    = 0x0000002e,
15492CS_DONE                                  = 0x0000002f,
15493PS_DONE                                  = 0x00000030,
15494FLUSH_AND_INV_CB_PIXEL_DATA              = 0x00000031,
15495SX_CB_RAT_ACK_REQUEST                    = 0x00000032,
15496THREAD_TRACE_START                       = 0x00000033,
15497THREAD_TRACE_STOP                        = 0x00000034,
15498THREAD_TRACE_MARKER                      = 0x00000035,
15499THREAD_TRACE_FLUSH                       = 0x00000036,
15500THREAD_TRACE_FINISH                      = 0x00000037,
15501PIXEL_PIPE_STAT_CONTROL                  = 0x00000038,
15502PIXEL_PIPE_STAT_DUMP                     = 0x00000039,
15503PIXEL_PIPE_STAT_RESET                    = 0x0000003a,
15504CONTEXT_SUSPEND                          = 0x0000003b,
15505OFFCHIP_HS_DEALLOC                       = 0x0000003c,
15506ENABLE_NGG_PIPELINE                      = 0x0000003d,
15507ENABLE_LEGACY_PIPELINE                   = 0x0000003e,
15508Reserved_0x3f                            = 0x0000003f,
15509} VGT_EVENT_TYPE;
15510
15511/*
15512 * VGT_DMA_SWAP_MODE enum
15513 */
15514
15515typedef enum VGT_DMA_SWAP_MODE {
15516VGT_DMA_SWAP_NONE                        = 0x00000000,
15517VGT_DMA_SWAP_16_BIT                      = 0x00000001,
15518VGT_DMA_SWAP_32_BIT                      = 0x00000002,
15519VGT_DMA_SWAP_WORD                        = 0x00000003,
15520} VGT_DMA_SWAP_MODE;
15521
15522/*
15523 * VGT_INDEX_TYPE_MODE enum
15524 */
15525
15526typedef enum VGT_INDEX_TYPE_MODE {
15527VGT_INDEX_16                             = 0x00000000,
15528VGT_INDEX_32                             = 0x00000001,
15529VGT_INDEX_8                              = 0x00000002,
15530} VGT_INDEX_TYPE_MODE;
15531
15532/*
15533 * VGT_DMA_BUF_TYPE enum
15534 */
15535
15536typedef enum VGT_DMA_BUF_TYPE {
15537VGT_DMA_BUF_MEM                          = 0x00000000,
15538VGT_DMA_BUF_RING                         = 0x00000001,
15539VGT_DMA_BUF_SETUP                        = 0x00000002,
15540VGT_DMA_PTR_UPDATE                       = 0x00000003,
15541} VGT_DMA_BUF_TYPE;
15542
15543/*
15544 * VGT_OUTPATH_SELECT enum
15545 */
15546
15547typedef enum VGT_OUTPATH_SELECT {
15548VGT_OUTPATH_VTX_REUSE                    = 0x00000000,
15549VGT_OUTPATH_TESS_EN                      = 0x00000001,
15550VGT_OUTPATH_PASSTHRU                     = 0x00000002,
15551VGT_OUTPATH_GS_BLOCK                     = 0x00000003,
15552VGT_OUTPATH_HS_BLOCK                     = 0x00000004,
15553VGT_OUTPATH_PRIM_GEN                     = 0x00000005,
15554} VGT_OUTPATH_SELECT;
15555
15556/*
15557 * VGT_GRP_PRIM_TYPE enum
15558 */
15559
15560typedef enum VGT_GRP_PRIM_TYPE {
15561VGT_GRP_3D_POINT                         = 0x00000000,
15562VGT_GRP_3D_LINE                          = 0x00000001,
15563VGT_GRP_3D_TRI                           = 0x00000002,
15564VGT_GRP_3D_RECT                          = 0x00000003,
15565VGT_GRP_3D_QUAD                          = 0x00000004,
15566VGT_GRP_2D_COPY_RECT_V0                  = 0x00000005,
15567VGT_GRP_2D_COPY_RECT_V1                  = 0x00000006,
15568VGT_GRP_2D_COPY_RECT_V2                  = 0x00000007,
15569VGT_GRP_2D_COPY_RECT_V3                  = 0x00000008,
15570VGT_GRP_2D_FILL_RECT                     = 0x00000009,
15571VGT_GRP_2D_LINE                          = 0x0000000a,
15572VGT_GRP_2D_TRI                           = 0x0000000b,
15573VGT_GRP_PRIM_INDEX_LINE                  = 0x0000000c,
15574VGT_GRP_PRIM_INDEX_TRI                   = 0x0000000d,
15575VGT_GRP_PRIM_INDEX_QUAD                  = 0x0000000e,
15576VGT_GRP_3D_LINE_ADJ                      = 0x0000000f,
15577VGT_GRP_3D_TRI_ADJ                       = 0x00000010,
15578VGT_GRP_3D_PATCH                         = 0x00000011,
15579VGT_GRP_2D_RECT                          = 0x00000012,
15580} VGT_GRP_PRIM_TYPE;
15581
15582/*
15583 * VGT_GRP_PRIM_ORDER enum
15584 */
15585
15586typedef enum VGT_GRP_PRIM_ORDER {
15587VGT_GRP_LIST                             = 0x00000000,
15588VGT_GRP_STRIP                            = 0x00000001,
15589VGT_GRP_FAN                              = 0x00000002,
15590VGT_GRP_LOOP                             = 0x00000003,
15591VGT_GRP_POLYGON                          = 0x00000004,
15592} VGT_GRP_PRIM_ORDER;
15593
15594/*
15595 * VGT_GROUP_CONV_SEL enum
15596 */
15597
15598typedef enum VGT_GROUP_CONV_SEL {
15599VGT_GRP_INDEX_16                         = 0x00000000,
15600VGT_GRP_INDEX_32                         = 0x00000001,
15601VGT_GRP_UINT_16                          = 0x00000002,
15602VGT_GRP_UINT_32                          = 0x00000003,
15603VGT_GRP_SINT_16                          = 0x00000004,
15604VGT_GRP_SINT_32                          = 0x00000005,
15605VGT_GRP_FLOAT_32                         = 0x00000006,
15606VGT_GRP_AUTO_PRIM                        = 0x00000007,
15607VGT_GRP_FIX_1_23_TO_FLOAT                = 0x00000008,
15608} VGT_GROUP_CONV_SEL;
15609
15610/*
15611 * VGT_GS_MODE_TYPE enum
15612 */
15613
15614typedef enum VGT_GS_MODE_TYPE {
15615GS_OFF                                   = 0x00000000,
15616GS_SCENARIO_A                            = 0x00000001,
15617GS_SCENARIO_B                            = 0x00000002,
15618GS_SCENARIO_G                            = 0x00000003,
15619GS_SCENARIO_C                            = 0x00000004,
15620SPRITE_EN                                = 0x00000005,
15621} VGT_GS_MODE_TYPE;
15622
15623/*
15624 * VGT_GS_CUT_MODE enum
15625 */
15626
15627typedef enum VGT_GS_CUT_MODE {
15628GS_CUT_1024                              = 0x00000000,
15629GS_CUT_512                               = 0x00000001,
15630GS_CUT_256                               = 0x00000002,
15631GS_CUT_128                               = 0x00000003,
15632} VGT_GS_CUT_MODE;
15633
15634/*
15635 * VGT_GS_OUTPRIM_TYPE enum
15636 */
15637
15638typedef enum VGT_GS_OUTPRIM_TYPE {
15639POINTLIST                                = 0x00000000,
15640LINESTRIP                                = 0x00000001,
15641TRISTRIP                                 = 0x00000002,
15642RECTLIST                                 = 0x00000003,
15643} VGT_GS_OUTPRIM_TYPE;
15644
15645/*
15646 * VGT_CACHE_INVALID_MODE enum
15647 */
15648
15649typedef enum VGT_CACHE_INVALID_MODE {
15650VC_ONLY                                  = 0x00000000,
15651TC_ONLY                                  = 0x00000001,
15652VC_AND_TC                                = 0x00000002,
15653} VGT_CACHE_INVALID_MODE;
15654
15655/*
15656 * VGT_TESS_TYPE enum
15657 */
15658
15659typedef enum VGT_TESS_TYPE {
15660TESS_ISOLINE                             = 0x00000000,
15661TESS_TRIANGLE                            = 0x00000001,
15662TESS_QUAD                                = 0x00000002,
15663} VGT_TESS_TYPE;
15664
15665/*
15666 * VGT_TESS_PARTITION enum
15667 */
15668
15669typedef enum VGT_TESS_PARTITION {
15670PART_INTEGER                             = 0x00000000,
15671PART_POW2                                = 0x00000001,
15672PART_FRAC_ODD                            = 0x00000002,
15673PART_FRAC_EVEN                           = 0x00000003,
15674} VGT_TESS_PARTITION;
15675
15676/*
15677 * VGT_TESS_TOPOLOGY enum
15678 */
15679
15680typedef enum VGT_TESS_TOPOLOGY {
15681OUTPUT_POINT                             = 0x00000000,
15682OUTPUT_LINE                              = 0x00000001,
15683OUTPUT_TRIANGLE_CW                       = 0x00000002,
15684OUTPUT_TRIANGLE_CCW                      = 0x00000003,
15685} VGT_TESS_TOPOLOGY;
15686
15687/*
15688 * VGT_RDREQ_POLICY enum
15689 */
15690
15691typedef enum VGT_RDREQ_POLICY {
15692VGT_POLICY_LRU                           = 0x00000000,
15693VGT_POLICY_STREAM                        = 0x00000001,
15694} VGT_RDREQ_POLICY;
15695
15696/*
15697 * VGT_DIST_MODE enum
15698 */
15699
15700typedef enum VGT_DIST_MODE {
15701NO_DIST                                  = 0x00000000,
15702PATCHES                                  = 0x00000001,
15703DONUTS                                   = 0x00000002,
15704TRAPEZOIDS                               = 0x00000003,
15705} VGT_DIST_MODE;
15706
15707/*
15708 * VGT_STAGES_LS_EN enum
15709 */
15710
15711typedef enum VGT_STAGES_LS_EN {
15712LS_STAGE_OFF                             = 0x00000000,
15713LS_STAGE_ON                              = 0x00000001,
15714CS_STAGE_ON                              = 0x00000002,
15715RESERVED_LS                              = 0x00000003,
15716} VGT_STAGES_LS_EN;
15717
15718/*
15719 * VGT_STAGES_HS_EN enum
15720 */
15721
15722typedef enum VGT_STAGES_HS_EN {
15723HS_STAGE_OFF                             = 0x00000000,
15724HS_STAGE_ON                              = 0x00000001,
15725} VGT_STAGES_HS_EN;
15726
15727/*
15728 * VGT_STAGES_ES_EN enum
15729 */
15730
15731typedef enum VGT_STAGES_ES_EN {
15732ES_STAGE_OFF                             = 0x00000000,
15733ES_STAGE_DS                              = 0x00000001,
15734ES_STAGE_REAL                            = 0x00000002,
15735RESERVED_ES                              = 0x00000003,
15736} VGT_STAGES_ES_EN;
15737
15738/*
15739 * VGT_STAGES_GS_EN enum
15740 */
15741
15742typedef enum VGT_STAGES_GS_EN {
15743GS_STAGE_OFF                             = 0x00000000,
15744GS_STAGE_ON                              = 0x00000001,
15745} VGT_STAGES_GS_EN;
15746
15747/*
15748 * VGT_STAGES_VS_EN enum
15749 */
15750
15751typedef enum VGT_STAGES_VS_EN {
15752VS_STAGE_REAL                            = 0x00000000,
15753VS_STAGE_DS                              = 0x00000001,
15754VS_STAGE_COPY_SHADER                     = 0x00000002,
15755RESERVED_VS                              = 0x00000003,
15756} VGT_STAGES_VS_EN;
15757
15758/*
15759 * VGT_PERFCOUNT_SELECT enum
15760 */
15761
15762typedef enum VGT_PERFCOUNT_SELECT {
15763vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE  = 0x00000000,
15764vgt_perf_VGT_SPI_ESVERT_VALID            = 0x00000001,
15765vgt_perf_VGT_SPI_ESVERT_EOV              = 0x00000002,
15766vgt_perf_VGT_SPI_ESVERT_STALLED          = 0x00000003,
15767vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY     = 0x00000004,
15768vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE     = 0x00000005,
15769vgt_perf_VGT_SPI_ESVERT_STATIC           = 0x00000006,
15770vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT       = 0x00000007,
15771vgt_perf_VGT_SPI_ESTHREAD_SEND           = 0x00000008,
15772vgt_perf_VGT_SPI_GSPRIM_VALID            = 0x00000009,
15773vgt_perf_VGT_SPI_GSPRIM_EOV              = 0x0000000a,
15774vgt_perf_VGT_SPI_GSPRIM_CONT             = 0x0000000b,
15775vgt_perf_VGT_SPI_GSPRIM_STALLED          = 0x0000000c,
15776vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY     = 0x0000000d,
15777vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE     = 0x0000000e,
15778vgt_perf_VGT_SPI_GSPRIM_STATIC           = 0x0000000f,
15779vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE  = 0x00000010,
15780vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT       = 0x00000011,
15781vgt_perf_VGT_SPI_GSTHREAD_SEND           = 0x00000012,
15782vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE  = 0x00000013,
15783vgt_perf_VGT_SPI_VSVERT_SEND             = 0x00000014,
15784vgt_perf_VGT_SPI_VSVERT_EOV              = 0x00000015,
15785vgt_perf_VGT_SPI_VSVERT_STALLED          = 0x00000016,
15786vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY     = 0x00000017,
15787vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE     = 0x00000018,
15788vgt_perf_VGT_SPI_VSVERT_STATIC           = 0x00000019,
15789vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT       = 0x0000001a,
15790vgt_perf_VGT_SPI_VSTHREAD_SEND           = 0x0000001b,
15791vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE      = 0x0000001c,
15792vgt_perf_VGT_PA_CLIPV_SEND               = 0x0000001d,
15793vgt_perf_VGT_PA_CLIPV_FIRSTVERT          = 0x0000001e,
15794vgt_perf_VGT_PA_CLIPV_STALLED            = 0x0000001f,
15795vgt_perf_VGT_PA_CLIPV_STARVED_BUSY       = 0x00000020,
15796vgt_perf_VGT_PA_CLIPV_STARVED_IDLE       = 0x00000021,
15797vgt_perf_VGT_PA_CLIPV_STATIC             = 0x00000022,
15798vgt_perf_VGT_PA_CLIPP_SEND               = 0x00000023,
15799vgt_perf_VGT_PA_CLIPP_EOP                = 0x00000024,
15800vgt_perf_VGT_PA_CLIPP_IS_EVENT           = 0x00000025,
15801vgt_perf_VGT_PA_CLIPP_NULL_PRIM          = 0x00000026,
15802vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT       = 0x00000027,
15803vgt_perf_VGT_PA_CLIPP_STALLED            = 0x00000028,
15804vgt_perf_VGT_PA_CLIPP_STARVED_BUSY       = 0x00000029,
15805vgt_perf_VGT_PA_CLIPP_STARVED_IDLE       = 0x0000002a,
15806vgt_perf_VGT_PA_CLIPP_STATIC             = 0x0000002b,
15807vgt_perf_VGT_PA_CLIPS_SEND               = 0x0000002c,
15808vgt_perf_VGT_PA_CLIPS_STALLED            = 0x0000002d,
15809vgt_perf_VGT_PA_CLIPS_STARVED_BUSY       = 0x0000002e,
15810vgt_perf_VGT_PA_CLIPS_STARVED_IDLE       = 0x0000002f,
15811vgt_perf_VGT_PA_CLIPS_STATIC             = 0x00000030,
15812vgt_perf_vsvert_ds_send                  = 0x00000031,
15813vgt_perf_vsvert_api_send                 = 0x00000032,
15814vgt_perf_hs_tif_stall                    = 0x00000033,
15815vgt_perf_hs_input_stall                  = 0x00000034,
15816vgt_perf_hs_interface_stall              = 0x00000035,
15817vgt_perf_hs_tfm_stall                    = 0x00000036,
15818vgt_perf_te11_starved                    = 0x00000037,
15819vgt_perf_gs_event_stall                  = 0x00000038,
15820vgt_perf_vgt_pa_clipp_send_not_event     = 0x00000039,
15821vgt_perf_vgt_pa_clipp_valid_prim         = 0x0000003a,
15822vgt_perf_reused_es_indices               = 0x0000003b,
15823vgt_perf_vs_cache_hits                   = 0x0000003c,
15824vgt_perf_gs_cache_hits                   = 0x0000003d,
15825vgt_perf_ds_cache_hits                   = 0x0000003e,
15826vgt_perf_total_cache_hits                = 0x0000003f,
15827vgt_perf_vgt_busy                        = 0x00000040,
15828vgt_perf_vgt_gs_busy                     = 0x00000041,
15829vgt_perf_esvert_stalled_es_tbl           = 0x00000042,
15830vgt_perf_esvert_stalled_gs_tbl           = 0x00000043,
15831vgt_perf_esvert_stalled_gs_event         = 0x00000044,
15832vgt_perf_esvert_stalled_gsprim           = 0x00000045,
15833vgt_perf_gsprim_stalled_es_tbl           = 0x00000046,
15834vgt_perf_gsprim_stalled_gs_tbl           = 0x00000047,
15835vgt_perf_gsprim_stalled_gs_event         = 0x00000048,
15836vgt_perf_gsprim_stalled_esvert           = 0x00000049,
15837vgt_perf_esthread_stalled_es_rb_full     = 0x0000004a,
15838vgt_perf_esthread_stalled_spi_bp         = 0x0000004b,
15839vgt_perf_counters_avail_stalled          = 0x0000004c,
15840vgt_perf_gs_rb_space_avail_stalled       = 0x0000004d,
15841vgt_perf_gs_issue_rtr_stalled            = 0x0000004e,
15842vgt_perf_gsthread_stalled                = 0x0000004f,
15843vgt_perf_strmout_stalled                 = 0x00000050,
15844vgt_perf_wait_for_es_done_stalled        = 0x00000051,
15845vgt_perf_cm_stalled_by_gog               = 0x00000052,
15846vgt_perf_cm_reading_stalled              = 0x00000053,
15847vgt_perf_cm_stalled_by_gsfetch_done      = 0x00000054,
15848vgt_perf_gog_vs_tbl_stalled              = 0x00000055,
15849vgt_perf_gog_out_indx_stalled            = 0x00000056,
15850vgt_perf_gog_out_prim_stalled            = 0x00000057,
15851vgt_perf_waveid_stalled                  = 0x00000058,
15852vgt_perf_gog_busy                        = 0x00000059,
15853vgt_perf_reused_vs_indices               = 0x0000005a,
15854vgt_perf_sclk_reg_vld_event              = 0x0000005b,
15855vgt_perf_vs_conflicting_indices          = 0x0000005c,
15856vgt_perf_sclk_core_vld_event             = 0x0000005d,
15857vgt_perf_hswave_stalled                  = 0x0000005e,
15858vgt_perf_sclk_gs_vld_event               = 0x0000005f,
15859vgt_perf_VGT_SPI_LSVERT_VALID            = 0x00000060,
15860vgt_perf_VGT_SPI_LSVERT_EOV              = 0x00000061,
15861vgt_perf_VGT_SPI_LSVERT_STALLED          = 0x00000062,
15862vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY     = 0x00000063,
15863vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE     = 0x00000064,
15864vgt_perf_VGT_SPI_LSVERT_STATIC           = 0x00000065,
15865vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE  = 0x00000066,
15866vgt_perf_VGT_SPI_LSWAVE_IS_EVENT         = 0x00000067,
15867vgt_perf_VGT_SPI_LSWAVE_SEND             = 0x00000068,
15868vgt_perf_VGT_SPI_HSVERT_VALID            = 0x00000069,
15869vgt_perf_VGT_SPI_HSVERT_EOV              = 0x0000006a,
15870vgt_perf_VGT_SPI_HSVERT_STALLED          = 0x0000006b,
15871vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY     = 0x0000006c,
15872vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE     = 0x0000006d,
15873vgt_perf_VGT_SPI_HSVERT_STATIC           = 0x0000006e,
15874vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE  = 0x0000006f,
15875vgt_perf_VGT_SPI_HSWAVE_IS_EVENT         = 0x00000070,
15876vgt_perf_VGT_SPI_HSWAVE_SEND             = 0x00000071,
15877vgt_perf_ds_prims                        = 0x00000072,
15878vgt_perf_ds_RESERVED                     = 0x00000073,
15879vgt_perf_ls_thread_groups                = 0x00000074,
15880vgt_perf_hs_thread_groups                = 0x00000075,
15881vgt_perf_es_thread_groups                = 0x00000076,
15882vgt_perf_vs_thread_groups                = 0x00000077,
15883vgt_perf_ls_done_latency                 = 0x00000078,
15884vgt_perf_hs_done_latency                 = 0x00000079,
15885vgt_perf_es_done_latency                 = 0x0000007a,
15886vgt_perf_gs_done_latency                 = 0x0000007b,
15887vgt_perf_vgt_hs_busy                     = 0x0000007c,
15888vgt_perf_vgt_te11_busy                   = 0x0000007d,
15889vgt_perf_ls_flush                        = 0x0000007e,
15890vgt_perf_hs_flush                        = 0x0000007f,
15891vgt_perf_es_flush                        = 0x00000080,
15892vgt_perf_vgt_pa_clipp_eopg               = 0x00000081,
15893vgt_perf_ls_done                         = 0x00000082,
15894vgt_perf_hs_done                         = 0x00000083,
15895vgt_perf_es_done                         = 0x00000084,
15896vgt_perf_gs_done                         = 0x00000085,
15897vgt_perf_vsfetch_done                    = 0x00000086,
15898vgt_perf_gs_done_received                = 0x00000087,
15899vgt_perf_es_ring_high_water_mark         = 0x00000088,
15900vgt_perf_gs_ring_high_water_mark         = 0x00000089,
15901vgt_perf_vs_table_high_water_mark        = 0x0000008a,
15902vgt_perf_hs_tgs_active_high_water_mark   = 0x0000008b,
15903vgt_perf_pa_clipp_dealloc                = 0x0000008c,
15904vgt_perf_cut_mem_flush_stalled           = 0x0000008d,
15905vgt_perf_vsvert_work_received            = 0x0000008e,
15906vgt_perf_vgt_pa_clipp_starved_after_work  = 0x0000008f,
15907vgt_perf_te11_con_starved_after_work     = 0x00000090,
15908vgt_perf_hs_waiting_on_ls_done_stall     = 0x00000091,
15909vgt_spi_vsvert_valid                     = 0x00000092,
15910} VGT_PERFCOUNT_SELECT;
15911
15912/*
15913 * IA_PERFCOUNT_SELECT enum
15914 */
15915
15916typedef enum IA_PERFCOUNT_SELECT {
15917ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE    = 0x00000000,
15918ia_perf_dma_data_fifo_full               = 0x00000001,
15919ia_perf_RESERVED1                        = 0x00000002,
15920ia_perf_RESERVED2                        = 0x00000003,
15921ia_perf_RESERVED3                        = 0x00000004,
15922ia_perf_RESERVED4                        = 0x00000005,
15923ia_perf_RESERVED5                        = 0x00000006,
15924ia_perf_MC_LAT_BIN_0                     = 0x00000007,
15925ia_perf_MC_LAT_BIN_1                     = 0x00000008,
15926ia_perf_MC_LAT_BIN_2                     = 0x00000009,
15927ia_perf_MC_LAT_BIN_3                     = 0x0000000a,
15928ia_perf_MC_LAT_BIN_4                     = 0x0000000b,
15929ia_perf_MC_LAT_BIN_5                     = 0x0000000c,
15930ia_perf_MC_LAT_BIN_6                     = 0x0000000d,
15931ia_perf_MC_LAT_BIN_7                     = 0x0000000e,
15932ia_perf_ia_busy                          = 0x0000000f,
15933ia_perf_ia_sclk_reg_vld_event            = 0x00000010,
15934ia_perf_RESERVED6                        = 0x00000011,
15935ia_perf_ia_sclk_core_vld_event           = 0x00000012,
15936ia_perf_RESERVED7                        = 0x00000013,
15937ia_perf_ia_dma_return                    = 0x00000014,
15938ia_perf_ia_stalled                       = 0x00000015,
15939ia_perf_shift_starved_pipe0_event        = 0x00000016,
15940ia_perf_shift_starved_pipe1_event        = 0x00000017,
15941} IA_PERFCOUNT_SELECT;
15942
15943/*
15944 * WD_PERFCOUNT_SELECT enum
15945 */
15946
15947typedef enum WD_PERFCOUNT_SELECT {
15948wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE   = 0x00000000,
15949wd_perf_RBIU_DR_FIFO_STARVED             = 0x00000001,
15950wd_perf_RBIU_DR_FIFO_STALLED             = 0x00000002,
15951wd_perf_RBIU_DI_FIFO_STARVED             = 0x00000003,
15952wd_perf_RBIU_DI_FIFO_STALLED             = 0x00000004,
15953wd_perf_wd_busy                          = 0x00000005,
15954wd_perf_wd_sclk_reg_vld_event            = 0x00000006,
15955wd_perf_wd_sclk_input_vld_event          = 0x00000007,
15956wd_perf_wd_sclk_core_vld_event           = 0x00000008,
15957wd_perf_wd_stalled                       = 0x00000009,
15958wd_perf_inside_tf_bin_0                  = 0x0000000a,
15959wd_perf_inside_tf_bin_1                  = 0x0000000b,
15960wd_perf_inside_tf_bin_2                  = 0x0000000c,
15961wd_perf_inside_tf_bin_3                  = 0x0000000d,
15962wd_perf_inside_tf_bin_4                  = 0x0000000e,
15963wd_perf_inside_tf_bin_5                  = 0x0000000f,
15964wd_perf_inside_tf_bin_6                  = 0x00000010,
15965wd_perf_inside_tf_bin_7                  = 0x00000011,
15966wd_perf_inside_tf_bin_8                  = 0x00000012,
15967wd_perf_tfreq_lat_bin_0                  = 0x00000013,
15968wd_perf_tfreq_lat_bin_1                  = 0x00000014,
15969wd_perf_tfreq_lat_bin_2                  = 0x00000015,
15970wd_perf_tfreq_lat_bin_3                  = 0x00000016,
15971wd_perf_tfreq_lat_bin_4                  = 0x00000017,
15972wd_perf_tfreq_lat_bin_5                  = 0x00000018,
15973wd_perf_tfreq_lat_bin_6                  = 0x00000019,
15974wd_perf_tfreq_lat_bin_7                  = 0x0000001a,
15975wd_starved_on_hs_done                    = 0x0000001b,
15976wd_perf_se0_hs_done_latency              = 0x0000001c,
15977wd_perf_se1_hs_done_latency              = 0x0000001d,
15978wd_perf_se2_hs_done_latency              = 0x0000001e,
15979wd_perf_se3_hs_done_latency              = 0x0000001f,
15980wd_perf_hs_done_se0                      = 0x00000020,
15981wd_perf_hs_done_se1                      = 0x00000021,
15982wd_perf_hs_done_se2                      = 0x00000022,
15983wd_perf_hs_done_se3                      = 0x00000023,
15984wd_perf_null_patches                     = 0x00000024,
15985} WD_PERFCOUNT_SELECT;
15986
15987/*
15988 * WD_IA_DRAW_TYPE enum
15989 */
15990
15991typedef enum WD_IA_DRAW_TYPE {
15992WD_IA_DRAW_TYPE_DI_MM0                   = 0x00000000,
15993WD_IA_DRAW_TYPE_REG_XFER                 = 0x00000001,
15994WD_IA_DRAW_TYPE_EVENT_INIT               = 0x00000002,
15995WD_IA_DRAW_TYPE_EVENT_ADDR               = 0x00000003,
15996WD_IA_DRAW_TYPE_MIN_INDX                 = 0x00000004,
15997WD_IA_DRAW_TYPE_MAX_INDX                 = 0x00000005,
15998WD_IA_DRAW_TYPE_INDX_OFF                 = 0x00000006,
15999WD_IA_DRAW_TYPE_IMM_DATA                 = 0x00000007,
16000} WD_IA_DRAW_TYPE;

16001
16002/*
16003 * WD_IA_DRAW_REG_XFER enum
16004 */
16005
16006typedef enum WD_IA_DRAW_REG_XFER {
16007WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM   = 0x00000000,
16008WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
16009} WD_IA_DRAW_REG_XFER;
16010
16011/*
16012 * WD_IA_DRAW_SOURCE enum
16013 */
16014
16015typedef enum WD_IA_DRAW_SOURCE {
16016WD_IA_DRAW_SOURCE_DMA                    = 0x00000000,
16017WD_IA_DRAW_SOURCE_IMMD                   = 0x00000001,
16018WD_IA_DRAW_SOURCE_AUTO                   = 0x00000002,
16019WD_IA_DRAW_SOURCE_OPAQ                   = 0x00000003,
16020} WD_IA_DRAW_SOURCE;
16021
16022/*
16023 * GS_THREADID_SIZE value
16024 */
16025
16026#define GSTHREADID_SIZE                0x00000002
16027
16028/*******************************************************
16029 * GB Enums
16030 *******************************************************/
16031
16032/*
16033 * GB_EDC_DED_MODE enum
16034 */
16035
16036typedef enum GB_EDC_DED_MODE {
16037GB_EDC_DED_MODE_LOG                      = 0x00000000,
16038GB_EDC_DED_MODE_HALT                     = 0x00000001,
16039GB_EDC_DED_MODE_INT_HALT                 = 0x00000002,
16040} GB_EDC_DED_MODE;
16041
16042/*
16043 * VALUE_GB_TILING_CONFIG_TABLE_SIZE value
16044 */
16045
16046#define GB_TILING_CONFIG_TABLE_SIZE    0x00000020
16047
16048/*
16049 * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value
16050 */
16051
16052#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010
16053
16054/*******************************************************
16055 * TP Enums
16056 *******************************************************/
16057
16058/*
16059 * TA_TC_ADDR_MODES enum
16060 */
16061
16062typedef enum TA_TC_ADDR_MODES {
16063TA_TC_ADDR_MODE_DEFAULT                  = 0x00000000,
16064TA_TC_ADDR_MODE_COMP0                    = 0x00000001,
16065TA_TC_ADDR_MODE_COMP1                    = 0x00000002,
16066TA_TC_ADDR_MODE_COMP2                    = 0x00000003,
16067TA_TC_ADDR_MODE_COMP3                    = 0x00000004,
16068TA_TC_ADDR_MODE_UNALIGNED                = 0x00000005,
16069TA_TC_ADDR_MODE_BORDER_COLOR             = 0x00000006,
16070} TA_TC_ADDR_MODES;
16071
16072/*
16073 * TA_PERFCOUNT_SEL enum
16074 */
16075
16076typedef enum TA_PERFCOUNT_SEL {
16077TA_PERF_SEL_NULL                         = 0x00000000,
16078TA_PERF_SEL_sh_fifo_busy                 = 0x00000001,
16079TA_PERF_SEL_sh_fifo_cmd_busy             = 0x00000002,
16080TA_PERF_SEL_sh_fifo_addr_busy            = 0x00000003,
16081TA_PERF_SEL_sh_fifo_data_busy            = 0x00000004,
16082TA_PERF_SEL_sh_fifo_data_sfifo_busy      = 0x00000005,
16083TA_PERF_SEL_sh_fifo_data_tfifo_busy      = 0x00000006,
16084TA_PERF_SEL_gradient_busy                = 0x00000007,
16085TA_PERF_SEL_gradient_fifo_busy           = 0x00000008,
16086TA_PERF_SEL_lod_busy                     = 0x00000009,
16087TA_PERF_SEL_lod_fifo_busy                = 0x0000000a,
16088TA_PERF_SEL_addresser_busy               = 0x0000000b,
16089TA_PERF_SEL_addresser_fifo_busy          = 0x0000000c,
16090TA_PERF_SEL_aligner_busy                 = 0x0000000d,
16091TA_PERF_SEL_write_path_busy              = 0x0000000e,
16092TA_PERF_SEL_ta_busy                      = 0x0000000f,
16093TA_PERF_SEL_sq_ta_cmd_cycles             = 0x00000010,
16094TA_PERF_SEL_sp_ta_addr_cycles            = 0x00000011,
16095TA_PERF_SEL_sp_ta_data_cycles            = 0x00000012,
16096TA_PERF_SEL_ta_fa_data_state_cycles      = 0x00000013,
16097TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles  = 0x00000014,
16098TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles  = 0x00000015,
16099TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles  = 0x00000016,
16100TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles  = 0x00000017,
16101TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles  = 0x00000018,
16102TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles  = 0x00000019,
16103TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles  = 0x0000001a,
16104TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles  = 0x0000001b,
16105TA_PERF_SEL_RESERVED_28                  = 0x0000001c,
16106TA_PERF_SEL_RESERVED_29                  = 0x0000001d,
16107TA_PERF_SEL_sh_fifo_addr_cycles          = 0x0000001e,
16108TA_PERF_SEL_sh_fifo_data_cycles          = 0x0000001f,
16109TA_PERF_SEL_total_wavefronts             = 0x00000020,
16110TA_PERF_SEL_gradient_cycles              = 0x00000021,
16111TA_PERF_SEL_walker_cycles                = 0x00000022,
16112TA_PERF_SEL_aligner_cycles               = 0x00000023,
16113TA_PERF_SEL_image_wavefronts             = 0x00000024,
16114TA_PERF_SEL_image_read_wavefronts        = 0x00000025,
16115TA_PERF_SEL_image_write_wavefronts       = 0x00000026,
16116TA_PERF_SEL_image_atomic_wavefronts      = 0x00000027,
16117TA_PERF_SEL_image_total_cycles           = 0x00000028,
16118TA_PERF_SEL_RESERVED_41                  = 0x00000029,
16119TA_PERF_SEL_RESERVED_42                  = 0x0000002a,
16120TA_PERF_SEL_RESERVED_43                  = 0x0000002b,
16121TA_PERF_SEL_buffer_wavefronts            = 0x0000002c,
16122TA_PERF_SEL_buffer_read_wavefronts       = 0x0000002d,
16123TA_PERF_SEL_buffer_write_wavefronts      = 0x0000002e,
16124TA_PERF_SEL_buffer_atomic_wavefronts     = 0x0000002f,
16125TA_PERF_SEL_buffer_coalescable_wavefronts  = 0x00000030,
16126TA_PERF_SEL_buffer_total_cycles          = 0x00000031,
16127TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles  = 0x00000032,
16128TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles  = 0x00000033,
16129TA_PERF_SEL_buffer_coalesced_read_cycles  = 0x00000034,
16130TA_PERF_SEL_buffer_coalesced_write_cycles  = 0x00000035,
16131TA_PERF_SEL_addr_stalled_by_tc_cycles    = 0x00000036,
16132TA_PERF_SEL_addr_stalled_by_td_cycles    = 0x00000037,
16133TA_PERF_SEL_data_stalled_by_tc_cycles    = 0x00000038,
16134TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles  = 0x00000039,
16135TA_PERF_SEL_addresser_stalled_cycles     = 0x0000003a,
16136TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles  = 0x0000003b,
16137TA_PERF_SEL_aniso_stalled_cycles         = 0x0000003c,
16138TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles  = 0x0000003d,
16139TA_PERF_SEL_deriv_stalled_cycles         = 0x0000003e,
16140TA_PERF_SEL_aniso_gt1_cycle_quads        = 0x0000003f,
16141TA_PERF_SEL_color_1_cycle_pixels         = 0x00000040,
16142TA_PERF_SEL_color_2_cycle_pixels         = 0x00000041,
16143TA_PERF_SEL_color_3_cycle_pixels         = 0x00000042,
16144TA_PERF_SEL_color_4_cycle_pixels         = 0x00000043,
16145TA_PERF_SEL_mip_1_cycle_pixels           = 0x00000044,
16146TA_PERF_SEL_mip_2_cycle_pixels           = 0x00000045,
16147TA_PERF_SEL_vol_1_cycle_pixels           = 0x00000046,
16148TA_PERF_SEL_vol_2_cycle_pixels           = 0x00000047,
16149TA_PERF_SEL_bilin_point_1_cycle_pixels   = 0x00000048,
16150TA_PERF_SEL_mipmap_lod_0_samples         = 0x00000049,
16151TA_PERF_SEL_mipmap_lod_1_samples         = 0x0000004a,
16152TA_PERF_SEL_mipmap_lod_2_samples         = 0x0000004b,
16153TA_PERF_SEL_mipmap_lod_3_samples         = 0x0000004c,
16154TA_PERF_SEL_mipmap_lod_4_samples         = 0x0000004d,
16155TA_PERF_SEL_mipmap_lod_5_samples         = 0x0000004e,
16156TA_PERF_SEL_mipmap_lod_6_samples         = 0x0000004f,
16157TA_PERF_SEL_mipmap_lod_7_samples         = 0x00000050,
16158TA_PERF_SEL_mipmap_lod_8_samples         = 0x00000051,
16159TA_PERF_SEL_mipmap_lod_9_samples         = 0x00000052,
16160TA_PERF_SEL_mipmap_lod_10_samples        = 0x00000053,
16161TA_PERF_SEL_mipmap_lod_11_samples        = 0x00000054,
16162TA_PERF_SEL_mipmap_lod_12_samples        = 0x00000055,
16163TA_PERF_SEL_mipmap_lod_13_samples        = 0x00000056,
16164TA_PERF_SEL_mipmap_lod_14_samples        = 0x00000057,
16165TA_PERF_SEL_mipmap_invalid_samples       = 0x00000058,
16166TA_PERF_SEL_aniso_1_cycle_quads          = 0x00000059,
16167TA_PERF_SEL_aniso_2_cycle_quads          = 0x0000005a,
16168TA_PERF_SEL_aniso_4_cycle_quads          = 0x0000005b,
16169TA_PERF_SEL_aniso_6_cycle_quads          = 0x0000005c,
16170TA_PERF_SEL_aniso_8_cycle_quads          = 0x0000005d,
16171TA_PERF_SEL_aniso_10_cycle_quads         = 0x0000005e,
16172TA_PERF_SEL_aniso_12_cycle_quads         = 0x0000005f,
16173TA_PERF_SEL_aniso_14_cycle_quads         = 0x00000060,
16174TA_PERF_SEL_aniso_16_cycle_quads         = 0x00000061,
16175TA_PERF_SEL_write_path_input_cycles      = 0x00000062,
16176TA_PERF_SEL_write_path_output_cycles     = 0x00000063,
16177TA_PERF_SEL_flat_wavefronts              = 0x00000064,
16178TA_PERF_SEL_flat_read_wavefronts         = 0x00000065,
16179TA_PERF_SEL_flat_write_wavefronts        = 0x00000066,
16180TA_PERF_SEL_flat_atomic_wavefronts       = 0x00000067,
16181TA_PERF_SEL_flat_coalesceable_wavefronts  = 0x00000068,
16182TA_PERF_SEL_reg_sclk_vld                 = 0x00000069,
16183TA_PERF_SEL_local_cg_dyn_sclk_grp0_en    = 0x0000006a,
16184TA_PERF_SEL_local_cg_dyn_sclk_grp1_en    = 0x0000006b,
16185TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en  = 0x0000006c,
16186TA_PERF_SEL_local_cg_dyn_sclk_grp4_en    = 0x0000006d,
16187TA_PERF_SEL_local_cg_dyn_sclk_grp5_en    = 0x0000006e,
16188TA_PERF_SEL_xnack_on_phase0              = 0x0000006f,
16189TA_PERF_SEL_xnack_on_phase1              = 0x00000070,
16190TA_PERF_SEL_xnack_on_phase2              = 0x00000071,
16191TA_PERF_SEL_xnack_on_phase3              = 0x00000072,
16192TA_PERF_SEL_first_xnack_on_phase0        = 0x00000073,
16193TA_PERF_SEL_first_xnack_on_phase1        = 0x00000074,
16194TA_PERF_SEL_first_xnack_on_phase2        = 0x00000075,
16195TA_PERF_SEL_first_xnack_on_phase3        = 0x00000076,
16196} TA_PERFCOUNT_SEL;
16197
16198/*
16199 * TD_PERFCOUNT_SEL enum
16200 */
16201
16202typedef enum TD_PERFCOUNT_SEL {
16203TD_PERF_SEL_none                         = 0x00000000,
16204TD_PERF_SEL_td_busy                      = 0x00000001,
16205TD_PERF_SEL_input_busy                   = 0x00000002,
16206TD_PERF_SEL_output_busy                  = 0x00000003,
16207TD_PERF_SEL_lerp_busy                    = 0x00000004,
16208TD_PERF_SEL_reg_sclk_vld                 = 0x00000005,
16209TD_PERF_SEL_local_cg_dyn_sclk_grp0_en    = 0x00000006,
16210TD_PERF_SEL_local_cg_dyn_sclk_grp1_en    = 0x00000007,
16211TD_PERF_SEL_local_cg_dyn_sclk_grp4_en    = 0x00000008,
16212TD_PERF_SEL_local_cg_dyn_sclk_grp5_en    = 0x00000009,
16213TD_PERF_SEL_tc_td_fifo_full              = 0x0000000a,
16214TD_PERF_SEL_constant_state_full          = 0x0000000b,
16215TD_PERF_SEL_sample_state_full            = 0x0000000c,
16216TD_PERF_SEL_output_fifo_full             = 0x0000000d,
16217TD_PERF_SEL_RESERVED_14                  = 0x0000000e,
16218TD_PERF_SEL_tc_stall                     = 0x0000000f,
16219TD_PERF_SEL_pc_stall                     = 0x00000010,
16220TD_PERF_SEL_gds_stall                    = 0x00000011,
16221TD_PERF_SEL_RESERVED_18                  = 0x00000012,
16222TD_PERF_SEL_RESERVED_19                  = 0x00000013,
16223TD_PERF_SEL_gather4_wavefront            = 0x00000014,
16224TD_PERF_SEL_gather4h_wavefront           = 0x00000015,
16225TD_PERF_SEL_gather4h_packed_wavefront    = 0x00000016,
16226TD_PERF_SEL_gather8h_packed_wavefront    = 0x00000017,
16227TD_PERF_SEL_sample_c_wavefront           = 0x00000018,
16228TD_PERF_SEL_load_wavefront               = 0x00000019,
16229TD_PERF_SEL_atomic_wavefront             = 0x0000001a,
16230TD_PERF_SEL_store_wavefront              = 0x0000001b,
16231TD_PERF_SEL_ldfptr_wavefront             = 0x0000001c,
16232TD_PERF_SEL_d16_en_wavefront             = 0x0000001d,
16233TD_PERF_SEL_bypass_filter_wavefront      = 0x0000001e,
16234TD_PERF_SEL_min_max_filter_wavefront     = 0x0000001f,
16235TD_PERF_SEL_coalescable_wavefront        = 0x00000020,
16236TD_PERF_SEL_coalesced_phase              = 0x00000021,
16237TD_PERF_SEL_four_phase_wavefront         = 0x00000022,
16238TD_PERF_SEL_eight_phase_wavefront        = 0x00000023,
16239TD_PERF_SEL_sixteen_phase_wavefront      = 0x00000024,
16240TD_PERF_SEL_four_phase_forward_wavefront  = 0x00000025,
16241TD_PERF_SEL_write_ack_wavefront          = 0x00000026,
16242TD_PERF_SEL_RESERVED_39                  = 0x00000027,
16243TD_PERF_SEL_user_defined_border          = 0x00000028,
16244TD_PERF_SEL_white_border                 = 0x00000029,
16245TD_PERF_SEL_opaque_black_border          = 0x0000002a,
16246TD_PERF_SEL_RESERVED_43                  = 0x0000002b,
16247TD_PERF_SEL_RESERVED_44                  = 0x0000002c,
16248TD_PERF_SEL_nack                         = 0x0000002d,
16249TD_PERF_SEL_td_sp_traffic                = 0x0000002e,
16250TD_PERF_SEL_consume_gds_traffic          = 0x0000002f,
16251TD_PERF_SEL_addresscmd_poison            = 0x00000030,
16252TD_PERF_SEL_data_poison                  = 0x00000031,
16253TD_PERF_SEL_start_cycle_0                = 0x00000032,
16254TD_PERF_SEL_start_cycle_1                = 0x00000033,
16255TD_PERF_SEL_start_cycle_2                = 0x00000034,
16256TD_PERF_SEL_start_cycle_3                = 0x00000035,
16257TD_PERF_SEL_null_cycle_output            = 0x00000036,
16258TD_PERF_SEL_d16_data_packed              = 0x00000037,
16259TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt  = 0x00000038,
16260} TD_PERFCOUNT_SEL;
16261
16262/*
16263 * TCP_PERFCOUNT_SELECT enum
16264 */
16265
16266typedef enum TCP_PERFCOUNT_SELECT {
16267TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES   = 0x00000000,
16268TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES   = 0x00000001,
16269TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES    = 0x00000002,
16270TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES    = 0x00000003,
16271TCP_PERF_SEL_TD_TCP_STALL_CYCLES         = 0x00000004,
16272TCP_PERF_SEL_TCR_TCP_STALL_CYCLES        = 0x00000005,
16273TCP_PERF_SEL_LOD_STALL_CYCLES            = 0x00000006,
16274TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES  = 0x00000007,
16275TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES  = 0x00000008,
16276TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES  = 0x00000009,
16277TCP_PERF_SEL_ALLOC_STALL_CYCLES          = 0x0000000a,
16278TCP_PERF_SEL_LFIFO_STALL_CYCLES          = 0x0000000b,
16279TCP_PERF_SEL_RFIFO_STALL_CYCLES          = 0x0000000c,
16280TCP_PERF_SEL_TCR_RDRET_STALL             = 0x0000000d,
16281TCP_PERF_SEL_WRITE_CONFLICT_STALL        = 0x0000000e,
16282TCP_PERF_SEL_HOLE_READ_STALL             = 0x0000000f,
16283TCP_PERF_SEL_READCONFLICT_STALL_CYCLES   = 0x00000010,
16284TCP_PERF_SEL_PENDING_STALL_CYCLES        = 0x00000011,
16285TCP_PERF_SEL_READFIFO_STALL_CYCLES       = 0x00000012,
16286TCP_PERF_SEL_TCP_LATENCY                 = 0x00000013,
16287TCP_PERF_SEL_TCC_READ_REQ_LATENCY        = 0x00000014,
16288TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY       = 0x00000015,
16289TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY  = 0x00000016,
16290TCP_PERF_SEL_TCC_READ_REQ                = 0x00000017,
16291TCP_PERF_SEL_TCC_WRITE_REQ               = 0x00000018,
16292TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ     = 0x00000019,
16293TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ  = 0x0000001a,
16294TCP_PERF_SEL_TOTAL_LOCAL_READ            = 0x0000001b,
16295TCP_PERF_SEL_TOTAL_GLOBAL_READ           = 0x0000001c,
16296TCP_PERF_SEL_TOTAL_LOCAL_WRITE           = 0x0000001d,
16297TCP_PERF_SEL_TOTAL_GLOBAL_WRITE          = 0x0000001e,
16298TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET       = 0x0000001f,
16299TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET    = 0x00000020,
16300TCP_PERF_SEL_TOTAL_WBINVL1               = 0x00000021,
16301TCP_PERF_SEL_IMG_READ_FMT_1              = 0x00000022,
16302TCP_PERF_SEL_IMG_READ_FMT_8              = 0x00000023,
16303TCP_PERF_SEL_IMG_READ_FMT_16             = 0x00000024,
16304TCP_PERF_SEL_IMG_READ_FMT_32             = 0x00000025,
16305TCP_PERF_SEL_IMG_READ_FMT_32_AS_8        = 0x00000026,
16306TCP_PERF_SEL_IMG_READ_FMT_32_AS_16       = 0x00000027,
16307TCP_PERF_SEL_IMG_READ_FMT_32_AS_128      = 0x00000028,
16308TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE     = 0x00000029,
16309TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE     = 0x0000002a,
16310TCP_PERF_SEL_IMG_READ_FMT_96             = 0x0000002b,
16311TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE    = 0x0000002c,
16312TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE    = 0x0000002d,
16313TCP_PERF_SEL_IMG_READ_FMT_BC1            = 0x0000002e,
16314TCP_PERF_SEL_IMG_READ_FMT_BC2            = 0x0000002f,
16315TCP_PERF_SEL_IMG_READ_FMT_BC3            = 0x00000030,
16316TCP_PERF_SEL_IMG_READ_FMT_BC4            = 0x00000031,
16317TCP_PERF_SEL_IMG_READ_FMT_BC5            = 0x00000032,
16318TCP_PERF_SEL_IMG_READ_FMT_BC6            = 0x00000033,
16319TCP_PERF_SEL_IMG_READ_FMT_BC7            = 0x00000034,
16320TCP_PERF_SEL_IMG_READ_FMT_I8             = 0x00000035,
16321TCP_PERF_SEL_IMG_READ_FMT_I16            = 0x00000036,
16322TCP_PERF_SEL_IMG_READ_FMT_I32            = 0x00000037,
16323TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8       = 0x00000038,
16324TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16      = 0x00000039,
16325TCP_PERF_SEL_IMG_READ_FMT_D8             = 0x0000003a,
16326TCP_PERF_SEL_IMG_READ_FMT_D16            = 0x0000003b,
16327TCP_PERF_SEL_IMG_READ_FMT_D32            = 0x0000003c,
16328TCP_PERF_SEL_IMG_WRITE_FMT_8             = 0x0000003d,
16329TCP_PERF_SEL_IMG_WRITE_FMT_16            = 0x0000003e,
16330TCP_PERF_SEL_IMG_WRITE_FMT_32            = 0x0000003f,
16331TCP_PERF_SEL_IMG_WRITE_FMT_64            = 0x00000040,
16332TCP_PERF_SEL_IMG_WRITE_FMT_128           = 0x00000041,
16333TCP_PERF_SEL_IMG_WRITE_FMT_D8            = 0x00000042,
16334TCP_PERF_SEL_IMG_WRITE_FMT_D16           = 0x00000043,
16335TCP_PERF_SEL_IMG_WRITE_FMT_D32           = 0x00000044,
16336TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32  = 0x00000045,
16337TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32  = 0x00000046,
16338TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64  = 0x00000047,
16339TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64  = 0x00000048,
16340TCP_PERF_SEL_BUF_READ_FMT_8              = 0x00000049,
16341TCP_PERF_SEL_BUF_READ_FMT_16             = 0x0000004a,
16342TCP_PERF_SEL_BUF_READ_FMT_32             = 0x0000004b,
16343TCP_PERF_SEL_BUF_WRITE_FMT_8             = 0x0000004c,
16344TCP_PERF_SEL_BUF_WRITE_FMT_16            = 0x0000004d,
16345TCP_PERF_SEL_BUF_WRITE_FMT_32            = 0x0000004e,
16346TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32  = 0x0000004f,
16347TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32  = 0x00000050,
16348TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64  = 0x00000051,
16349TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64  = 0x00000052,
16350TCP_PERF_SEL_ARR_LINEAR_GENERAL          = 0x00000053,
16351TCP_PERF_SEL_ARR_LINEAR_ALIGNED          = 0x00000054,
16352TCP_PERF_SEL_ARR_1D_THIN1                = 0x00000055,
16353TCP_PERF_SEL_ARR_1D_THICK                = 0x00000056,
16354TCP_PERF_SEL_ARR_2D_THIN1                = 0x00000057,
16355TCP_PERF_SEL_ARR_2D_THICK                = 0x00000058,
16356TCP_PERF_SEL_ARR_2D_XTHICK               = 0x00000059,
16357TCP_PERF_SEL_ARR_3D_THIN1                = 0x0000005a,
16358TCP_PERF_SEL_ARR_3D_THICK                = 0x0000005b,
16359TCP_PERF_SEL_ARR_3D_XTHICK               = 0x0000005c,
16360TCP_PERF_SEL_DIM_1D                      = 0x0000005d,
16361TCP_PERF_SEL_DIM_2D                      = 0x0000005e,
16362TCP_PERF_SEL_DIM_3D                      = 0x0000005f,
16363TCP_PERF_SEL_DIM_1D_ARRAY                = 0x00000060,
16364TCP_PERF_SEL_DIM_2D_ARRAY                = 0x00000061,
16365TCP_PERF_SEL_DIM_2D_MSAA                 = 0x00000062,
16366TCP_PERF_SEL_DIM_2D_ARRAY_MSAA           = 0x00000063,
16367TCP_PERF_SEL_DIM_CUBE_ARRAY              = 0x00000064,
16368TCP_PERF_SEL_CP_TCP_INVALIDATE           = 0x00000065,
16369TCP_PERF_SEL_TA_TCP_STATE_READ           = 0x00000066,
16370TCP_PERF_SEL_TAGRAM0_REQ                 = 0x00000067,
16371TCP_PERF_SEL_TAGRAM1_REQ                 = 0x00000068,
16372TCP_PERF_SEL_TAGRAM2_REQ                 = 0x00000069,
16373TCP_PERF_SEL_TAGRAM3_REQ                 = 0x0000006a,
16374TCP_PERF_SEL_GATE_EN1                    = 0x0000006b,
16375TCP_PERF_SEL_GATE_EN2                    = 0x0000006c,
16376TCP_PERF_SEL_CORE_REG_SCLK_VLD           = 0x0000006d,
16377TCP_PERF_SEL_TCC_REQ                     = 0x0000006e,
16378TCP_PERF_SEL_TCC_NON_READ_REQ            = 0x0000006f,
16379TCP_PERF_SEL_TCC_BYPASS_READ_REQ         = 0x00000070,
16380TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ     = 0x00000071,
16381TCP_PERF_SEL_TCC_VOLATILE_READ_REQ       = 0x00000072,
16382TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ  = 0x00000073,
16383TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ  = 0x00000074,
16384TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ        = 0x00000075,
16385TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ    = 0x00000076,
16386TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ  = 0x00000077,
16387TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ      = 0x00000078,
16388TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ  = 0x00000079,
16389TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ       = 0x0000007a,
16390TCP_PERF_SEL_TCC_ATOMIC_REQ              = 0x0000007b,
16391TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ     = 0x0000007c,
16392TCP_PERF_SEL_TCC_DATA_BUS_BUSY           = 0x0000007d,
16393TCP_PERF_SEL_TOTAL_ACCESSES              = 0x0000007e,
16394TCP_PERF_SEL_TOTAL_READ                  = 0x0000007f,
16395TCP_PERF_SEL_TOTAL_HIT_LRU_READ          = 0x00000080,
16396TCP_PERF_SEL_TOTAL_HIT_EVICT_READ        = 0x00000081,
16397TCP_PERF_SEL_TOTAL_MISS_LRU_READ         = 0x00000082,
16398TCP_PERF_SEL_TOTAL_MISS_EVICT_READ       = 0x00000083,
16399TCP_PERF_SEL_TOTAL_NON_READ              = 0x00000084,
16400TCP_PERF_SEL_TOTAL_WRITE                 = 0x00000085,
16401TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE        = 0x00000086,
16402TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE      = 0x00000087,
16403TCP_PERF_SEL_TOTAL_WBINVL1_VOL           = 0x00000088,
16404TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES  = 0x00000089,
16405TCP_PERF_SEL_DISPLAY_MICROTILING         = 0x0000008a,
16406TCP_PERF_SEL_THIN_MICROTILING            = 0x0000008b,
16407TCP_PERF_SEL_DEPTH_MICROTILING           = 0x0000008c,
16408TCP_PERF_SEL_ARR_PRT_THIN1               = 0x0000008d,
16409TCP_PERF_SEL_ARR_PRT_2D_THIN1            = 0x0000008e,
16410TCP_PERF_SEL_ARR_PRT_3D_THIN1            = 0x0000008f,
16411TCP_PERF_SEL_ARR_PRT_THICK               = 0x00000090,
16412TCP_PERF_SEL_ARR_PRT_2D_THICK            = 0x00000091,
16413TCP_PERF_SEL_ARR_PRT_3D_THICK            = 0x00000092,
16414TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL       = 0x00000093,
16415TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL       = 0x00000094,
16416TCP_PERF_SEL_UNALIGNED                   = 0x00000095,
16417TCP_PERF_SEL_ROTATED_MICROTILING         = 0x00000096,
16418TCP_PERF_SEL_THICK_MICROTILING           = 0x00000097,
16419TCP_PERF_SEL_ATC                         = 0x00000098,
16420TCP_PERF_SEL_POWER_STALL                 = 0x00000099,
16421TCP_PERF_SEL_RESERVED_154                = 0x0000009a,
16422TCP_PERF_SEL_TCC_LRU_REQ                 = 0x0000009b,
16423TCP_PERF_SEL_TCC_STREAM_REQ              = 0x0000009c,
16424TCP_PERF_SEL_TCC_NC_READ_REQ             = 0x0000009d,
16425TCP_PERF_SEL_TCC_NC_WRITE_REQ            = 0x0000009e,
16426TCP_PERF_SEL_TCC_NC_ATOMIC_REQ           = 0x0000009f,
16427TCP_PERF_SEL_TCC_UC_READ_REQ             = 0x000000a0,
16428TCP_PERF_SEL_TCC_UC_WRITE_REQ            = 0x000000a1,
16429TCP_PERF_SEL_TCC_UC_ATOMIC_REQ           = 0x000000a2,
16430TCP_PERF_SEL_TCC_CC_READ_REQ             = 0x000000a3,
16431TCP_PERF_SEL_TCC_CC_WRITE_REQ            = 0x000000a4,
16432TCP_PERF_SEL_TCC_CC_ATOMIC_REQ           = 0x000000a5,
16433TCP_PERF_SEL_TCC_DCC_REQ                 = 0x000000a6,
16434TCP_PERF_SEL_TCC_PHYSICAL_REQ            = 0x000000a7,
16435TCP_PERF_SEL_UNORDERED_MTYPE_STALL       = 0x000000a8,
16436TCP_PERF_SEL_VOLATILE                    = 0x000000a9,
16437TCP_PERF_SEL_TC_TA_XNACK_STALL           = 0x000000aa,
16438TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL   = 0x000000ab,
16439TCP_PERF_SEL_SHOOTDOWN                   = 0x000000ac,
16440TCP_PERF_SEL_UTCL1_TRANSLATION_MISS      = 0x000000ad,
16441TCP_PERF_SEL_UTCL1_PERMISSION_MISS       = 0x000000ae,
16442TCP_PERF_SEL_UTCL1_REQUEST               = 0x000000af,
16443TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX    = 0x000000b0,
16444TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT    = 0x000000b1,
16445TCP_PERF_SEL_UTCL1_LFIFO_FULL            = 0x000000b2,
16446TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES   = 0x000000b3,
16447TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x000000b4,
16448TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT        = 0x000000b5,
16449TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL   = 0x000000b6,
16450TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB       = 0x000000b7,
16451TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA      = 0x000000b8,
16452TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1     = 0x000000b9,
16453TCP_PERF_SEL_IMG_READ_FMT_ETC2_R         = 0x000000ba,
16454TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG        = 0x000000bb,
16455TCP_PERF_SEL_IMG_READ_FMT_8_AS_32        = 0x000000bc,
16456TCP_PERF_SEL_IMG_READ_FMT_8_AS_64        = 0x000000bd,
16457TCP_PERF_SEL_IMG_READ_FMT_16_AS_64       = 0x000000be,
16458TCP_PERF_SEL_IMG_READ_FMT_16_AS_128      = 0x000000bf,
16459TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32       = 0x000000c0,
16460TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64       = 0x000000c1,
16461TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64      = 0x000000c2,
16462TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128     = 0x000000c3,
16463} TCP_PERFCOUNT_SELECT;
16464
16465/*
16466 * TCP_CACHE_POLICIES enum
16467 */
16468
16469typedef enum TCP_CACHE_POLICIES {
16470TCP_CACHE_POLICY_MISS_LRU                = 0x00000000,
16471TCP_CACHE_POLICY_MISS_EVICT              = 0x00000001,
16472TCP_CACHE_POLICY_HIT_LRU                 = 0x00000002,
16473TCP_CACHE_POLICY_HIT_EVICT               = 0x00000003,
16474} TCP_CACHE_POLICIES;
16475
16476/*
16477 * TCP_CACHE_STORE_POLICIES enum
16478 */
16479
16480typedef enum TCP_CACHE_STORE_POLICIES {
16481TCP_CACHE_STORE_POLICY_WT_LRU            = 0x00000000,
16482TCP_CACHE_STORE_POLICY_WT_EVICT          = 0x00000001,
16483} TCP_CACHE_STORE_POLICIES;
16484
16485/*
16486 * TCP_WATCH_MODES enum
16487 */
16488
16489typedef enum TCP_WATCH_MODES {
16490TCP_WATCH_MODE_READ                      = 0x00000000,
16491TCP_WATCH_MODE_NONREAD                   = 0x00000001,
16492TCP_WATCH_MODE_ATOMIC                    = 0x00000002,
16493TCP_WATCH_MODE_ALL                       = 0x00000003,
16494} TCP_WATCH_MODES;
16495
16496/*
16497 * TCP_DSM_DATA_SEL enum
16498 */
16499
16500typedef enum TCP_DSM_DATA_SEL {
16501TCP_DSM_DISABLE                          = 0x00000000,
16502TCP_DSM_SEL0                             = 0x00000001,
16503TCP_DSM_SEL1                             = 0x00000002,
16504TCP_DSM_SEL_BOTH                         = 0x00000003,
16505} TCP_DSM_DATA_SEL;
16506
16507/*
16508 * TCP_DSM_SINGLE_WRITE enum
16509 */
16510
16511typedef enum TCP_DSM_SINGLE_WRITE {
16512TCP_DSM_SINGLE_WRITE_DIS                 = 0x00000000,
16513TCP_DSM_SINGLE_WRITE_EN                  = 0x00000001,
16514} TCP_DSM_SINGLE_WRITE;
16515
16516/*
16517 * TCP_DSM_INJECT_SEL enum
16518 */
16519
16520typedef enum TCP_DSM_INJECT_SEL {
16521TCP_DSM_INJECT_SEL0                      = 0x00000000,
16522TCP_DSM_INJECT_SEL1                      = 0x00000001,
16523TCP_DSM_INJECT_SEL2                      = 0x00000002,
16524TCP_DSM_INJECT_SEL3                      = 0x00000003,
16525} TCP_DSM_INJECT_SEL;
16526
16527/*******************************************************
16528 * TCC Enums
16529 *******************************************************/
16530
16531/*
16532 * TCC_PERF_SEL enum
16533 */
16534
16535typedef enum TCC_PERF_SEL {
16536TCC_PERF_SEL_NONE                        = 0x00000000,
16537TCC_PERF_SEL_CYCLE                       = 0x00000001,
16538TCC_PERF_SEL_BUSY                        = 0x00000002,
16539TCC_PERF_SEL_REQ                         = 0x00000003,
16540TCC_PERF_SEL_STREAMING_REQ               = 0x00000004,
16541TCC_PERF_SEL_EXE_REQ                     = 0x00000005,
16542TCC_PERF_SEL_COMPRESSED_REQ              = 0x00000006,
16543TCC_PERF_SEL_COMPRESSED_0_REQ            = 0x00000007,
16544TCC_PERF_SEL_METADATA_REQ                = 0x00000008,
16545TCC_PERF_SEL_NC_VIRTUAL_REQ              = 0x00000009,
16546TCC_PERF_SEL_UC_VIRTUAL_REQ              = 0x0000000a,
16547TCC_PERF_SEL_CC_PHYSICAL_REQ             = 0x0000000b,
16548TCC_PERF_SEL_PROBE                       = 0x0000000c,
16549TCC_PERF_SEL_PROBE_ALL                   = 0x0000000d,
16550TCC_PERF_SEL_READ                        = 0x0000000e,
16551TCC_PERF_SEL_WRITE                       = 0x0000000f,
16552TCC_PERF_SEL_ATOMIC                      = 0x00000010,
16553TCC_PERF_SEL_HIT                         = 0x00000011,
16554TCC_PERF_SEL_SECTOR_HIT                  = 0x00000012,
16555TCC_PERF_SEL_MISS                        = 0x00000013,
16556TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT        = 0x00000014,
16557TCC_PERF_SEL_FULLY_WRITTEN_HIT           = 0x00000015,
16558TCC_PERF_SEL_WRITEBACK                   = 0x00000016,
16559TCC_PERF_SEL_LATENCY_FIFO_FULL           = 0x00000017,
16560TCC_PERF_SEL_SRC_FIFO_FULL               = 0x00000018,
16561TCC_PERF_SEL_HOLE_FIFO_FULL              = 0x00000019,
16562TCC_PERF_SEL_EA_WRREQ                    = 0x0000001a,
16563TCC_PERF_SEL_EA_WRREQ_64B                = 0x0000001b,
16564TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND      = 0x0000001c,
16565TCC_PERF_SEL_EA_WR_UNCACHED_32B          = 0x0000001d,
16566TCC_PERF_SEL_EA_WRREQ_STALL              = 0x0000001e,
16567TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL       = 0x0000001f,
16568TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL    = 0x00000020,
16569TCC_PERF_SEL_EA_WRREQ_LEVEL              = 0x00000021,
16570TCC_PERF_SEL_EA_ATOMIC                   = 0x00000022,
16571TCC_PERF_SEL_EA_ATOMIC_LEVEL             = 0x00000023,
16572TCC_PERF_SEL_EA_RDREQ                    = 0x00000024,
16573TCC_PERF_SEL_EA_RDREQ_32B                = 0x00000025,
16574TCC_PERF_SEL_EA_RD_UNCACHED_32B          = 0x00000026,
16575TCC_PERF_SEL_EA_RD_MDC_32B               = 0x00000027,
16576TCC_PERF_SEL_EA_RD_COMPRESSED_32B        = 0x00000028,
16577TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL       = 0x00000029,
16578TCC_PERF_SEL_EA_RDREQ_LEVEL              = 0x0000002a,
16579TCC_PERF_SEL_TAG_STALL                   = 0x0000002b,
16580TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL  = 0x0000002c,
16581TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL  = 0x0000002d,
16582TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL  = 0x0000002e,
16583TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL  = 0x0000002f,
16584TCC_PERF_SEL_TAG_PROBE_STALL             = 0x00000030,
16585TCC_PERF_SEL_TAG_PROBE_FILTER_STALL      = 0x00000031,
16586TCC_PERF_SEL_READ_RETURN_TIMEOUT         = 0x00000032,
16587TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT      = 0x00000033,
16588TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE     = 0x00000034,
16589TCC_PERF_SEL_BUBBLE                      = 0x00000035,
16590TCC_PERF_SEL_RETURN_ACK                  = 0x00000036,
16591TCC_PERF_SEL_RETURN_DATA                 = 0x00000037,
16592TCC_PERF_SEL_RETURN_HOLE                 = 0x00000038,
16593TCC_PERF_SEL_RETURN_ACK_HOLE             = 0x00000039,
16594TCC_PERF_SEL_IB_REQ                      = 0x0000003a,
16595TCC_PERF_SEL_IB_STALL                    = 0x0000003b,
16596TCC_PERF_SEL_IB_TAG_STALL                = 0x0000003c,
16597TCC_PERF_SEL_IB_MDC_STALL                = 0x0000003d,
16598TCC_PERF_SEL_TCA_LEVEL                   = 0x0000003e,
16599TCC_PERF_SEL_HOLE_LEVEL                  = 0x0000003f,
16600TCC_PERF_SEL_NORMAL_WRITEBACK            = 0x00000040,
16601TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK     = 0x00000041,
16602TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK     = 0x00000042,
16603TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK     = 0x00000043,
16604TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK  = 0x00000044,
16605TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK  = 0x00000045,
16606TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK      = 0x00000046,
16607TCC_PERF_SEL_NORMAL_EVICT                = 0x00000047,
16608TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT         = 0x00000048,
16609TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT         = 0x00000049,
16610TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT        = 0x0000004a,
16611TCC_PERF_SEL_TC_OP_WBINVL2_EVICT         = 0x0000004b,
16612TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT      = 0x0000004c,
16613TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT      = 0x0000004d,
16614TCC_PERF_SEL_ALL_TC_OP_INV_EVICT         = 0x0000004e,
16615TCC_PERF_SEL_PROBE_EVICT                 = 0x0000004f,
16616TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE         = 0x00000050,
16617TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE         = 0x00000051,
16618TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE        = 0x00000052,
16619TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE         = 0x00000053,
16620TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE      = 0x00000054,
16621TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE      = 0x00000055,
16622TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE   = 0x00000056,
16623TCC_PERF_SEL_TC_OP_WBL2_NC_START         = 0x00000057,
16624TCC_PERF_SEL_TC_OP_WBL2_WC_START         = 0x00000058,
16625TCC_PERF_SEL_TC_OP_INVL2_NC_START        = 0x00000059,
16626TCC_PERF_SEL_TC_OP_WBINVL2_START         = 0x0000005a,
16627TCC_PERF_SEL_TC_OP_WBINVL2_NC_START      = 0x0000005b,
16628TCC_PERF_SEL_TC_OP_WBINVL2_SD_START      = 0x0000005c,
16629TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START   = 0x0000005d,
16630TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH        = 0x0000005e,
16631TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH        = 0x0000005f,
16632TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH       = 0x00000060,
16633TCC_PERF_SEL_TC_OP_WBINVL2_FINISH        = 0x00000061,
16634TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH     = 0x00000062,
16635TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH     = 0x00000063,
16636TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH  = 0x00000064,
16637TCC_PERF_SEL_MDC_REQ                     = 0x00000065,
16638TCC_PERF_SEL_MDC_LEVEL                   = 0x00000066,
16639TCC_PERF_SEL_MDC_TAG_HIT                 = 0x00000067,
16640TCC_PERF_SEL_MDC_SECTOR_HIT              = 0x00000068,
16641TCC_PERF_SEL_MDC_SECTOR_MISS             = 0x00000069,
16642TCC_PERF_SEL_MDC_TAG_STALL               = 0x0000006a,
16643TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL  = 0x0000006b,
16644TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL  = 0x0000006c,
16645TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL  = 0x0000006d,
16646TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION  = 0x0000006e,
16647TCC_PERF_SEL_PROBE_FILTER_DISABLED       = 0x0000006f,
16648TCC_PERF_SEL_CLIENT0_REQ                 = 0x00000080,
16649TCC_PERF_SEL_CLIENT1_REQ                 = 0x00000081,
16650TCC_PERF_SEL_CLIENT2_REQ                 = 0x00000082,
16651TCC_PERF_SEL_CLIENT3_REQ                 = 0x00000083,
16652TCC_PERF_SEL_CLIENT4_REQ                 = 0x00000084,
16653TCC_PERF_SEL_CLIENT5_REQ                 = 0x00000085,
16654TCC_PERF_SEL_CLIENT6_REQ                 = 0x00000086,
16655TCC_PERF_SEL_CLIENT7_REQ                 = 0x00000087,
16656TCC_PERF_SEL_CLIENT8_REQ                 = 0x00000088,
16657TCC_PERF_SEL_CLIENT9_REQ                 = 0x00000089,
16658TCC_PERF_SEL_CLIENT10_REQ                = 0x0000008a,
16659TCC_PERF_SEL_CLIENT11_REQ                = 0x0000008b,
16660TCC_PERF_SEL_CLIENT12_REQ                = 0x0000008c,
16661TCC_PERF_SEL_CLIENT13_REQ                = 0x0000008d,
16662TCC_PERF_SEL_CLIENT14_REQ                = 0x0000008e,
16663TCC_PERF_SEL_CLIENT15_REQ                = 0x0000008f,
16664TCC_PERF_SEL_CLIENT16_REQ                = 0x00000090,
16665TCC_PERF_SEL_CLIENT17_REQ                = 0x00000091,
16666TCC_PERF_SEL_CLIENT18_REQ                = 0x00000092,
16667TCC_PERF_SEL_CLIENT19_REQ                = 0x00000093,
16668TCC_PERF_SEL_CLIENT20_REQ                = 0x00000094,
16669TCC_PERF_SEL_CLIENT21_REQ                = 0x00000095,
16670TCC_PERF_SEL_CLIENT22_REQ                = 0x00000096,
16671TCC_PERF_SEL_CLIENT23_REQ                = 0x00000097,
16672TCC_PERF_SEL_CLIENT24_REQ                = 0x00000098,
16673TCC_PERF_SEL_CLIENT25_REQ                = 0x00000099,
16674TCC_PERF_SEL_CLIENT26_REQ                = 0x0000009a,
16675TCC_PERF_SEL_CLIENT27_REQ                = 0x0000009b,
16676TCC_PERF_SEL_CLIENT28_REQ                = 0x0000009c,
16677TCC_PERF_SEL_CLIENT29_REQ                = 0x0000009d,
16678TCC_PERF_SEL_CLIENT30_REQ                = 0x0000009e,
16679TCC_PERF_SEL_CLIENT31_REQ                = 0x0000009f,
16680TCC_PERF_SEL_CLIENT32_REQ                = 0x000000a0,
16681TCC_PERF_SEL_CLIENT33_REQ                = 0x000000a1,
16682TCC_PERF_SEL_CLIENT34_REQ                = 0x000000a2,
16683TCC_PERF_SEL_CLIENT35_REQ                = 0x000000a3,
16684TCC_PERF_SEL_CLIENT36_REQ                = 0x000000a4,
16685TCC_PERF_SEL_CLIENT37_REQ                = 0x000000a5,
16686TCC_PERF_SEL_CLIENT38_REQ                = 0x000000a6,
16687TCC_PERF_SEL_CLIENT39_REQ                = 0x000000a7,
16688TCC_PERF_SEL_CLIENT40_REQ                = 0x000000a8,
16689TCC_PERF_SEL_CLIENT41_REQ                = 0x000000a9,
16690TCC_PERF_SEL_CLIENT42_REQ                = 0x000000aa,
16691TCC_PERF_SEL_CLIENT43_REQ                = 0x000000ab,
16692TCC_PERF_SEL_CLIENT44_REQ                = 0x000000ac,
16693TCC_PERF_SEL_CLIENT45_REQ                = 0x000000ad,
16694TCC_PERF_SEL_CLIENT46_REQ                = 0x000000ae,
16695TCC_PERF_SEL_CLIENT47_REQ                = 0x000000af,
16696TCC_PERF_SEL_CLIENT48_REQ                = 0x000000b0,
16697TCC_PERF_SEL_CLIENT49_REQ                = 0x000000b1,
16698TCC_PERF_SEL_CLIENT50_REQ                = 0x000000b2,
16699TCC_PERF_SEL_CLIENT51_REQ                = 0x000000b3,
16700TCC_PERF_SEL_CLIENT52_REQ                = 0x000000b4,
16701TCC_PERF_SEL_CLIENT53_REQ                = 0x000000b5,
16702TCC_PERF_SEL_CLIENT54_REQ                = 0x000000b6,
16703TCC_PERF_SEL_CLIENT55_REQ                = 0x000000b7,
16704TCC_PERF_SEL_CLIENT56_REQ                = 0x000000b8,
16705TCC_PERF_SEL_CLIENT57_REQ                = 0x000000b9,
16706TCC_PERF_SEL_CLIENT58_REQ                = 0x000000ba,
16707TCC_PERF_SEL_CLIENT59_REQ                = 0x000000bb,
16708TCC_PERF_SEL_CLIENT60_REQ                = 0x000000bc,
16709TCC_PERF_SEL_CLIENT61_REQ                = 0x000000bd,
16710TCC_PERF_SEL_CLIENT62_REQ                = 0x000000be,
16711TCC_PERF_SEL_CLIENT63_REQ                = 0x000000bf,
16712TCC_PERF_SEL_CLIENT64_REQ                = 0x000000c0,
16713TCC_PERF_SEL_CLIENT65_REQ                = 0x000000c1,
16714TCC_PERF_SEL_CLIENT66_REQ                = 0x000000c2,
16715TCC_PERF_SEL_CLIENT67_REQ                = 0x000000c3,
16716TCC_PERF_SEL_CLIENT68_REQ                = 0x000000c4,
16717TCC_PERF_SEL_CLIENT69_REQ                = 0x000000c5,
16718TCC_PERF_SEL_CLIENT70_REQ                = 0x000000c6,
16719TCC_PERF_SEL_CLIENT71_REQ                = 0x000000c7,
16720TCC_PERF_SEL_CLIENT72_REQ                = 0x000000c8,
16721TCC_PERF_SEL_CLIENT73_REQ                = 0x000000c9,
16722TCC_PERF_SEL_CLIENT74_REQ                = 0x000000ca,
16723TCC_PERF_SEL_CLIENT75_REQ                = 0x000000cb,
16724TCC_PERF_SEL_CLIENT76_REQ                = 0x000000cc,
16725TCC_PERF_SEL_CLIENT77_REQ                = 0x000000cd,
16726TCC_PERF_SEL_CLIENT78_REQ                = 0x000000ce,
16727TCC_PERF_SEL_CLIENT79_REQ                = 0x000000cf,
16728TCC_PERF_SEL_CLIENT80_REQ                = 0x000000d0,
16729TCC_PERF_SEL_CLIENT81_REQ                = 0x000000d1,
16730TCC_PERF_SEL_CLIENT82_REQ                = 0x000000d2,
16731TCC_PERF_SEL_CLIENT83_REQ                = 0x000000d3,
16732TCC_PERF_SEL_CLIENT84_REQ                = 0x000000d4,
16733TCC_PERF_SEL_CLIENT85_REQ                = 0x000000d5,
16734TCC_PERF_SEL_CLIENT86_REQ                = 0x000000d6,
16735TCC_PERF_SEL_CLIENT87_REQ                = 0x000000d7,
16736TCC_PERF_SEL_CLIENT88_REQ                = 0x000000d8,
16737TCC_PERF_SEL_CLIENT89_REQ                = 0x000000d9,
16738TCC_PERF_SEL_CLIENT90_REQ                = 0x000000da,
16739TCC_PERF_SEL_CLIENT91_REQ                = 0x000000db,
16740TCC_PERF_SEL_CLIENT92_REQ                = 0x000000dc,
16741TCC_PERF_SEL_CLIENT93_REQ                = 0x000000dd,
16742TCC_PERF_SEL_CLIENT94_REQ                = 0x000000de,
16743TCC_PERF_SEL_CLIENT95_REQ                = 0x000000df,
16744TCC_PERF_SEL_CLIENT96_REQ                = 0x000000e0,
16745TCC_PERF_SEL_CLIENT97_REQ                = 0x000000e1,
16746TCC_PERF_SEL_CLIENT98_REQ                = 0x000000e2,
16747TCC_PERF_SEL_CLIENT99_REQ                = 0x000000e3,
16748TCC_PERF_SEL_CLIENT100_REQ               = 0x000000e4,
16749TCC_PERF_SEL_CLIENT101_REQ               = 0x000000e5,
16750TCC_PERF_SEL_CLIENT102_REQ               = 0x000000e6,
16751TCC_PERF_SEL_CLIENT103_REQ               = 0x000000e7,
16752TCC_PERF_SEL_CLIENT104_REQ               = 0x000000e8,
16753TCC_PERF_SEL_CLIENT105_REQ               = 0x000000e9,
16754TCC_PERF_SEL_CLIENT106_REQ               = 0x000000ea,
16755TCC_PERF_SEL_CLIENT107_REQ               = 0x000000eb,
16756TCC_PERF_SEL_CLIENT108_REQ               = 0x000000ec,
16757TCC_PERF_SEL_CLIENT109_REQ               = 0x000000ed,
16758TCC_PERF_SEL_CLIENT110_REQ               = 0x000000ee,
16759TCC_PERF_SEL_CLIENT111_REQ               = 0x000000ef,
16760TCC_PERF_SEL_CLIENT112_REQ               = 0x000000f0,
16761TCC_PERF_SEL_CLIENT113_REQ               = 0x000000f1,
16762TCC_PERF_SEL_CLIENT114_REQ               = 0x000000f2,
16763TCC_PERF_SEL_CLIENT115_REQ               = 0x000000f3,
16764TCC_PERF_SEL_CLIENT116_REQ               = 0x000000f4,
16765TCC_PERF_SEL_CLIENT117_REQ               = 0x000000f5,
16766TCC_PERF_SEL_CLIENT118_REQ               = 0x000000f6,
16767TCC_PERF_SEL_CLIENT119_REQ               = 0x000000f7,
16768TCC_PERF_SEL_CLIENT120_REQ               = 0x000000f8,
16769TCC_PERF_SEL_CLIENT121_REQ               = 0x000000f9,
16770TCC_PERF_SEL_CLIENT122_REQ               = 0x000000fa,
16771TCC_PERF_SEL_CLIENT123_REQ               = 0x000000fb,
16772TCC_PERF_SEL_CLIENT124_REQ               = 0x000000fc,
16773TCC_PERF_SEL_CLIENT125_REQ               = 0x000000fd,
16774TCC_PERF_SEL_CLIENT126_REQ               = 0x000000fe,
16775TCC_PERF_SEL_CLIENT127_REQ               = 0x000000ff,
16776} TCC_PERF_SEL;
16777
16778/*
16779 * TCA_PERF_SEL enum
16780 */
16781
16782typedef enum TCA_PERF_SEL {
16783TCA_PERF_SEL_NONE                        = 0x00000000,
16784TCA_PERF_SEL_CYCLE                       = 0x00000001,
16785TCA_PERF_SEL_BUSY                        = 0x00000002,
16786TCA_PERF_SEL_FORCED_HOLE_TCC0            = 0x00000003,
16787TCA_PERF_SEL_FORCED_HOLE_TCC1            = 0x00000004,
16788TCA_PERF_SEL_FORCED_HOLE_TCC2            = 0x00000005,
16789TCA_PERF_SEL_FORCED_HOLE_TCC3            = 0x00000006,
16790TCA_PERF_SEL_FORCED_HOLE_TCC4            = 0x00000007,
16791TCA_PERF_SEL_FORCED_HOLE_TCC5            = 0x00000008,
16792TCA_PERF_SEL_FORCED_HOLE_TCC6            = 0x00000009,
16793TCA_PERF_SEL_FORCED_HOLE_TCC7            = 0x0000000a,
16794TCA_PERF_SEL_REQ_TCC0                    = 0x0000000b,
16795TCA_PERF_SEL_REQ_TCC1                    = 0x0000000c,
16796TCA_PERF_SEL_REQ_TCC2                    = 0x0000000d,
16797TCA_PERF_SEL_REQ_TCC3                    = 0x0000000e,
16798TCA_PERF_SEL_REQ_TCC4                    = 0x0000000f,
16799TCA_PERF_SEL_REQ_TCC5                    = 0x00000010,
16800TCA_PERF_SEL_REQ_TCC6                    = 0x00000011,
16801TCA_PERF_SEL_REQ_TCC7                    = 0x00000012,
16802TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0    = 0x00000013,
16803TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1    = 0x00000014,
16804TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2    = 0x00000015,
16805TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3    = 0x00000016,
16806TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4    = 0x00000017,
16807TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5    = 0x00000018,
16808TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6    = 0x00000019,
16809TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7    = 0x0000001a,
16810TCA_PERF_SEL_CROSSBAR_STALL_TCC0         = 0x0000001b,
16811TCA_PERF_SEL_CROSSBAR_STALL_TCC1         = 0x0000001c,
16812TCA_PERF_SEL_CROSSBAR_STALL_TCC2         = 0x0000001d,
16813TCA_PERF_SEL_CROSSBAR_STALL_TCC3         = 0x0000001e,
16814TCA_PERF_SEL_CROSSBAR_STALL_TCC4         = 0x0000001f,
16815TCA_PERF_SEL_CROSSBAR_STALL_TCC5         = 0x00000020,
16816TCA_PERF_SEL_CROSSBAR_STALL_TCC6         = 0x00000021,
16817TCA_PERF_SEL_CROSSBAR_STALL_TCC7         = 0x00000022,
16818} TCA_PERF_SEL;
16819
16820/*******************************************************
16821 * GRBM Enums
16822 *******************************************************/
16823
16824/*
16825 * GRBM_PERF_SEL enum
16826 */
16827
16828typedef enum GRBM_PERF_SEL {
16829GRBM_PERF_SEL_COUNT                      = 0x00000000,
16830GRBM_PERF_SEL_USER_DEFINED               = 0x00000001,
16831GRBM_PERF_SEL_GUI_ACTIVE                 = 0x00000002,
16832GRBM_PERF_SEL_CP_BUSY                    = 0x00000003,
16833GRBM_PERF_SEL_CP_COHER_BUSY              = 0x00000004,
16834GRBM_PERF_SEL_CP_DMA_BUSY                = 0x00000005,
16835GRBM_PERF_SEL_CB_BUSY                    = 0x00000006,
16836GRBM_PERF_SEL_DB_BUSY                    = 0x00000007,
16837GRBM_PERF_SEL_PA_BUSY                    = 0x00000008,
16838GRBM_PERF_SEL_SC_BUSY                    = 0x00000009,
16839GRBM_PERF_SEL_RESERVED_6                 = 0x0000000a,
16840GRBM_PERF_SEL_SPI_BUSY                   = 0x0000000b,
16841GRBM_PERF_SEL_SX_BUSY                    = 0x0000000c,
16842GRBM_PERF_SEL_TA_BUSY                    = 0x0000000d,
16843GRBM_PERF_SEL_CB_CLEAN                   = 0x0000000e,
16844GRBM_PERF_SEL_DB_CLEAN                   = 0x0000000f,
16845GRBM_PERF_SEL_RESERVED_5                 = 0x00000010,
16846GRBM_PERF_SEL_VGT_BUSY                   = 0x00000011,
16847GRBM_PERF_SEL_RESERVED_4                 = 0x00000012,
16848GRBM_PERF_SEL_RESERVED_3                 = 0x00000013,
16849GRBM_PERF_SEL_RESERVED_2                 = 0x00000014,
16850GRBM_PERF_SEL_RESERVED_1                 = 0x00000015,
16851GRBM_PERF_SEL_RESERVED_0                 = 0x00000016,
16852GRBM_PERF_SEL_IA_BUSY                    = 0x00000017,
16853GRBM_PERF_SEL_IA_NO_DMA_BUSY             = 0x00000018,
16854GRBM_PERF_SEL_GDS_BUSY                   = 0x00000019,
16855GRBM_PERF_SEL_BCI_BUSY                   = 0x0000001a,
16856GRBM_PERF_SEL_RLC_BUSY                   = 0x0000001b,
16857GRBM_PERF_SEL_TC_BUSY                    = 0x0000001c,
16858GRBM_PERF_SEL_CPG_BUSY                   = 0x0000001d,
16859GRBM_PERF_SEL_CPC_BUSY                   = 0x0000001e,
16860GRBM_PERF_SEL_CPF_BUSY                   = 0x0000001f,
16861GRBM_PERF_SEL_WD_BUSY                    = 0x00000020,
16862GRBM_PERF_SEL_WD_NO_DMA_BUSY             = 0x00000021,
16863GRBM_PERF_SEL_UTCL2_BUSY                 = 0x00000022,
16864GRBM_PERF_SEL_EA_BUSY                    = 0x00000023,
16865GRBM_PERF_SEL_RMI_BUSY                   = 0x00000024,
16866GRBM_PERF_SEL_CPAXI_BUSY                 = 0x00000025,
16867} GRBM_PERF_SEL;
16868
16869/*
16870 * GRBM_SE0_PERF_SEL enum
16871 */
16872
16873typedef enum GRBM_SE0_PERF_SEL {
16874GRBM_SE0_PERF_SEL_COUNT                  = 0x00000000,
16875GRBM_SE0_PERF_SEL_USER_DEFINED           = 0x00000001,
16876GRBM_SE0_PERF_SEL_CB_BUSY                = 0x00000002,
16877GRBM_SE0_PERF_SEL_DB_BUSY                = 0x00000003,
16878GRBM_SE0_PERF_SEL_SC_BUSY                = 0x00000004,
16879GRBM_SE0_PERF_SEL_RESERVED_1             = 0x00000005,
16880GRBM_SE0_PERF_SEL_SPI_BUSY               = 0x00000006,
16881GRBM_SE0_PERF_SEL_SX_BUSY                = 0x00000007,
16882GRBM_SE0_PERF_SEL_TA_BUSY                = 0x00000008,
16883GRBM_SE0_PERF_SEL_CB_CLEAN               = 0x00000009,
16884GRBM_SE0_PERF_SEL_DB_CLEAN               = 0x0000000a,
16885GRBM_SE0_PERF_SEL_RESERVED_0             = 0x0000000b,
16886GRBM_SE0_PERF_SEL_PA_BUSY                = 0x0000000c,
16887GRBM_SE0_PERF_SEL_VGT_BUSY               = 0x0000000d,
16888GRBM_SE0_PERF_SEL_BCI_BUSY               = 0x0000000e,
16889GRBM_SE0_PERF_SEL_RMI_BUSY               = 0x0000000f,
16890} GRBM_SE0_PERF_SEL;
16891
16892/*
16893 * GRBM_SE1_PERF_SEL enum
16894 */
16895
16896typedef enum GRBM_SE1_PERF_SEL {
16897GRBM_SE1_PERF_SEL_COUNT                  = 0x00000000,
16898GRBM_SE1_PERF_SEL_USER_DEFINED           = 0x00000001,
16899GRBM_SE1_PERF_SEL_CB_BUSY                = 0x00000002,
16900GRBM_SE1_PERF_SEL_DB_BUSY                = 0x00000003,
16901GRBM_SE1_PERF_SEL_SC_BUSY                = 0x00000004,
16902GRBM_SE1_PERF_SEL_RESERVED_1             = 0x00000005,
16903GRBM_SE1_PERF_SEL_SPI_BUSY               = 0x00000006,
16904GRBM_SE1_PERF_SEL_SX_BUSY                = 0x00000007,
16905GRBM_SE1_PERF_SEL_TA_BUSY                = 0x00000008,
16906GRBM_SE1_PERF_SEL_CB_CLEAN               = 0x00000009,
16907GRBM_SE1_PERF_SEL_DB_CLEAN               = 0x0000000a,
16908GRBM_SE1_PERF_SEL_RESERVED_0             = 0x0000000b,
16909GRBM_SE1_PERF_SEL_PA_BUSY                = 0x0000000c,
16910GRBM_SE1_PERF_SEL_VGT_BUSY               = 0x0000000d,
16911GRBM_SE1_PERF_SEL_BCI_BUSY               = 0x0000000e,
16912GRBM_SE1_PERF_SEL_RMI_BUSY               = 0x0000000f,
16913} GRBM_SE1_PERF_SEL;
16914
16915/*
16916 * GRBM_SE2_PERF_SEL enum
16917 */
16918
16919typedef enum GRBM_SE2_PERF_SEL {
16920GRBM_SE2_PERF_SEL_COUNT                  = 0x00000000,
16921GRBM_SE2_PERF_SEL_USER_DEFINED           = 0x00000001,
16922GRBM_SE2_PERF_SEL_CB_BUSY                = 0x00000002,
16923GRBM_SE2_PERF_SEL_DB_BUSY                = 0x00000003,
16924GRBM_SE2_PERF_SEL_SC_BUSY                = 0x00000004,
16925GRBM_SE2_PERF_SEL_RESERVED_1             = 0x00000005,
16926GRBM_SE2_PERF_SEL_SPI_BUSY               = 0x00000006,
16927GRBM_SE2_PERF_SEL_SX_BUSY                = 0x00000007,
16928GRBM_SE2_PERF_SEL_TA_BUSY                = 0x00000008,
16929GRBM_SE2_PERF_SEL_CB_CLEAN               = 0x00000009,
16930GRBM_SE2_PERF_SEL_DB_CLEAN               = 0x0000000a,
16931GRBM_SE2_PERF_SEL_RESERVED_0             = 0x0000000b,
16932GRBM_SE2_PERF_SEL_PA_BUSY                = 0x0000000c,
16933GRBM_SE2_PERF_SEL_VGT_BUSY               = 0x0000000d,
16934GRBM_SE2_PERF_SEL_BCI_BUSY               = 0x0000000e,
16935GRBM_SE2_PERF_SEL_RMI_BUSY               = 0x0000000f,
16936} GRBM_SE2_PERF_SEL;
16937
16938/*
16939 * GRBM_SE3_PERF_SEL enum
16940 */
16941
16942typedef enum GRBM_SE3_PERF_SEL {
16943GRBM_SE3_PERF_SEL_COUNT                  = 0x00000000,
16944GRBM_SE3_PERF_SEL_USER_DEFINED           = 0x00000001,
16945GRBM_SE3_PERF_SEL_CB_BUSY                = 0x00000002,
16946GRBM_SE3_PERF_SEL_DB_BUSY                = 0x00000003,
16947GRBM_SE3_PERF_SEL_SC_BUSY                = 0x00000004,
16948GRBM_SE3_PERF_SEL_RESERVED_1             = 0x00000005,
16949GRBM_SE3_PERF_SEL_SPI_BUSY               = 0x00000006,
16950GRBM_SE3_PERF_SEL_SX_BUSY                = 0x00000007,
16951GRBM_SE3_PERF_SEL_TA_BUSY                = 0x00000008,
16952GRBM_SE3_PERF_SEL_CB_CLEAN               = 0x00000009,
16953GRBM_SE3_PERF_SEL_DB_CLEAN               = 0x0000000a,
16954GRBM_SE3_PERF_SEL_RESERVED_0             = 0x0000000b,
16955GRBM_SE3_PERF_SEL_PA_BUSY                = 0x0000000c,
16956GRBM_SE3_PERF_SEL_VGT_BUSY               = 0x0000000d,
16957GRBM_SE3_PERF_SEL_BCI_BUSY               = 0x0000000e,
16958GRBM_SE3_PERF_SEL_RMI_BUSY               = 0x0000000f,
16959} GRBM_SE3_PERF_SEL;
16960
16961/*******************************************************
16962 * CP Enums
16963 *******************************************************/
16964
16965/*
16966 * CP_RING_ID enum
16967 */
16968
16969typedef enum CP_RING_ID {
16970RINGID0                                  = 0x00000000,
16971RINGID1                                  = 0x00000001,
16972RINGID2                                  = 0x00000002,
16973RINGID3                                  = 0x00000003,
16974} CP_RING_ID;
16975
16976/*
16977 * CP_PIPE_ID enum
16978 */
16979
16980typedef enum CP_PIPE_ID {
16981PIPE_ID0                                 = 0x00000000,
16982PIPE_ID1                                 = 0x00000001,
16983PIPE_ID2                                 = 0x00000002,
16984PIPE_ID3                                 = 0x00000003,
16985} CP_PIPE_ID;
16986
16987/*
16988 * CP_ME_ID enum
16989 */
16990
16991typedef enum CP_ME_ID {
16992ME_ID0                                   = 0x00000000,
16993ME_ID1                                   = 0x00000001,
16994ME_ID2                                   = 0x00000002,
16995ME_ID3                                   = 0x00000003,
16996} CP_ME_ID;
16997
16998/*
16999 * SPM_PERFMON_STATE enum
17000 */

17001
17002typedef enum SPM_PERFMON_STATE {
17003STRM_PERFMON_STATE_DISABLE_AND_RESET     = 0x00000000,
17004STRM_PERFMON_STATE_START_COUNTING        = 0x00000001,
17005STRM_PERFMON_STATE_STOP_COUNTING         = 0x00000002,
17006STRM_PERFMON_STATE_RESERVED_3            = 0x00000003,
17007STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM  = 0x00000004,
17008STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
17009} SPM_PERFMON_STATE;
17010
17011/*
17012 * CP_PERFMON_STATE enum
17013 */
17014
17015typedef enum CP_PERFMON_STATE {
17016CP_PERFMON_STATE_DISABLE_AND_RESET       = 0x00000000,
17017CP_PERFMON_STATE_START_COUNTING          = 0x00000001,
17018CP_PERFMON_STATE_STOP_COUNTING           = 0x00000002,
17019CP_PERFMON_STATE_RESERVED_3              = 0x00000003,
17020CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM  = 0x00000004,
17021CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
17022} CP_PERFMON_STATE;
17023
17024/*
17025 * CP_PERFMON_ENABLE_MODE enum
17026 */
17027
17028typedef enum CP_PERFMON_ENABLE_MODE {
17029CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT      = 0x00000000,
17030CP_PERFMON_ENABLE_MODE_RESERVED_1        = 0x00000001,
17031CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE  = 0x00000002,
17032CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE  = 0x00000003,
17033} CP_PERFMON_ENABLE_MODE;
17034
17035/*
17036 * CPG_PERFCOUNT_SEL enum
17037 */
17038
17039typedef enum CPG_PERFCOUNT_SEL {
17040CPG_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
17041CPG_PERF_SEL_RBIU_FIFO_FULL              = 0x00000001,
17042CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR     = 0x00000002,
17043CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL  = 0x00000003,
17044CPG_PERF_SEL_CP_GRBM_DWORDS_SENT         = 0x00000004,
17045CPG_PERF_SEL_ME_PARSER_BUSY              = 0x00000005,
17046CPG_PERF_SEL_COUNT_TYPE0_PACKETS         = 0x00000006,
17047CPG_PERF_SEL_COUNT_TYPE3_PACKETS         = 0x00000007,
17048CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x00000008,
17049CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS      = 0x00000009,
17050CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS  = 0x0000000a,
17051CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS  = 0x0000000b,
17052CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ     = 0x0000000c,
17053CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ    = 0x0000000d,
17054CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX  = 0x0000000e,
17055CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS  = 0x0000000f,
17056CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE  = 0x00000010,
17057CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM  = 0x00000011,
17058CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY    = 0x00000012,
17059CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY    = 0x00000013,
17060CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY   = 0x00000014,
17061CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ  = 0x00000015,
17062CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP  = 0x00000016,
17063CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ  = 0x00000017,
17064CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX  = 0x00000018,
17065CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU  = 0x00000019,
17066CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS  = 0x0000001a,
17067CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH  = 0x0000001b,
17068CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER       = 0x0000001c,
17069CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER     = 0x0000001d,
17070CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS  = 0x0000001e,
17071CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY  = 0x0000001f,
17072CPG_PERF_SEL_DYNAMIC_CLK_VALID           = 0x00000020,
17073CPG_PERF_SEL_REGISTER_CLK_VALID          = 0x00000021,
17074CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT      = 0x00000022,
17075CPG_PERF_SEL_MIU_READ_REQUEST_SENT       = 0x00000023,
17076CPG_PERF_SEL_CE_STALL_RAM_DUMP           = 0x00000024,
17077CPG_PERF_SEL_CE_STALL_RAM_WRITE          = 0x00000025,
17078CPG_PERF_SEL_CE_STALL_ON_INC_FIFO        = 0x00000026,
17079CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO     = 0x00000027,
17080CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU   = 0x00000028,
17081CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ   = 0x00000029,
17082CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG  = 0x0000002a,
17083CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER      = 0x0000002b,
17084CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x0000002c,
17085CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS     = 0x0000002d,
17086CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x0000002e,
17087CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x0000002f,
17088CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000030,
17089} CPG_PERFCOUNT_SEL;
17090
17091/*
17092 * CPF_PERFCOUNT_SEL enum
17093 */
17094
17095typedef enum CPF_PERFCOUNT_SEL {
17096CPF_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
17097CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE  = 0x00000001,
17098CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE  = 0x00000002,
17099CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS  = 0x00000003,
17100CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING  = 0x00000004,
17101CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1   = 0x00000005,
17102CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2   = 0x00000006,
17103CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE  = 0x00000007,
17104CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS  = 0x00000008,
17105CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR         = 0x00000009,
17106CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR      = 0x0000000a,
17107CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x0000000b,
17108CPF_PERF_SEL_GRBM_DWORDS_SENT            = 0x0000000c,
17109CPF_PERF_SEL_DYNAMIC_CLOCK_VALID         = 0x0000000d,
17110CPF_PERF_SEL_REGISTER_CLOCK_VALID        = 0x0000000e,
17111CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND      = 0x0000000f,
17112CPF_PERF_SEL_MIU_READ_REQUEST_SEND       = 0x00000010,
17113CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000011,
17114CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000012,
17115CPF_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000013,
17116CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000014,
17117} CPF_PERFCOUNT_SEL;
17118
17119/*
17120 * CPC_PERFCOUNT_SEL enum
17121 */
17122
17123typedef enum CPC_PERFCOUNT_SEL {
17124CPC_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
17125CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000001,
17126CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION   = 0x00000002,
17127CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE     = 0x00000003,
17128CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE     = 0x00000004,
17129CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x00000005,
17130CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY  = 0x00000006,
17131CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF  = 0x00000007,
17132CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ  = 0x00000008,
17133CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ  = 0x00000009,
17134CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE  = 0x0000000a,
17135CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ  = 0x0000000b,
17136CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF  = 0x0000000c,
17137CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE  = 0x0000000d,
17138CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY  = 0x0000000e,
17139CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF  = 0x0000000f,
17140CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ  = 0x00000010,
17141CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ  = 0x00000011,
17142CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE  = 0x00000012,
17143CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ  = 0x00000013,
17144CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF  = 0x00000014,
17145CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE  = 0x00000015,
17146CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE  = 0x00000016,
17147CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS  = 0x00000017,
17148CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION  = 0x00000018,
17149} CPC_PERFCOUNT_SEL;
17150
17151/*
17152 * CP_ALPHA_TAG_RAM_SEL enum
17153 */
17154
17155typedef enum CP_ALPHA_TAG_RAM_SEL {
17156CPG_TAG_RAM                              = 0x00000000,
17157CPC_TAG_RAM                              = 0x00000001,
17158CPF_TAG_RAM                              = 0x00000002,
17159RSV_TAG_RAM                              = 0x00000003,
17160} CP_ALPHA_TAG_RAM_SEL;
17161
17162/*
17163 * SEM_RESPONSE value
17164 */
17165
17166#define SEM_ECC_ERROR                  0x00000000
17167#define SEM_TRANS_ERROR                0x00000001
17168#define SEM_FAILED                     0x00000002
17169#define SEM_PASSED                     0x00000003
17170
17171/*
17172 * IQ_RETRY_TYPE value
17173 */
17174
17175#define IQ_QUEUE_SLEEP                 0x00000000
17176#define IQ_OFFLOAD_RETRY               0x00000001
17177#define IQ_SCH_WAVE_MSG                0x00000002
17178#define IQ_SEM_REARM                   0x00000003
17179#define IQ_DEQUEUE_RETRY               0x00000004
17180
17181/*
17182 * IQ_INTR_TYPE value
17183 */
17184
17185#define IQ_INTR_TYPE_PQ                0x00000000
17186#define IQ_INTR_TYPE_IB                0x00000001
17187#define IQ_INTR_TYPE_MQD               0x00000002
17188
17189/*
17190 * VMID_SIZE value
17191 */
17192
17193#define VMID_SZ                        0x00000004
17194
17195/*
17196 * CONFIG_SPACE value
17197 */
17198
17199#define CONFIG_SPACE_START             0x00002000
17200#define CONFIG_SPACE_END               0x00009fff
17201
17202/*
17203 * CONFIG_SPACE1 value
17204 */
17205
17206#define CONFIG_SPACE1_START            0x00002000
17207#define CONFIG_SPACE1_END              0x00002bff
17208
17209/*
17210 * CONFIG_SPACE2 value
17211 */
17212
17213#define CONFIG_SPACE2_START            0x00003000
17214#define CONFIG_SPACE2_END              0x00009fff
17215
17216/*
17217 * UCONFIG_SPACE value
17218 */
17219
17220#define UCONFIG_SPACE_START            0x0000c000
17221#define UCONFIG_SPACE_END              0x0000ffff
17222
17223/*
17224 * PERSISTENT_SPACE value
17225 */
17226
17227#define PERSISTENT_SPACE_START         0x00002c00
17228#define PERSISTENT_SPACE_END           0x00002fff
17229
17230/*
17231 * CONTEXT_SPACE value
17232 */
17233
17234#define CONTEXT_SPACE_START            0x0000a000
17235#define CONTEXT_SPACE_END              0x0000bfff
17236
17237/*******************************************************
17238 * SQ_UC Enums
17239 *******************************************************/
17240
17241/*
17242 * VALUE_SQ_ENC_SOP1 value
17243 */
17244
17245#define SQ_ENC_SOP1_BITS               0xbe800000
17246#define SQ_ENC_SOP1_MASK               0xff800000
17247#define SQ_ENC_SOP1_FIELD              0x0000017d
17248
17249/*
17250 * VALUE_SQ_ENC_SOPC value
17251 */
17252
17253#define SQ_ENC_SOPC_BITS               0xbf000000
17254#define SQ_ENC_SOPC_MASK               0xff800000
17255#define SQ_ENC_SOPC_FIELD              0x0000017e
17256
17257/*
17258 * VALUE_SQ_ENC_SOPP value
17259 */
17260
17261#define SQ_ENC_SOPP_BITS               0xbf800000
17262#define SQ_ENC_SOPP_MASK               0xff800000
17263#define SQ_ENC_SOPP_FIELD              0x0000017f
17264
17265/*
17266 * VALUE_SQ_ENC_SOPK value
17267 */
17268
17269#define SQ_ENC_SOPK_BITS               0xb0000000
17270#define SQ_ENC_SOPK_MASK               0xf0000000
17271#define SQ_ENC_SOPK_FIELD              0x0000000b
17272
17273/*
17274 * VALUE_SQ_ENC_SOP2 value
17275 */
17276
17277#define SQ_ENC_SOP2_BITS               0x80000000
17278#define SQ_ENC_SOP2_MASK               0xc0000000
17279#define SQ_ENC_SOP2_FIELD              0x00000002
17280
17281/*
17282 * VALUE_SQ_ENC_SMEM value
17283 */
17284
17285#define SQ_ENC_SMEM_BITS               0xc0000000
17286#define SQ_ENC_SMEM_MASK               0xfc000000
17287#define SQ_ENC_SMEM_FIELD              0x00000030
17288
17289/*
17290 * VALUE_SQ_ENC_VOP1 value
17291 */
17292
17293#define SQ_ENC_VOP1_BITS               0x7e000000
17294#define SQ_ENC_VOP1_MASK               0xfe000000
17295#define SQ_ENC_VOP1_FIELD              0x0000003f
17296
17297/*
17298 * VALUE_SQ_ENC_VOPC value
17299 */
17300
17301#define SQ_ENC_VOPC_BITS               0x7c000000
17302#define SQ_ENC_VOPC_MASK               0xfe000000
17303#define SQ_ENC_VOPC_FIELD              0x0000003e
17304
17305/*
17306 * VALUE_SQ_ENC_VOP2 value
17307 */
17308
17309#define SQ_ENC_VOP2_BITS               0x00000000
17310#define SQ_ENC_VOP2_MASK               0x80000000
17311#define SQ_ENC_VOP2_FIELD              0x00000000
17312
17313/*
17314 * VALUE_SQ_ENC_VINTRP value
17315 */
17316
17317#define SQ_ENC_VINTRP_BITS             0xd4000000
17318#define SQ_ENC_VINTRP_MASK             0xfc000000
17319#define SQ_ENC_VINTRP_FIELD            0x00000035
17320
17321/*
17322 * VALUE_SQ_ENC_VOP3P value
17323 */
17324
17325#define SQ_ENC_VOP3P_BITS              0xd3800000
17326#define SQ_ENC_VOP3P_MASK              0xff800000
17327#define SQ_ENC_VOP3P_FIELD             0x000001a7
17328
17329/*
17330 * VALUE_SQ_ENC_VOP3 value
17331 */
17332
17333#define SQ_ENC_VOP3_BITS               0xd0000000
17334#define SQ_ENC_VOP3_MASK               0xfc000000
17335#define SQ_ENC_VOP3_FIELD              0x00000034
17336
17337/*
17338 * VALUE_SQ_ENC_DS value
17339 */
17340
17341#define SQ_ENC_DS_BITS                 0xd8000000
17342#define SQ_ENC_DS_MASK                 0xfc000000
17343#define SQ_ENC_DS_FIELD                0x00000036
17344
17345/*
17346 * VALUE_SQ_ENC_MUBUF value
17347 */
17348
17349#define SQ_ENC_MUBUF_BITS              0xe0000000
17350#define SQ_ENC_MUBUF_MASK              0xfc000000
17351#define SQ_ENC_MUBUF_FIELD             0x00000038
17352
17353/*
17354 * VALUE_SQ_ENC_MTBUF value
17355 */
17356
17357#define SQ_ENC_MTBUF_BITS              0xe8000000
17358#define SQ_ENC_MTBUF_MASK              0xfc000000
17359#define SQ_ENC_MTBUF_FIELD             0x0000003a
17360
17361/*
17362 * VALUE_SQ_ENC_MIMG value
17363 */
17364
17365#define SQ_ENC_MIMG_BITS               0xf0000000
17366#define SQ_ENC_MIMG_MASK               0xfc000000
17367#define SQ_ENC_MIMG_FIELD              0x0000003c
17368
17369/*
17370 * VALUE_SQ_ENC_EXP value
17371 */
17372
17373#define SQ_ENC_EXP_BITS                0xc4000000
17374#define SQ_ENC_EXP_MASK                0xfc000000
17375#define SQ_ENC_EXP_FIELD               0x00000031
17376
17377/*
17378 * VALUE_SQ_ENC_FLAT value
17379 */
17380
17381#define SQ_ENC_FLAT_BITS               0xdc000000
17382#define SQ_ENC_FLAT_MASK               0xfc000000
17383#define SQ_ENC_FLAT_FIELD              0x00000037
17384
17385/*
17386 * VALUE_SQ_V_OP3_INTRP_COUNT value
17387 */
17388
17389#define SQ_V_OP3_INTRP_COUNT           0x0000000c
17390
17391/*
17392 * VALUE_SQ_SENDMSG_SYSTEM_SIZE value
17393 */
17394
17395#define SQ_SENDMSG_SYSTEM_SIZE         0x00000003
17396
17397/*
17398 * VALUE_SQ_HWREG_ID_SIZE value
17399 */
17400
17401#define SQ_HWREG_ID_SIZE               0x00000006
17402
17403/*
17404 * VALUE_SQ_V_OPC_COUNT value
17405 */
17406
17407#define SQ_V_OPC_COUNT                 0x00000100
17408
17409/*
17410 * VALUE_SQ_NUM_VGPR value
17411 */
17412
17413#define SQ_NUM_VGPR                    0x00000100
17414
17415/*
17416 * VALUE_SQ_WAITCNT_LGKM_SHIFT value
17417 */
17418
17419#define SQ_WAITCNT_LGKM_SHIFT          0x00000008
17420
17421/*
17422 * VALUE_SQ_HWREG_ID_SHIFT value
17423 */
17424
17425#define SQ_HWREG_ID_SHIFT              0x00000000
17426
17427/*
17428 * VALUE_SQ_EXP_NUM_POS value
17429 */
17430
17431#define SQ_EXP_NUM_POS                 0x00000004
17432
17433/*
17434 * VALUE_SQ_XLATE_VOP3_TO_VOPC_OFFSET value
17435 */
17436
17437#define SQ_XLATE_VOP3_TO_VOPC_OFFSET   0x00000000
17438
17439/*
17440 * VALUE_SQ_V_OP3_2IN_OFFSET value
17441 */
17442
17443#define SQ_V_OP3_2IN_OFFSET            0x00000280
17444
17445/*
17446 * VALUE_SQ_XLATE_VOP3_TO_VOP2_OFFSET value
17447 */
17448
17449#define SQ_XLATE_VOP3_TO_VOP2_OFFSET   0x00000100
17450
17451/*
17452 * VALUE_SQ_EXP_NUM_MRT value
17453 */
17454
17455#define SQ_EXP_NUM_MRT                 0x00000008
17456
17457/*
17458 * VALUE_SQ_NUM_TTMP value
17459 */
17460
17461#define SQ_NUM_TTMP                    0x00000010
17462
17463/*
17464 * VALUE_SQ_SENDMSG_STREAMID_SHIFT value
17465 */
17466
17467#define SQ_SENDMSG_STREAMID_SHIFT      0x00000008
17468
17469/*
17470 * VALUE_SQ_V_OP1_COUNT value
17471 */
17472
17473#define SQ_V_OP1_COUNT                 0x00000080
17474
17475/*
17476 * VALUE_SQ_WAITCNT_LGKM_SIZE value
17477 */
17478
17479#define SQ_WAITCNT_LGKM_SIZE           0x00000004
17480
17481/*
17482 * VALUE_SQ_XLATE_VOP3_TO_VOPC_COUNT value
17483 */
17484
17485#define SQ_XLATE_VOP3_TO_VOPC_COUNT    0x00000100
17486
17487/*
17488 * VALUE_SQ_SENDMSG_MSG_SHIFT value
17489 */
17490
17491#define SQ_SENDMSG_MSG_SHIFT           0x00000000
17492
17493/*
17494 * VALUE_SQ_V_OP3_3IN_OFFSET value
17495 */
17496
17497#define SQ_V_OP3_3IN_OFFSET            0x000001c0
17498
17499/*
17500 * VALUE_SQ_HWREG_OFFSET_SHIFT value
17501 */
17502
17503#define SQ_HWREG_OFFSET_SHIFT          0x00000006
17504
17505/*
17506 * VALUE_SQ_HWREG_SIZE_SHIFT value
17507 */
17508
17509#define SQ_HWREG_SIZE_SHIFT            0x0000000b
17510
17511/*
17512 * VALUE_SQ_HWREG_OFFSET_SIZE value
17513 */
17514
17515#define SQ_HWREG_OFFSET_SIZE           0x00000005
17516
17517/*
17518 * VALUE_SQ_V_OP3_3IN_COUNT value
17519 */
17520
17521#define SQ_V_OP3_3IN_COUNT             0x000000b0
17522
17523/*
17524 * VALUE_SQ_SENDMSG_MSG_SIZE value
17525 */
17526
17527#define SQ_SENDMSG_MSG_SIZE            0x00000004
17528
17529/*
17530 * VALUE_SQ_XLATE_VOP3_TO_VOP1_COUNT value
17531 */
17532
17533#define SQ_XLATE_VOP3_TO_VOP1_COUNT    0x00000080
17534
17535/*
17536 * VALUE_SQ_EXP_NUM_GDS value
17537 */
17538
17539#define SQ_EXP_NUM_GDS                 0x00000005
17540
17541/*
17542 * VALUE_SQ_V_OP2_COUNT value
17543 */
17544
17545#define SQ_V_OP2_COUNT                 0x00000040
17546
17547/*
17548 * VALUE_SQ_SENDMSG_GSOP_SIZE value
17549 */
17550
17551#define SQ_SENDMSG_GSOP_SIZE           0x00000002
17552
17553/*
17554 * VALUE_SQ_WAITCNT_VM_SHIFT value
17555 */
17556
17557#define SQ_WAITCNT_VM_SHIFT            0x00000000
17558
17559/*
17560 * VALUE_SQ_XLATE_VOP3_TO_VOP3P_COUNT value
17561 */
17562
17563#define SQ_XLATE_VOP3_TO_VOP3P_COUNT   0x00000080
17564
17565/*
17566 * VALUE_SQ_V_OP3_2IN_COUNT value
17567 */
17568
17569#define SQ_V_OP3_2IN_COUNT             0x00000080
17570
17571/*
17572 * VALUE_SQ_SENDMSG_SYSTEM_SHIFT value
17573 */
17574
17575#define SQ_SENDMSG_SYSTEM_SHIFT        0x00000004
17576
17577/*
17578 * VALUE_SQ_WAITCNT_VM_SIZE value
17579 */
17580
17581#define SQ_WAITCNT_VM_SIZE             0x00000004
17582
17583/*
17584 * VALUE_SQ_XLATE_VOP3_TO_VOP3P_OFFSET value
17585 */
17586
17587#define SQ_XLATE_VOP3_TO_VOP3P_OFFSET  0x00000380
17588
17589/*
17590 * VALUE_SQ_WAITCNT_EXP_SHIFT value
17591 */
17592
17593#define SQ_WAITCNT_EXP_SHIFT           0x00000004
17594
17595/*
17596 * VALUE_SQ_XLATE_VOP3_TO_VOP2_COUNT value
17597 */
17598
17599#define SQ_XLATE_VOP3_TO_VOP2_COUNT    0x00000040
17600
17601/*
17602 * VALUE_SQ_EXP_NUM_PARAM value
17603 */
17604
17605#define SQ_EXP_NUM_PARAM               0x00000020
17606
17607/*
17608 * VALUE_SQ_HWREG_SIZE_SIZE value
17609 */
17610
17611#define SQ_HWREG_SIZE_SIZE             0x00000005
17612
17613/*
17614 * VALUE_SQ_WAITCNT_EXP_SIZE value
17615 */
17616
17617#define SQ_WAITCNT_EXP_SIZE            0x00000003
17618
17619/*
17620 * VALUE_SQ_V_OP3_INTRP_OFFSET value
17621 */
17622
17623#define SQ_V_OP3_INTRP_OFFSET          0x00000274
17624
17625/*
17626 * VALUE_SQ_SENDMSG_GSOP_SHIFT value
17627 */
17628
17629#define SQ_SENDMSG_GSOP_SHIFT          0x00000004
17630
17631/*
17632 * VALUE_SQ_XLATE_VOP3_TO_VINTRP_OFFSET value
17633 */
17634
17635#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x00000270
17636
17637/*
17638 * VALUE_SQ_NUM_ATTR value
17639 */
17640
17641#define SQ_NUM_ATTR                    0x00000021
17642
17643/*
17644 * VALUE_SQ_NUM_SGPR value
17645 */
17646
17647#define SQ_NUM_SGPR                    0x00000066
17648
17649/*
17650 * VALUE_SQ_SRC_VGPR_BIT value
17651 */
17652
17653#define SQ_SRC_VGPR_BIT                0x00000100
17654
17655/*
17656 * VALUE_SQ_V_INTRP_COUNT value
17657 */
17658
17659#define SQ_V_INTRP_COUNT               0x00000004
17660
17661/*
17662 * VALUE_SQ_SENDMSG_STREAMID_SIZE value
17663 */
17664
17665#define SQ_SENDMSG_STREAMID_SIZE       0x00000002
17666
17667/*
17668 * VALUE_SQ_V_OP3P_COUNT value
17669 */
17670
17671#define SQ_V_OP3P_COUNT                0x00000080
17672
17673/*
17674 * VALUE_SQ_XLATE_VOP3_TO_VOP1_OFFSET value
17675 */
17676
17677#define SQ_XLATE_VOP3_TO_VOP1_OFFSET   0x00000140
17678
17679/*
17680 * VALUE_SQ_XLATE_VOP3_TO_VINTRP_COUNT value
17681 */
17682
17683#define SQ_XLATE_VOP3_TO_VINTRP_COUNT  0x00000004
17684
17685/*
17686 * VALUE_SQ_SSRC_SPECIAL_DPP value
17687 */
17688
17689#define SQ_SRC_DPP                     0x000000fa
17690
17691/*
17692 * VALUE_SQ_OP_MTBUF value
17693 */
17694
17695#define SQ_TBUFFER_LOAD_FORMAT_X       0x00000000
17696#define SQ_TBUFFER_LOAD_FORMAT_XY      0x00000001
17697#define SQ_TBUFFER_LOAD_FORMAT_XYZ     0x00000002
17698#define SQ_TBUFFER_LOAD_FORMAT_XYZW    0x00000003
17699#define SQ_TBUFFER_STORE_FORMAT_X      0x00000004
17700#define SQ_TBUFFER_STORE_FORMAT_XY     0x00000005
17701#define SQ_TBUFFER_STORE_FORMAT_XYZ    0x00000006
17702#define SQ_TBUFFER_STORE_FORMAT_XYZW   0x00000007
17703#define SQ_TBUFFER_LOAD_FORMAT_D16_X   0x00000008
17704#define SQ_TBUFFER_LOAD_FORMAT_D16_XY  0x00000009
17705#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0x0000000a
17706#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
17707#define SQ_TBUFFER_STORE_FORMAT_D16_X  0x0000000c
17708#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0x0000000d
17709#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
17710#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
17711
17712/*
17713 * VALUE_SQ_OP_FLAT_GLBL value
17714 */
17715
17716#define SQ_GLOBAL_LOAD_UBYTE           0x00000010
17717#define SQ_GLOBAL_LOAD_SBYTE           0x00000011
17718#define SQ_GLOBAL_LOAD_USHORT          0x00000012
17719#define SQ_GLOBAL_LOAD_SSHORT          0x00000013
17720#define SQ_GLOBAL_LOAD_DWORD           0x00000014
17721#define SQ_GLOBAL_LOAD_DWORDX2         0x00000015
17722#define SQ_GLOBAL_LOAD_DWORDX3         0x00000016
17723#define SQ_GLOBAL_LOAD_DWORDX4         0x00000017
17724#define SQ_GLOBAL_STORE_BYTE           0x00000018
17725#define SQ_GLOBAL_STORE_SHORT          0x0000001a
17726#define SQ_GLOBAL_STORE_DWORD          0x0000001c
17727#define SQ_GLOBAL_STORE_DWORDX2        0x0000001d
17728#define SQ_GLOBAL_STORE_DWORDX3        0x0000001e
17729#define SQ_GLOBAL_STORE_DWORDX4        0x0000001f
17730#define SQ_GLOBAL_ATOMIC_SWAP          0x00000040
17731#define SQ_GLOBAL_ATOMIC_CMPSWAP       0x00000041
17732#define SQ_GLOBAL_ATOMIC_ADD           0x00000042
17733#define SQ_GLOBAL_ATOMIC_SUB           0x00000043
17734#define SQ_GLOBAL_ATOMIC_SMIN          0x00000044
17735#define SQ_GLOBAL_ATOMIC_UMIN          0x00000045
17736#define SQ_GLOBAL_ATOMIC_SMAX          0x00000046
17737#define SQ_GLOBAL_ATOMIC_UMAX          0x00000047
17738#define SQ_GLOBAL_ATOMIC_AND           0x00000048
17739#define SQ_GLOBAL_ATOMIC_OR            0x00000049
17740#define SQ_GLOBAL_ATOMIC_XOR           0x0000004a
17741#define SQ_GLOBAL_ATOMIC_INC           0x0000004b
17742#define SQ_GLOBAL_ATOMIC_DEC           0x0000004c
17743#define SQ_GLOBAL_ATOMIC_SWAP_X2       0x00000060
17744#define SQ_GLOBAL_ATOMIC_CMPSWAP_X2    0x00000061
17745#define SQ_GLOBAL_ATOMIC_ADD_X2        0x00000062
17746#define SQ_GLOBAL_ATOMIC_SUB_X2        0x00000063
17747#define SQ_GLOBAL_ATOMIC_SMIN_X2       0x00000064
17748#define SQ_GLOBAL_ATOMIC_UMIN_X2       0x00000065
17749#define SQ_GLOBAL_ATOMIC_SMAX_X2       0x00000066
17750#define SQ_GLOBAL_ATOMIC_UMAX_X2       0x00000067
17751#define SQ_GLOBAL_ATOMIC_AND_X2        0x00000068
17752#define SQ_GLOBAL_ATOMIC_OR_X2         0x00000069
17753#define SQ_GLOBAL_ATOMIC_XOR_X2        0x0000006a
17754#define SQ_GLOBAL_ATOMIC_INC_X2        0x0000006b
17755#define SQ_GLOBAL_ATOMIC_DEC_X2        0x0000006c
17756
17757/*
17758 * VALUE_SQ_VGPR value
17759 */
17760
17761#define SQ_VGPR0                       0x00000000
17762
17763/*
17764 * VALUE_SQ_OP_FLAT_SCRATCH value
17765 */
17766
17767#define SQ_SCRATCH_LOAD_UBYTE          0x00000010
17768#define SQ_SCRATCH_LOAD_SBYTE          0x00000011
17769#define SQ_SCRATCH_LOAD_USHORT         0x00000012
17770#define SQ_SCRATCH_LOAD_SSHORT         0x00000013
17771#define SQ_SCRATCH_LOAD_DWORD          0x00000014
17772#define SQ_SCRATCH_LOAD_DWORDX2        0x00000015
17773#define SQ_SCRATCH_LOAD_DWORDX3        0x00000016
17774#define SQ_SCRATCH_LOAD_DWORDX4        0x00000017
17775#define SQ_SCRATCH_STORE_BYTE          0x00000018
17776#define SQ_SCRATCH_STORE_SHORT         0x0000001a
17777#define SQ_SCRATCH_STORE_DWORD         0x0000001c
17778#define SQ_SCRATCH_STORE_DWORDX2       0x0000001d
17779#define SQ_SCRATCH_STORE_DWORDX3       0x0000001e
17780#define SQ_SCRATCH_STORE_DWORDX4       0x0000001f
17781
17782/*
17783 * VALUE_SQ_VCC value
17784 */
17785
17786#define SQ_VCC_ALL                     0x00000000
17787
17788/*
17789 * VALUE_SQ_SSRC_0_63_INLINES value
17790 */
17791
17792#define SQ_SRC_0                       0x00000080
17793#define SQ_SRC_1_INT                   0x00000081
17794#define SQ_SRC_2_INT                   0x00000082
17795#define SQ_SRC_3_INT                   0x00000083
17796#define SQ_SRC_4_INT                   0x00000084
17797#define SQ_SRC_5_INT                   0x00000085
17798#define SQ_SRC_6_INT                   0x00000086
17799#define SQ_SRC_7_INT                   0x00000087
17800#define SQ_SRC_8_INT                   0x00000088
17801#define SQ_SRC_9_INT                   0x00000089
17802#define SQ_SRC_10_INT                  0x0000008a
17803#define SQ_SRC_11_INT                  0x0000008b
17804#define SQ_SRC_12_INT                  0x0000008c
17805#define SQ_SRC_13_INT                  0x0000008d
17806#define SQ_SRC_14_INT                  0x0000008e
17807#define SQ_SRC_15_INT                  0x0000008f
17808#define SQ_SRC_16_INT                  0x00000090
17809#define SQ_SRC_17_INT                  0x00000091
17810#define SQ_SRC_18_INT                  0x00000092
17811#define SQ_SRC_19_INT                  0x00000093
17812#define SQ_SRC_20_INT                  0x00000094
17813#define SQ_SRC_21_INT                  0x00000095
17814#define SQ_SRC_22_INT                  0x00000096
17815#define SQ_SRC_23_INT                  0x00000097
17816#define SQ_SRC_24_INT                  0x00000098
17817#define SQ_SRC_25_INT                  0x00000099
17818#define SQ_SRC_26_INT                  0x0000009a
17819#define SQ_SRC_27_INT                  0x0000009b
17820#define SQ_SRC_28_INT                  0x0000009c
17821#define SQ_SRC_29_INT                  0x0000009d
17822#define SQ_SRC_30_INT                  0x0000009e
17823#define SQ_SRC_31_INT                  0x0000009f
17824#define SQ_SRC_32_INT                  0x000000a0
17825#define SQ_SRC_33_INT                  0x000000a1
17826#define SQ_SRC_34_INT                  0x000000a2
17827#define SQ_SRC_35_INT                  0x000000a3
17828#define SQ_SRC_36_INT                  0x000000a4
17829#define SQ_SRC_37_INT                  0x000000a5
17830#define SQ_SRC_38_INT                  0x000000a6
17831#define SQ_SRC_39_INT                  0x000000a7
17832#define SQ_SRC_40_INT                  0x000000a8
17833#define SQ_SRC_41_INT                  0x000000a9
17834#define SQ_SRC_42_INT                  0x000000aa
17835#define SQ_SRC_43_INT                  0x000000ab
17836#define SQ_SRC_44_INT                  0x000000ac
17837#define SQ_SRC_45_INT                  0x000000ad
17838#define SQ_SRC_46_INT                  0x000000ae
17839#define SQ_SRC_47_INT                  0x000000af
17840#define SQ_SRC_48_INT                  0x000000b0
17841#define SQ_SRC_49_INT                  0x000000b1
17842#define SQ_SRC_50_INT                  0x000000b2
17843#define SQ_SRC_51_INT                  0x000000b3
17844#define SQ_SRC_52_INT                  0x000000b4
17845#define SQ_SRC_53_INT                  0x000000b5
17846#define SQ_SRC_54_INT                  0x000000b6
17847#define SQ_SRC_55_INT                  0x000000b7
17848#define SQ_SRC_56_INT                  0x000000b8
17849#define SQ_SRC_57_INT                  0x000000b9
17850#define SQ_SRC_58_INT                  0x000000ba
17851#define SQ_SRC_59_INT                  0x000000bb
17852#define SQ_SRC_60_INT                  0x000000bc
17853#define SQ_SRC_61_INT                  0x000000bd
17854#define SQ_SRC_62_INT                  0x000000be
17855#define SQ_SRC_63_INT                  0x000000bf
17856
17857/*
17858 * VALUE_SQ_OP_MIMG value
17859 */
17860
17861#define SQ_IMAGE_LOAD                  0x00000000
17862#define SQ_IMAGE_LOAD_MIP              0x00000001
17863#define SQ_IMAGE_LOAD_PCK              0x00000002
17864#define SQ_IMAGE_LOAD_PCK_SGN          0x00000003
17865#define SQ_IMAGE_LOAD_MIP_PCK          0x00000004
17866#define SQ_IMAGE_LOAD_MIP_PCK_SGN      0x00000005
17867#define SQ_IMAGE_STORE                 0x00000008
17868#define SQ_IMAGE_STORE_MIP             0x00000009
17869#define SQ_IMAGE_STORE_PCK             0x0000000a
17870#define SQ_IMAGE_STORE_MIP_PCK         0x0000000b
17871#define SQ_IMAGE_GET_RESINFO           0x0000000e
17872#define SQ_IMAGE_ATOMIC_SWAP           0x00000010
17873#define SQ_IMAGE_ATOMIC_CMPSWAP        0x00000011
17874#define SQ_IMAGE_ATOMIC_ADD            0x00000012
17875#define SQ_IMAGE_ATOMIC_SUB            0x00000013
17876#define SQ_IMAGE_ATOMIC_SMIN           0x00000014
17877#define SQ_IMAGE_ATOMIC_UMIN           0x00000015
17878#define SQ_IMAGE_ATOMIC_SMAX           0x00000016
17879#define SQ_IMAGE_ATOMIC_UMAX           0x00000017
17880#define SQ_IMAGE_ATOMIC_AND            0x00000018
17881#define SQ_IMAGE_ATOMIC_OR             0x00000019
17882#define SQ_IMAGE_ATOMIC_XOR            0x0000001a
17883#define SQ_IMAGE_ATOMIC_INC            0x0000001b
17884#define SQ_IMAGE_ATOMIC_DEC            0x0000001c
17885#define SQ_IMAGE_SAMPLE                0x00000020
17886#define SQ_IMAGE_SAMPLE_CL             0x00000021
17887#define SQ_IMAGE_SAMPLE_D              0x00000022
17888#define SQ_IMAGE_SAMPLE_D_CL           0x00000023
17889#define SQ_IMAGE_SAMPLE_L              0x00000024
17890#define SQ_IMAGE_SAMPLE_B              0x00000025
17891#define SQ_IMAGE_SAMPLE_B_CL           0x00000026
17892#define SQ_IMAGE_SAMPLE_LZ             0x00000027
17893#define SQ_IMAGE_SAMPLE_C              0x00000028
17894#define SQ_IMAGE_SAMPLE_C_CL           0x00000029
17895#define SQ_IMAGE_SAMPLE_C_D            0x0000002a
17896#define SQ_IMAGE_SAMPLE_C_D_CL         0x0000002b
17897#define SQ_IMAGE_SAMPLE_C_L            0x0000002c
17898#define SQ_IMAGE_SAMPLE_C_B            0x0000002d
17899#define SQ_IMAGE_SAMPLE_C_B_CL         0x0000002e
17900#define SQ_IMAGE_SAMPLE_C_LZ           0x0000002f
17901#define SQ_IMAGE_SAMPLE_O              0x00000030
17902#define SQ_IMAGE_SAMPLE_CL_O           0x00000031
17903#define SQ_IMAGE_SAMPLE_D_O            0x00000032
17904#define SQ_IMAGE_SAMPLE_D_CL_O         0x00000033
17905#define SQ_IMAGE_SAMPLE_L_O            0x00000034
17906#define SQ_IMAGE_SAMPLE_B_O            0x00000035
17907#define SQ_IMAGE_SAMPLE_B_CL_O         0x00000036
17908#define SQ_IMAGE_SAMPLE_LZ_O           0x00000037
17909#define SQ_IMAGE_SAMPLE_C_O            0x00000038
17910#define SQ_IMAGE_SAMPLE_C_CL_O         0x00000039
17911#define SQ_IMAGE_SAMPLE_C_D_O          0x0000003a
17912#define SQ_IMAGE_SAMPLE_C_D_CL_O       0x0000003b
17913#define SQ_IMAGE_SAMPLE_C_L_O          0x0000003c
17914#define SQ_IMAGE_SAMPLE_C_B_O          0x0000003d
17915#define SQ_IMAGE_SAMPLE_C_B_CL_O       0x0000003e
17916#define SQ_IMAGE_SAMPLE_C_LZ_O         0x0000003f
17917#define SQ_IMAGE_GATHER4               0x00000040
17918#define SQ_IMAGE_GATHER4_CL            0x00000041
17919#define SQ_IMAGE_GATHER4H              0x00000042
17920#define SQ_IMAGE_GATHER4_L             0x00000044
17921#define SQ_IMAGE_GATHER4_B             0x00000045
17922#define SQ_IMAGE_GATHER4_B_CL          0x00000046
17923#define SQ_IMAGE_GATHER4_LZ            0x00000047
17924#define SQ_IMAGE_GATHER4_C             0x00000048
17925#define SQ_IMAGE_GATHER4_C_CL          0x00000049
17926#define SQ_IMAGE_GATHER4H_PCK          0x0000004a
17927#define SQ_IMAGE_GATHER8H_PCK          0x0000004b
17928#define SQ_IMAGE_GATHER4_C_L           0x0000004c
17929#define SQ_IMAGE_GATHER4_C_B           0x0000004d
17930#define SQ_IMAGE_GATHER4_C_B_CL        0x0000004e
17931#define SQ_IMAGE_GATHER4_C_LZ          0x0000004f
17932#define SQ_IMAGE_GATHER4_O             0x00000050
17933#define SQ_IMAGE_GATHER4_CL_O          0x00000051
17934#define SQ_IMAGE_GATHER4_L_O           0x00000054
17935#define SQ_IMAGE_GATHER4_B_O           0x00000055
17936#define SQ_IMAGE_GATHER4_B_CL_O        0x00000056
17937#define SQ_IMAGE_GATHER4_LZ_O          0x00000057
17938#define SQ_IMAGE_GATHER4_C_O           0x00000058
17939#define SQ_IMAGE_GATHER4_C_CL_O        0x00000059
17940#define SQ_IMAGE_GATHER4_C_L_O         0x0000005c
17941#define SQ_IMAGE_GATHER4_C_B_O         0x0000005d
17942#define SQ_IMAGE_GATHER4_C_B_CL_O      0x0000005e
17943#define SQ_IMAGE_GATHER4_C_LZ_O        0x0000005f
17944#define SQ_IMAGE_GET_LOD               0x00000060
17945#define SQ_IMAGE_SAMPLE_CD             0x00000068
17946#define SQ_IMAGE_SAMPLE_CD_CL          0x00000069
17947#define SQ_IMAGE_SAMPLE_C_CD           0x0000006a
17948#define SQ_IMAGE_SAMPLE_C_CD_CL        0x0000006b
17949#define SQ_IMAGE_SAMPLE_CD_O           0x0000006c
17950#define SQ_IMAGE_SAMPLE_CD_CL_O        0x0000006d
17951#define SQ_IMAGE_SAMPLE_C_CD_O         0x0000006e
17952#define SQ_IMAGE_SAMPLE_C_CD_CL_O      0x0000006f
17953#define SQ_IMAGE_RSRC256               0x0000007e
17954#define SQ_IMAGE_SAMPLER               0x0000007f
17955
17956/*
17957 * VALUE_SQ_HW_REG value
17958 */
17959
17960#define SQ_HW_REG_MODE                 0x00000001
17961#define SQ_HW_REG_STATUS               0x00000002
17962#define SQ_HW_REG_TRAPSTS              0x00000003
17963#define SQ_HW_REG_HW_ID                0x00000004
17964#define SQ_HW_REG_GPR_ALLOC            0x00000005
17965#define SQ_HW_REG_LDS_ALLOC            0x00000006
17966#define SQ_HW_REG_IB_STS               0x00000007
17967#define SQ_HW_REG_PC_LO                0x00000008
17968#define SQ_HW_REG_PC_HI                0x00000009
17969#define SQ_HW_REG_INST_DW0             0x0000000a
17970#define SQ_HW_REG_INST_DW1             0x0000000b
17971#define SQ_HW_REG_IB_DBG0              0x0000000c
17972#define SQ_HW_REG_IB_DBG1              0x0000000d
17973#define SQ_HW_REG_FLUSH_IB             0x0000000e
17974#define SQ_HW_REG_SH_MEM_BASES         0x0000000f
17975#define SQ_HW_REG_SQ_SHADER_TBA_LO     0x00000010
17976#define SQ_HW_REG_SQ_SHADER_TBA_HI     0x00000011
17977#define SQ_HW_REG_SQ_SHADER_TMA_LO     0x00000012
17978#define SQ_HW_REG_SQ_SHADER_TMA_HI     0x00000013
17979
17980/*
17981 * VALUE_SQ_OP_SOP1 value
17982 */
17983
17984#define SQ_S_MOV_B32                   0x00000000
17985#define SQ_S_MOV_B64                   0x00000001
17986#define SQ_S_CMOV_B32                  0x00000002
17987#define SQ_S_CMOV_B64                  0x00000003
17988#define SQ_S_NOT_B32                   0x00000004
17989#define SQ_S_NOT_B64                   0x00000005
17990#define SQ_S_WQM_B32                   0x00000006
17991#define SQ_S_WQM_B64                   0x00000007
17992#define SQ_S_BREV_B32                  0x00000008
17993#define SQ_S_BREV_B64                  0x00000009
17994#define SQ_S_BCNT0_I32_B32             0x0000000a
17995#define SQ_S_BCNT0_I32_B64             0x0000000b
17996#define SQ_S_BCNT1_I32_B32             0x0000000c
17997#define SQ_S_BCNT1_I32_B64             0x0000000d
17998#define SQ_S_FF0_I32_B32               0x0000000e
17999#define SQ_S_FF0_I32_B64               0x0000000f
18000#define SQ_S_FF1_I32_B32               0x00000010

18001#define SQ_S_FF1_I32_B64               0x00000011
18002#define SQ_S_FLBIT_I32_B32             0x00000012
18003#define SQ_S_FLBIT_I32_B64             0x00000013
18004#define SQ_S_FLBIT_I32                 0x00000014
18005#define SQ_S_FLBIT_I32_I64             0x00000015
18006#define SQ_S_SEXT_I32_I8               0x00000016
18007#define SQ_S_SEXT_I32_I16              0x00000017
18008#define SQ_S_BITSET0_B32               0x00000018
18009#define SQ_S_BITSET0_B64               0x00000019
18010#define SQ_S_BITSET1_B32               0x0000001a
18011#define SQ_S_BITSET1_B64               0x0000001b
18012#define SQ_S_GETPC_B64                 0x0000001c
18013#define SQ_S_SETPC_B64                 0x0000001d
18014#define SQ_S_SWAPPC_B64                0x0000001e
18015#define SQ_S_RFE_B64                   0x0000001f
18016#define SQ_S_AND_SAVEEXEC_B64          0x00000020
18017#define SQ_S_OR_SAVEEXEC_B64           0x00000021
18018#define SQ_S_XOR_SAVEEXEC_B64          0x00000022
18019#define SQ_S_ANDN2_SAVEEXEC_B64        0x00000023
18020#define SQ_S_ORN2_SAVEEXEC_B64         0x00000024
18021#define SQ_S_NAND_SAVEEXEC_B64         0x00000025
18022#define SQ_S_NOR_SAVEEXEC_B64          0x00000026
18023#define SQ_S_XNOR_SAVEEXEC_B64         0x00000027
18024#define SQ_S_QUADMASK_B32              0x00000028
18025#define SQ_S_QUADMASK_B64              0x00000029
18026#define SQ_S_MOVRELS_B32               0x0000002a
18027#define SQ_S_MOVRELS_B64               0x0000002b
18028#define SQ_S_MOVRELD_B32               0x0000002c
18029#define SQ_S_MOVRELD_B64               0x0000002d
18030#define SQ_S_CBRANCH_JOIN              0x0000002e
18031#define SQ_S_MOV_REGRD_B32             0x0000002f
18032#define SQ_S_ABS_I32                   0x00000030
18033#define SQ_S_MOV_FED_B32               0x00000031
18034#define SQ_S_SET_GPR_IDX_IDX           0x00000032
18035#define SQ_S_ANDN1_SAVEEXEC_B64        0x00000033
18036#define SQ_S_ORN1_SAVEEXEC_B64         0x00000034
18037#define SQ_S_ANDN1_WREXEC_B64          0x00000035
18038#define SQ_S_ANDN2_WREXEC_B64          0x00000036
18039#define SQ_S_BITREPLICATE_B64_B32      0x00000037
18040
18041/*
18042 * VALUE_SQ_CNT value
18043 */
18044
18045#define SQ_CNT1                        0x00000000
18046#define SQ_CNT2                        0x00000001
18047#define SQ_CNT3                        0x00000002
18048#define SQ_CNT4                        0x00000003
18049
18050/*
18051 * VALUE_SQ_OP_VOP3 value
18052 */
18053
18054#define SQ_V_MAD_LEGACY_F32            0x000001c0
18055#define SQ_V_MAD_F32                   0x000001c1
18056#define SQ_V_MAD_I32_I24               0x000001c2
18057#define SQ_V_MAD_U32_U24               0x000001c3
18058#define SQ_V_CUBEID_F32                0x000001c4
18059#define SQ_V_CUBESC_F32                0x000001c5
18060#define SQ_V_CUBETC_F32                0x000001c6
18061#define SQ_V_CUBEMA_F32                0x000001c7
18062#define SQ_V_BFE_U32                   0x000001c8
18063#define SQ_V_BFE_I32                   0x000001c9
18064#define SQ_V_BFI_B32                   0x000001ca
18065#define SQ_V_FMA_F32                   0x000001cb
18066#define SQ_V_FMA_F64                   0x000001cc
18067#define SQ_V_LERP_U8                   0x000001cd
18068#define SQ_V_ALIGNBIT_B32              0x000001ce
18069#define SQ_V_ALIGNBYTE_B32             0x000001cf
18070#define SQ_V_MIN3_F32                  0x000001d0
18071#define SQ_V_MIN3_I32                  0x000001d1
18072#define SQ_V_MIN3_U32                  0x000001d2
18073#define SQ_V_MAX3_F32                  0x000001d3
18074#define SQ_V_MAX3_I32                  0x000001d4
18075#define SQ_V_MAX3_U32                  0x000001d5
18076#define SQ_V_MED3_F32                  0x000001d6
18077#define SQ_V_MED3_I32                  0x000001d7
18078#define SQ_V_MED3_U32                  0x000001d8
18079#define SQ_V_SAD_U8                    0x000001d9
18080#define SQ_V_SAD_HI_U8                 0x000001da
18081#define SQ_V_SAD_U16                   0x000001db
18082#define SQ_V_SAD_U32                   0x000001dc
18083#define SQ_V_CVT_PK_U8_F32             0x000001dd
18084#define SQ_V_DIV_FIXUP_F32             0x000001de
18085#define SQ_V_DIV_FIXUP_F64             0x000001df
18086#define SQ_V_DIV_SCALE_F32             0x000001e0
18087#define SQ_V_DIV_SCALE_F64             0x000001e1
18088#define SQ_V_DIV_FMAS_F32              0x000001e2
18089#define SQ_V_DIV_FMAS_F64              0x000001e3
18090#define SQ_V_MSAD_U8                   0x000001e4
18091#define SQ_V_QSAD_PK_U16_U8            0x000001e5
18092#define SQ_V_MQSAD_PK_U16_U8           0x000001e6
18093#define SQ_V_MQSAD_U32_U8              0x000001e7
18094#define SQ_V_MAD_U64_U32               0x000001e8
18095#define SQ_V_MAD_I64_I32               0x000001e9
18096#define SQ_V_MAD_LEGACY_F16            0x000001ea
18097#define SQ_V_MAD_LEGACY_U16            0x000001eb
18098#define SQ_V_MAD_LEGACY_I16            0x000001ec
18099#define SQ_V_PERM_B32                  0x000001ed
18100#define SQ_V_FMA_LEGACY_F16            0x000001ee
18101#define SQ_V_DIV_FIXUP_LEGACY_F16      0x000001ef
18102#define SQ_V_CVT_PKACCUM_U8_F32        0x000001f0
18103#define SQ_V_MAD_U32_U16               0x000001f1
18104#define SQ_V_MAD_I32_I16               0x000001f2
18105#define SQ_V_XAD_U32                   0x000001f3
18106#define SQ_V_MIN3_F16                  0x000001f4
18107#define SQ_V_MIN3_I16                  0x000001f5
18108#define SQ_V_MIN3_U16                  0x000001f6
18109#define SQ_V_MAX3_F16                  0x000001f7
18110#define SQ_V_MAX3_I16                  0x000001f8
18111#define SQ_V_MAX3_U16                  0x000001f9
18112#define SQ_V_MED3_F16                  0x000001fa
18113#define SQ_V_MED3_I16                  0x000001fb
18114#define SQ_V_MED3_U16                  0x000001fc
18115#define SQ_V_LSHL_ADD_U32              0x000001fd
18116#define SQ_V_ADD_LSHL_U32              0x000001fe
18117#define SQ_V_ADD3_U32                  0x000001ff
18118#define SQ_V_LSHL_OR_B32               0x00000200
18119#define SQ_V_AND_OR_B32                0x00000201
18120#define SQ_V_OR3_B32                   0x00000202
18121#define SQ_V_MAD_F16                   0x00000203
18122#define SQ_V_MAD_U16                   0x00000204
18123#define SQ_V_MAD_I16                   0x00000205
18124#define SQ_V_FMA_F16                   0x00000206
18125#define SQ_V_DIV_FIXUP_F16             0x00000207
18126#define SQ_V_INTERP_P1LL_F16           0x00000274
18127#define SQ_V_INTERP_P1LV_F16           0x00000275
18128#define SQ_V_INTERP_P2_LEGACY_F16      0x00000276
18129#define SQ_V_INTERP_P2_F16             0x00000277
18130#define SQ_V_ADD_F64                   0x00000280
18131#define SQ_V_MUL_F64                   0x00000281
18132#define SQ_V_MIN_F64                   0x00000282
18133#define SQ_V_MAX_F64                   0x00000283
18134#define SQ_V_LDEXP_F64                 0x00000284
18135#define SQ_V_MUL_LO_U32                0x00000285
18136#define SQ_V_MUL_HI_U32                0x00000286
18137#define SQ_V_MUL_HI_I32                0x00000287
18138#define SQ_V_LDEXP_F32                 0x00000288
18139#define SQ_V_READLANE_B32              0x00000289
18140#define SQ_V_WRITELANE_B32             0x0000028a
18141#define SQ_V_BCNT_U32_B32              0x0000028b
18142#define SQ_V_MBCNT_LO_U32_B32          0x0000028c
18143#define SQ_V_MBCNT_HI_U32_B32          0x0000028d
18144#define SQ_V_MAC_LEGACY_F32            0x0000028e
18145#define SQ_V_LSHLREV_B64               0x0000028f
18146#define SQ_V_LSHRREV_B64               0x00000290
18147#define SQ_V_ASHRREV_I64               0x00000291
18148#define SQ_V_TRIG_PREOP_F64            0x00000292
18149#define SQ_V_BFM_B32                   0x00000293
18150#define SQ_V_CVT_PKNORM_I16_F32        0x00000294
18151#define SQ_V_CVT_PKNORM_U16_F32        0x00000295
18152#define SQ_V_CVT_PKRTZ_F16_F32         0x00000296
18153#define SQ_V_CVT_PK_U16_U32            0x00000297
18154#define SQ_V_CVT_PK_I16_I32            0x00000298
18155#define SQ_V_CVT_PKNORM_I16_F16        0x00000299
18156#define SQ_V_CVT_PKNORM_U16_F16        0x0000029a
18157#define SQ_V_READLANE_REGRD_B32        0x0000029b
18158#define SQ_V_ADD_I32                   0x0000029c
18159#define SQ_V_SUB_I32                   0x0000029d
18160#define SQ_V_ADD_I16                   0x0000029e
18161#define SQ_V_SUB_I16                   0x0000029f
18162#define SQ_V_PACK_B32_F16              0x000002a0
18163
18164/*
18165 * VALUE_SQ_SSRC_SPECIAL_LIT value
18166 */
18167
18168#define SQ_SRC_LITERAL                 0x000000ff
18169
18170/*
18171 * VALUE_SQ_DPP_CTRL value
18172 */
18173
18174#define SQ_DPP_QUAD_PERM               0x00000000
18175#define SQ_DPP_ROW_SL1                 0x00000101
18176#define SQ_DPP_ROW_SL2                 0x00000102
18177#define SQ_DPP_ROW_SL3                 0x00000103
18178#define SQ_DPP_ROW_SL4                 0x00000104
18179#define SQ_DPP_ROW_SL5                 0x00000105
18180#define SQ_DPP_ROW_SL6                 0x00000106
18181#define SQ_DPP_ROW_SL7                 0x00000107
18182#define SQ_DPP_ROW_SL8                 0x00000108
18183#define SQ_DPP_ROW_SL9                 0x00000109
18184#define SQ_DPP_ROW_SL10                0x0000010a
18185#define SQ_DPP_ROW_SL11                0x0000010b
18186#define SQ_DPP_ROW_SL12                0x0000010c
18187#define SQ_DPP_ROW_SL13                0x0000010d
18188#define SQ_DPP_ROW_SL14                0x0000010e
18189#define SQ_DPP_ROW_SL15                0x0000010f
18190#define SQ_DPP_ROW_SR1                 0x00000111
18191#define SQ_DPP_ROW_SR2                 0x00000112
18192#define SQ_DPP_ROW_SR3                 0x00000113
18193#define SQ_DPP_ROW_SR4                 0x00000114
18194#define SQ_DPP_ROW_SR5                 0x00000115
18195#define SQ_DPP_ROW_SR6                 0x00000116
18196#define SQ_DPP_ROW_SR7                 0x00000117
18197#define SQ_DPP_ROW_SR8                 0x00000118
18198#define SQ_DPP_ROW_SR9                 0x00000119
18199#define SQ_DPP_ROW_SR10                0x0000011a
18200#define SQ_DPP_ROW_SR11                0x0000011b
18201#define SQ_DPP_ROW_SR12                0x0000011c
18202#define SQ_DPP_ROW_SR13                0x0000011d
18203#define SQ_DPP_ROW_SR14                0x0000011e
18204#define SQ_DPP_ROW_SR15                0x0000011f
18205#define SQ_DPP_ROW_RR1                 0x00000121
18206#define SQ_DPP_ROW_RR2                 0x00000122
18207#define SQ_DPP_ROW_RR3                 0x00000123
18208#define SQ_DPP_ROW_RR4                 0x00000124
18209#define SQ_DPP_ROW_RR5                 0x00000125
18210#define SQ_DPP_ROW_RR6                 0x00000126
18211#define SQ_DPP_ROW_RR7                 0x00000127
18212#define SQ_DPP_ROW_RR8                 0x00000128
18213#define SQ_DPP_ROW_RR9                 0x00000129
18214#define SQ_DPP_ROW_RR10                0x0000012a
18215#define SQ_DPP_ROW_RR11                0x0000012b
18216#define SQ_DPP_ROW_RR12                0x0000012c
18217#define SQ_DPP_ROW_RR13                0x0000012d
18218#define SQ_DPP_ROW_RR14                0x0000012e
18219#define SQ_DPP_ROW_RR15                0x0000012f
18220#define SQ_DPP_WF_SL1                  0x00000130
18221#define SQ_DPP_WF_RL1                  0x00000134
18222#define SQ_DPP_WF_SR1                  0x00000138
18223#define SQ_DPP_WF_RR1                  0x0000013c
18224#define SQ_DPP_ROW_MIRROR              0x00000140
18225#define SQ_DPP_ROW_HALF_MIRROR         0x00000141
18226#define SQ_DPP_ROW_BCAST15             0x00000142
18227#define SQ_DPP_ROW_BCAST31             0x00000143
18228
18229/*
18230 * VALUE_SQ_FLAT_SCRATCH_LOHI value
18231 */
18232
18233#define SQ_FLAT_SCRATCH_LO             0x00000066
18234#define SQ_FLAT_SCRATCH_HI             0x00000067
18235
18236/*
18237 * VALUE_SQ_OP_VOP1 value
18238 */
18239
18240#define SQ_V_NOP                       0x00000000
18241#define SQ_V_MOV_B32                   0x00000001
18242#define SQ_V_READFIRSTLANE_B32         0x00000002
18243#define SQ_V_CVT_I32_F64               0x00000003
18244#define SQ_V_CVT_F64_I32               0x00000004
18245#define SQ_V_CVT_F32_I32               0x00000005
18246#define SQ_V_CVT_F32_U32               0x00000006
18247#define SQ_V_CVT_U32_F32               0x00000007
18248#define SQ_V_CVT_I32_F32               0x00000008
18249#define SQ_V_MOV_FED_B32               0x00000009
18250#define SQ_V_CVT_F16_F32               0x0000000a
18251#define SQ_V_CVT_F32_F16               0x0000000b
18252#define SQ_V_CVT_RPI_I32_F32           0x0000000c
18253#define SQ_V_CVT_FLR_I32_F32           0x0000000d
18254#define SQ_V_CVT_OFF_F32_I4            0x0000000e
18255#define SQ_V_CVT_F32_F64               0x0000000f
18256#define SQ_V_CVT_F64_F32               0x00000010
18257#define SQ_V_CVT_F32_UBYTE0            0x00000011
18258#define SQ_V_CVT_F32_UBYTE1            0x00000012
18259#define SQ_V_CVT_F32_UBYTE2            0x00000013
18260#define SQ_V_CVT_F32_UBYTE3            0x00000014
18261#define SQ_V_CVT_U32_F64               0x00000015
18262#define SQ_V_CVT_F64_U32               0x00000016
18263#define SQ_V_TRUNC_F64                 0x00000017
18264#define SQ_V_CEIL_F64                  0x00000018
18265#define SQ_V_RNDNE_F64                 0x00000019
18266#define SQ_V_FLOOR_F64                 0x0000001a
18267#define SQ_V_FRACT_F32                 0x0000001b
18268#define SQ_V_TRUNC_F32                 0x0000001c
18269#define SQ_V_CEIL_F32                  0x0000001d
18270#define SQ_V_RNDNE_F32                 0x0000001e
18271#define SQ_V_FLOOR_F32                 0x0000001f
18272#define SQ_V_EXP_F32                   0x00000020
18273#define SQ_V_LOG_F32                   0x00000021
18274#define SQ_V_RCP_F32                   0x00000022
18275#define SQ_V_RCP_IFLAG_F32             0x00000023
18276#define SQ_V_RSQ_F32                   0x00000024
18277#define SQ_V_RCP_F64                   0x00000025
18278#define SQ_V_RSQ_F64                   0x00000026
18279#define SQ_V_SQRT_F32                  0x00000027
18280#define SQ_V_SQRT_F64                  0x00000028
18281#define SQ_V_SIN_F32                   0x00000029
18282#define SQ_V_COS_F32                   0x0000002a
18283#define SQ_V_NOT_B32                   0x0000002b
18284#define SQ_V_BFREV_B32                 0x0000002c
18285#define SQ_V_FFBH_U32                  0x0000002d
18286#define SQ_V_FFBL_B32                  0x0000002e
18287#define SQ_V_FFBH_I32                  0x0000002f
18288#define SQ_V_FREXP_EXP_I32_F64         0x00000030
18289#define SQ_V_FREXP_MANT_F64            0x00000031
18290#define SQ_V_FRACT_F64                 0x00000032
18291#define SQ_V_FREXP_EXP_I32_F32         0x00000033
18292#define SQ_V_FREXP_MANT_F32            0x00000034
18293#define SQ_V_CLREXCP                   0x00000035
18294#define SQ_V_MOV_PRSV_B32              0x00000036
18295#define SQ_V_CVT_F16_U16               0x00000039
18296#define SQ_V_CVT_F16_I16               0x0000003a
18297#define SQ_V_CVT_U16_F16               0x0000003b
18298#define SQ_V_CVT_I16_F16               0x0000003c
18299#define SQ_V_RCP_F16                   0x0000003d
18300#define SQ_V_SQRT_F16                  0x0000003e
18301#define SQ_V_RSQ_F16                   0x0000003f
18302#define SQ_V_LOG_F16                   0x00000040
18303#define SQ_V_EXP_F16                   0x00000041
18304#define SQ_V_FREXP_MANT_F16            0x00000042
18305#define SQ_V_FREXP_EXP_I16_F16         0x00000043
18306#define SQ_V_FLOOR_F16                 0x00000044
18307#define SQ_V_CEIL_F16                  0x00000045
18308#define SQ_V_TRUNC_F16                 0x00000046
18309#define SQ_V_RNDNE_F16                 0x00000047
18310#define SQ_V_FRACT_F16                 0x00000048
18311#define SQ_V_SIN_F16                   0x00000049
18312#define SQ_V_COS_F16                   0x0000004a
18313#define SQ_V_EXP_LEGACY_F32            0x0000004b
18314#define SQ_V_LOG_LEGACY_F32            0x0000004c
18315#define SQ_V_CVT_NORM_I16_F16          0x0000004d
18316#define SQ_V_CVT_NORM_U16_F16          0x0000004e
18317#define SQ_V_SAT_PK_U8_I16             0x0000004f
18318#define SQ_V_WRITELANE_IMM32           0x00000050
18319#define SQ_V_SWAP_B32                  0x00000051
18320
18321/*
18322 * VALUE_SQ_OP_FLAT value
18323 */
18324
18325#define SQ_FLAT_LOAD_UBYTE             0x00000010
18326#define SQ_FLAT_LOAD_SBYTE             0x00000011
18327#define SQ_FLAT_LOAD_USHORT            0x00000012
18328#define SQ_FLAT_LOAD_SSHORT            0x00000013
18329#define SQ_FLAT_LOAD_DWORD             0x00000014
18330#define SQ_FLAT_LOAD_DWORDX2           0x00000015
18331#define SQ_FLAT_LOAD_DWORDX3           0x00000016
18332#define SQ_FLAT_LOAD_DWORDX4           0x00000017
18333#define SQ_FLAT_STORE_BYTE             0x00000018
18334#define SQ_FLAT_STORE_SHORT            0x0000001a
18335#define SQ_FLAT_STORE_DWORD            0x0000001c
18336#define SQ_FLAT_STORE_DWORDX2          0x0000001d
18337#define SQ_FLAT_STORE_DWORDX3          0x0000001e
18338#define SQ_FLAT_STORE_DWORDX4          0x0000001f
18339#define SQ_FLAT_ATOMIC_SWAP            0x00000040
18340#define SQ_FLAT_ATOMIC_CMPSWAP         0x00000041
18341#define SQ_FLAT_ATOMIC_ADD             0x00000042
18342#define SQ_FLAT_ATOMIC_SUB             0x00000043
18343#define SQ_FLAT_ATOMIC_SMIN            0x00000044
18344#define SQ_FLAT_ATOMIC_UMIN            0x00000045
18345#define SQ_FLAT_ATOMIC_SMAX            0x00000046
18346#define SQ_FLAT_ATOMIC_UMAX            0x00000047
18347#define SQ_FLAT_ATOMIC_AND             0x00000048
18348#define SQ_FLAT_ATOMIC_OR              0x00000049
18349#define SQ_FLAT_ATOMIC_XOR             0x0000004a
18350#define SQ_FLAT_ATOMIC_INC             0x0000004b
18351#define SQ_FLAT_ATOMIC_DEC             0x0000004c
18352#define SQ_FLAT_ATOMIC_SWAP_X2         0x00000060
18353#define SQ_FLAT_ATOMIC_CMPSWAP_X2      0x00000061
18354#define SQ_FLAT_ATOMIC_ADD_X2          0x00000062
18355#define SQ_FLAT_ATOMIC_SUB_X2          0x00000063
18356#define SQ_FLAT_ATOMIC_SMIN_X2         0x00000064
18357#define SQ_FLAT_ATOMIC_UMIN_X2         0x00000065
18358#define SQ_FLAT_ATOMIC_SMAX_X2         0x00000066
18359#define SQ_FLAT_ATOMIC_UMAX_X2         0x00000067
18360#define SQ_FLAT_ATOMIC_AND_X2          0x00000068
18361#define SQ_FLAT_ATOMIC_OR_X2           0x00000069
18362#define SQ_FLAT_ATOMIC_XOR_X2          0x0000006a
18363#define SQ_FLAT_ATOMIC_INC_X2          0x0000006b
18364#define SQ_FLAT_ATOMIC_DEC_X2          0x0000006c
18365
18366/*
18367 * VALUE_SQ_OP_DS value
18368 */
18369
18370#define SQ_DS_ADD_U32                  0x00000000
18371#define SQ_DS_SUB_U32                  0x00000001
18372#define SQ_DS_RSUB_U32                 0x00000002
18373#define SQ_DS_INC_U32                  0x00000003
18374#define SQ_DS_DEC_U32                  0x00000004
18375#define SQ_DS_MIN_I32                  0x00000005
18376#define SQ_DS_MAX_I32                  0x00000006
18377#define SQ_DS_MIN_U32                  0x00000007
18378#define SQ_DS_MAX_U32                  0x00000008
18379#define SQ_DS_AND_B32                  0x00000009
18380#define SQ_DS_OR_B32                   0x0000000a
18381#define SQ_DS_XOR_B32                  0x0000000b
18382#define SQ_DS_MSKOR_B32                0x0000000c
18383#define SQ_DS_WRITE_B32                0x0000000d
18384#define SQ_DS_WRITE2_B32               0x0000000e
18385#define SQ_DS_WRITE2ST64_B32           0x0000000f
18386#define SQ_DS_CMPST_B32                0x00000010
18387#define SQ_DS_CMPST_F32                0x00000011
18388#define SQ_DS_MIN_F32                  0x00000012
18389#define SQ_DS_MAX_F32                  0x00000013
18390#define SQ_DS_NOP                      0x00000014
18391#define SQ_DS_ADD_F32                  0x00000015
18392#define SQ_DS_WRITE_ADDTID_B32         0x0000001d
18393#define SQ_DS_WRITE_B8                 0x0000001e
18394#define SQ_DS_WRITE_B16                0x0000001f
18395#define SQ_DS_ADD_RTN_U32              0x00000020
18396#define SQ_DS_SUB_RTN_U32              0x00000021
18397#define SQ_DS_RSUB_RTN_U32             0x00000022
18398#define SQ_DS_INC_RTN_U32              0x00000023
18399#define SQ_DS_DEC_RTN_U32              0x00000024
18400#define SQ_DS_MIN_RTN_I32              0x00000025
18401#define SQ_DS_MAX_RTN_I32              0x00000026
18402#define SQ_DS_MIN_RTN_U32              0x00000027
18403#define SQ_DS_MAX_RTN_U32              0x00000028
18404#define SQ_DS_AND_RTN_B32              0x00000029
18405#define SQ_DS_OR_RTN_B32               0x0000002a
18406#define SQ_DS_XOR_RTN_B32              0x0000002b
18407#define SQ_DS_MSKOR_RTN_B32            0x0000002c
18408#define SQ_DS_WRXCHG_RTN_B32           0x0000002d
18409#define SQ_DS_WRXCHG2_RTN_B32          0x0000002e
18410#define SQ_DS_WRXCHG2ST64_RTN_B32      0x0000002f
18411#define SQ_DS_CMPST_RTN_B32            0x00000030
18412#define SQ_DS_CMPST_RTN_F32            0x00000031
18413#define SQ_DS_MIN_RTN_F32              0x00000032
18414#define SQ_DS_MAX_RTN_F32              0x00000033
18415#define SQ_DS_WRAP_RTN_B32             0x00000034
18416#define SQ_DS_ADD_RTN_F32              0x00000035
18417#define SQ_DS_READ_B32                 0x00000036
18418#define SQ_DS_READ2_B32                0x00000037
18419#define SQ_DS_READ2ST64_B32            0x00000038
18420#define SQ_DS_READ_I8                  0x00000039
18421#define SQ_DS_READ_U8                  0x0000003a
18422#define SQ_DS_READ_I16                 0x0000003b
18423#define SQ_DS_READ_U16                 0x0000003c
18424#define SQ_DS_SWIZZLE_B32              0x0000003d
18425#define SQ_DS_PERMUTE_B32              0x0000003e
18426#define SQ_DS_BPERMUTE_B32             0x0000003f
18427#define SQ_DS_ADD_U64                  0x00000040
18428#define SQ_DS_SUB_U64                  0x00000041
18429#define SQ_DS_RSUB_U64                 0x00000042
18430#define SQ_DS_INC_U64                  0x00000043
18431#define SQ_DS_DEC_U64                  0x00000044
18432#define SQ_DS_MIN_I64                  0x00000045
18433#define SQ_DS_MAX_I64                  0x00000046
18434#define SQ_DS_MIN_U64                  0x00000047
18435#define SQ_DS_MAX_U64                  0x00000048
18436#define SQ_DS_AND_B64                  0x00000049
18437#define SQ_DS_OR_B64                   0x0000004a
18438#define SQ_DS_XOR_B64                  0x0000004b
18439#define SQ_DS_MSKOR_B64                0x0000004c
18440#define SQ_DS_WRITE_B64                0x0000004d
18441#define SQ_DS_WRITE2_B64               0x0000004e
18442#define SQ_DS_WRITE2ST64_B64           0x0000004f
18443#define SQ_DS_CMPST_B64                0x00000050
18444#define SQ_DS_CMPST_F64                0x00000051
18445#define SQ_DS_MIN_F64                  0x00000052
18446#define SQ_DS_MAX_F64                  0x00000053
18447#define SQ_DS_ADD_RTN_U64              0x00000060
18448#define SQ_DS_SUB_RTN_U64              0x00000061
18449#define SQ_DS_RSUB_RTN_U64             0x00000062
18450#define SQ_DS_INC_RTN_U64              0x00000063
18451#define SQ_DS_DEC_RTN_U64              0x00000064
18452#define SQ_DS_MIN_RTN_I64              0x00000065
18453#define SQ_DS_MAX_RTN_I64              0x00000066
18454#define SQ_DS_MIN_RTN_U64              0x00000067
18455#define SQ_DS_MAX_RTN_U64              0x00000068
18456#define SQ_DS_AND_RTN_B64              0x00000069
18457#define SQ_DS_OR_RTN_B64               0x0000006a
18458#define SQ_DS_XOR_RTN_B64              0x0000006b
18459#define SQ_DS_MSKOR_RTN_B64            0x0000006c
18460#define SQ_DS_WRXCHG_RTN_B64           0x0000006d
18461#define SQ_DS_WRXCHG2_RTN_B64          0x0000006e
18462#define SQ_DS_WRXCHG2ST64_RTN_B64      0x0000006f
18463#define SQ_DS_CMPST_RTN_B64            0x00000070
18464#define SQ_DS_CMPST_RTN_F64            0x00000071
18465#define SQ_DS_MIN_RTN_F64              0x00000072
18466#define SQ_DS_MAX_RTN_F64              0x00000073
18467#define SQ_DS_READ_B64                 0x00000076
18468#define SQ_DS_READ2_B64                0x00000077
18469#define SQ_DS_READ2ST64_B64            0x00000078
18470#define SQ_DS_CONDXCHG32_RTN_B64       0x0000007e
18471#define SQ_DS_ADD_SRC2_U32             0x00000080
18472#define SQ_DS_SUB_SRC2_U32             0x00000081
18473#define SQ_DS_RSUB_SRC2_U32            0x00000082
18474#define SQ_DS_INC_SRC2_U32             0x00000083
18475#define SQ_DS_DEC_SRC2_U32             0x00000084
18476#define SQ_DS_MIN_SRC2_I32             0x00000085
18477#define SQ_DS_MAX_SRC2_I32             0x00000086
18478#define SQ_DS_MIN_SRC2_U32             0x00000087
18479#define SQ_DS_MAX_SRC2_U32             0x00000088
18480#define SQ_DS_AND_SRC2_B32             0x00000089
18481#define SQ_DS_OR_SRC2_B32              0x0000008a
18482#define SQ_DS_XOR_SRC2_B32             0x0000008b
18483#define SQ_DS_WRITE_SRC2_B32           0x0000008d
18484#define SQ_DS_MIN_SRC2_F32             0x00000092
18485#define SQ_DS_MAX_SRC2_F32             0x00000093
18486#define SQ_DS_ADD_SRC2_F32             0x00000095
18487#define SQ_DS_GWS_SEMA_RELEASE_ALL     0x00000098
18488#define SQ_DS_GWS_INIT                 0x00000099
18489#define SQ_DS_GWS_SEMA_V               0x0000009a
18490#define SQ_DS_GWS_SEMA_BR              0x0000009b
18491#define SQ_DS_GWS_SEMA_P               0x0000009c
18492#define SQ_DS_GWS_BARRIER              0x0000009d
18493#define SQ_DS_READ_ADDTID_B32          0x000000b6
18494#define SQ_DS_CONSUME                  0x000000bd
18495#define SQ_DS_APPEND                   0x000000be
18496#define SQ_DS_ORDERED_COUNT            0x000000bf
18497#define SQ_DS_ADD_SRC2_U64             0x000000c0
18498#define SQ_DS_SUB_SRC2_U64             0x000000c1
18499#define SQ_DS_RSUB_SRC2_U64            0x000000c2
18500#define SQ_DS_INC_SRC2_U64             0x000000c3
18501#define SQ_DS_DEC_SRC2_U64             0x000000c4
18502#define SQ_DS_MIN_SRC2_I64             0x000000c5
18503#define SQ_DS_MAX_SRC2_I64             0x000000c6
18504#define SQ_DS_MIN_SRC2_U64             0x000000c7
18505#define SQ_DS_MAX_SRC2_U64             0x000000c8
18506#define SQ_DS_AND_SRC2_B64             0x000000c9
18507#define SQ_DS_OR_SRC2_B64              0x000000ca
18508#define SQ_DS_XOR_SRC2_B64             0x000000cb
18509#define SQ_DS_WRITE_SRC2_B64           0x000000cd
18510#define SQ_DS_MIN_SRC2_F64             0x000000d2
18511#define SQ_DS_MAX_SRC2_F64             0x000000d3
18512#define SQ_DS_WRITE_B96                0x000000de
18513#define SQ_DS_WRITE_B128               0x000000df
18514#define SQ_DS_CONDXCHG32_RTN_B128      0x000000fd
18515#define SQ_DS_READ_B96                 0x000000fe
18516#define SQ_DS_READ_B128                0x000000ff
18517
18518/*
18519 * VALUE_SQ_OP_SMEM value
18520 */
18521
18522#define SQ_S_LOAD_DWORD                0x00000000
18523#define SQ_S_LOAD_DWORDX2              0x00000001
18524#define SQ_S_LOAD_DWORDX4              0x00000002
18525#define SQ_S_LOAD_DWORDX8              0x00000003
18526#define SQ_S_LOAD_DWORDX16             0x00000004
18527#define SQ_S_SCRATCH_LOAD_DWORD        0x00000005
18528#define SQ_S_SCRATCH_LOAD_DWORDX2      0x00000006
18529#define SQ_S_SCRATCH_LOAD_DWORDX4      0x00000007
18530#define SQ_S_BUFFER_LOAD_DWORD         0x00000008
18531#define SQ_S_BUFFER_LOAD_DWORDX2       0x00000009
18532#define SQ_S_BUFFER_LOAD_DWORDX4       0x0000000a
18533#define SQ_S_BUFFER_LOAD_DWORDX8       0x0000000b
18534#define SQ_S_BUFFER_LOAD_DWORDX16      0x0000000c
18535#define SQ_S_STORE_DWORD               0x00000010
18536#define SQ_S_STORE_DWORDX2             0x00000011
18537#define SQ_S_STORE_DWORDX4             0x00000012
18538#define SQ_S_SCRATCH_STORE_DWORD       0x00000015
18539#define SQ_S_SCRATCH_STORE_DWORDX2     0x00000016
18540#define SQ_S_SCRATCH_STORE_DWORDX4     0x00000017
18541#define SQ_S_BUFFER_STORE_DWORD        0x00000018
18542#define SQ_S_BUFFER_STORE_DWORDX2      0x00000019
18543#define SQ_S_BUFFER_STORE_DWORDX4      0x0000001a
18544#define SQ_S_DCACHE_INV                0x00000020
18545#define SQ_S_DCACHE_WB                 0x00000021
18546#define SQ_S_DCACHE_INV_VOL            0x00000022
18547#define SQ_S_DCACHE_WB_VOL             0x00000023
18548#define SQ_S_MEMTIME                   0x00000024
18549#define SQ_S_MEMREALTIME               0x00000025
18550#define SQ_S_ATC_PROBE                 0x00000026
18551#define SQ_S_ATC_PROBE_BUFFER          0x00000027
18552#define SQ_S_BUFFER_ATOMIC_SWAP        0x00000040
18553#define SQ_S_BUFFER_ATOMIC_CMPSWAP     0x00000041
18554#define SQ_S_BUFFER_ATOMIC_ADD         0x00000042
18555#define SQ_S_BUFFER_ATOMIC_SUB         0x00000043
18556#define SQ_S_BUFFER_ATOMIC_SMIN        0x00000044
18557#define SQ_S_BUFFER_ATOMIC_UMIN        0x00000045
18558#define SQ_S_BUFFER_ATOMIC_SMAX        0x00000046
18559#define SQ_S_BUFFER_ATOMIC_UMAX        0x00000047
18560#define SQ_S_BUFFER_ATOMIC_AND         0x00000048
18561#define SQ_S_BUFFER_ATOMIC_OR          0x00000049
18562#define SQ_S_BUFFER_ATOMIC_XOR         0x0000004a
18563#define SQ_S_BUFFER_ATOMIC_INC         0x0000004b
18564#define SQ_S_BUFFER_ATOMIC_DEC         0x0000004c
18565#define SQ_S_BUFFER_ATOMIC_SWAP_X2     0x00000060
18566#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2  0x00000061
18567#define SQ_S_BUFFER_ATOMIC_ADD_X2      0x00000062
18568#define SQ_S_BUFFER_ATOMIC_SUB_X2      0x00000063
18569#define SQ_S_BUFFER_ATOMIC_SMIN_X2     0x00000064
18570#define SQ_S_BUFFER_ATOMIC_UMIN_X2     0x00000065
18571#define SQ_S_BUFFER_ATOMIC_SMAX_X2     0x00000066
18572#define SQ_S_BUFFER_ATOMIC_UMAX_X2     0x00000067
18573#define SQ_S_BUFFER_ATOMIC_AND_X2      0x00000068
18574#define SQ_S_BUFFER_ATOMIC_OR_X2       0x00000069
18575#define SQ_S_BUFFER_ATOMIC_XOR_X2      0x0000006a
18576#define SQ_S_BUFFER_ATOMIC_INC_X2      0x0000006b
18577#define SQ_S_BUFFER_ATOMIC_DEC_X2      0x0000006c
18578#define SQ_S_ATOMIC_SWAP               0x00000080
18579#define SQ_S_ATOMIC_CMPSWAP            0x00000081
18580#define SQ_S_ATOMIC_ADD                0x00000082
18581#define SQ_S_ATOMIC_SUB                0x00000083
18582#define SQ_S_ATOMIC_SMIN               0x00000084
18583#define SQ_S_ATOMIC_UMIN               0x00000085
18584#define SQ_S_ATOMIC_SMAX               0x00000086
18585#define SQ_S_ATOMIC_UMAX               0x00000087
18586#define SQ_S_ATOMIC_AND                0x00000088
18587#define SQ_S_ATOMIC_OR                 0x00000089
18588#define SQ_S_ATOMIC_XOR                0x0000008a
18589#define SQ_S_ATOMIC_INC                0x0000008b
18590#define SQ_S_ATOMIC_DEC                0x0000008c
18591#define SQ_S_ATOMIC_SWAP_X2            0x000000a0
18592#define SQ_S_ATOMIC_CMPSWAP_X2         0x000000a1
18593#define SQ_S_ATOMIC_ADD_X2             0x000000a2
18594#define SQ_S_ATOMIC_SUB_X2             0x000000a3
18595#define SQ_S_ATOMIC_SMIN_X2            0x000000a4
18596#define SQ_S_ATOMIC_UMIN_X2            0x000000a5
18597#define SQ_S_ATOMIC_SMAX_X2            0x000000a6
18598#define SQ_S_ATOMIC_UMAX_X2            0x000000a7
18599#define SQ_S_ATOMIC_AND_X2             0x000000a8
18600#define SQ_S_ATOMIC_OR_X2              0x000000a9
18601#define SQ_S_ATOMIC_XOR_X2             0x000000aa
18602#define SQ_S_ATOMIC_INC_X2             0x000000ab
18603#define SQ_S_ATOMIC_DEC_X2             0x000000ac
18604
18605/*
18606 * VALUE_SQ_OP_VOP2 value
18607 */
18608
18609#define SQ_V_CNDMASK_B32               0x00000000
18610#define SQ_V_ADD_F32                   0x00000001
18611#define SQ_V_SUB_F32                   0x00000002
18612#define SQ_V_SUBREV_F32                0x00000003
18613#define SQ_V_MUL_LEGACY_F32            0x00000004
18614#define SQ_V_MUL_F32                   0x00000005
18615#define SQ_V_MUL_I32_I24               0x00000006
18616#define SQ_V_MUL_HI_I32_I24            0x00000007
18617#define SQ_V_MUL_U32_U24               0x00000008
18618#define SQ_V_MUL_HI_U32_U24            0x00000009
18619#define SQ_V_MIN_F32                   0x0000000a
18620#define SQ_V_MAX_F32                   0x0000000b
18621#define SQ_V_MIN_I32                   0x0000000c
18622#define SQ_V_MAX_I32                   0x0000000d
18623#define SQ_V_MIN_U32                   0x0000000e
18624#define SQ_V_MAX_U32                   0x0000000f
18625#define SQ_V_LSHRREV_B32               0x00000010
18626#define SQ_V_ASHRREV_I32               0x00000011
18627#define SQ_V_LSHLREV_B32               0x00000012
18628#define SQ_V_AND_B32                   0x00000013
18629#define SQ_V_OR_B32                    0x00000014
18630#define SQ_V_XOR_B32                   0x00000015
18631#define SQ_V_MAC_F32                   0x00000016
18632#define SQ_V_MADMK_F32                 0x00000017
18633#define SQ_V_MADAK_F32                 0x00000018
18634#define SQ_V_ADD_CO_U32                0x00000019
18635#define SQ_V_SUB_CO_U32                0x0000001a
18636#define SQ_V_SUBREV_CO_U32             0x0000001b
18637#define SQ_V_ADDC_CO_U32               0x0000001c
18638#define SQ_V_SUBB_CO_U32               0x0000001d
18639#define SQ_V_SUBBREV_CO_U32            0x0000001e
18640#define SQ_V_ADD_F16                   0x0000001f
18641#define SQ_V_SUB_F16                   0x00000020
18642#define SQ_V_SUBREV_F16                0x00000021
18643#define SQ_V_MUL_F16                   0x00000022
18644#define SQ_V_MAC_F16                   0x00000023
18645#define SQ_V_MADMK_F16                 0x00000024
18646#define SQ_V_MADAK_F16                 0x00000025
18647#define SQ_V_ADD_U16                   0x00000026
18648#define SQ_V_SUB_U16                   0x00000027
18649#define SQ_V_SUBREV_U16                0x00000028
18650#define SQ_V_MUL_LO_U16                0x00000029
18651#define SQ_V_LSHLREV_B16               0x0000002a
18652#define SQ_V_LSHRREV_B16               0x0000002b
18653#define SQ_V_ASHRREV_I16               0x0000002c
18654#define SQ_V_MAX_F16                   0x0000002d
18655#define SQ_V_MIN_F16                   0x0000002e
18656#define SQ_V_MAX_U16                   0x0000002f
18657#define SQ_V_MAX_I16                   0x00000030
18658#define SQ_V_MIN_U16                   0x00000031
18659#define SQ_V_MIN_I16                   0x00000032
18660#define SQ_V_LDEXP_F16                 0x00000033
18661#define SQ_V_ADD_U32                   0x00000034
18662#define SQ_V_SUB_U32                   0x00000035
18663#define SQ_V_SUBREV_U32                0x00000036
18664
18665/*
18666 * VALUE_SQ_SYSMSG_OP value
18667 */
18668
18669#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x00000001
18670#define SQ_SYSMSG_OP_REG_RD            0x00000002
18671#define SQ_SYSMSG_OP_HOST_TRAP_ACK     0x00000003
18672#define SQ_SYSMSG_OP_TTRACE_PC         0x00000004
18673#define SQ_SYSMSG_OP_ILLEGAL_INST_INTERRUPT 0x00000005
18674#define SQ_SYSMSG_OP_MEMVIOL_INTERRUPT 0x00000006
18675
18676/*
18677 * VALUE_SQ_SSRC_SPECIAL_VCCZ value
18678 */
18679
18680#define SQ_SRC_VCCZ                    0x000000fb
18681
18682/*
18683 * VALUE_SQ_CHAN value
18684 */
18685
18686#define SQ_CHAN_X                      0x00000000
18687#define SQ_CHAN_Y                      0x00000001
18688#define SQ_CHAN_Z                      0x00000002
18689#define SQ_CHAN_W                      0x00000003
18690
18691/*
18692 * VALUE_SQ_OP_SOPK value
18693 */
18694
18695#define SQ_S_MOVK_I32                  0x00000000
18696#define SQ_S_CMOVK_I32                 0x00000001
18697#define SQ_S_CMPK_EQ_I32               0x00000002
18698#define SQ_S_CMPK_LG_I32               0x00000003
18699#define SQ_S_CMPK_GT_I32               0x00000004
18700#define SQ_S_CMPK_GE_I32               0x00000005
18701#define SQ_S_CMPK_LT_I32               0x00000006
18702#define SQ_S_CMPK_LE_I32               0x00000007
18703#define SQ_S_CMPK_EQ_U32               0x00000008
18704#define SQ_S_CMPK_LG_U32               0x00000009
18705#define SQ_S_CMPK_GT_U32               0x0000000a
18706#define SQ_S_CMPK_GE_U32               0x0000000b
18707#define SQ_S_CMPK_LT_U32               0x0000000c
18708#define SQ_S_CMPK_LE_U32               0x0000000d
18709#define SQ_S_ADDK_I32                  0x0000000e
18710#define SQ_S_MULK_I32                  0x0000000f
18711#define SQ_S_CBRANCH_I_FORK            0x00000010
18712#define SQ_S_GETREG_B32                0x00000011
18713#define SQ_S_SETREG_B32                0x00000012
18714#define SQ_S_GETREG_REGRD_B32          0x00000013
18715#define SQ_S_SETREG_IMM32_B32          0x00000014
18716#define SQ_S_CALL_B64                  0x00000015
18717
18718/*
18719 * VALUE_SQ_DPP_CTRL_L_1_15 value
18720 */
18721
18722#define SQ_L1                          0x00000001
18723#define SQ_L2                          0x00000002
18724#define SQ_L3                          0x00000003
18725#define SQ_L4                          0x00000004
18726#define SQ_L5                          0x00000005
18727#define SQ_L6                          0x00000006
18728#define SQ_L7                          0x00000007
18729#define SQ_L8                          0x00000008
18730#define SQ_L9                          0x00000009
18731#define SQ_L10                         0x0000000a
18732#define SQ_L11                         0x0000000b
18733#define SQ_L12                         0x0000000c
18734#define SQ_L13                         0x0000000d
18735#define SQ_L14                         0x0000000e
18736#define SQ_L15                         0x0000000f
18737
18738/*
18739 * VALUE_SQ_SGPR value
18740 */
18741
18742#define SQ_SGPR0                       0x00000000
18743
18744/*
18745 * VALUE_SQ_OP_VOP3P value
18746 */
18747
18748#define SQ_V_PK_MAD_I16                0x00000000
18749#define SQ_V_PK_MUL_LO_U16             0x00000001
18750#define SQ_V_PK_ADD_I16                0x00000002
18751#define SQ_V_PK_SUB_I16                0x00000003
18752#define SQ_V_PK_LSHLREV_B16            0x00000004
18753#define SQ_V_PK_LSHRREV_B16            0x00000005
18754#define SQ_V_PK_ASHRREV_I16            0x00000006
18755#define SQ_V_PK_MAX_I16                0x00000007
18756#define SQ_V_PK_MIN_I16                0x00000008
18757#define SQ_V_PK_MAD_U16                0x00000009
18758#define SQ_V_PK_ADD_U16                0x0000000a
18759#define SQ_V_PK_SUB_U16                0x0000000b
18760#define SQ_V_PK_MAX_U16                0x0000000c
18761#define SQ_V_PK_MIN_U16                0x0000000d
18762#define SQ_V_PK_MAD_F16                0x0000000e
18763#define SQ_V_PK_ADD_F16                0x0000000f
18764#define SQ_V_PK_MUL_F16                0x00000010
18765#define SQ_V_PK_MIN_F16                0x00000011
18766#define SQ_V_PK_MAX_F16                0x00000012
18767#define SQ_V_MAD_MIX_F32               0x00000020
18768#define SQ_V_MAD_MIXLO_F16             0x00000021
18769#define SQ_V_MAD_MIXHI_F16             0x00000022
18770
18771/*
18772 * VALUE_SQ_OP_VINTRP value
18773 */
18774
18775#define SQ_V_INTERP_P1_F32             0x00000000
18776#define SQ_V_INTERP_P2_F32             0x00000001
18777#define SQ_V_INTERP_MOV_F32            0x00000002
18778
18779/*
18780 * VALUE_SQ_DPP_CTRL_R_1_15 value
18781 */
18782
18783#define SQ_R1                          0x00000001
18784#define SQ_R2                          0x00000002
18785#define SQ_R3                          0x00000003
18786#define SQ_R4                          0x00000004
18787#define SQ_R5                          0x00000005
18788#define SQ_R6                          0x00000006
18789#define SQ_R7                          0x00000007
18790#define SQ_R8                          0x00000008
18791#define SQ_R9                          0x00000009
18792#define SQ_R10                         0x0000000a
18793#define SQ_R11                         0x0000000b
18794#define SQ_R12                         0x0000000c
18795#define SQ_R13                         0x0000000d
18796#define SQ_R14                         0x0000000e
18797#define SQ_R15                         0x0000000f
18798
18799/*
18800 * VALUE_SQ_OP_SOP2 value
18801 */
18802
18803#define SQ_S_ADD_U32                   0x00000000
18804#define SQ_S_SUB_U32                   0x00000001
18805#define SQ_S_ADD_I32                   0x00000002
18806#define SQ_S_SUB_I32                   0x00000003
18807#define SQ_S_ADDC_U32                  0x00000004
18808#define SQ_S_SUBB_U32                  0x00000005
18809#define SQ_S_MIN_I32                   0x00000006
18810#define SQ_S_MIN_U32                   0x00000007
18811#define SQ_S_MAX_I32                   0x00000008
18812#define SQ_S_MAX_U32                   0x00000009
18813#define SQ_S_CSELECT_B32               0x0000000a
18814#define SQ_S_CSELECT_B64               0x0000000b
18815#define SQ_S_AND_B32                   0x0000000c
18816#define SQ_S_AND_B64                   0x0000000d
18817#define SQ_S_OR_B32                    0x0000000e
18818#define SQ_S_OR_B64                    0x0000000f
18819#define SQ_S_XOR_B32                   0x00000010
18820#define SQ_S_XOR_B64                   0x00000011
18821#define SQ_S_ANDN2_B32                 0x00000012
18822#define SQ_S_ANDN2_B64                 0x00000013
18823#define SQ_S_ORN2_B32                  0x00000014
18824#define SQ_S_ORN2_B64                  0x00000015
18825#define SQ_S_NAND_B32                  0x00000016
18826#define SQ_S_NAND_B64                  0x00000017
18827#define SQ_S_NOR_B32                   0x00000018
18828#define SQ_S_NOR_B64                   0x00000019
18829#define SQ_S_XNOR_B32                  0x0000001a
18830#define SQ_S_XNOR_B64                  0x0000001b
18831#define SQ_S_LSHL_B32                  0x0000001c
18832#define SQ_S_LSHL_B64                  0x0000001d
18833#define SQ_S_LSHR_B32                  0x0000001e
18834#define SQ_S_LSHR_B64                  0x0000001f
18835#define SQ_S_ASHR_I32                  0x00000020
18836#define SQ_S_ASHR_I64                  0x00000021
18837#define SQ_S_BFM_B32                   0x00000022
18838#define SQ_S_BFM_B64                   0x00000023
18839#define SQ_S_MUL_I32                   0x00000024
18840#define SQ_S_BFE_U32                   0x00000025
18841#define SQ_S_BFE_I32                   0x00000026
18842#define SQ_S_BFE_U64                   0x00000027
18843#define SQ_S_BFE_I64                   0x00000028
18844#define SQ_S_CBRANCH_G_FORK            0x00000029
18845#define SQ_S_ABSDIFF_I32               0x0000002a
18846#define SQ_S_RFE_RESTORE_B64           0x0000002b
18847#define SQ_S_MUL_HI_U32                0x0000002c
18848#define SQ_S_MUL_HI_I32                0x0000002d
18849#define SQ_S_LSHL1_ADD_U32             0x0000002e
18850#define SQ_S_LSHL2_ADD_U32             0x0000002f
18851#define SQ_S_LSHL3_ADD_U32             0x00000030
18852#define SQ_S_LSHL4_ADD_U32             0x00000031
18853#define SQ_S_PACK_LL_B32_B16           0x00000032
18854#define SQ_S_PACK_LH_B32_B16           0x00000033
18855#define SQ_S_PACK_HH_B32_B16           0x00000034
18856
18857/*
18858 * VALUE_SQ_SEG value
18859 */
18860
18861#define SQ_FLAT                        0x00000000
18862#define SQ_SCRATCH                     0x00000001
18863#define SQ_GLOBAL                      0x00000002
18864
18865/*
18866 * VALUE_SQ_SDST_EXEC value
18867 */
18868
18869#define SQ_EXEC_LO                     0x0000007e
18870#define SQ_EXEC_HI                     0x0000007f
18871
18872/*
18873 * VALUE_SQ_SSRC_SPECIAL_NOLIT value
18874 */
18875
18876#define SQ_SRC_64_INT                  0x000000c0
18877#define SQ_SRC_M_1_INT                 0x000000c1
18878#define SQ_SRC_M_2_INT                 0x000000c2
18879#define SQ_SRC_M_3_INT                 0x000000c3
18880#define SQ_SRC_M_4_INT                 0x000000c4
18881#define SQ_SRC_M_5_INT                 0x000000c5
18882#define SQ_SRC_M_6_INT                 0x000000c6
18883#define SQ_SRC_M_7_INT                 0x000000c7
18884#define SQ_SRC_M_8_INT                 0x000000c8
18885#define SQ_SRC_M_9_INT                 0x000000c9
18886#define SQ_SRC_M_10_INT                0x000000ca
18887#define SQ_SRC_M_11_INT                0x000000cb
18888#define SQ_SRC_M_12_INT                0x000000cc
18889#define SQ_SRC_M_13_INT                0x000000cd
18890#define SQ_SRC_M_14_INT                0x000000ce
18891#define SQ_SRC_M_15_INT                0x000000cf
18892#define SQ_SRC_M_16_INT                0x000000d0
18893#define SQ_SRC_0_5                     0x000000f0
18894#define SQ_SRC_M_0_5                   0x000000f1
18895#define SQ_SRC_1                       0x000000f2
18896#define SQ_SRC_M_1                     0x000000f3
18897#define SQ_SRC_2                       0x000000f4
18898#define SQ_SRC_M_2                     0x000000f5
18899#define SQ_SRC_4                       0x000000f6
18900#define SQ_SRC_M_4                     0x000000f7
18901#define SQ_SRC_INV_2PI                 0x000000f8
18902
18903/*
18904 * VALUE_SQ_VCC_LOHI value
18905 */
18906
18907#define SQ_VCC_LO                      0x0000006a
18908#define SQ_VCC_HI                      0x0000006b
18909
18910/*
18911 * VALUE_SQ_TGT value
18912 */
18913
18914#define SQ_EXP_MRT0                    0x00000000
18915#define SQ_EXP_MRTZ                    0x00000008
18916#define SQ_EXP_NULL                    0x00000009
18917#define SQ_EXP_POS0                    0x0000000c
18918#define SQ_EXP_PARAM0                  0x00000020
18919
18920/*
18921 * VALUE_SQ_OP_SOPP value
18922 */
18923
18924#define SQ_S_NOP                       0x00000000
18925#define SQ_S_ENDPGM                    0x00000001
18926#define SQ_S_BRANCH                    0x00000002
18927#define SQ_S_WAKEUP                    0x00000003
18928#define SQ_S_CBRANCH_SCC0              0x00000004
18929#define SQ_S_CBRANCH_SCC1              0x00000005
18930#define SQ_S_CBRANCH_VCCZ              0x00000006
18931#define SQ_S_CBRANCH_VCCNZ             0x00000007
18932#define SQ_S_CBRANCH_EXECZ             0x00000008
18933#define SQ_S_CBRANCH_EXECNZ            0x00000009
18934#define SQ_S_BARRIER                   0x0000000a
18935#define SQ_S_SETKILL                   0x0000000b
18936#define SQ_S_WAITCNT                   0x0000000c
18937#define SQ_S_SETHALT                   0x0000000d
18938#define SQ_S_SLEEP                     0x0000000e
18939#define SQ_S_SETPRIO                   0x0000000f
18940#define SQ_S_SENDMSG                   0x00000010
18941#define SQ_S_SENDMSGHALT               0x00000011
18942#define SQ_S_TRAP                      0x00000012
18943#define SQ_S_ICACHE_INV                0x00000013
18944#define SQ_S_INCPERFLEVEL              0x00000014
18945#define SQ_S_DECPERFLEVEL              0x00000015
18946#define SQ_S_TTRACEDATA                0x00000016
18947#define SQ_S_CBRANCH_CDBGSYS           0x00000017
18948#define SQ_S_CBRANCH_CDBGUSER          0x00000018
18949#define SQ_S_CBRANCH_CDBGSYS_OR_USER   0x00000019
18950#define SQ_S_CBRANCH_CDBGSYS_AND_USER  0x0000001a
18951#define SQ_S_ENDPGM_SAVED              0x0000001b
18952#define SQ_S_SET_GPR_IDX_OFF           0x0000001c
18953#define SQ_S_SET_GPR_IDX_MODE          0x0000001d
18954#define SQ_S_ENDPGM_ORDERED_PS_DONE    0x0000001e
18955
18956/*
18957 * VALUE_SQ_OP_EXP value
18958 */
18959
18960#define SQ_EXP                         0x00000000
18961
18962/*
18963 * VALUE_SQ_SSRC_SPECIAL_POPS_EXITING_WAVE_ID value
18964 */
18965
18966#define SQ_SRC_POPS_EXITING_WAVE_ID    0x000000ef
18967
18968/*
18969 * VALUE_SQ_XNACK_MASK_LOHI value
18970 */
18971
18972#define SQ_XNACK_MASK_LO               0x00000068
18973#define SQ_XNACK_MASK_HI               0x00000069
18974
18975/*
18976 * VALUE_SQ_OMOD value
18977 */
18978
18979#define SQ_OMOD_OFF                    0x00000000
18980#define SQ_OMOD_M2                     0x00000001
18981#define SQ_OMOD_M4                     0x00000002
18982#define SQ_OMOD_D2                     0x00000003
18983
18984/*
18985 * VALUE_SQ_SSRC_SPECIAL_EXECZ value
18986 */
18987
18988#define SQ_SRC_EXECZ                   0x000000fc
18989
18990/*
18991 * VALUE_SQ_COMPI value
18992 */
18993
18994#define SQ_F                           0x00000000
18995#define SQ_LT                          0x00000001
18996#define SQ_EQ                          0x00000002
18997#define SQ_LE                          0x00000003
18998#define SQ_GT                          0x00000004
18999#define SQ_NE                          0x00000005
19000#define SQ_GE                          0x00000006

19001#define SQ_T                           0x00000007
19002
19003/*
19004 * VALUE_SQ_DPP_BOUND_CTRL value
19005 */
19006
19007#define SQ_DPP_BOUND_OFF               0x00000000
19008#define SQ_DPP_BOUND_ZERO              0x00000001
19009
19010/*
19011 * VALUE_SQ_SDST_M0 value
19012 */
19013
19014#define SQ_M0                          0x0000007c
19015
19016/*
19017 * VALUE_SQ_MSG value
19018 */
19019
19020#define SQ_MSG_INTERRUPT               0x00000001
19021#define SQ_MSG_GS                      0x00000002
19022#define SQ_MSG_GS_DONE                 0x00000003
19023#define SQ_MSG_SAVEWAVE                0x00000004
19024#define SQ_MSG_STALL_WAVE_GEN          0x00000005
19025#define SQ_MSG_HALT_WAVES              0x00000006
19026#define SQ_MSG_ORDERED_PS_DONE         0x00000007
19027#define SQ_MSG_EARLY_PRIM_DEALLOC      0x00000008
19028#define SQ_MSG_GS_ALLOC_REQ            0x00000009
19029#define SQ_MSG_SYSMSG                  0x0000000f
19030
19031/*
19032 * VALUE_SQ_PARAM value
19033 */
19034
19035#define SQ_PARAM_P10                   0x00000000
19036#define SQ_PARAM_P20                   0x00000001
19037#define SQ_PARAM_P0                    0x00000002
19038
19039/*
19040 * VALUE_SQ_OPU_VOP3 value
19041 */
19042
19043#define SQ_V_OPC_OFFSET                0x00000000
19044#define SQ_V_OP2_OFFSET                0x00000100
19045#define SQ_V_OP1_OFFSET                0x00000140
19046#define SQ_V_INTRP_OFFSET              0x00000270
19047#define SQ_V_OP3P_OFFSET               0x00000380
19048
19049/*
19050 * VALUE_SQ_SSRC_SPECIAL_SDWA value
19051 */
19052
19053#define SQ_SRC_SDWA                    0x000000f9
19054
19055/*
19056 * VALUE_SQ_SSRC_SPECIAL_APERTURE value
19057 */
19058
19059#define SQ_SRC_SHARED_BASE             0x000000eb
19060#define SQ_SRC_SHARED_LIMIT            0x000000ec
19061#define SQ_SRC_PRIVATE_BASE            0x000000ed
19062#define SQ_SRC_PRIVATE_LIMIT           0x000000ee
19063
19064/*
19065 * VALUE_SQ_COMPF value
19066 */
19067
19068#define SQ_F                           0x00000000
19069#define SQ_LT                          0x00000001
19070#define SQ_EQ                          0x00000002
19071#define SQ_LE                          0x00000003
19072#define SQ_GT                          0x00000004
19073#define SQ_LG                          0x00000005
19074#define SQ_GE                          0x00000006
19075#define SQ_O                           0x00000007
19076#define SQ_U                           0x00000008
19077#define SQ_NGE                         0x00000009
19078#define SQ_NLG                         0x0000000a
19079#define SQ_NGT                         0x0000000b
19080#define SQ_NLE                         0x0000000c
19081#define SQ_NEQ                         0x0000000d
19082#define SQ_NLT                         0x0000000e
19083#define SQ_TRU                         0x0000000f
19084
19085/*
19086 * VALUE_SQ_SDWA_UNUSED value
19087 */
19088
19089#define SQ_SDWA_UNUSED_PAD             0x00000000
19090#define SQ_SDWA_UNUSED_SEXT            0x00000001
19091#define SQ_SDWA_UNUSED_PRESERVE        0x00000002
19092
19093/*
19094 * VALUE_SQ_SSRC_SPECIAL_SCC value
19095 */
19096
19097#define SQ_SRC_SCC                     0x000000fd
19098
19099/*
19100 * VALUE_SQ_OP_VOPC value
19101 */
19102
19103#define SQ_V_CMP_CLASS_F32             0x00000010
19104#define SQ_V_CMPX_CLASS_F32            0x00000011
19105#define SQ_V_CMP_CLASS_F64             0x00000012
19106#define SQ_V_CMPX_CLASS_F64            0x00000013
19107#define SQ_V_CMP_CLASS_F16             0x00000014
19108#define SQ_V_CMPX_CLASS_F16            0x00000015
19109#define SQ_V_CMP_F_F16                 0x00000020
19110#define SQ_V_CMP_LT_F16                0x00000021
19111#define SQ_V_CMP_EQ_F16                0x00000022
19112#define SQ_V_CMP_LE_F16                0x00000023
19113#define SQ_V_CMP_GT_F16                0x00000024
19114#define SQ_V_CMP_LG_F16                0x00000025
19115#define SQ_V_CMP_GE_F16                0x00000026
19116#define SQ_V_CMP_O_F16                 0x00000027
19117#define SQ_V_CMP_U_F16                 0x00000028
19118#define SQ_V_CMP_NGE_F16               0x00000029
19119#define SQ_V_CMP_NLG_F16               0x0000002a
19120#define SQ_V_CMP_NGT_F16               0x0000002b
19121#define SQ_V_CMP_NLE_F16               0x0000002c
19122#define SQ_V_CMP_NEQ_F16               0x0000002d
19123#define SQ_V_CMP_NLT_F16               0x0000002e
19124#define SQ_V_CMP_TRU_F16               0x0000002f
19125#define SQ_V_CMPX_F_F16                0x00000030
19126#define SQ_V_CMPX_LT_F16               0x00000031
19127#define SQ_V_CMPX_EQ_F16               0x00000032
19128#define SQ_V_CMPX_LE_F16               0x00000033
19129#define SQ_V_CMPX_GT_F16               0x00000034
19130#define SQ_V_CMPX_LG_F16               0x00000035
19131#define SQ_V_CMPX_GE_F16               0x00000036
19132#define SQ_V_CMPX_O_F16                0x00000037
19133#define SQ_V_CMPX_U_F16                0x00000038
19134#define SQ_V_CMPX_NGE_F16              0x00000039
19135#define SQ_V_CMPX_NLG_F16              0x0000003a
19136#define SQ_V_CMPX_NGT_F16              0x0000003b
19137#define SQ_V_CMPX_NLE_F16              0x0000003c
19138#define SQ_V_CMPX_NEQ_F16              0x0000003d
19139#define SQ_V_CMPX_NLT_F16              0x0000003e
19140#define SQ_V_CMPX_TRU_F16              0x0000003f
19141#define SQ_V_CMP_F_F32                 0x00000040
19142#define SQ_V_CMP_LT_F32                0x00000041
19143#define SQ_V_CMP_EQ_F32                0x00000042
19144#define SQ_V_CMP_LE_F32                0x00000043
19145#define SQ_V_CMP_GT_F32                0x00000044
19146#define SQ_V_CMP_LG_F32                0x00000045
19147#define SQ_V_CMP_GE_F32                0x00000046
19148#define SQ_V_CMP_O_F32                 0x00000047
19149#define SQ_V_CMP_U_F32                 0x00000048
19150#define SQ_V_CMP_NGE_F32               0x00000049
19151#define SQ_V_CMP_NLG_F32               0x0000004a
19152#define SQ_V_CMP_NGT_F32               0x0000004b
19153#define SQ_V_CMP_NLE_F32               0x0000004c
19154#define SQ_V_CMP_NEQ_F32               0x0000004d
19155#define SQ_V_CMP_NLT_F32               0x0000004e
19156#define SQ_V_CMP_TRU_F32               0x0000004f
19157#define SQ_V_CMPX_F_F32                0x00000050
19158#define SQ_V_CMPX_LT_F32               0x00000051
19159#define SQ_V_CMPX_EQ_F32               0x00000052
19160#define SQ_V_CMPX_LE_F32               0x00000053
19161#define SQ_V_CMPX_GT_F32               0x00000054
19162#define SQ_V_CMPX_LG_F32               0x00000055
19163#define SQ_V_CMPX_GE_F32               0x00000056
19164#define SQ_V_CMPX_O_F32                0x00000057
19165#define SQ_V_CMPX_U_F32                0x00000058
19166#define SQ_V_CMPX_NGE_F32              0x00000059
19167#define SQ_V_CMPX_NLG_F32              0x0000005a
19168#define SQ_V_CMPX_NGT_F32              0x0000005b
19169#define SQ_V_CMPX_NLE_F32              0x0000005c
19170#define SQ_V_CMPX_NEQ_F32              0x0000005d
19171#define SQ_V_CMPX_NLT_F32              0x0000005e
19172#define SQ_V_CMPX_TRU_F32              0x0000005f
19173#define SQ_V_CMP_F_F64                 0x00000060
19174#define SQ_V_CMP_LT_F64                0x00000061
19175#define SQ_V_CMP_EQ_F64                0x00000062
19176#define SQ_V_CMP_LE_F64                0x00000063
19177#define SQ_V_CMP_GT_F64                0x00000064
19178#define SQ_V_CMP_LG_F64                0x00000065
19179#define SQ_V_CMP_GE_F64                0x00000066
19180#define SQ_V_CMP_O_F64                 0x00000067
19181#define SQ_V_CMP_U_F64                 0x00000068
19182#define SQ_V_CMP_NGE_F64               0x00000069
19183#define SQ_V_CMP_NLG_F64               0x0000006a
19184#define SQ_V_CMP_NGT_F64               0x0000006b
19185#define SQ_V_CMP_NLE_F64               0x0000006c
19186#define SQ_V_CMP_NEQ_F64               0x0000006d
19187#define SQ_V_CMP_NLT_F64               0x0000006e
19188#define SQ_V_CMP_TRU_F64               0x0000006f
19189#define SQ_V_CMPX_F_F64                0x00000070
19190#define SQ_V_CMPX_LT_F64               0x00000071
19191#define SQ_V_CMPX_EQ_F64               0x00000072
19192#define SQ_V_CMPX_LE_F64               0x00000073
19193#define SQ_V_CMPX_GT_F64               0x00000074
19194#define SQ_V_CMPX_LG_F64               0x00000075
19195#define SQ_V_CMPX_GE_F64               0x00000076
19196#define SQ_V_CMPX_O_F64                0x00000077
19197#define SQ_V_CMPX_U_F64                0x00000078
19198#define SQ_V_CMPX_NGE_F64              0x00000079
19199#define SQ_V_CMPX_NLG_F64              0x0000007a
19200#define SQ_V_CMPX_NGT_F64              0x0000007b
19201#define SQ_V_CMPX_NLE_F64              0x0000007c
19202#define SQ_V_CMPX_NEQ_F64              0x0000007d
19203#define SQ_V_CMPX_NLT_F64              0x0000007e
19204#define SQ_V_CMPX_TRU_F64              0x0000007f
19205#define SQ_V_CMP_F_I16                 0x000000a0
19206#define SQ_V_CMP_LT_I16                0x000000a1
19207#define SQ_V_CMP_EQ_I16                0x000000a2
19208#define SQ_V_CMP_LE_I16                0x000000a3
19209#define SQ_V_CMP_GT_I16                0x000000a4
19210#define SQ_V_CMP_NE_I16                0x000000a5
19211#define SQ_V_CMP_GE_I16                0x000000a6
19212#define SQ_V_CMP_T_I16                 0x000000a7
19213#define SQ_V_CMP_F_U16                 0x000000a8
19214#define SQ_V_CMP_LT_U16                0x000000a9
19215#define SQ_V_CMP_EQ_U16                0x000000aa
19216#define SQ_V_CMP_LE_U16                0x000000ab
19217#define SQ_V_CMP_GT_U16                0x000000ac
19218#define SQ_V_CMP_NE_U16                0x000000ad
19219#define SQ_V_CMP_GE_U16                0x000000ae
19220#define SQ_V_CMP_T_U16                 0x000000af
19221#define SQ_V_CMPX_F_I16                0x000000b0
19222#define SQ_V_CMPX_LT_I16               0x000000b1
19223#define SQ_V_CMPX_EQ_I16               0x000000b2
19224#define SQ_V_CMPX_LE_I16               0x000000b3
19225#define SQ_V_CMPX_GT_I16               0x000000b4
19226#define SQ_V_CMPX_NE_I16               0x000000b5
19227#define SQ_V_CMPX_GE_I16               0x000000b6
19228#define SQ_V_CMPX_T_I16                0x000000b7
19229#define SQ_V_CMPX_F_U16                0x000000b8
19230#define SQ_V_CMPX_LT_U16               0x000000b9
19231#define SQ_V_CMPX_EQ_U16               0x000000ba
19232#define SQ_V_CMPX_LE_U16               0x000000bb
19233#define SQ_V_CMPX_GT_U16               0x000000bc
19234#define SQ_V_CMPX_NE_U16               0x000000bd
19235#define SQ_V_CMPX_GE_U16               0x000000be
19236#define SQ_V_CMPX_T_U16                0x000000bf
19237#define SQ_V_CMP_F_I32                 0x000000c0
19238#define SQ_V_CMP_LT_I32                0x000000c1
19239#define SQ_V_CMP_EQ_I32                0x000000c2
19240#define SQ_V_CMP_LE_I32                0x000000c3
19241#define SQ_V_CMP_GT_I32                0x000000c4
19242#define SQ_V_CMP_NE_I32                0x000000c5
19243#define SQ_V_CMP_GE_I32                0x000000c6
19244#define SQ_V_CMP_T_I32                 0x000000c7
19245#define SQ_V_CMP_F_U32                 0x000000c8
19246#define SQ_V_CMP_LT_U32                0x000000c9
19247#define SQ_V_CMP_EQ_U32                0x000000ca
19248#define SQ_V_CMP_LE_U32                0x000000cb
19249#define SQ_V_CMP_GT_U32                0x000000cc
19250#define SQ_V_CMP_NE_U32                0x000000cd
19251#define SQ_V_CMP_GE_U32                0x000000ce
19252#define SQ_V_CMP_T_U32                 0x000000cf
19253#define SQ_V_CMPX_F_I32                0x000000d0
19254#define SQ_V_CMPX_LT_I32               0x000000d1
19255#define SQ_V_CMPX_EQ_I32               0x000000d2
19256#define SQ_V_CMPX_LE_I32               0x000000d3
19257#define SQ_V_CMPX_GT_I32               0x000000d4
19258#define SQ_V_CMPX_NE_I32               0x000000d5
19259#define SQ_V_CMPX_GE_I32               0x000000d6
19260#define SQ_V_CMPX_T_I32                0x000000d7
19261#define SQ_V_CMPX_F_U32                0x000000d8
19262#define SQ_V_CMPX_LT_U32               0x000000d9
19263#define SQ_V_CMPX_EQ_U32               0x000000da
19264#define SQ_V_CMPX_LE_U32               0x000000db
19265#define SQ_V_CMPX_GT_U32               0x000000dc
19266#define SQ_V_CMPX_NE_U32               0x000000dd
19267#define SQ_V_CMPX_GE_U32               0x000000de
19268#define SQ_V_CMPX_T_U32                0x000000df
19269#define SQ_V_CMP_F_I64                 0x000000e0
19270#define SQ_V_CMP_LT_I64                0x000000e1
19271#define SQ_V_CMP_EQ_I64                0x000000e2
19272#define SQ_V_CMP_LE_I64                0x000000e3
19273#define SQ_V_CMP_GT_I64                0x000000e4
19274#define SQ_V_CMP_NE_I64                0x000000e5
19275#define SQ_V_CMP_GE_I64                0x000000e6
19276#define SQ_V_CMP_T_I64                 0x000000e7
19277#define SQ_V_CMP_F_U64                 0x000000e8
19278#define SQ_V_CMP_LT_U64                0x000000e9
19279#define SQ_V_CMP_EQ_U64                0x000000ea
19280#define SQ_V_CMP_LE_U64                0x000000eb
19281#define SQ_V_CMP_GT_U64                0x000000ec
19282#define SQ_V_CMP_NE_U64                0x000000ed
19283#define SQ_V_CMP_GE_U64                0x000000ee
19284#define SQ_V_CMP_T_U64                 0x000000ef
19285#define SQ_V_CMPX_F_I64                0x000000f0
19286#define SQ_V_CMPX_LT_I64               0x000000f1
19287#define SQ_V_CMPX_EQ_I64               0x000000f2
19288#define SQ_V_CMPX_LE_I64               0x000000f3
19289#define SQ_V_CMPX_GT_I64               0x000000f4
19290#define SQ_V_CMPX_NE_I64               0x000000f5
19291#define SQ_V_CMPX_GE_I64               0x000000f6
19292#define SQ_V_CMPX_T_I64                0x000000f7
19293#define SQ_V_CMPX_F_U64                0x000000f8
19294#define SQ_V_CMPX_LT_U64               0x000000f9
19295#define SQ_V_CMPX_EQ_U64               0x000000fa
19296#define SQ_V_CMPX_LE_U64               0x000000fb
19297#define SQ_V_CMPX_GT_U64               0x000000fc
19298#define SQ_V_CMPX_NE_U64               0x000000fd
19299#define SQ_V_CMPX_GE_U64               0x000000fe
19300#define SQ_V_CMPX_T_U64                0x000000ff
19301
19302/*
19303 * VALUE_SQ_GS_OP value
19304 */
19305
19306#define SQ_GS_OP_NOP                   0x00000000
19307#define SQ_GS_OP_CUT                   0x00000001
19308#define SQ_GS_OP_EMIT                  0x00000002
19309#define SQ_GS_OP_EMIT_CUT              0x00000003
19310
19311/*
19312 * VALUE_SQ_SSRC_SPECIAL_LDS value
19313 */
19314
19315#define SQ_SRC_LDS_DIRECT              0x000000fe
19316
19317/*
19318 * VALUE_SQ_ATTR value
19319 */
19320
19321#define SQ_ATTR0                       0x00000000
19322
19323/*
19324 * VALUE_SQ_TGT_INTERNAL value
19325 */
19326
19327#define SQ_EXP_GDS0                    0x00000018
19328
19329/*
19330 * VALUE_SQ_OP_SOPC value
19331 */
19332
19333#define SQ_S_CMP_EQ_I32                0x00000000
19334#define SQ_S_CMP_LG_I32                0x00000001
19335#define SQ_S_CMP_GT_I32                0x00000002
19336#define SQ_S_CMP_GE_I32                0x00000003
19337#define SQ_S_CMP_LT_I32                0x00000004
19338#define SQ_S_CMP_LE_I32                0x00000005
19339#define SQ_S_CMP_EQ_U32                0x00000006
19340#define SQ_S_CMP_LG_U32                0x00000007
19341#define SQ_S_CMP_GT_U32                0x00000008
19342#define SQ_S_CMP_GE_U32                0x00000009
19343#define SQ_S_CMP_LT_U32                0x0000000a
19344#define SQ_S_CMP_LE_U32                0x0000000b
19345#define SQ_S_BITCMP0_B32               0x0000000c
19346#define SQ_S_BITCMP1_B32               0x0000000d
19347#define SQ_S_BITCMP0_B64               0x0000000e
19348#define SQ_S_BITCMP1_B64               0x0000000f
19349#define SQ_S_SETVSKIP                  0x00000010
19350#define SQ_S_SET_GPR_IDX_ON            0x00000011
19351#define SQ_S_CMP_EQ_U64                0x00000012
19352#define SQ_S_CMP_LG_U64                0x00000013
19353
19354/*
19355 * VALUE_SQ_TRAP value
19356 */
19357
19358#define SQ_TTMP0                       0x0000006c
19359#define SQ_TTMP1                       0x0000006d
19360#define SQ_TTMP2                       0x0000006e
19361#define SQ_TTMP3                       0x0000006f
19362#define SQ_TTMP4                       0x00000070
19363#define SQ_TTMP5                       0x00000071
19364#define SQ_TTMP6                       0x00000072
19365#define SQ_TTMP7                       0x00000073
19366#define SQ_TTMP8                       0x00000074
19367#define SQ_TTMP9                       0x00000075
19368#define SQ_TTMP10                      0x00000076
19369#define SQ_TTMP11                      0x00000077
19370#define SQ_TTMP12                      0x00000078
19371#define SQ_TTMP13                      0x00000079
19372#define SQ_TTMP14                      0x0000007a
19373#define SQ_TTMP15                      0x0000007b
19374
19375/*
19376 * VALUE_SQ_SRC_VGPR value
19377 */
19378
19379#define SQ_SRC_VGPR0                   0x00000100
19380
19381/*
19382 * VALUE_SQ_OP_MUBUF value
19383 */
19384
19385#define SQ_BUFFER_LOAD_FORMAT_X        0x00000000
19386#define SQ_BUFFER_LOAD_FORMAT_XY       0x00000001
19387#define SQ_BUFFER_LOAD_FORMAT_XYZ      0x00000002
19388#define SQ_BUFFER_LOAD_FORMAT_XYZW     0x00000003
19389#define SQ_BUFFER_STORE_FORMAT_X       0x00000004
19390#define SQ_BUFFER_STORE_FORMAT_XY      0x00000005
19391#define SQ_BUFFER_STORE_FORMAT_XYZ     0x00000006
19392#define SQ_BUFFER_STORE_FORMAT_XYZW    0x00000007
19393#define SQ_BUFFER_LOAD_FORMAT_D16_X    0x00000008
19394#define SQ_BUFFER_LOAD_FORMAT_D16_XY   0x00000009
19395#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ  0x0000000a
19396#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0x0000000b
19397#define SQ_BUFFER_STORE_FORMAT_D16_X   0x0000000c
19398#define SQ_BUFFER_STORE_FORMAT_D16_XY  0x0000000d
19399#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0x0000000e
19400#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0x0000000f
19401#define SQ_BUFFER_LOAD_UBYTE           0x00000010
19402#define SQ_BUFFER_LOAD_SBYTE           0x00000011
19403#define SQ_BUFFER_LOAD_USHORT          0x00000012
19404#define SQ_BUFFER_LOAD_SSHORT          0x00000013
19405#define SQ_BUFFER_LOAD_DWORD           0x00000014
19406#define SQ_BUFFER_LOAD_DWORDX2         0x00000015
19407#define SQ_BUFFER_LOAD_DWORDX3         0x00000016
19408#define SQ_BUFFER_LOAD_DWORDX4         0x00000017
19409#define SQ_BUFFER_STORE_BYTE           0x00000018
19410#define SQ_BUFFER_STORE_SHORT          0x0000001a
19411#define SQ_BUFFER_STORE_DWORD          0x0000001c
19412#define SQ_BUFFER_STORE_DWORDX2        0x0000001d
19413#define SQ_BUFFER_STORE_DWORDX3        0x0000001e
19414#define SQ_BUFFER_STORE_DWORDX4        0x0000001f
19415#define SQ_BUFFER_STORE_LDS_DWORD      0x0000003d
19416#define SQ_BUFFER_WBINVL1              0x0000003e
19417#define SQ_BUFFER_WBINVL1_VOL          0x0000003f
19418#define SQ_BUFFER_ATOMIC_SWAP          0x00000040
19419#define SQ_BUFFER_ATOMIC_CMPSWAP       0x00000041
19420#define SQ_BUFFER_ATOMIC_ADD           0x00000042
19421#define SQ_BUFFER_ATOMIC_SUB           0x00000043
19422#define SQ_BUFFER_ATOMIC_SMIN          0x00000044
19423#define SQ_BUFFER_ATOMIC_UMIN          0x00000045
19424#define SQ_BUFFER_ATOMIC_SMAX          0x00000046
19425#define SQ_BUFFER_ATOMIC_UMAX          0x00000047
19426#define SQ_BUFFER_ATOMIC_AND           0x00000048
19427#define SQ_BUFFER_ATOMIC_OR            0x00000049
19428#define SQ_BUFFER_ATOMIC_XOR           0x0000004a
19429#define SQ_BUFFER_ATOMIC_INC           0x0000004b
19430#define SQ_BUFFER_ATOMIC_DEC           0x0000004c
19431#define SQ_BUFFER_ATOMIC_SWAP_X2       0x00000060
19432#define SQ_BUFFER_ATOMIC_CMPSWAP_X2    0x00000061
19433#define SQ_BUFFER_ATOMIC_ADD_X2        0x00000062
19434#define SQ_BUFFER_ATOMIC_SUB_X2        0x00000063
19435#define SQ_BUFFER_ATOMIC_SMIN_X2       0x00000064
19436#define SQ_BUFFER_ATOMIC_UMIN_X2       0x00000065
19437#define SQ_BUFFER_ATOMIC_SMAX_X2       0x00000066
19438#define SQ_BUFFER_ATOMIC_UMAX_X2       0x00000067
19439#define SQ_BUFFER_ATOMIC_AND_X2        0x00000068
19440#define SQ_BUFFER_ATOMIC_OR_X2         0x00000069
19441#define SQ_BUFFER_ATOMIC_XOR_X2        0x0000006a
19442#define SQ_BUFFER_ATOMIC_INC_X2        0x0000006b
19443#define SQ_BUFFER_ATOMIC_DEC_X2        0x0000006c
19444
19445/*
19446 * VALUE_SQ_SDWA_SEL value
19447 */
19448
19449#define SQ_SDWA_BYTE_0                 0x00000000
19450#define SQ_SDWA_BYTE_1                 0x00000001
19451#define SQ_SDWA_BYTE_2                 0x00000002
19452#define SQ_SDWA_BYTE_3                 0x00000003
19453#define SQ_SDWA_WORD_0                 0x00000004
19454#define SQ_SDWA_WORD_1                 0x00000005
19455#define SQ_SDWA_DWORD                  0x00000006
19456
19457/*******************************************************
19458 * SX Enums
19459 *******************************************************/
19460
19461/*
19462 * SX_BLEND_OPT enum
19463 */
19464
19465typedef enum SX_BLEND_OPT {
19466BLEND_OPT_PRESERVE_NONE_IGNORE_ALL       = 0x00000000,
19467BLEND_OPT_PRESERVE_ALL_IGNORE_NONE       = 0x00000001,
19468BLEND_OPT_PRESERVE_C1_IGNORE_C0          = 0x00000002,
19469BLEND_OPT_PRESERVE_C0_IGNORE_C1          = 0x00000003,
19470BLEND_OPT_PRESERVE_A1_IGNORE_A0          = 0x00000004,
19471BLEND_OPT_PRESERVE_A0_IGNORE_A1          = 0x00000005,
19472BLEND_OPT_PRESERVE_NONE_IGNORE_A0        = 0x00000006,
19473BLEND_OPT_PRESERVE_NONE_IGNORE_NONE      = 0x00000007,
19474} SX_BLEND_OPT;
19475
19476/*
19477 * SX_OPT_COMB_FCN enum
19478 */
19479
19480typedef enum SX_OPT_COMB_FCN {
19481OPT_COMB_NONE                            = 0x00000000,
19482OPT_COMB_ADD                             = 0x00000001,
19483OPT_COMB_SUBTRACT                        = 0x00000002,
19484OPT_COMB_MIN                             = 0x00000003,
19485OPT_COMB_MAX                             = 0x00000004,
19486OPT_COMB_REVSUBTRACT                     = 0x00000005,
19487OPT_COMB_BLEND_DISABLED                  = 0x00000006,
19488OPT_COMB_SAFE_ADD                        = 0x00000007,
19489} SX_OPT_COMB_FCN;
19490
19491/*
19492 * SX_DOWNCONVERT_FORMAT enum
19493 */
19494
19495typedef enum SX_DOWNCONVERT_FORMAT {
19496SX_RT_EXPORT_NO_CONVERSION               = 0x00000000,
19497SX_RT_EXPORT_32_R                        = 0x00000001,
19498SX_RT_EXPORT_32_A                        = 0x00000002,
19499SX_RT_EXPORT_10_11_11                    = 0x00000003,
19500SX_RT_EXPORT_2_10_10_10                  = 0x00000004,
19501SX_RT_EXPORT_8_8_8_8                     = 0x00000005,
19502SX_RT_EXPORT_5_6_5                       = 0x00000006,
19503SX_RT_EXPORT_1_5_5_5                     = 0x00000007,
19504SX_RT_EXPORT_4_4_4_4                     = 0x00000008,
19505SX_RT_EXPORT_16_16_GR                    = 0x00000009,
19506SX_RT_EXPORT_16_16_AR                    = 0x0000000a,
19507} SX_DOWNCONVERT_FORMAT;
19508
19509/*
19510 * SX_PERFCOUNTER_VALS enum
19511 */
19512
19513typedef enum SX_PERFCOUNTER_VALS {
19514SX_PERF_SEL_PA_IDLE_CYCLES               = 0x00000000,
19515SX_PERF_SEL_PA_REQ                       = 0x00000001,
19516SX_PERF_SEL_PA_POS                       = 0x00000002,
19517SX_PERF_SEL_CLOCK                        = 0x00000003,
19518SX_PERF_SEL_GATE_EN1                     = 0x00000004,
19519SX_PERF_SEL_GATE_EN2                     = 0x00000005,
19520SX_PERF_SEL_GATE_EN3                     = 0x00000006,
19521SX_PERF_SEL_GATE_EN4                     = 0x00000007,
19522SX_PERF_SEL_SH_POS_STARVE                = 0x00000008,
19523SX_PERF_SEL_SH_COLOR_STARVE              = 0x00000009,
19524SX_PERF_SEL_SH_POS_STALL                 = 0x0000000a,
19525SX_PERF_SEL_SH_COLOR_STALL               = 0x0000000b,
19526SX_PERF_SEL_DB0_PIXELS                   = 0x0000000c,
19527SX_PERF_SEL_DB0_HALF_QUADS               = 0x0000000d,
19528SX_PERF_SEL_DB0_PIXEL_STALL              = 0x0000000e,
19529SX_PERF_SEL_DB0_PIXEL_IDLE               = 0x0000000f,
19530SX_PERF_SEL_DB0_PRED_PIXELS              = 0x00000010,
19531SX_PERF_SEL_DB1_PIXELS                   = 0x00000011,
19532SX_PERF_SEL_DB1_HALF_QUADS               = 0x00000012,
19533SX_PERF_SEL_DB1_PIXEL_STALL              = 0x00000013,
19534SX_PERF_SEL_DB1_PIXEL_IDLE               = 0x00000014,
19535SX_PERF_SEL_DB1_PRED_PIXELS              = 0x00000015,
19536SX_PERF_SEL_DB2_PIXELS                   = 0x00000016,
19537SX_PERF_SEL_DB2_HALF_QUADS               = 0x00000017,
19538SX_PERF_SEL_DB2_PIXEL_STALL              = 0x00000018,
19539SX_PERF_SEL_DB2_PIXEL_IDLE               = 0x00000019,
19540SX_PERF_SEL_DB2_PRED_PIXELS              = 0x0000001a,
19541SX_PERF_SEL_DB3_PIXELS                   = 0x0000001b,
19542SX_PERF_SEL_DB3_HALF_QUADS               = 0x0000001c,
19543SX_PERF_SEL_DB3_PIXEL_STALL              = 0x0000001d,
19544SX_PERF_SEL_DB3_PIXEL_IDLE               = 0x0000001e,
19545SX_PERF_SEL_DB3_PRED_PIXELS              = 0x0000001f,
19546SX_PERF_SEL_COL_BUSY                     = 0x00000020,
19547SX_PERF_SEL_POS_BUSY                     = 0x00000021,
19548SX_PERF_SEL_DB0_A2M_DISCARD_QUADS        = 0x00000022,
19549SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS        = 0x00000023,
19550SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST        = 0x00000024,
19551SX_PERF_SEL_DB0_MRT0_DISCARD_SRC         = 0x00000025,
19552SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS        = 0x00000026,
19553SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS        = 0x00000027,
19554SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS        = 0x00000028,
19555SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST        = 0x00000029,
19556SX_PERF_SEL_DB0_MRT1_DISCARD_SRC         = 0x0000002a,
19557SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS        = 0x0000002b,
19558SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS        = 0x0000002c,
19559SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS        = 0x0000002d,
19560SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST        = 0x0000002e,
19561SX_PERF_SEL_DB0_MRT2_DISCARD_SRC         = 0x0000002f,
19562SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS        = 0x00000030,
19563SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS        = 0x00000031,
19564SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS        = 0x00000032,
19565SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST        = 0x00000033,
19566SX_PERF_SEL_DB0_MRT3_DISCARD_SRC         = 0x00000034,
19567SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS        = 0x00000035,
19568SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS        = 0x00000036,
19569SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS        = 0x00000037,
19570SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST        = 0x00000038,
19571SX_PERF_SEL_DB0_MRT4_DISCARD_SRC         = 0x00000039,
19572SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS        = 0x0000003a,
19573SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS        = 0x0000003b,
19574SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS        = 0x0000003c,
19575SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST        = 0x0000003d,
19576SX_PERF_SEL_DB0_MRT5_DISCARD_SRC         = 0x0000003e,
19577SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS        = 0x0000003f,
19578SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS        = 0x00000040,
19579SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS        = 0x00000041,
19580SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST        = 0x00000042,
19581SX_PERF_SEL_DB0_MRT6_DISCARD_SRC         = 0x00000043,
19582SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS        = 0x00000044,
19583SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS        = 0x00000045,
19584SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS        = 0x00000046,
19585SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST        = 0x00000047,
19586SX_PERF_SEL_DB0_MRT7_DISCARD_SRC         = 0x00000048,
19587SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS        = 0x00000049,
19588SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS        = 0x0000004a,
19589SX_PERF_SEL_DB1_A2M_DISCARD_QUADS        = 0x0000004b,
19590SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS        = 0x0000004c,
19591SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST        = 0x0000004d,
19592SX_PERF_SEL_DB1_MRT0_DISCARD_SRC         = 0x0000004e,
19593SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS        = 0x0000004f,
19594SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS        = 0x00000050,
19595SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS        = 0x00000051,
19596SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST        = 0x00000052,
19597SX_PERF_SEL_DB1_MRT1_DISCARD_SRC         = 0x00000053,
19598SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS        = 0x00000054,
19599SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS        = 0x00000055,
19600SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS        = 0x00000056,
19601SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST        = 0x00000057,
19602SX_PERF_SEL_DB1_MRT2_DISCARD_SRC         = 0x00000058,
19603SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS        = 0x00000059,
19604SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS        = 0x0000005a,
19605SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS        = 0x0000005b,
19606SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST        = 0x0000005c,
19607SX_PERF_SEL_DB1_MRT3_DISCARD_SRC         = 0x0000005d,
19608SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS        = 0x0000005e,
19609SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS        = 0x0000005f,
19610SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS        = 0x00000060,
19611SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST        = 0x00000061,
19612SX_PERF_SEL_DB1_MRT4_DISCARD_SRC         = 0x00000062,
19613SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS        = 0x00000063,
19614SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS        = 0x00000064,
19615SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS        = 0x00000065,
19616SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST        = 0x00000066,
19617SX_PERF_SEL_DB1_MRT5_DISCARD_SRC         = 0x00000067,
19618SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS        = 0x00000068,
19619SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS        = 0x00000069,
19620SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS        = 0x0000006a,
19621SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST        = 0x0000006b,
19622SX_PERF_SEL_DB1_MRT6_DISCARD_SRC         = 0x0000006c,
19623SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS        = 0x0000006d,
19624SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS        = 0x0000006e,
19625SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS        = 0x0000006f,
19626SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST        = 0x00000070,
19627SX_PERF_SEL_DB1_MRT7_DISCARD_SRC         = 0x00000071,
19628SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS        = 0x00000072,
19629SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS        = 0x00000073,
19630SX_PERF_SEL_DB2_A2M_DISCARD_QUADS        = 0x00000074,
19631SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS        = 0x00000075,
19632SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST        = 0x00000076,
19633SX_PERF_SEL_DB2_MRT0_DISCARD_SRC         = 0x00000077,
19634SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS        = 0x00000078,
19635SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS        = 0x00000079,
19636SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS        = 0x0000007a,
19637SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST        = 0x0000007b,
19638SX_PERF_SEL_DB2_MRT1_DISCARD_SRC         = 0x0000007c,
19639SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS        = 0x0000007d,
19640SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS        = 0x0000007e,
19641SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS        = 0x0000007f,
19642SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST        = 0x00000080,
19643SX_PERF_SEL_DB2_MRT2_DISCARD_SRC         = 0x00000081,
19644SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS        = 0x00000082,
19645SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS        = 0x00000083,
19646SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS        = 0x00000084,
19647SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST        = 0x00000085,
19648SX_PERF_SEL_DB2_MRT3_DISCARD_SRC         = 0x00000086,
19649SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS        = 0x00000087,
19650SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS        = 0x00000088,
19651SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS        = 0x00000089,
19652SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST        = 0x0000008a,
19653SX_PERF_SEL_DB2_MRT4_DISCARD_SRC         = 0x0000008b,
19654SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS        = 0x0000008c,
19655SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS        = 0x0000008d,
19656SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS        = 0x0000008e,
19657SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST        = 0x0000008f,
19658SX_PERF_SEL_DB2_MRT5_DISCARD_SRC         = 0x00000090,
19659SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS        = 0x00000091,
19660SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS        = 0x00000092,
19661SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS        = 0x00000093,
19662SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST        = 0x00000094,
19663SX_PERF_SEL_DB2_MRT6_DISCARD_SRC         = 0x00000095,
19664SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS        = 0x00000096,
19665SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS        = 0x00000097,
19666SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS        = 0x00000098,
19667SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST        = 0x00000099,
19668SX_PERF_SEL_DB2_MRT7_DISCARD_SRC         = 0x0000009a,
19669SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS        = 0x0000009b,
19670SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS        = 0x0000009c,
19671SX_PERF_SEL_DB3_A2M_DISCARD_QUADS        = 0x0000009d,
19672SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS        = 0x0000009e,
19673SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST        = 0x0000009f,
19674SX_PERF_SEL_DB3_MRT0_DISCARD_SRC         = 0x000000a0,
19675SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS        = 0x000000a1,
19676SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS        = 0x000000a2,
19677SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS        = 0x000000a3,
19678SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST        = 0x000000a4,
19679SX_PERF_SEL_DB3_MRT1_DISCARD_SRC         = 0x000000a5,
19680SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS        = 0x000000a6,
19681SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS        = 0x000000a7,
19682SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS        = 0x000000a8,
19683SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST        = 0x000000a9,
19684SX_PERF_SEL_DB3_MRT2_DISCARD_SRC         = 0x000000aa,
19685SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS        = 0x000000ab,
19686SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS        = 0x000000ac,
19687SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS        = 0x000000ad,
19688SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST        = 0x000000ae,
19689SX_PERF_SEL_DB3_MRT3_DISCARD_SRC         = 0x000000af,
19690SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS        = 0x000000b0,
19691SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS        = 0x000000b1,
19692SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS        = 0x000000b2,
19693SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST        = 0x000000b3,
19694SX_PERF_SEL_DB3_MRT4_DISCARD_SRC         = 0x000000b4,
19695SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS        = 0x000000b5,
19696SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS        = 0x000000b6,
19697SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS        = 0x000000b7,
19698SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST        = 0x000000b8,
19699SX_PERF_SEL_DB3_MRT5_DISCARD_SRC         = 0x000000b9,
19700SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS        = 0x000000ba,
19701SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS        = 0x000000bb,
19702SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS        = 0x000000bc,
19703SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST        = 0x000000bd,
19704SX_PERF_SEL_DB3_MRT6_DISCARD_SRC         = 0x000000be,
19705SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS        = 0x000000bf,
19706SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS        = 0x000000c0,
19707SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS        = 0x000000c1,
19708SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST        = 0x000000c2,
19709SX_PERF_SEL_DB3_MRT7_DISCARD_SRC         = 0x000000c3,
19710SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS        = 0x000000c4,
19711SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS        = 0x000000c5,
19712} SX_PERFCOUNTER_VALS;
19713
19714/*******************************************************
19715 * DB Enums
19716 *******************************************************/
19717
19718/*
19719 * ForceControl enum
19720 */
19721
19722typedef enum ForceControl {
19723FORCE_OFF                                = 0x00000000,
19724FORCE_ENABLE                             = 0x00000001,
19725FORCE_DISABLE                            = 0x00000002,
19726FORCE_RESERVED                           = 0x00000003,
19727} ForceControl;
19728
19729/*
19730 * ZSamplePosition enum
19731 */
19732
19733typedef enum ZSamplePosition {
19734Z_SAMPLE_CENTER                          = 0x00000000,
19735Z_SAMPLE_CENTROID                        = 0x00000001,
19736} ZSamplePosition;
19737
19738/*
19739 * ZOrder enum
19740 */
19741
19742typedef enum ZOrder {
19743LATE_Z                                   = 0x00000000,
19744EARLY_Z_THEN_LATE_Z                      = 0x00000001,
19745RE_Z                                     = 0x00000002,
19746EARLY_Z_THEN_RE_Z                        = 0x00000003,
19747} ZOrder;
19748
19749/*
19750 * ZpassControl enum
19751 */
19752
19753typedef enum ZpassControl {
19754ZPASS_DISABLE                            = 0x00000000,
19755ZPASS_SAMPLES                            = 0x00000001,
19756ZPASS_PIXELS                             = 0x00000002,
19757} ZpassControl;
19758
19759/*
19760 * ZModeForce enum
19761 */
19762
19763typedef enum ZModeForce {
19764NO_FORCE                                 = 0x00000000,
19765FORCE_EARLY_Z                            = 0x00000001,
19766FORCE_LATE_Z                             = 0x00000002,
19767FORCE_RE_Z                               = 0x00000003,
19768} ZModeForce;
19769
19770/*
19771 * ZLimitSumm enum
19772 */
19773
19774typedef enum ZLimitSumm {
19775FORCE_SUMM_OFF                           = 0x00000000,
19776FORCE_SUMM_MINZ                          = 0x00000001,
19777FORCE_SUMM_MAXZ                          = 0x00000002,
19778FORCE_SUMM_BOTH                          = 0x00000003,
19779} ZLimitSumm;
19780
19781/*
19782 * CompareFrag enum
19783 */
19784
19785typedef enum CompareFrag {
19786FRAG_NEVER                               = 0x00000000,
19787FRAG_LESS                                = 0x00000001,
19788FRAG_EQUAL                               = 0x00000002,
19789FRAG_LEQUAL                              = 0x00000003,
19790FRAG_GREATER                             = 0x00000004,
19791FRAG_NOTEQUAL                            = 0x00000005,
19792FRAG_GEQUAL                              = 0x00000006,
19793FRAG_ALWAYS                              = 0x00000007,
19794} CompareFrag;
19795
19796/*
19797 * StencilOp enum
19798 */
19799
19800typedef enum StencilOp {
19801STENCIL_KEEP                             = 0x00000000,
19802STENCIL_ZERO                             = 0x00000001,
19803STENCIL_ONES                             = 0x00000002,
19804STENCIL_REPLACE_TEST                     = 0x00000003,
19805STENCIL_REPLACE_OP                       = 0x00000004,
19806STENCIL_ADD_CLAMP                        = 0x00000005,
19807STENCIL_SUB_CLAMP                        = 0x00000006,
19808STENCIL_INVERT                           = 0x00000007,
19809STENCIL_ADD_WRAP                         = 0x00000008,
19810STENCIL_SUB_WRAP                         = 0x00000009,
19811STENCIL_AND                              = 0x0000000a,
19812STENCIL_OR                               = 0x0000000b,
19813STENCIL_XOR                              = 0x0000000c,
19814STENCIL_NAND                             = 0x0000000d,
19815STENCIL_NOR                              = 0x0000000e,
19816STENCIL_XNOR                             = 0x0000000f,
19817} StencilOp;
19818
19819/*
19820 * ConservativeZExport enum
19821 */
19822
19823typedef enum ConservativeZExport {
19824EXPORT_ANY_Z                             = 0x00000000,
19825EXPORT_LESS_THAN_Z                       = 0x00000001,
19826EXPORT_GREATER_THAN_Z                    = 0x00000002,
19827EXPORT_RESERVED                          = 0x00000003,
19828} ConservativeZExport;
19829
19830/*
19831 * DbPSLControl enum
19832 */
19833
19834typedef enum DbPSLControl {
19835PSLC_AUTO                                = 0x00000000,
19836PSLC_ON_HANG_ONLY                        = 0x00000001,
19837PSLC_ASAP                                = 0x00000002,
19838PSLC_COUNTDOWN                           = 0x00000003,
19839} DbPSLControl;
19840
19841/*
19842 * DbPRTFaultBehavior enum
19843 */
19844
19845typedef enum DbPRTFaultBehavior {
19846FAULT_ZERO                               = 0x00000000,
19847FAULT_ONE                                = 0x00000001,
19848FAULT_FAIL                               = 0x00000002,
19849FAULT_PASS                               = 0x00000003,
19850} DbPRTFaultBehavior;
19851
19852/*
19853 * PerfCounter_Vals enum
19854 */
19855
19856typedef enum PerfCounter_Vals {
19857DB_PERF_SEL_SC_DB_tile_sends             = 0x00000000,
19858DB_PERF_SEL_SC_DB_tile_busy              = 0x00000001,
19859DB_PERF_SEL_SC_DB_tile_stalls            = 0x00000002,
19860DB_PERF_SEL_SC_DB_tile_events            = 0x00000003,
19861DB_PERF_SEL_SC_DB_tile_tiles             = 0x00000004,
19862DB_PERF_SEL_SC_DB_tile_covered           = 0x00000005,
19863DB_PERF_SEL_hiz_tc_read_starved          = 0x00000006,
19864DB_PERF_SEL_hiz_tc_write_stall           = 0x00000007,
19865DB_PERF_SEL_hiz_qtiles_culled            = 0x00000008,
19866DB_PERF_SEL_his_qtiles_culled            = 0x00000009,
19867DB_PERF_SEL_DB_SC_tile_sends             = 0x0000000a,
19868DB_PERF_SEL_DB_SC_tile_busy              = 0x0000000b,
19869DB_PERF_SEL_DB_SC_tile_stalls            = 0x0000000c,
19870DB_PERF_SEL_DB_SC_tile_df_stalls         = 0x0000000d,
19871DB_PERF_SEL_DB_SC_tile_tiles             = 0x0000000e,
19872DB_PERF_SEL_DB_SC_tile_culled            = 0x0000000f,
19873DB_PERF_SEL_DB_SC_tile_hier_kill         = 0x00000010,
19874DB_PERF_SEL_DB_SC_tile_fast_ops          = 0x00000011,
19875DB_PERF_SEL_DB_SC_tile_no_ops            = 0x00000012,
19876DB_PERF_SEL_DB_SC_tile_tile_rate         = 0x00000013,
19877DB_PERF_SEL_DB_SC_tile_ssaa_kill         = 0x00000014,
19878DB_PERF_SEL_DB_SC_tile_fast_z_ops        = 0x00000015,
19879DB_PERF_SEL_DB_SC_tile_fast_stencil_ops  = 0x00000016,
19880DB_PERF_SEL_SC_DB_quad_sends             = 0x00000017,
19881DB_PERF_SEL_SC_DB_quad_busy              = 0x00000018,
19882DB_PERF_SEL_SC_DB_quad_squads            = 0x00000019,
19883DB_PERF_SEL_SC_DB_quad_tiles             = 0x0000001a,
19884DB_PERF_SEL_SC_DB_quad_pixels            = 0x0000001b,
19885DB_PERF_SEL_SC_DB_quad_killed_tiles      = 0x0000001c,
19886DB_PERF_SEL_DB_SC_quad_sends             = 0x0000001d,
19887DB_PERF_SEL_DB_SC_quad_busy              = 0x0000001e,
19888DB_PERF_SEL_DB_SC_quad_stalls            = 0x0000001f,
19889DB_PERF_SEL_DB_SC_quad_tiles             = 0x00000020,
19890DB_PERF_SEL_DB_SC_quad_lit_quad          = 0x00000021,
19891DB_PERF_SEL_DB_CB_tile_sends             = 0x00000022,
19892DB_PERF_SEL_DB_CB_tile_busy              = 0x00000023,
19893DB_PERF_SEL_DB_CB_tile_stalls            = 0x00000024,
19894DB_PERF_SEL_SX_DB_quad_sends             = 0x00000025,
19895DB_PERF_SEL_SX_DB_quad_busy              = 0x00000026,
19896DB_PERF_SEL_SX_DB_quad_stalls            = 0x00000027,
19897DB_PERF_SEL_SX_DB_quad_quads             = 0x00000028,
19898DB_PERF_SEL_SX_DB_quad_pixels            = 0x00000029,
19899DB_PERF_SEL_SX_DB_quad_exports           = 0x0000002a,
19900DB_PERF_SEL_SH_quads_outstanding_sum     = 0x0000002b,
19901DB_PERF_SEL_DB_CB_lquad_sends            = 0x0000002c,
19902DB_PERF_SEL_DB_CB_lquad_busy             = 0x0000002d,
19903DB_PERF_SEL_DB_CB_lquad_stalls           = 0x0000002e,
19904DB_PERF_SEL_DB_CB_lquad_quads            = 0x0000002f,
19905DB_PERF_SEL_tile_rd_sends                = 0x00000030,
19906DB_PERF_SEL_mi_tile_rd_outstanding_sum   = 0x00000031,
19907DB_PERF_SEL_quad_rd_sends                = 0x00000032,
19908DB_PERF_SEL_quad_rd_busy                 = 0x00000033,
19909DB_PERF_SEL_quad_rd_mi_stall             = 0x00000034,
19910DB_PERF_SEL_quad_rd_rw_collision         = 0x00000035,
19911DB_PERF_SEL_quad_rd_tag_stall            = 0x00000036,
19912DB_PERF_SEL_quad_rd_32byte_reqs          = 0x00000037,
19913DB_PERF_SEL_quad_rd_panic                = 0x00000038,
19914DB_PERF_SEL_mi_quad_rd_outstanding_sum   = 0x00000039,
19915DB_PERF_SEL_quad_rdret_sends             = 0x0000003a,
19916DB_PERF_SEL_quad_rdret_busy              = 0x0000003b,
19917DB_PERF_SEL_tile_wr_sends                = 0x0000003c,
19918DB_PERF_SEL_tile_wr_acks                 = 0x0000003d,
19919DB_PERF_SEL_mi_tile_wr_outstanding_sum   = 0x0000003e,
19920DB_PERF_SEL_quad_wr_sends                = 0x0000003f,
19921DB_PERF_SEL_quad_wr_busy                 = 0x00000040,
19922DB_PERF_SEL_quad_wr_mi_stall             = 0x00000041,
19923DB_PERF_SEL_quad_wr_coherency_stall      = 0x00000042,
19924DB_PERF_SEL_quad_wr_acks                 = 0x00000043,
19925DB_PERF_SEL_mi_quad_wr_outstanding_sum   = 0x00000044,
19926DB_PERF_SEL_Tile_Cache_misses            = 0x00000045,
19927DB_PERF_SEL_Tile_Cache_hits              = 0x00000046,
19928DB_PERF_SEL_Tile_Cache_flushes           = 0x00000047,
19929DB_PERF_SEL_Tile_Cache_surface_stall     = 0x00000048,
19930DB_PERF_SEL_Tile_Cache_starves           = 0x00000049,
19931DB_PERF_SEL_Tile_Cache_mem_return_starve  = 0x0000004a,
19932DB_PERF_SEL_tcp_dispatcher_reads         = 0x0000004b,
19933DB_PERF_SEL_tcp_prefetcher_reads         = 0x0000004c,
19934DB_PERF_SEL_tcp_preloader_reads          = 0x0000004d,
19935DB_PERF_SEL_tcp_dispatcher_flushes       = 0x0000004e,
19936DB_PERF_SEL_tcp_prefetcher_flushes       = 0x0000004f,
19937DB_PERF_SEL_tcp_preloader_flushes        = 0x00000050,
19938DB_PERF_SEL_Depth_Tile_Cache_sends       = 0x00000051,
19939DB_PERF_SEL_Depth_Tile_Cache_busy        = 0x00000052,
19940DB_PERF_SEL_Depth_Tile_Cache_starves     = 0x00000053,
19941DB_PERF_SEL_Depth_Tile_Cache_dtile_locked  = 0x00000054,
19942DB_PERF_SEL_Depth_Tile_Cache_alloc_stall  = 0x00000055,
19943DB_PERF_SEL_Depth_Tile_Cache_misses      = 0x00000056,
19944DB_PERF_SEL_Depth_Tile_Cache_hits        = 0x00000057,
19945DB_PERF_SEL_Depth_Tile_Cache_flushes     = 0x00000058,
19946DB_PERF_SEL_Depth_Tile_Cache_noop_tile   = 0x00000059,
19947DB_PERF_SEL_Depth_Tile_Cache_detailed_noop  = 0x0000005a,
19948DB_PERF_SEL_Depth_Tile_Cache_event       = 0x0000005b,
19949DB_PERF_SEL_Depth_Tile_Cache_tile_frees  = 0x0000005c,
19950DB_PERF_SEL_Depth_Tile_Cache_data_frees  = 0x0000005d,
19951DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve  = 0x0000005e,
19952DB_PERF_SEL_Stencil_Cache_misses         = 0x0000005f,
19953DB_PERF_SEL_Stencil_Cache_hits           = 0x00000060,
19954DB_PERF_SEL_Stencil_Cache_flushes        = 0x00000061,
19955DB_PERF_SEL_Stencil_Cache_starves        = 0x00000062,
19956DB_PERF_SEL_Stencil_Cache_frees          = 0x00000063,
19957DB_PERF_SEL_Z_Cache_separate_Z_misses    = 0x00000064,
19958DB_PERF_SEL_Z_Cache_separate_Z_hits      = 0x00000065,
19959DB_PERF_SEL_Z_Cache_separate_Z_flushes   = 0x00000066,
19960DB_PERF_SEL_Z_Cache_separate_Z_starves   = 0x00000067,
19961DB_PERF_SEL_Z_Cache_pmask_misses         = 0x00000068,
19962DB_PERF_SEL_Z_Cache_pmask_hits           = 0x00000069,
19963DB_PERF_SEL_Z_Cache_pmask_flushes        = 0x0000006a,
19964DB_PERF_SEL_Z_Cache_pmask_starves        = 0x0000006b,
19965DB_PERF_SEL_Z_Cache_frees                = 0x0000006c,
19966DB_PERF_SEL_Plane_Cache_misses           = 0x0000006d,
19967DB_PERF_SEL_Plane_Cache_hits             = 0x0000006e,
19968DB_PERF_SEL_Plane_Cache_flushes          = 0x0000006f,
19969DB_PERF_SEL_Plane_Cache_starves          = 0x00000070,
19970DB_PERF_SEL_Plane_Cache_frees            = 0x00000071,
19971DB_PERF_SEL_flush_expanded_stencil       = 0x00000072,
19972DB_PERF_SEL_flush_compressed_stencil     = 0x00000073,
19973DB_PERF_SEL_flush_single_stencil         = 0x00000074,
19974DB_PERF_SEL_planes_flushed               = 0x00000075,
19975DB_PERF_SEL_flush_1plane                 = 0x00000076,
19976DB_PERF_SEL_flush_2plane                 = 0x00000077,
19977DB_PERF_SEL_flush_3plane                 = 0x00000078,
19978DB_PERF_SEL_flush_4plane                 = 0x00000079,
19979DB_PERF_SEL_flush_5plane                 = 0x0000007a,
19980DB_PERF_SEL_flush_6plane                 = 0x0000007b,
19981DB_PERF_SEL_flush_7plane                 = 0x0000007c,
19982DB_PERF_SEL_flush_8plane                 = 0x0000007d,
19983DB_PERF_SEL_flush_9plane                 = 0x0000007e,
19984DB_PERF_SEL_flush_10plane                = 0x0000007f,
19985DB_PERF_SEL_flush_11plane                = 0x00000080,
19986DB_PERF_SEL_flush_12plane                = 0x00000081,
19987DB_PERF_SEL_flush_13plane                = 0x00000082,
19988DB_PERF_SEL_flush_14plane                = 0x00000083,
19989DB_PERF_SEL_flush_15plane                = 0x00000084,
19990DB_PERF_SEL_flush_16plane                = 0x00000085,
19991DB_PERF_SEL_flush_expanded_z             = 0x00000086,
19992DB_PERF_SEL_earlyZ_waiting_for_postZ_done  = 0x00000087,
19993DB_PERF_SEL_reZ_waiting_for_postZ_done   = 0x00000088,
19994DB_PERF_SEL_dk_tile_sends                = 0x00000089,
19995DB_PERF_SEL_dk_tile_busy                 = 0x0000008a,
19996DB_PERF_SEL_dk_tile_quad_starves         = 0x0000008b,
19997DB_PERF_SEL_dk_tile_stalls               = 0x0000008c,
19998DB_PERF_SEL_dk_squad_sends               = 0x0000008d,
19999DB_PERF_SEL_dk_squad_busy                = 0x0000008e,
20000DB_PERF_SEL_dk_squad_stalls              = 0x0000008f,

20001DB_PERF_SEL_Op_Pipe_Busy                 = 0x00000090,
20002DB_PERF_SEL_Op_Pipe_MC_Read_stall        = 0x00000091,
20003DB_PERF_SEL_qc_busy                      = 0x00000092,
20004DB_PERF_SEL_qc_xfc                       = 0x00000093,
20005DB_PERF_SEL_qc_conflicts                 = 0x00000094,
20006DB_PERF_SEL_qc_full_stall                = 0x00000095,
20007DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ  = 0x00000096,
20008DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ  = 0x00000097,
20009DB_PERF_SEL_tsc_insert_summarize_stall   = 0x00000098,
20010DB_PERF_SEL_tl_busy                      = 0x00000099,
20011DB_PERF_SEL_tl_dtc_read_starved          = 0x0000009a,
20012DB_PERF_SEL_tl_z_fetch_stall             = 0x0000009b,
20013DB_PERF_SEL_tl_stencil_stall             = 0x0000009c,
20014DB_PERF_SEL_tl_z_decompress_stall        = 0x0000009d,
20015DB_PERF_SEL_tl_stencil_locked_stall      = 0x0000009e,
20016DB_PERF_SEL_tl_events                    = 0x0000009f,
20017DB_PERF_SEL_tl_summarize_squads          = 0x000000a0,
20018DB_PERF_SEL_tl_flush_expand_squads       = 0x000000a1,
20019DB_PERF_SEL_tl_expand_squads             = 0x000000a2,
20020DB_PERF_SEL_tl_preZ_squads               = 0x000000a3,
20021DB_PERF_SEL_tl_postZ_squads              = 0x000000a4,
20022DB_PERF_SEL_tl_preZ_noop_squads          = 0x000000a5,
20023DB_PERF_SEL_tl_postZ_noop_squads         = 0x000000a6,
20024DB_PERF_SEL_tl_tile_ops                  = 0x000000a7,
20025DB_PERF_SEL_tl_in_xfc                    = 0x000000a8,
20026DB_PERF_SEL_tl_in_single_stencil_expand_stall  = 0x000000a9,
20027DB_PERF_SEL_tl_in_fast_z_stall           = 0x000000aa,
20028DB_PERF_SEL_tl_out_xfc                   = 0x000000ab,
20029DB_PERF_SEL_tl_out_squads                = 0x000000ac,
20030DB_PERF_SEL_zf_plane_multicycle          = 0x000000ad,
20031DB_PERF_SEL_PostZ_Samples_passing_Z      = 0x000000ae,
20032DB_PERF_SEL_PostZ_Samples_failing_Z      = 0x000000af,
20033DB_PERF_SEL_PostZ_Samples_failing_S      = 0x000000b0,
20034DB_PERF_SEL_PreZ_Samples_passing_Z       = 0x000000b1,
20035DB_PERF_SEL_PreZ_Samples_failing_Z       = 0x000000b2,
20036DB_PERF_SEL_PreZ_Samples_failing_S       = 0x000000b3,
20037DB_PERF_SEL_ts_tc_update_stall           = 0x000000b4,
20038DB_PERF_SEL_sc_kick_start                = 0x000000b5,
20039DB_PERF_SEL_sc_kick_end                  = 0x000000b6,
20040DB_PERF_SEL_clock_reg_active             = 0x000000b7,
20041DB_PERF_SEL_clock_main_active            = 0x000000b8,
20042DB_PERF_SEL_clock_mem_export_active      = 0x000000b9,
20043DB_PERF_SEL_esr_ps_out_busy              = 0x000000ba,
20044DB_PERF_SEL_esr_ps_lqf_busy              = 0x000000bb,
20045DB_PERF_SEL_esr_ps_lqf_stall             = 0x000000bc,
20046DB_PERF_SEL_etr_out_send                 = 0x000000bd,
20047DB_PERF_SEL_etr_out_busy                 = 0x000000be,
20048DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0x000000bf,
20049DB_PERF_SEL_etr_out_cb_tile_stall        = 0x000000c0,
20050DB_PERF_SEL_etr_out_esr_stall            = 0x000000c1,
20051DB_PERF_SEL_esr_ps_sqq_busy              = 0x000000c2,
20052DB_PERF_SEL_esr_ps_sqq_stall             = 0x000000c3,
20053DB_PERF_SEL_esr_eot_fwd_busy             = 0x000000c4,
20054DB_PERF_SEL_esr_eot_fwd_holding_squad    = 0x000000c5,
20055DB_PERF_SEL_esr_eot_fwd_forward          = 0x000000c6,
20056DB_PERF_SEL_esr_sqq_zi_busy              = 0x000000c7,
20057DB_PERF_SEL_esr_sqq_zi_stall             = 0x000000c8,
20058DB_PERF_SEL_postzl_sq_pt_busy            = 0x000000c9,
20059DB_PERF_SEL_postzl_sq_pt_stall           = 0x000000ca,
20060DB_PERF_SEL_postzl_se_busy               = 0x000000cb,
20061DB_PERF_SEL_postzl_se_stall              = 0x000000cc,
20062DB_PERF_SEL_postzl_partial_launch        = 0x000000cd,
20063DB_PERF_SEL_postzl_full_launch           = 0x000000ce,
20064DB_PERF_SEL_postzl_partial_waiting       = 0x000000cf,
20065DB_PERF_SEL_postzl_tile_mem_stall        = 0x000000d0,
20066DB_PERF_SEL_postzl_tile_init_stall       = 0x000000d1,
20067DB_PEFF_SEL_prezl_tile_mem_stall         = 0x000000d2,
20068DB_PERF_SEL_prezl_tile_init_stall        = 0x000000d3,
20069DB_PERF_SEL_dtt_sm_clash_stall           = 0x000000d4,
20070DB_PERF_SEL_dtt_sm_slot_stall            = 0x000000d5,
20071DB_PERF_SEL_dtt_sm_miss_stall            = 0x000000d6,
20072DB_PERF_SEL_mi_rdreq_busy                = 0x000000d7,
20073DB_PERF_SEL_mi_rdreq_stall               = 0x000000d8,
20074DB_PERF_SEL_mi_wrreq_busy                = 0x000000d9,
20075DB_PERF_SEL_mi_wrreq_stall               = 0x000000da,
20076DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop  = 0x000000db,
20077DB_PERF_SEL_dkg_tile_rate_tile           = 0x000000dc,
20078DB_PERF_SEL_prezl_src_in_sends           = 0x000000dd,
20079DB_PERF_SEL_prezl_src_in_stall           = 0x000000de,
20080DB_PERF_SEL_prezl_src_in_squads          = 0x000000df,
20081DB_PERF_SEL_prezl_src_in_squads_unrolled  = 0x000000e0,
20082DB_PERF_SEL_prezl_src_in_tile_rate       = 0x000000e1,
20083DB_PERF_SEL_prezl_src_in_tile_rate_unrolled  = 0x000000e2,
20084DB_PERF_SEL_prezl_src_out_stall          = 0x000000e3,
20085DB_PERF_SEL_postzl_src_in_sends          = 0x000000e4,
20086DB_PERF_SEL_postzl_src_in_stall          = 0x000000e5,
20087DB_PERF_SEL_postzl_src_in_squads         = 0x000000e6,
20088DB_PERF_SEL_postzl_src_in_squads_unrolled  = 0x000000e7,
20089DB_PERF_SEL_postzl_src_in_tile_rate      = 0x000000e8,
20090DB_PERF_SEL_postzl_src_in_tile_rate_unrolled  = 0x000000e9,
20091DB_PERF_SEL_postzl_src_out_stall         = 0x000000ea,
20092DB_PERF_SEL_esr_ps_src_in_sends          = 0x000000eb,
20093DB_PERF_SEL_esr_ps_src_in_stall          = 0x000000ec,
20094DB_PERF_SEL_esr_ps_src_in_squads         = 0x000000ed,
20095DB_PERF_SEL_esr_ps_src_in_squads_unrolled  = 0x000000ee,
20096DB_PERF_SEL_esr_ps_src_in_tile_rate      = 0x000000ef,
20097DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled  = 0x000000f0,
20098DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate  = 0x000000f1,
20099DB_PERF_SEL_esr_ps_src_out_stall         = 0x000000f2,
20100DB_PERF_SEL_depth_bounds_qtiles_culled   = 0x000000f3,
20101DB_PERF_SEL_PreZ_Samples_failing_DB      = 0x000000f4,
20102DB_PERF_SEL_PostZ_Samples_failing_DB     = 0x000000f5,
20103DB_PERF_SEL_flush_compressed             = 0x000000f6,
20104DB_PERF_SEL_flush_plane_le4              = 0x000000f7,
20105DB_PERF_SEL_tiles_z_fully_summarized     = 0x000000f8,
20106DB_PERF_SEL_tiles_stencil_fully_summarized  = 0x000000f9,
20107DB_PERF_SEL_tiles_z_clear_on_expclear    = 0x000000fa,
20108DB_PERF_SEL_tiles_s_clear_on_expclear    = 0x000000fb,
20109DB_PERF_SEL_tiles_decomp_on_expclear     = 0x000000fc,
20110DB_PERF_SEL_tiles_compressed_to_decompressed  = 0x000000fd,
20111DB_PERF_SEL_Op_Pipe_Prez_Busy            = 0x000000fe,
20112DB_PERF_SEL_Op_Pipe_Postz_Busy           = 0x000000ff,
20113DB_PERF_SEL_di_dt_stall                  = 0x00000100,
20114DB_PERF_SEL_DB_SC_quad_double_quad       = 0x00000101,
20115DB_PERF_SEL_SX_DB_quad_export_quads      = 0x00000102,
20116DB_PERF_SEL_SX_DB_quad_double_format     = 0x00000103,
20117DB_PERF_SEL_SX_DB_quad_fast_format       = 0x00000104,
20118DB_PERF_SEL_SX_DB_quad_slow_format       = 0x00000105,
20119DB_PERF_SEL_DB_CB_lquad_export_quads     = 0x00000106,
20120DB_PERF_SEL_DB_CB_lquad_double_format    = 0x00000107,
20121DB_PERF_SEL_DB_CB_lquad_fast_format      = 0x00000108,
20122DB_PERF_SEL_DB_CB_lquad_slow_format      = 0x00000109,
20123DB_PERF_SEL_CB_DB_rdreq_sends            = 0x0000010a,
20124DB_PERF_SEL_CB_DB_rdreq_prt_sends        = 0x0000010b,
20125DB_PERF_SEL_CB_DB_wrreq_sends            = 0x0000010c,
20126DB_PERF_SEL_CB_DB_wrreq_prt_sends        = 0x0000010d,
20127DB_PERF_SEL_DB_CB_rdret_ack              = 0x0000010e,
20128DB_PERF_SEL_DB_CB_rdret_nack             = 0x0000010f,
20129DB_PERF_SEL_DB_CB_wrret_ack              = 0x00000110,
20130DB_PERF_SEL_DB_CB_wrret_nack             = 0x00000111,
20131DB_PERF_SEL_DFSM_squads_in               = 0x00000112,
20132DB_PERF_SEL_DFSM_full_cleared_squads_out  = 0x00000113,
20133DB_PERF_SEL_DFSM_quads_in                = 0x00000114,
20134DB_PERF_SEL_DFSM_fully_cleared_quads_out  = 0x00000115,
20135DB_PERF_SEL_DFSM_lit_pixels_in           = 0x00000116,
20136DB_PERF_SEL_DFSM_fully_cleared_pixels_out  = 0x00000117,
20137DB_PERF_SEL_DFSM_lit_samples_in          = 0x00000118,
20138DB_PERF_SEL_DFSM_lit_samples_out         = 0x00000119,
20139DB_PERF_SEL_DFSM_cycles_above_watermark  = 0x0000011a,
20140DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream  = 0x0000011b,
20141DB_PERF_SEL_DFSM_stalled_by_downstream   = 0x0000011c,
20142DB_PERF_SEL_DFSM_evicted_squads_above_watermark  = 0x0000011d,
20143DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow  = 0x0000011e,
20144DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO  = 0x0000011f,
20145DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark  = 0x00000120,
20146} PerfCounter_Vals;
20147
20148/*
20149 * RingCounterControl enum
20150 */
20151
20152typedef enum RingCounterControl {
20153COUNTER_RING_SPLIT                       = 0x00000000,
20154COUNTER_RING_0                           = 0x00000001,
20155COUNTER_RING_1                           = 0x00000002,
20156} RingCounterControl;
20157
20158/*
20159 * DbMemArbWatermarks enum
20160 */
20161
20162typedef enum DbMemArbWatermarks {
20163TRANSFERRED_64_BYTES                     = 0x00000000,
20164TRANSFERRED_128_BYTES                    = 0x00000001,
20165TRANSFERRED_256_BYTES                    = 0x00000002,
20166TRANSFERRED_512_BYTES                    = 0x00000003,
20167TRANSFERRED_1024_BYTES                   = 0x00000004,
20168TRANSFERRED_2048_BYTES                   = 0x00000005,
20169TRANSFERRED_4096_BYTES                   = 0x00000006,
20170TRANSFERRED_8192_BYTES                   = 0x00000007,
20171} DbMemArbWatermarks;
20172
20173/*
20174 * DFSMFlushEvents enum
20175 */
20176
20177typedef enum DFSMFlushEvents {
20178DB_FLUSH_AND_INV_DB_DATA_TS              = 0x00000000,
20179DB_FLUSH_AND_INV_DB_META                 = 0x00000001,
20180DB_CACHE_FLUSH                           = 0x00000002,
20181DB_CACHE_FLUSH_TS                        = 0x00000003,
20182DB_CACHE_FLUSH_AND_INV_EVENT             = 0x00000004,
20183DB_CACHE_FLUSH_AND_INV_TS_EVENT          = 0x00000005,
20184} DFSMFlushEvents;
20185
20186/*
20187 * PixelPipeCounterId enum
20188 */
20189
20190typedef enum PixelPipeCounterId {
20191PIXEL_PIPE_OCCLUSION_COUNT_0             = 0x00000000,
20192PIXEL_PIPE_OCCLUSION_COUNT_1             = 0x00000001,
20193PIXEL_PIPE_OCCLUSION_COUNT_2             = 0x00000002,
20194PIXEL_PIPE_OCCLUSION_COUNT_3             = 0x00000003,
20195PIXEL_PIPE_SCREEN_MIN_EXTENTS_0          = 0x00000004,
20196PIXEL_PIPE_SCREEN_MAX_EXTENTS_0          = 0x00000005,
20197PIXEL_PIPE_SCREEN_MIN_EXTENTS_1          = 0x00000006,
20198PIXEL_PIPE_SCREEN_MAX_EXTENTS_1          = 0x00000007,
20199} PixelPipeCounterId;
20200
20201/*
20202 * PixelPipeStride enum
20203 */
20204
20205typedef enum PixelPipeStride {
20206PIXEL_PIPE_STRIDE_32_BITS                = 0x00000000,
20207PIXEL_PIPE_STRIDE_64_BITS                = 0x00000001,
20208PIXEL_PIPE_STRIDE_128_BITS               = 0x00000002,
20209PIXEL_PIPE_STRIDE_256_BITS               = 0x00000003,
20210} PixelPipeStride;
20211
20212/*******************************************************
20213 * TA Enums
20214 *******************************************************/
20215
20216/*
20217 * TEX_BORDER_COLOR_TYPE enum
20218 */
20219
20220typedef enum TEX_BORDER_COLOR_TYPE {
20221TEX_BorderColor_TransparentBlack         = 0x00000000,
20222TEX_BorderColor_OpaqueBlack              = 0x00000001,
20223TEX_BorderColor_OpaqueWhite              = 0x00000002,
20224TEX_BorderColor_Register                 = 0x00000003,
20225} TEX_BORDER_COLOR_TYPE;
20226
20227/*
20228 * TEX_CHROMA_KEY enum
20229 */
20230
20231typedef enum TEX_CHROMA_KEY {
20232TEX_ChromaKey_Disabled                   = 0x00000000,
20233TEX_ChromaKey_Kill                       = 0x00000001,
20234TEX_ChromaKey_Blend                      = 0x00000002,
20235TEX_ChromaKey_RESERVED_3                 = 0x00000003,
20236} TEX_CHROMA_KEY;
20237
20238/*
20239 * TEX_CLAMP enum
20240 */
20241
20242typedef enum TEX_CLAMP {
20243TEX_Clamp_Repeat                         = 0x00000000,
20244TEX_Clamp_Mirror                         = 0x00000001,
20245TEX_Clamp_ClampToLast                    = 0x00000002,
20246TEX_Clamp_MirrorOnceToLast               = 0x00000003,
20247TEX_Clamp_ClampHalfToBorder              = 0x00000004,
20248TEX_Clamp_MirrorOnceHalfToBorder         = 0x00000005,
20249TEX_Clamp_ClampToBorder                  = 0x00000006,
20250TEX_Clamp_MirrorOnceToBorder             = 0x00000007,
20251} TEX_CLAMP;
20252
20253/*
20254 * TEX_COORD_TYPE enum
20255 */
20256
20257typedef enum TEX_COORD_TYPE {
20258TEX_CoordType_Unnormalized               = 0x00000000,
20259TEX_CoordType_Normalized                 = 0x00000001,
20260} TEX_COORD_TYPE;
20261
20262/*
20263 * TEX_DEPTH_COMPARE_FUNCTION enum
20264 */
20265
20266typedef enum TEX_DEPTH_COMPARE_FUNCTION {
20267TEX_DepthCompareFunction_Never           = 0x00000000,
20268TEX_DepthCompareFunction_Less            = 0x00000001,
20269TEX_DepthCompareFunction_Equal           = 0x00000002,
20270TEX_DepthCompareFunction_LessEqual       = 0x00000003,
20271TEX_DepthCompareFunction_Greater         = 0x00000004,
20272TEX_DepthCompareFunction_NotEqual        = 0x00000005,
20273TEX_DepthCompareFunction_GreaterEqual    = 0x00000006,
20274TEX_DepthCompareFunction_Always          = 0x00000007,
20275} TEX_DEPTH_COMPARE_FUNCTION;
20276
20277/*
20278 * TEX_DIM enum
20279 */
20280
20281typedef enum TEX_DIM {
20282TEX_Dim_1D                               = 0x00000000,
20283TEX_Dim_2D                               = 0x00000001,
20284TEX_Dim_3D                               = 0x00000002,
20285TEX_Dim_CubeMap                          = 0x00000003,
20286TEX_Dim_1DArray                          = 0x00000004,
20287TEX_Dim_2DArray                          = 0x00000005,
20288TEX_Dim_2D_MSAA                          = 0x00000006,
20289TEX_Dim_2DArray_MSAA                     = 0x00000007,
20290} TEX_DIM;
20291
20292/*
20293 * TEX_FORMAT_COMP enum
20294 */
20295
20296typedef enum TEX_FORMAT_COMP {
20297TEX_FormatComp_Unsigned                  = 0x00000000,
20298TEX_FormatComp_Signed                    = 0x00000001,
20299TEX_FormatComp_UnsignedBiased            = 0x00000002,
20300TEX_FormatComp_RESERVED_3                = 0x00000003,
20301} TEX_FORMAT_COMP;
20302
20303/*
20304 * TEX_MAX_ANISO_RATIO enum
20305 */
20306
20307typedef enum TEX_MAX_ANISO_RATIO {
20308TEX_MaxAnisoRatio_1to1                   = 0x00000000,
20309TEX_MaxAnisoRatio_2to1                   = 0x00000001,
20310TEX_MaxAnisoRatio_4to1                   = 0x00000002,
20311TEX_MaxAnisoRatio_8to1                   = 0x00000003,
20312TEX_MaxAnisoRatio_16to1                  = 0x00000004,
20313TEX_MaxAnisoRatio_RESERVED_5             = 0x00000005,
20314TEX_MaxAnisoRatio_RESERVED_6             = 0x00000006,
20315TEX_MaxAnisoRatio_RESERVED_7             = 0x00000007,
20316} TEX_MAX_ANISO_RATIO;
20317
20318/*
20319 * TEX_MIP_FILTER enum
20320 */
20321
20322typedef enum TEX_MIP_FILTER {
20323TEX_MipFilter_None                       = 0x00000000,
20324TEX_MipFilter_Point                      = 0x00000001,
20325TEX_MipFilter_Linear                     = 0x00000002,
20326TEX_MipFilter_Point_Aniso_Adj            = 0x00000003,
20327} TEX_MIP_FILTER;
20328
20329/*
20330 * TEX_REQUEST_SIZE enum
20331 */
20332
20333typedef enum TEX_REQUEST_SIZE {
20334TEX_RequestSize_32B                      = 0x00000000,
20335TEX_RequestSize_64B                      = 0x00000001,
20336TEX_RequestSize_128B                     = 0x00000002,
20337TEX_RequestSize_2X64B                    = 0x00000003,
20338} TEX_REQUEST_SIZE;
20339
20340/*
20341 * TEX_SAMPLER_TYPE enum
20342 */
20343
20344typedef enum TEX_SAMPLER_TYPE {
20345TEX_SamplerType_Invalid                  = 0x00000000,
20346TEX_SamplerType_Valid                    = 0x00000001,
20347} TEX_SAMPLER_TYPE;
20348
20349/*
20350 * TEX_XY_FILTER enum
20351 */
20352
20353typedef enum TEX_XY_FILTER {
20354TEX_XYFilter_Point                       = 0x00000000,
20355TEX_XYFilter_Linear                      = 0x00000001,
20356TEX_XYFilter_AnisoPoint                  = 0x00000002,
20357TEX_XYFilter_AnisoLinear                 = 0x00000003,
20358} TEX_XY_FILTER;
20359
20360/*
20361 * TEX_Z_FILTER enum
20362 */
20363
20364typedef enum TEX_Z_FILTER {
20365TEX_ZFilter_None                         = 0x00000000,
20366TEX_ZFilter_Point                        = 0x00000001,
20367TEX_ZFilter_Linear                       = 0x00000002,
20368TEX_ZFilter_RESERVED_3                   = 0x00000003,
20369} TEX_Z_FILTER;
20370
20371/*
20372 * VTX_CLAMP enum
20373 */
20374
20375typedef enum VTX_CLAMP {
20376VTX_Clamp_ClampToZero                    = 0x00000000,
20377VTX_Clamp_ClampToNAN                     = 0x00000001,
20378} VTX_CLAMP;
20379
20380/*
20381 * VTX_FETCH_TYPE enum
20382 */
20383
20384typedef enum VTX_FETCH_TYPE {
20385VTX_FetchType_VertexData                 = 0x00000000,
20386VTX_FetchType_InstanceData               = 0x00000001,
20387VTX_FetchType_NoIndexOffset              = 0x00000002,
20388VTX_FetchType_RESERVED_3                 = 0x00000003,
20389} VTX_FETCH_TYPE;
20390
20391/*
20392 * VTX_FORMAT_COMP_ALL enum
20393 */
20394
20395typedef enum VTX_FORMAT_COMP_ALL {
20396VTX_FormatCompAll_Unsigned               = 0x00000000,
20397VTX_FormatCompAll_Signed                 = 0x00000001,
20398} VTX_FORMAT_COMP_ALL;
20399
20400/*
20401 * VTX_MEM_REQUEST_SIZE enum
20402 */
20403
20404typedef enum VTX_MEM_REQUEST_SIZE {
20405VTX_MemRequestSize_32B                   = 0x00000000,
20406VTX_MemRequestSize_64B                   = 0x00000001,
20407} VTX_MEM_REQUEST_SIZE;
20408
20409/*
20410 * TVX_DATA_FORMAT enum
20411 */
20412
20413typedef enum TVX_DATA_FORMAT {
20414TVX_FMT_INVALID                          = 0x00000000,
20415TVX_FMT_8                                = 0x00000001,
20416TVX_FMT_4_4                              = 0x00000002,
20417TVX_FMT_3_3_2                            = 0x00000003,
20418TVX_FMT_RESERVED_4                       = 0x00000004,
20419TVX_FMT_16                               = 0x00000005,
20420TVX_FMT_16_FLOAT                         = 0x00000006,
20421TVX_FMT_8_8                              = 0x00000007,
20422TVX_FMT_5_6_5                            = 0x00000008,
20423TVX_FMT_6_5_5                            = 0x00000009,
20424TVX_FMT_1_5_5_5                          = 0x0000000a,
20425TVX_FMT_4_4_4_4                          = 0x0000000b,
20426TVX_FMT_5_5_5_1                          = 0x0000000c,
20427TVX_FMT_32                               = 0x0000000d,
20428TVX_FMT_32_FLOAT                         = 0x0000000e,
20429TVX_FMT_16_16                            = 0x0000000f,
20430TVX_FMT_16_16_FLOAT                      = 0x00000010,
20431TVX_FMT_8_24                             = 0x00000011,
20432TVX_FMT_8_24_FLOAT                       = 0x00000012,
20433TVX_FMT_24_8                             = 0x00000013,
20434TVX_FMT_24_8_FLOAT                       = 0x00000014,
20435TVX_FMT_10_11_11                         = 0x00000015,
20436TVX_FMT_10_11_11_FLOAT                   = 0x00000016,
20437TVX_FMT_11_11_10                         = 0x00000017,
20438TVX_FMT_11_11_10_FLOAT                   = 0x00000018,
20439TVX_FMT_2_10_10_10                       = 0x00000019,
20440TVX_FMT_8_8_8_8                          = 0x0000001a,
20441TVX_FMT_10_10_10_2                       = 0x0000001b,
20442TVX_FMT_X24_8_32_FLOAT                   = 0x0000001c,
20443TVX_FMT_32_32                            = 0x0000001d,
20444TVX_FMT_32_32_FLOAT                      = 0x0000001e,
20445TVX_FMT_16_16_16_16                      = 0x0000001f,
20446TVX_FMT_16_16_16_16_FLOAT                = 0x00000020,
20447TVX_FMT_RESERVED_33                      = 0x00000021,
20448TVX_FMT_32_32_32_32                      = 0x00000022,
20449TVX_FMT_32_32_32_32_FLOAT                = 0x00000023,
20450TVX_FMT_RESERVED_36                      = 0x00000024,
20451TVX_FMT_1                                = 0x00000025,
20452TVX_FMT_1_REVERSED                       = 0x00000026,
20453TVX_FMT_GB_GR                            = 0x00000027,
20454TVX_FMT_BG_RG                            = 0x00000028,
20455TVX_FMT_32_AS_8                          = 0x00000029,
20456TVX_FMT_32_AS_8_8                        = 0x0000002a,
20457TVX_FMT_5_9_9_9_SHAREDEXP                = 0x0000002b,
20458TVX_FMT_8_8_8                            = 0x0000002c,
20459TVX_FMT_16_16_16                         = 0x0000002d,
20460TVX_FMT_16_16_16_FLOAT                   = 0x0000002e,
20461TVX_FMT_32_32_32                         = 0x0000002f,
20462TVX_FMT_32_32_32_FLOAT                   = 0x00000030,
20463TVX_FMT_BC1                              = 0x00000031,
20464TVX_FMT_BC2                              = 0x00000032,
20465TVX_FMT_BC3                              = 0x00000033,
20466TVX_FMT_BC4                              = 0x00000034,
20467TVX_FMT_BC5                              = 0x00000035,
20468TVX_FMT_APC0                             = 0x00000036,
20469TVX_FMT_APC1                             = 0x00000037,
20470TVX_FMT_APC2                             = 0x00000038,
20471TVX_FMT_APC3                             = 0x00000039,
20472TVX_FMT_APC4                             = 0x0000003a,
20473TVX_FMT_APC5                             = 0x0000003b,
20474TVX_FMT_APC6                             = 0x0000003c,
20475TVX_FMT_APC7                             = 0x0000003d,
20476TVX_FMT_CTX1                             = 0x0000003e,
20477TVX_FMT_RESERVED_63                      = 0x0000003f,
20478} TVX_DATA_FORMAT;
20479
20480/*
20481 * TVX_DST_SEL enum
20482 */
20483
20484typedef enum TVX_DST_SEL {
20485TVX_DstSel_X                             = 0x00000000,
20486TVX_DstSel_Y                             = 0x00000001,
20487TVX_DstSel_Z                             = 0x00000002,
20488TVX_DstSel_W                             = 0x00000003,
20489TVX_DstSel_0f                            = 0x00000004,
20490TVX_DstSel_1f                            = 0x00000005,
20491TVX_DstSel_RESERVED_6                    = 0x00000006,
20492TVX_DstSel_Mask                          = 0x00000007,
20493} TVX_DST_SEL;
20494
20495/*
20496 * TVX_ENDIAN_SWAP enum
20497 */
20498
20499typedef enum TVX_ENDIAN_SWAP {
20500TVX_EndianSwap_None                      = 0x00000000,
20501TVX_EndianSwap_8in16                     = 0x00000001,
20502TVX_EndianSwap_8in32                     = 0x00000002,
20503TVX_EndianSwap_8in64                     = 0x00000003,
20504} TVX_ENDIAN_SWAP;
20505
20506/*
20507 * TVX_INST enum
20508 */
20509
20510typedef enum TVX_INST {
20511TVX_Inst_NormalVertexFetch               = 0x00000000,
20512TVX_Inst_SemanticVertexFetch             = 0x00000001,
20513TVX_Inst_RESERVED_2                      = 0x00000002,
20514TVX_Inst_LD                              = 0x00000003,
20515TVX_Inst_GetTextureResInfo               = 0x00000004,
20516TVX_Inst_GetNumberOfSamples              = 0x00000005,
20517TVX_Inst_GetLOD                          = 0x00000006,
20518TVX_Inst_GetGradientsH                   = 0x00000007,
20519TVX_Inst_GetGradientsV                   = 0x00000008,
20520TVX_Inst_SetTextureOffsets               = 0x00000009,
20521TVX_Inst_KeepGradients                   = 0x0000000a,
20522TVX_Inst_SetGradientsH                   = 0x0000000b,
20523TVX_Inst_SetGradientsV                   = 0x0000000c,
20524TVX_Inst_Pass                            = 0x0000000d,
20525TVX_Inst_GetBufferResInfo                = 0x0000000e,
20526TVX_Inst_RESERVED_15                     = 0x0000000f,
20527TVX_Inst_Sample                          = 0x00000010,
20528TVX_Inst_Sample_L                        = 0x00000011,
20529TVX_Inst_Sample_LB                       = 0x00000012,
20530TVX_Inst_Sample_LZ                       = 0x00000013,
20531TVX_Inst_Sample_G                        = 0x00000014,
20532TVX_Inst_Gather4                         = 0x00000015,
20533TVX_Inst_Sample_G_LB                     = 0x00000016,
20534TVX_Inst_Gather4_O                       = 0x00000017,
20535TVX_Inst_Sample_C                        = 0x00000018,
20536TVX_Inst_Sample_C_L                      = 0x00000019,
20537TVX_Inst_Sample_C_LB                     = 0x0000001a,
20538TVX_Inst_Sample_C_LZ                     = 0x0000001b,
20539TVX_Inst_Sample_C_G                      = 0x0000001c,
20540TVX_Inst_Gather4_C                       = 0x0000001d,
20541TVX_Inst_Sample_C_G_LB                   = 0x0000001e,
20542TVX_Inst_Gather4_C_O                     = 0x0000001f,
20543} TVX_INST;
20544
20545/*
20546 * TVX_NUM_FORMAT_ALL enum
20547 */
20548
20549typedef enum TVX_NUM_FORMAT_ALL {
20550TVX_NumFormatAll_Norm                    = 0x00000000,
20551TVX_NumFormatAll_Int                     = 0x00000001,
20552TVX_NumFormatAll_Scaled                  = 0x00000002,
20553TVX_NumFormatAll_RESERVED_3              = 0x00000003,
20554} TVX_NUM_FORMAT_ALL;
20555
20556/*
20557 * TVX_SRC_SEL enum
20558 */
20559
20560typedef enum TVX_SRC_SEL {
20561TVX_SrcSel_X                             = 0x00000000,
20562TVX_SrcSel_Y                             = 0x00000001,
20563TVX_SrcSel_Z                             = 0x00000002,
20564TVX_SrcSel_W                             = 0x00000003,
20565TVX_SrcSel_0f                            = 0x00000004,
20566TVX_SrcSel_1f                            = 0x00000005,
20567} TVX_SRC_SEL;
20568
20569/*
20570 * TVX_SRF_MODE_ALL enum
20571 */
20572
20573typedef enum TVX_SRF_MODE_ALL {
20574TVX_SRFModeAll_ZCMO                      = 0x00000000,
20575TVX_SRFModeAll_NZ                        = 0x00000001,
20576} TVX_SRF_MODE_ALL;
20577
20578/*
20579 * TVX_TYPE enum
20580 */
20581
20582typedef enum TVX_TYPE {
20583TVX_Type_InvalidTextureResource          = 0x00000000,
20584TVX_Type_InvalidVertexBuffer             = 0x00000001,
20585TVX_Type_ValidTextureResource            = 0x00000002,
20586TVX_Type_ValidVertexBuffer               = 0x00000003,
20587} TVX_TYPE;
20588
20589/*******************************************************
20590 * PA Enums
20591 *******************************************************/
20592
20593/*
20594 * SU_PERFCNT_SEL enum
20595 */
20596
20597typedef enum SU_PERFCNT_SEL {
20598PERF_PAPC_PASX_REQ                       = 0x00000000,
20599PERF_PAPC_PASX_DISABLE_PIPE              = 0x00000001,
20600PERF_PAPC_PASX_FIRST_VECTOR              = 0x00000002,
20601PERF_PAPC_PASX_SECOND_VECTOR             = 0x00000003,
20602PERF_PAPC_PASX_FIRST_DEAD                = 0x00000004,
20603PERF_PAPC_PASX_SECOND_DEAD               = 0x00000005,
20604PERF_PAPC_PASX_VTX_KILL_DISCARD          = 0x00000006,
20605PERF_PAPC_PASX_VTX_NAN_DISCARD           = 0x00000007,
20606PERF_PAPC_PA_INPUT_PRIM                  = 0x00000008,
20607PERF_PAPC_PA_INPUT_NULL_PRIM             = 0x00000009,
20608PERF_PAPC_PA_INPUT_EVENT_FLAG            = 0x0000000a,
20609PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT       = 0x0000000b,
20610PERF_PAPC_PA_INPUT_END_OF_PACKET         = 0x0000000c,
20611PERF_PAPC_PA_INPUT_EXTENDED_EVENT        = 0x0000000d,
20612PERF_PAPC_CLPR_CULL_PRIM                 = 0x0000000e,
20613PERF_PAPC_CLPR_VVUCP_CULL_PRIM           = 0x0000000f,
20614PERF_PAPC_CLPR_VV_CULL_PRIM              = 0x00000010,
20615PERF_PAPC_CLPR_UCP_CULL_PRIM             = 0x00000011,
20616PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM        = 0x00000012,
20617PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM         = 0x00000013,
20618PERF_PAPC_CLPR_CULL_TO_NULL_PRIM         = 0x00000014,
20619PERF_PAPC_CLPR_VVUCP_CLIP_PRIM           = 0x00000015,
20620PERF_PAPC_CLPR_VV_CLIP_PRIM              = 0x00000016,
20621PERF_PAPC_CLPR_UCP_CLIP_PRIM             = 0x00000017,
20622PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE      = 0x00000018,
20623PERF_PAPC_CLPR_CLIP_PLANE_CNT_1          = 0x00000019,
20624PERF_PAPC_CLPR_CLIP_PLANE_CNT_2          = 0x0000001a,
20625PERF_PAPC_CLPR_CLIP_PLANE_CNT_3          = 0x0000001b,
20626PERF_PAPC_CLPR_CLIP_PLANE_CNT_4          = 0x0000001c,
20627PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8        = 0x0000001d,
20628PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12       = 0x0000001e,
20629PERF_PAPC_CLPR_CLIP_PLANE_NEAR           = 0x0000001f,
20630PERF_PAPC_CLPR_CLIP_PLANE_FAR            = 0x00000020,
20631PERF_PAPC_CLPR_CLIP_PLANE_LEFT           = 0x00000021,
20632PERF_PAPC_CLPR_CLIP_PLANE_RIGHT          = 0x00000022,
20633PERF_PAPC_CLPR_CLIP_PLANE_TOP            = 0x00000023,
20634PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM         = 0x00000024,
20635PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM        = 0x00000025,
20636PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM     = 0x00000026,
20637PERF_PAPC_CLSM_NULL_PRIM                 = 0x00000027,
20638PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM      = 0x00000028,
20639PERF_PAPC_CLSM_CULL_TO_NULL_PRIM         = 0x00000029,
20640PERF_PAPC_CLSM_OUT_PRIM_CNT_1            = 0x0000002a,
20641PERF_PAPC_CLSM_OUT_PRIM_CNT_2            = 0x0000002b,
20642PERF_PAPC_CLSM_OUT_PRIM_CNT_3            = 0x0000002c,
20643PERF_PAPC_CLSM_OUT_PRIM_CNT_4            = 0x0000002d,
20644PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8          = 0x0000002e,
20645PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13         = 0x0000002f,
20646PERF_PAPC_CLIPGA_VTE_KILL_PRIM           = 0x00000030,
20647PERF_PAPC_SU_INPUT_PRIM                  = 0x00000031,
20648PERF_PAPC_SU_INPUT_CLIP_PRIM             = 0x00000032,
20649PERF_PAPC_SU_INPUT_NULL_PRIM             = 0x00000033,
20650PERF_PAPC_SU_INPUT_PRIM_DUAL             = 0x00000034,
20651PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL        = 0x00000035,
20652PERF_PAPC_SU_ZERO_AREA_CULL_PRIM         = 0x00000036,
20653PERF_PAPC_SU_BACK_FACE_CULL_PRIM         = 0x00000037,
20654PERF_PAPC_SU_FRONT_FACE_CULL_PRIM        = 0x00000038,
20655PERF_PAPC_SU_POLYMODE_FACE_CULL          = 0x00000039,
20656PERF_PAPC_SU_POLYMODE_BACK_CULL          = 0x0000003a,
20657PERF_PAPC_SU_POLYMODE_FRONT_CULL         = 0x0000003b,
20658PERF_PAPC_SU_POLYMODE_INVALID_FILL       = 0x0000003c,
20659PERF_PAPC_SU_OUTPUT_PRIM                 = 0x0000003d,
20660PERF_PAPC_SU_OUTPUT_CLIP_PRIM            = 0x0000003e,
20661PERF_PAPC_SU_OUTPUT_NULL_PRIM            = 0x0000003f,
20662PERF_PAPC_SU_OUTPUT_EVENT_FLAG           = 0x00000040,
20663PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT      = 0x00000041,
20664PERF_PAPC_SU_OUTPUT_END_OF_PACKET        = 0x00000042,
20665PERF_PAPC_SU_OUTPUT_POLYMODE_FACE        = 0x00000043,
20666PERF_PAPC_SU_OUTPUT_POLYMODE_BACK        = 0x00000044,
20667PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT       = 0x00000045,
20668PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE      = 0x00000046,
20669PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK      = 0x00000047,
20670PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT     = 0x00000048,
20671PERF_PAPC_SU_OUTPUT_PRIM_DUAL            = 0x00000049,
20672PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL       = 0x0000004a,
20673PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL        = 0x0000004b,
20674PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL   = 0x0000004c,
20675PERF_PAPC_PASX_REQ_IDLE                  = 0x0000004d,
20676PERF_PAPC_PASX_REQ_BUSY                  = 0x0000004e,
20677PERF_PAPC_PASX_REQ_STALLED               = 0x0000004f,
20678PERF_PAPC_PASX_REC_IDLE                  = 0x00000050,
20679PERF_PAPC_PASX_REC_BUSY                  = 0x00000051,
20680PERF_PAPC_PASX_REC_STARVED_SX            = 0x00000052,
20681PERF_PAPC_PASX_REC_STALLED               = 0x00000053,
20682PERF_PAPC_PASX_REC_STALLED_POS_MEM       = 0x00000054,
20683PERF_PAPC_PASX_REC_STALLED_CCGSM_IN      = 0x00000055,
20684PERF_PAPC_CCGSM_IDLE                     = 0x00000056,
20685PERF_PAPC_CCGSM_BUSY                     = 0x00000057,
20686PERF_PAPC_CCGSM_STALLED                  = 0x00000058,
20687PERF_PAPC_CLPRIM_IDLE                    = 0x00000059,
20688PERF_PAPC_CLPRIM_BUSY                    = 0x0000005a,
20689PERF_PAPC_CLPRIM_STALLED                 = 0x0000005b,
20690PERF_PAPC_CLPRIM_STARVED_CCGSM           = 0x0000005c,
20691PERF_PAPC_CLIPSM_IDLE                    = 0x0000005d,
20692PERF_PAPC_CLIPSM_BUSY                    = 0x0000005e,
20693PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH     = 0x0000005f,
20694PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ       = 0x00000060,
20695PERF_PAPC_CLIPSM_WAIT_CLIPGA             = 0x00000061,
20696PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP     = 0x00000062,
20697PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM         = 0x00000063,
20698PERF_PAPC_CLIPGA_IDLE                    = 0x00000064,
20699PERF_PAPC_CLIPGA_BUSY                    = 0x00000065,
20700PERF_PAPC_CLIPGA_STARVED_VTE_CLIP        = 0x00000066,
20701PERF_PAPC_CLIPGA_STALLED                 = 0x00000067,
20702PERF_PAPC_CLIP_IDLE                      = 0x00000068,
20703PERF_PAPC_CLIP_BUSY                      = 0x00000069,
20704PERF_PAPC_SU_IDLE                        = 0x0000006a,
20705PERF_PAPC_SU_BUSY                        = 0x0000006b,
20706PERF_PAPC_SU_STARVED_CLIP                = 0x0000006c,
20707PERF_PAPC_SU_STALLED_SC                  = 0x0000006d,
20708PERF_PAPC_CL_DYN_SCLK_VLD                = 0x0000006e,
20709PERF_PAPC_SU_DYN_SCLK_VLD                = 0x0000006f,
20710PERF_PAPC_PA_REG_SCLK_VLD                = 0x00000070,
20711PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL  = 0x00000071,
20712PERF_PAPC_PASX_SE0_REQ                   = 0x00000072,
20713PERF_PAPC_PASX_SE1_REQ                   = 0x00000073,
20714PERF_PAPC_PASX_SE0_FIRST_VECTOR          = 0x00000074,
20715PERF_PAPC_PASX_SE0_SECOND_VECTOR         = 0x00000075,
20716PERF_PAPC_PASX_SE1_FIRST_VECTOR          = 0x00000076,
20717PERF_PAPC_PASX_SE1_SECOND_VECTOR         = 0x00000077,
20718PERF_PAPC_SU_SE0_PRIM_FILTER_CULL        = 0x00000078,
20719PERF_PAPC_SU_SE1_PRIM_FILTER_CULL        = 0x00000079,
20720PERF_PAPC_SU_SE01_PRIM_FILTER_CULL       = 0x0000007a,
20721PERF_PAPC_SU_SE0_OUTPUT_PRIM             = 0x0000007b,
20722PERF_PAPC_SU_SE1_OUTPUT_PRIM             = 0x0000007c,
20723PERF_PAPC_SU_SE01_OUTPUT_PRIM            = 0x0000007d,
20724PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM        = 0x0000007e,
20725PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM        = 0x0000007f,
20726PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM       = 0x00000080,
20727PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT  = 0x00000081,
20728PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT  = 0x00000082,
20729PERF_PAPC_SU_SE0_STALLED_SC              = 0x00000083,
20730PERF_PAPC_SU_SE1_STALLED_SC              = 0x00000084,
20731PERF_PAPC_SU_SE01_STALLED_SC             = 0x00000085,
20732PERF_PAPC_CLSM_CLIPPING_PRIM             = 0x00000086,
20733PERF_PAPC_SU_CULLED_PRIM                 = 0x00000087,
20734PERF_PAPC_SU_OUTPUT_EOPG                 = 0x00000088,
20735PERF_PAPC_SU_SE2_PRIM_FILTER_CULL        = 0x00000089,
20736PERF_PAPC_SU_SE3_PRIM_FILTER_CULL        = 0x0000008a,
20737PERF_PAPC_SU_SE2_OUTPUT_PRIM             = 0x0000008b,
20738PERF_PAPC_SU_SE3_OUTPUT_PRIM             = 0x0000008c,
20739PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM        = 0x0000008d,
20740PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM        = 0x0000008e,
20741PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET    = 0x0000008f,
20742PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET    = 0x00000090,
20743PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET    = 0x00000091,
20744PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET    = 0x00000092,
20745PERF_PAPC_SU_SE0_OUTPUT_EOPG             = 0x00000093,
20746PERF_PAPC_SU_SE1_OUTPUT_EOPG             = 0x00000094,
20747PERF_PAPC_SU_SE2_OUTPUT_EOPG             = 0x00000095,
20748PERF_PAPC_SU_SE3_OUTPUT_EOPG             = 0x00000096,
20749PERF_PAPC_SU_SE2_STALLED_SC              = 0x00000097,
20750PERF_PAPC_SU_SE3_STALLED_SC              = 0x00000098,
20751} SU_PERFCNT_SEL;
20752
20753/*
20754 * SC_PERFCNT_SEL enum
20755 */
20756
20757typedef enum SC_PERFCNT_SEL {
20758SC_SRPS_WINDOW_VALID                     = 0x00000000,
20759SC_PSSW_WINDOW_VALID                     = 0x00000001,
20760SC_TPQZ_WINDOW_VALID                     = 0x00000002,
20761SC_QZQP_WINDOW_VALID                     = 0x00000003,
20762SC_TRPK_WINDOW_VALID                     = 0x00000004,
20763SC_SRPS_WINDOW_VALID_BUSY                = 0x00000005,
20764SC_PSSW_WINDOW_VALID_BUSY                = 0x00000006,
20765SC_TPQZ_WINDOW_VALID_BUSY                = 0x00000007,
20766SC_QZQP_WINDOW_VALID_BUSY                = 0x00000008,
20767SC_TRPK_WINDOW_VALID_BUSY                = 0x00000009,
20768SC_STARVED_BY_PA                         = 0x0000000a,
20769SC_STALLED_BY_PRIMFIFO                   = 0x0000000b,
20770SC_STALLED_BY_DB_TILE                    = 0x0000000c,
20771SC_STARVED_BY_DB_TILE                    = 0x0000000d,
20772SC_STALLED_BY_TILEORDERFIFO              = 0x0000000e,
20773SC_STALLED_BY_TILEFIFO                   = 0x0000000f,
20774SC_STALLED_BY_DB_QUAD                    = 0x00000010,
20775SC_STARVED_BY_DB_QUAD                    = 0x00000011,
20776SC_STALLED_BY_QUADFIFO                   = 0x00000012,
20777SC_STALLED_BY_BCI                        = 0x00000013,
20778SC_STALLED_BY_SPI                        = 0x00000014,
20779SC_SCISSOR_DISCARD                       = 0x00000015,
20780SC_BB_DISCARD                            = 0x00000016,
20781SC_SUPERTILE_COUNT                       = 0x00000017,
20782SC_SUPERTILE_PER_PRIM_H0                 = 0x00000018,
20783SC_SUPERTILE_PER_PRIM_H1                 = 0x00000019,
20784SC_SUPERTILE_PER_PRIM_H2                 = 0x0000001a,
20785SC_SUPERTILE_PER_PRIM_H3                 = 0x0000001b,
20786SC_SUPERTILE_PER_PRIM_H4                 = 0x0000001c,
20787SC_SUPERTILE_PER_PRIM_H5                 = 0x0000001d,
20788SC_SUPERTILE_PER_PRIM_H6                 = 0x0000001e,
20789SC_SUPERTILE_PER_PRIM_H7                 = 0x0000001f,
20790SC_SUPERTILE_PER_PRIM_H8                 = 0x00000020,
20791SC_SUPERTILE_PER_PRIM_H9                 = 0x00000021,
20792SC_SUPERTILE_PER_PRIM_H10                = 0x00000022,
20793SC_SUPERTILE_PER_PRIM_H11                = 0x00000023,
20794SC_SUPERTILE_PER_PRIM_H12                = 0x00000024,
20795SC_SUPERTILE_PER_PRIM_H13                = 0x00000025,
20796SC_SUPERTILE_PER_PRIM_H14                = 0x00000026,
20797SC_SUPERTILE_PER_PRIM_H15                = 0x00000027,
20798SC_SUPERTILE_PER_PRIM_H16                = 0x00000028,
20799SC_TILE_PER_PRIM_H0                      = 0x00000029,
20800SC_TILE_PER_PRIM_H1                      = 0x0000002a,
20801SC_TILE_PER_PRIM_H2                      = 0x0000002b,
20802SC_TILE_PER_PRIM_H3                      = 0x0000002c,
20803SC_TILE_PER_PRIM_H4                      = 0x0000002d,
20804SC_TILE_PER_PRIM_H5                      = 0x0000002e,
20805SC_TILE_PER_PRIM_H6                      = 0x0000002f,
20806SC_TILE_PER_PRIM_H7                      = 0x00000030,
20807SC_TILE_PER_PRIM_H8                      = 0x00000031,
20808SC_TILE_PER_PRIM_H9                      = 0x00000032,
20809SC_TILE_PER_PRIM_H10                     = 0x00000033,
20810SC_TILE_PER_PRIM_H11                     = 0x00000034,
20811SC_TILE_PER_PRIM_H12                     = 0x00000035,
20812SC_TILE_PER_PRIM_H13                     = 0x00000036,
20813SC_TILE_PER_PRIM_H14                     = 0x00000037,
20814SC_TILE_PER_PRIM_H15                     = 0x00000038,
20815SC_TILE_PER_PRIM_H16                     = 0x00000039,
20816SC_TILE_PER_SUPERTILE_H0                 = 0x0000003a,
20817SC_TILE_PER_SUPERTILE_H1                 = 0x0000003b,
20818SC_TILE_PER_SUPERTILE_H2                 = 0x0000003c,
20819SC_TILE_PER_SUPERTILE_H3                 = 0x0000003d,
20820SC_TILE_PER_SUPERTILE_H4                 = 0x0000003e,
20821SC_TILE_PER_SUPERTILE_H5                 = 0x0000003f,
20822SC_TILE_PER_SUPERTILE_H6                 = 0x00000040,
20823SC_TILE_PER_SUPERTILE_H7                 = 0x00000041,
20824SC_TILE_PER_SUPERTILE_H8                 = 0x00000042,
20825SC_TILE_PER_SUPERTILE_H9                 = 0x00000043,
20826SC_TILE_PER_SUPERTILE_H10                = 0x00000044,
20827SC_TILE_PER_SUPERTILE_H11                = 0x00000045,
20828SC_TILE_PER_SUPERTILE_H12                = 0x00000046,
20829SC_TILE_PER_SUPERTILE_H13                = 0x00000047,
20830SC_TILE_PER_SUPERTILE_H14                = 0x00000048,
20831SC_TILE_PER_SUPERTILE_H15                = 0x00000049,
20832SC_TILE_PER_SUPERTILE_H16                = 0x0000004a,
20833SC_TILE_PICKED_H1                        = 0x0000004b,
20834SC_TILE_PICKED_H2                        = 0x0000004c,
20835SC_TILE_PICKED_H3                        = 0x0000004d,
20836SC_TILE_PICKED_H4                        = 0x0000004e,
20837SC_QZ0_MULTI_GPU_TILE_DISCARD            = 0x0000004f,
20838SC_QZ1_MULTI_GPU_TILE_DISCARD            = 0x00000050,
20839SC_QZ2_MULTI_GPU_TILE_DISCARD            = 0x00000051,
20840SC_QZ3_MULTI_GPU_TILE_DISCARD            = 0x00000052,
20841SC_QZ0_TILE_COUNT                        = 0x00000053,
20842SC_QZ1_TILE_COUNT                        = 0x00000054,
20843SC_QZ2_TILE_COUNT                        = 0x00000055,
20844SC_QZ3_TILE_COUNT                        = 0x00000056,
20845SC_QZ0_TILE_COVERED_COUNT                = 0x00000057,
20846SC_QZ1_TILE_COVERED_COUNT                = 0x00000058,
20847SC_QZ2_TILE_COVERED_COUNT                = 0x00000059,
20848SC_QZ3_TILE_COVERED_COUNT                = 0x0000005a,
20849SC_QZ0_TILE_NOT_COVERED_COUNT            = 0x0000005b,
20850SC_QZ1_TILE_NOT_COVERED_COUNT            = 0x0000005c,
20851SC_QZ2_TILE_NOT_COVERED_COUNT            = 0x0000005d,
20852SC_QZ3_TILE_NOT_COVERED_COUNT            = 0x0000005e,
20853SC_QZ0_QUAD_PER_TILE_H0                  = 0x0000005f,
20854SC_QZ0_QUAD_PER_TILE_H1                  = 0x00000060,
20855SC_QZ0_QUAD_PER_TILE_H2                  = 0x00000061,
20856SC_QZ0_QUAD_PER_TILE_H3                  = 0x00000062,
20857SC_QZ0_QUAD_PER_TILE_H4                  = 0x00000063,
20858SC_QZ0_QUAD_PER_TILE_H5                  = 0x00000064,
20859SC_QZ0_QUAD_PER_TILE_H6                  = 0x00000065,
20860SC_QZ0_QUAD_PER_TILE_H7                  = 0x00000066,
20861SC_QZ0_QUAD_PER_TILE_H8                  = 0x00000067,
20862SC_QZ0_QUAD_PER_TILE_H9                  = 0x00000068,
20863SC_QZ0_QUAD_PER_TILE_H10                 = 0x00000069,
20864SC_QZ0_QUAD_PER_TILE_H11                 = 0x0000006a,
20865SC_QZ0_QUAD_PER_TILE_H12                 = 0x0000006b,
20866SC_QZ0_QUAD_PER_TILE_H13                 = 0x0000006c,
20867SC_QZ0_QUAD_PER_TILE_H14                 = 0x0000006d,
20868SC_QZ0_QUAD_PER_TILE_H15                 = 0x0000006e,
20869SC_QZ0_QUAD_PER_TILE_H16                 = 0x0000006f,
20870SC_QZ1_QUAD_PER_TILE_H0                  = 0x00000070,
20871SC_QZ1_QUAD_PER_TILE_H1                  = 0x00000071,
20872SC_QZ1_QUAD_PER_TILE_H2                  = 0x00000072,
20873SC_QZ1_QUAD_PER_TILE_H3                  = 0x00000073,
20874SC_QZ1_QUAD_PER_TILE_H4                  = 0x00000074,
20875SC_QZ1_QUAD_PER_TILE_H5                  = 0x00000075,
20876SC_QZ1_QUAD_PER_TILE_H6                  = 0x00000076,
20877SC_QZ1_QUAD_PER_TILE_H7                  = 0x00000077,
20878SC_QZ1_QUAD_PER_TILE_H8                  = 0x00000078,
20879SC_QZ1_QUAD_PER_TILE_H9                  = 0x00000079,
20880SC_QZ1_QUAD_PER_TILE_H10                 = 0x0000007a,
20881SC_QZ1_QUAD_PER_TILE_H11                 = 0x0000007b,
20882SC_QZ1_QUAD_PER_TILE_H12                 = 0x0000007c,
20883SC_QZ1_QUAD_PER_TILE_H13                 = 0x0000007d,
20884SC_QZ1_QUAD_PER_TILE_H14                 = 0x0000007e,
20885SC_QZ1_QUAD_PER_TILE_H15                 = 0x0000007f,
20886SC_QZ1_QUAD_PER_TILE_H16                 = 0x00000080,
20887SC_QZ2_QUAD_PER_TILE_H0                  = 0x00000081,
20888SC_QZ2_QUAD_PER_TILE_H1                  = 0x00000082,
20889SC_QZ2_QUAD_PER_TILE_H2                  = 0x00000083,
20890SC_QZ2_QUAD_PER_TILE_H3                  = 0x00000084,
20891SC_QZ2_QUAD_PER_TILE_H4                  = 0x00000085,
20892SC_QZ2_QUAD_PER_TILE_H5                  = 0x00000086,
20893SC_QZ2_QUAD_PER_TILE_H6                  = 0x00000087,
20894SC_QZ2_QUAD_PER_TILE_H7                  = 0x00000088,
20895SC_QZ2_QUAD_PER_TILE_H8                  = 0x00000089,
20896SC_QZ2_QUAD_PER_TILE_H9                  = 0x0000008a,
20897SC_QZ2_QUAD_PER_TILE_H10                 = 0x0000008b,
20898SC_QZ2_QUAD_PER_TILE_H11                 = 0x0000008c,
20899SC_QZ2_QUAD_PER_TILE_H12                 = 0x0000008d,
20900SC_QZ2_QUAD_PER_TILE_H13                 = 0x0000008e,
20901SC_QZ2_QUAD_PER_TILE_H14                 = 0x0000008f,
20902SC_QZ2_QUAD_PER_TILE_H15                 = 0x00000090,
20903SC_QZ2_QUAD_PER_TILE_H16                 = 0x00000091,
20904SC_QZ3_QUAD_PER_TILE_H0                  = 0x00000092,
20905SC_QZ3_QUAD_PER_TILE_H1                  = 0x00000093,
20906SC_QZ3_QUAD_PER_TILE_H2                  = 0x00000094,
20907SC_QZ3_QUAD_PER_TILE_H3                  = 0x00000095,
20908SC_QZ3_QUAD_PER_TILE_H4                  = 0x00000096,
20909SC_QZ3_QUAD_PER_TILE_H5                  = 0x00000097,
20910SC_QZ3_QUAD_PER_TILE_H6                  = 0x00000098,
20911SC_QZ3_QUAD_PER_TILE_H7                  = 0x00000099,
20912SC_QZ3_QUAD_PER_TILE_H8                  = 0x0000009a,
20913SC_QZ3_QUAD_PER_TILE_H9                  = 0x0000009b,
20914SC_QZ3_QUAD_PER_TILE_H10                 = 0x0000009c,
20915SC_QZ3_QUAD_PER_TILE_H11                 = 0x0000009d,
20916SC_QZ3_QUAD_PER_TILE_H12                 = 0x0000009e,
20917SC_QZ3_QUAD_PER_TILE_H13                 = 0x0000009f,
20918SC_QZ3_QUAD_PER_TILE_H14                 = 0x000000a0,
20919SC_QZ3_QUAD_PER_TILE_H15                 = 0x000000a1,
20920SC_QZ3_QUAD_PER_TILE_H16                 = 0x000000a2,
20921SC_QZ0_QUAD_COUNT                        = 0x000000a3,
20922SC_QZ1_QUAD_COUNT                        = 0x000000a4,
20923SC_QZ2_QUAD_COUNT                        = 0x000000a5,
20924SC_QZ3_QUAD_COUNT                        = 0x000000a6,
20925SC_P0_HIZ_TILE_COUNT                     = 0x000000a7,
20926SC_P1_HIZ_TILE_COUNT                     = 0x000000a8,
20927SC_P2_HIZ_TILE_COUNT                     = 0x000000a9,
20928SC_P3_HIZ_TILE_COUNT                     = 0x000000aa,
20929SC_P0_HIZ_QUAD_PER_TILE_H0               = 0x000000ab,
20930SC_P0_HIZ_QUAD_PER_TILE_H1               = 0x000000ac,
20931SC_P0_HIZ_QUAD_PER_TILE_H2               = 0x000000ad,
20932SC_P0_HIZ_QUAD_PER_TILE_H3               = 0x000000ae,
20933SC_P0_HIZ_QUAD_PER_TILE_H4               = 0x000000af,
20934SC_P0_HIZ_QUAD_PER_TILE_H5               = 0x000000b0,
20935SC_P0_HIZ_QUAD_PER_TILE_H6               = 0x000000b1,
20936SC_P0_HIZ_QUAD_PER_TILE_H7               = 0x000000b2,
20937SC_P0_HIZ_QUAD_PER_TILE_H8               = 0x000000b3,
20938SC_P0_HIZ_QUAD_PER_TILE_H9               = 0x000000b4,
20939SC_P0_HIZ_QUAD_PER_TILE_H10              = 0x000000b5,
20940SC_P0_HIZ_QUAD_PER_TILE_H11              = 0x000000b6,
20941SC_P0_HIZ_QUAD_PER_TILE_H12              = 0x000000b7,
20942SC_P0_HIZ_QUAD_PER_TILE_H13              = 0x000000b8,
20943SC_P0_HIZ_QUAD_PER_TILE_H14              = 0x000000b9,
20944SC_P0_HIZ_QUAD_PER_TILE_H15              = 0x000000ba,
20945SC_P0_HIZ_QUAD_PER_TILE_H16              = 0x000000bb,
20946SC_P1_HIZ_QUAD_PER_TILE_H0               = 0x000000bc,
20947SC_P1_HIZ_QUAD_PER_TILE_H1               = 0x000000bd,
20948SC_P1_HIZ_QUAD_PER_TILE_H2               = 0x000000be,
20949SC_P1_HIZ_QUAD_PER_TILE_H3               = 0x000000bf,
20950SC_P1_HIZ_QUAD_PER_TILE_H4               = 0x000000c0,
20951SC_P1_HIZ_QUAD_PER_TILE_H5               = 0x000000c1,
20952SC_P1_HIZ_QUAD_PER_TILE_H6               = 0x000000c2,
20953SC_P1_HIZ_QUAD_PER_TILE_H7               = 0x000000c3,
20954SC_P1_HIZ_QUAD_PER_TILE_H8               = 0x000000c4,
20955SC_P1_HIZ_QUAD_PER_TILE_H9               = 0x000000c5,
20956SC_P1_HIZ_QUAD_PER_TILE_H10              = 0x000000c6,
20957SC_P1_HIZ_QUAD_PER_TILE_H11              = 0x000000c7,
20958SC_P1_HIZ_QUAD_PER_TILE_H12              = 0x000000c8,
20959SC_P1_HIZ_QUAD_PER_TILE_H13              = 0x000000c9,
20960SC_P1_HIZ_QUAD_PER_TILE_H14              = 0x000000ca,
20961SC_P1_HIZ_QUAD_PER_TILE_H15              = 0x000000cb,
20962SC_P1_HIZ_QUAD_PER_TILE_H16              = 0x000000cc,
20963SC_P2_HIZ_QUAD_PER_TILE_H0               = 0x000000cd,
20964SC_P2_HIZ_QUAD_PER_TILE_H1               = 0x000000ce,
20965SC_P2_HIZ_QUAD_PER_TILE_H2               = 0x000000cf,
20966SC_P2_HIZ_QUAD_PER_TILE_H3               = 0x000000d0,
20967SC_P2_HIZ_QUAD_PER_TILE_H4               = 0x000000d1,
20968SC_P2_HIZ_QUAD_PER_TILE_H5               = 0x000000d2,
20969SC_P2_HIZ_QUAD_PER_TILE_H6               = 0x000000d3,
20970SC_P2_HIZ_QUAD_PER_TILE_H7               = 0x000000d4,
20971SC_P2_HIZ_QUAD_PER_TILE_H8               = 0x000000d5,
20972SC_P2_HIZ_QUAD_PER_TILE_H9               = 0x000000d6,
20973SC_P2_HIZ_QUAD_PER_TILE_H10              = 0x000000d7,
20974SC_P2_HIZ_QUAD_PER_TILE_H11              = 0x000000d8,
20975SC_P2_HIZ_QUAD_PER_TILE_H12              = 0x000000d9,
20976SC_P2_HIZ_QUAD_PER_TILE_H13              = 0x000000da,
20977SC_P2_HIZ_QUAD_PER_TILE_H14              = 0x000000db,
20978SC_P2_HIZ_QUAD_PER_TILE_H15              = 0x000000dc,
20979SC_P2_HIZ_QUAD_PER_TILE_H16              = 0x000000dd,
20980SC_P3_HIZ_QUAD_PER_TILE_H0               = 0x000000de,
20981SC_P3_HIZ_QUAD_PER_TILE_H1               = 0x000000df,
20982SC_P3_HIZ_QUAD_PER_TILE_H2               = 0x000000e0,
20983SC_P3_HIZ_QUAD_PER_TILE_H3               = 0x000000e1,
20984SC_P3_HIZ_QUAD_PER_TILE_H4               = 0x000000e2,
20985SC_P3_HIZ_QUAD_PER_TILE_H5               = 0x000000e3,
20986SC_P3_HIZ_QUAD_PER_TILE_H6               = 0x000000e4,
20987SC_P3_HIZ_QUAD_PER_TILE_H7               = 0x000000e5,
20988SC_P3_HIZ_QUAD_PER_TILE_H8               = 0x000000e6,
20989SC_P3_HIZ_QUAD_PER_TILE_H9               = 0x000000e7,
20990SC_P3_HIZ_QUAD_PER_TILE_H10              = 0x000000e8,
20991SC_P3_HIZ_QUAD_PER_TILE_H11              = 0x000000e9,
20992SC_P3_HIZ_QUAD_PER_TILE_H12              = 0x000000ea,
20993SC_P3_HIZ_QUAD_PER_TILE_H13              = 0x000000eb,
20994SC_P3_HIZ_QUAD_PER_TILE_H14              = 0x000000ec,
20995SC_P3_HIZ_QUAD_PER_TILE_H15              = 0x000000ed,
20996SC_P3_HIZ_QUAD_PER_TILE_H16              = 0x000000ee,
20997SC_P0_HIZ_QUAD_COUNT                     = 0x000000ef,
20998SC_P1_HIZ_QUAD_COUNT                     = 0x000000f0,
20999SC_P2_HIZ_QUAD_COUNT                     = 0x000000f1,
21000SC_P3_HIZ_QUAD_COUNT                     = 0x000000f2,

21001SC_P0_DETAIL_QUAD_COUNT                  = 0x000000f3,
21002SC_P1_DETAIL_QUAD_COUNT                  = 0x000000f4,
21003SC_P2_DETAIL_QUAD_COUNT                  = 0x000000f5,
21004SC_P3_DETAIL_QUAD_COUNT                  = 0x000000f6,
21005SC_P0_DETAIL_QUAD_WITH_1_PIX             = 0x000000f7,
21006SC_P0_DETAIL_QUAD_WITH_2_PIX             = 0x000000f8,
21007SC_P0_DETAIL_QUAD_WITH_3_PIX             = 0x000000f9,
21008SC_P0_DETAIL_QUAD_WITH_4_PIX             = 0x000000fa,
21009SC_P1_DETAIL_QUAD_WITH_1_PIX             = 0x000000fb,
21010SC_P1_DETAIL_QUAD_WITH_2_PIX             = 0x000000fc,
21011SC_P1_DETAIL_QUAD_WITH_3_PIX             = 0x000000fd,
21012SC_P1_DETAIL_QUAD_WITH_4_PIX             = 0x000000fe,
21013SC_P2_DETAIL_QUAD_WITH_1_PIX             = 0x000000ff,
21014SC_P2_DETAIL_QUAD_WITH_2_PIX             = 0x00000100,
21015SC_P2_DETAIL_QUAD_WITH_3_PIX             = 0x00000101,
21016SC_P2_DETAIL_QUAD_WITH_4_PIX             = 0x00000102,
21017SC_P3_DETAIL_QUAD_WITH_1_PIX             = 0x00000103,
21018SC_P3_DETAIL_QUAD_WITH_2_PIX             = 0x00000104,
21019SC_P3_DETAIL_QUAD_WITH_3_PIX             = 0x00000105,
21020SC_P3_DETAIL_QUAD_WITH_4_PIX             = 0x00000106,
21021SC_EARLYZ_QUAD_COUNT                     = 0x00000107,
21022SC_EARLYZ_QUAD_WITH_1_PIX                = 0x00000108,
21023SC_EARLYZ_QUAD_WITH_2_PIX                = 0x00000109,
21024SC_EARLYZ_QUAD_WITH_3_PIX                = 0x0000010a,
21025SC_EARLYZ_QUAD_WITH_4_PIX                = 0x0000010b,
21026SC_PKR_QUAD_PER_ROW_H1                   = 0x0000010c,
21027SC_PKR_QUAD_PER_ROW_H2                   = 0x0000010d,
21028SC_PKR_4X2_QUAD_SPLIT                    = 0x0000010e,
21029SC_PKR_4X2_FILL_QUAD                     = 0x0000010f,
21030SC_PKR_END_OF_VECTOR                     = 0x00000110,
21031SC_PKR_CONTROL_XFER                      = 0x00000111,
21032SC_PKR_DBHANG_FORCE_EOV                  = 0x00000112,
21033SC_REG_SCLK_BUSY                         = 0x00000113,
21034SC_GRP0_DYN_SCLK_BUSY                    = 0x00000114,
21035SC_GRP1_DYN_SCLK_BUSY                    = 0x00000115,
21036SC_GRP2_DYN_SCLK_BUSY                    = 0x00000116,
21037SC_GRP3_DYN_SCLK_BUSY                    = 0x00000117,
21038SC_GRP4_DYN_SCLK_BUSY                    = 0x00000118,
21039SC_PA0_SC_DATA_FIFO_RD                   = 0x00000119,
21040SC_PA0_SC_DATA_FIFO_WE                   = 0x0000011a,
21041SC_PA1_SC_DATA_FIFO_RD                   = 0x0000011b,
21042SC_PA1_SC_DATA_FIFO_WE                   = 0x0000011c,
21043SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES   = 0x0000011d,
21044SC_PS_ARB_XFC_ONLY_PRIM_CYCLES           = 0x0000011e,
21045SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM      = 0x0000011f,
21046SC_PS_ARB_STALLED_FROM_BELOW             = 0x00000120,
21047SC_PS_ARB_STARVED_FROM_ABOVE             = 0x00000121,
21048SC_PS_ARB_SC_BUSY                        = 0x00000122,
21049SC_PS_ARB_PA_SC_BUSY                     = 0x00000123,
21050SC_PA2_SC_DATA_FIFO_RD                   = 0x00000124,
21051SC_PA2_SC_DATA_FIFO_WE                   = 0x00000125,
21052SC_PA3_SC_DATA_FIFO_RD                   = 0x00000126,
21053SC_PA3_SC_DATA_FIFO_WE                   = 0x00000127,
21054SC_PA_SC_DEALLOC_0_0_WE                  = 0x00000128,
21055SC_PA_SC_DEALLOC_0_1_WE                  = 0x00000129,
21056SC_PA_SC_DEALLOC_1_0_WE                  = 0x0000012a,
21057SC_PA_SC_DEALLOC_1_1_WE                  = 0x0000012b,
21058SC_PA_SC_DEALLOC_2_0_WE                  = 0x0000012c,
21059SC_PA_SC_DEALLOC_2_1_WE                  = 0x0000012d,
21060SC_PA_SC_DEALLOC_3_0_WE                  = 0x0000012e,
21061SC_PA_SC_DEALLOC_3_1_WE                  = 0x0000012f,
21062SC_PA0_SC_EOP_WE                         = 0x00000130,
21063SC_PA0_SC_EOPG_WE                        = 0x00000131,
21064SC_PA0_SC_EVENT_WE                       = 0x00000132,
21065SC_PA1_SC_EOP_WE                         = 0x00000133,
21066SC_PA1_SC_EOPG_WE                        = 0x00000134,
21067SC_PA1_SC_EVENT_WE                       = 0x00000135,
21068SC_PA2_SC_EOP_WE                         = 0x00000136,
21069SC_PA2_SC_EOPG_WE                        = 0x00000137,
21070SC_PA2_SC_EVENT_WE                       = 0x00000138,
21071SC_PA3_SC_EOP_WE                         = 0x00000139,
21072SC_PA3_SC_EOPG_WE                        = 0x0000013a,
21073SC_PA3_SC_EVENT_WE                       = 0x0000013b,
21074SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO  = 0x0000013c,
21075SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH          = 0x0000013d,
21076SC_PS_ARB_NULL_PRIM_BUBBLE_POP           = 0x0000013e,
21077SC_PS_ARB_EOP_POP_SYNC_POP               = 0x0000013f,
21078SC_PS_ARB_EVENT_SYNC_POP                 = 0x00000140,
21079SC_SC_PS_ENG_MULTICYCLE_BUBBLE           = 0x00000141,
21080SC_PA0_SC_FPOV_WE                        = 0x00000142,
21081SC_PA1_SC_FPOV_WE                        = 0x00000143,
21082SC_PA2_SC_FPOV_WE                        = 0x00000144,
21083SC_PA3_SC_FPOV_WE                        = 0x00000145,
21084SC_PA0_SC_LPOV_WE                        = 0x00000146,
21085SC_PA1_SC_LPOV_WE                        = 0x00000147,
21086SC_PA2_SC_LPOV_WE                        = 0x00000148,
21087SC_PA3_SC_LPOV_WE                        = 0x00000149,
21088SC_SC_SPI_DEALLOC_0_0                    = 0x0000014a,
21089SC_SC_SPI_DEALLOC_0_1                    = 0x0000014b,
21090SC_SC_SPI_DEALLOC_0_2                    = 0x0000014c,
21091SC_SC_SPI_DEALLOC_1_0                    = 0x0000014d,
21092SC_SC_SPI_DEALLOC_1_1                    = 0x0000014e,
21093SC_SC_SPI_DEALLOC_1_2                    = 0x0000014f,
21094SC_SC_SPI_DEALLOC_2_0                    = 0x00000150,
21095SC_SC_SPI_DEALLOC_2_1                    = 0x00000151,
21096SC_SC_SPI_DEALLOC_2_2                    = 0x00000152,
21097SC_SC_SPI_DEALLOC_3_0                    = 0x00000153,
21098SC_SC_SPI_DEALLOC_3_1                    = 0x00000154,
21099SC_SC_SPI_DEALLOC_3_2                    = 0x00000155,
21100SC_SC_SPI_FPOV_0                         = 0x00000156,
21101SC_SC_SPI_FPOV_1                         = 0x00000157,
21102SC_SC_SPI_FPOV_2                         = 0x00000158,
21103SC_SC_SPI_FPOV_3                         = 0x00000159,
21104SC_SC_SPI_EVENT                          = 0x0000015a,
21105SC_PS_TS_EVENT_FIFO_PUSH                 = 0x0000015b,
21106SC_PS_TS_EVENT_FIFO_POP                  = 0x0000015c,
21107SC_PS_CTX_DONE_FIFO_PUSH                 = 0x0000015d,
21108SC_PS_CTX_DONE_FIFO_POP                  = 0x0000015e,
21109SC_MULTICYCLE_BUBBLE_FREEZE              = 0x0000015f,
21110SC_EOP_SYNC_WINDOW                       = 0x00000160,
21111SC_PA0_SC_NULL_WE                        = 0x00000161,
21112SC_PA0_SC_NULL_DEALLOC_WE                = 0x00000162,
21113SC_PA0_SC_DATA_FIFO_EOPG_RD              = 0x00000163,
21114SC_PA0_SC_DATA_FIFO_EOP_RD               = 0x00000164,
21115SC_PA0_SC_DEALLOC_0_RD                   = 0x00000165,
21116SC_PA0_SC_DEALLOC_1_RD                   = 0x00000166,
21117SC_PA1_SC_DATA_FIFO_EOPG_RD              = 0x00000167,
21118SC_PA1_SC_DATA_FIFO_EOP_RD               = 0x00000168,
21119SC_PA1_SC_DEALLOC_0_RD                   = 0x00000169,
21120SC_PA1_SC_DEALLOC_1_RD                   = 0x0000016a,
21121SC_PA1_SC_NULL_WE                        = 0x0000016b,
21122SC_PA1_SC_NULL_DEALLOC_WE                = 0x0000016c,
21123SC_PA2_SC_DATA_FIFO_EOPG_RD              = 0x0000016d,
21124SC_PA2_SC_DATA_FIFO_EOP_RD               = 0x0000016e,
21125SC_PA2_SC_DEALLOC_0_RD                   = 0x0000016f,
21126SC_PA2_SC_DEALLOC_1_RD                   = 0x00000170,
21127SC_PA2_SC_NULL_WE                        = 0x00000171,
21128SC_PA2_SC_NULL_DEALLOC_WE                = 0x00000172,
21129SC_PA3_SC_DATA_FIFO_EOPG_RD              = 0x00000173,
21130SC_PA3_SC_DATA_FIFO_EOP_RD               = 0x00000174,
21131SC_PA3_SC_DEALLOC_0_RD                   = 0x00000175,
21132SC_PA3_SC_DEALLOC_1_RD                   = 0x00000176,
21133SC_PA3_SC_NULL_WE                        = 0x00000177,
21134SC_PA3_SC_NULL_DEALLOC_WE                = 0x00000178,
21135SC_PS_PA0_SC_FIFO_EMPTY                  = 0x00000179,
21136SC_PS_PA0_SC_FIFO_FULL                   = 0x0000017a,
21137SC_PA0_PS_DATA_SEND                      = 0x0000017b,
21138SC_PS_PA1_SC_FIFO_EMPTY                  = 0x0000017c,
21139SC_PS_PA1_SC_FIFO_FULL                   = 0x0000017d,
21140SC_PA1_PS_DATA_SEND                      = 0x0000017e,
21141SC_PS_PA2_SC_FIFO_EMPTY                  = 0x0000017f,
21142SC_PS_PA2_SC_FIFO_FULL                   = 0x00000180,
21143SC_PA2_PS_DATA_SEND                      = 0x00000181,
21144SC_PS_PA3_SC_FIFO_EMPTY                  = 0x00000182,
21145SC_PS_PA3_SC_FIFO_FULL                   = 0x00000183,
21146SC_PA3_PS_DATA_SEND                      = 0x00000184,
21147SC_BUSY_PROCESSING_MULTICYCLE_PRIM       = 0x00000185,
21148SC_BUSY_CNT_NOT_ZERO                     = 0x00000186,
21149SC_BM_BUSY                               = 0x00000187,
21150SC_BACKEND_BUSY                          = 0x00000188,
21151SC_SCF_SCB_INTERFACE_BUSY                = 0x00000189,
21152SC_SCB_BUSY                              = 0x0000018a,
21153SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY  = 0x0000018b,
21154SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL  = 0x0000018c,
21155SC_PBB_BIN_HIST_NUM_PRIMS                = 0x0000018d,
21156SC_PBB_BATCH_HIST_NUM_PRIMS              = 0x0000018e,
21157SC_PBB_BIN_HIST_NUM_CONTEXTS             = 0x0000018f,
21158SC_PBB_BATCH_HIST_NUM_CONTEXTS           = 0x00000190,
21159SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES    = 0x00000191,
21160SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES  = 0x00000192,
21161SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS     = 0x00000193,
21162SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS  = 0x00000194,
21163SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM      = 0x00000195,
21164SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW    = 0x00000196,
21165SC_PBB_BUSY                              = 0x00000197,
21166SC_PBB_BUSY_AND_RTR                      = 0x00000198,
21167SC_PBB_STALLS_PA_DUE_TO_NO_TILES         = 0x00000199,
21168SC_PBB_NUM_BINS                          = 0x0000019a,
21169SC_PBB_END_OF_BIN                        = 0x0000019b,
21170SC_PBB_END_OF_BATCH                      = 0x0000019c,
21171SC_PBB_PRIMBIN_PROCESSED                 = 0x0000019d,
21172SC_PBB_PRIM_ADDED_TO_BATCH               = 0x0000019e,
21173SC_PBB_NONBINNED_PRIM                    = 0x0000019f,
21174SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB       = 0x000001a0,
21175SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB       = 0x000001a1,
21176SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION  = 0x000001a2,
21177SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW  = 0x000001a3,
21178SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN  = 0x000001a4,
21179SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE  = 0x000001a5,
21180SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE  = 0x000001a6,
21181SC_PBB_BATCH_BREAK_DUE_TO_PRIM           = 0x000001a7,
21182SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE     = 0x000001a8,
21183SC_PBB_BATCH_BREAK_DUE_TO_EVENT          = 0x000001a9,
21184SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT     = 0x000001aa,
21185SC_POPS_INTRA_WAVE_OVERLAPS              = 0x000001ab,
21186SC_POPS_FORCE_EOV                        = 0x000001ac,
21187SC_PKR_QUAD_OVERLAP_NOT_FOUND_IN_WAVE_TABLE  = 0x000001ad,
21188SC_PKR_QUAD_OVERLAP_FOUND_IN_WAVE_TABLE  = 0x000001ae,
21189} SC_PERFCNT_SEL;
21190
21191/*
21192 * SePairXsel enum
21193 */
21194
21195typedef enum SePairXsel {
21196RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE   = 0x00000000,
21197RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE  = 0x00000001,
21198RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE  = 0x00000002,
21199RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE  = 0x00000003,
21200RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE  = 0x00000004,
21201} SePairXsel;
21202
21203/*
21204 * SePairYsel enum
21205 */
21206
21207typedef enum SePairYsel {
21208RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE   = 0x00000000,
21209RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE  = 0x00000001,
21210RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE  = 0x00000002,
21211RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE  = 0x00000003,
21212RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE  = 0x00000004,
21213} SePairYsel;
21214
21215/*
21216 * SePairMap enum
21217 */
21218
21219typedef enum SePairMap {
21220RASTER_CONFIG_SE_PAIR_MAP_0              = 0x00000000,
21221RASTER_CONFIG_SE_PAIR_MAP_1              = 0x00000001,
21222RASTER_CONFIG_SE_PAIR_MAP_2              = 0x00000002,
21223RASTER_CONFIG_SE_PAIR_MAP_3              = 0x00000003,
21224} SePairMap;
21225
21226/*
21227 * SeXsel enum
21228 */
21229
21230typedef enum SeXsel {
21231RASTER_CONFIG_SE_XSEL_8_WIDE_TILE        = 0x00000000,
21232RASTER_CONFIG_SE_XSEL_16_WIDE_TILE       = 0x00000001,
21233RASTER_CONFIG_SE_XSEL_32_WIDE_TILE       = 0x00000002,
21234RASTER_CONFIG_SE_XSEL_64_WIDE_TILE       = 0x00000003,
21235RASTER_CONFIG_SE_XSEL_128_WIDE_TILE      = 0x00000004,
21236} SeXsel;
21237
21238/*
21239 * SeYsel enum
21240 */
21241
21242typedef enum SeYsel {
21243RASTER_CONFIG_SE_YSEL_8_WIDE_TILE        = 0x00000000,
21244RASTER_CONFIG_SE_YSEL_16_WIDE_TILE       = 0x00000001,
21245RASTER_CONFIG_SE_YSEL_32_WIDE_TILE       = 0x00000002,
21246RASTER_CONFIG_SE_YSEL_64_WIDE_TILE       = 0x00000003,
21247RASTER_CONFIG_SE_YSEL_128_WIDE_TILE      = 0x00000004,
21248} SeYsel;
21249
21250/*
21251 * SeMap enum
21252 */
21253
21254typedef enum SeMap {
21255RASTER_CONFIG_SE_MAP_0                   = 0x00000000,
21256RASTER_CONFIG_SE_MAP_1                   = 0x00000001,
21257RASTER_CONFIG_SE_MAP_2                   = 0x00000002,
21258RASTER_CONFIG_SE_MAP_3                   = 0x00000003,
21259} SeMap;
21260
21261/*
21262 * ScXsel enum
21263 */
21264
21265typedef enum ScXsel {
21266RASTER_CONFIG_SC_XSEL_8_WIDE_TILE        = 0x00000000,
21267RASTER_CONFIG_SC_XSEL_16_WIDE_TILE       = 0x00000001,
21268RASTER_CONFIG_SC_XSEL_32_WIDE_TILE       = 0x00000002,
21269RASTER_CONFIG_SC_XSEL_64_WIDE_TILE       = 0x00000003,
21270} ScXsel;
21271
21272/*
21273 * ScYsel enum
21274 */
21275
21276typedef enum ScYsel {
21277RASTER_CONFIG_SC_YSEL_8_WIDE_TILE        = 0x00000000,
21278RASTER_CONFIG_SC_YSEL_16_WIDE_TILE       = 0x00000001,
21279RASTER_CONFIG_SC_YSEL_32_WIDE_TILE       = 0x00000002,
21280RASTER_CONFIG_SC_YSEL_64_WIDE_TILE       = 0x00000003,
21281} ScYsel;
21282
21283/*
21284 * ScMap enum
21285 */
21286
21287typedef enum ScMap {
21288RASTER_CONFIG_SC_MAP_0                   = 0x00000000,
21289RASTER_CONFIG_SC_MAP_1                   = 0x00000001,
21290RASTER_CONFIG_SC_MAP_2                   = 0x00000002,
21291RASTER_CONFIG_SC_MAP_3                   = 0x00000003,
21292} ScMap;
21293
21294/*
21295 * PkrXsel2 enum
21296 */
21297
21298typedef enum PkrXsel2 {
21299RASTER_CONFIG_PKR_XSEL2_0                = 0x00000000,
21300RASTER_CONFIG_PKR_XSEL2_1                = 0x00000001,
21301RASTER_CONFIG_PKR_XSEL2_2                = 0x00000002,
21302RASTER_CONFIG_PKR_XSEL2_3                = 0x00000003,
21303} PkrXsel2;
21304
21305/*
21306 * PkrXsel enum
21307 */
21308
21309typedef enum PkrXsel {
21310RASTER_CONFIG_PKR_XSEL_0                 = 0x00000000,
21311RASTER_CONFIG_PKR_XSEL_1                 = 0x00000001,
21312RASTER_CONFIG_PKR_XSEL_2                 = 0x00000002,
21313RASTER_CONFIG_PKR_XSEL_3                 = 0x00000003,
21314} PkrXsel;
21315
21316/*
21317 * PkrYsel enum
21318 */
21319
21320typedef enum PkrYsel {
21321RASTER_CONFIG_PKR_YSEL_0                 = 0x00000000,
21322RASTER_CONFIG_PKR_YSEL_1                 = 0x00000001,
21323RASTER_CONFIG_PKR_YSEL_2                 = 0x00000002,
21324RASTER_CONFIG_PKR_YSEL_3                 = 0x00000003,
21325} PkrYsel;
21326
21327/*
21328 * PkrMap enum
21329 */
21330
21331typedef enum PkrMap {
21332RASTER_CONFIG_PKR_MAP_0                  = 0x00000000,
21333RASTER_CONFIG_PKR_MAP_1                  = 0x00000001,
21334RASTER_CONFIG_PKR_MAP_2                  = 0x00000002,
21335RASTER_CONFIG_PKR_MAP_3                  = 0x00000003,
21336} PkrMap;
21337
21338/*
21339 * RbXsel enum
21340 */
21341
21342typedef enum RbXsel {
21343RASTER_CONFIG_RB_XSEL_0                  = 0x00000000,
21344RASTER_CONFIG_RB_XSEL_1                  = 0x00000001,
21345} RbXsel;
21346
21347/*
21348 * RbYsel enum
21349 */
21350
21351typedef enum RbYsel {
21352RASTER_CONFIG_RB_YSEL_0                  = 0x00000000,
21353RASTER_CONFIG_RB_YSEL_1                  = 0x00000001,
21354} RbYsel;
21355
21356/*
21357 * RbXsel2 enum
21358 */
21359
21360typedef enum RbXsel2 {
21361RASTER_CONFIG_RB_XSEL2_0                 = 0x00000000,
21362RASTER_CONFIG_RB_XSEL2_1                 = 0x00000001,
21363RASTER_CONFIG_RB_XSEL2_2                 = 0x00000002,
21364RASTER_CONFIG_RB_XSEL2_3                 = 0x00000003,
21365} RbXsel2;
21366
21367/*
21368 * RbMap enum
21369 */
21370
21371typedef enum RbMap {
21372RASTER_CONFIG_RB_MAP_0                   = 0x00000000,
21373RASTER_CONFIG_RB_MAP_1                   = 0x00000001,
21374RASTER_CONFIG_RB_MAP_2                   = 0x00000002,
21375RASTER_CONFIG_RB_MAP_3                   = 0x00000003,
21376} RbMap;
21377
21378/*
21379 * BinningMode enum
21380 */
21381
21382typedef enum BinningMode {
21383BINNING_ALLOWED                          = 0x00000000,
21384FORCE_BINNING_ON                         = 0x00000001,
21385DISABLE_BINNING_USE_NEW_SC               = 0x00000002,
21386DISABLE_BINNING_USE_LEGACY_SC            = 0x00000003,
21387} BinningMode;
21388
21389/*
21390 * BinEventCntl enum
21391 */
21392
21393typedef enum BinEventCntl {
21394BINNER_BREAK_BATCH                       = 0x00000000,
21395BINNER_PIPELINE                          = 0x00000001,
21396BINNER_DROP_ASSERT                       = 0x00000002,
21397} BinEventCntl;
21398
21399/*
21400 * CovToShaderSel enum
21401 */
21402
21403typedef enum CovToShaderSel {
21404INPUT_COVERAGE                           = 0x00000000,
21405INPUT_INNER_COVERAGE                     = 0x00000001,
21406INPUT_DEPTH_COVERAGE                     = 0x00000002,
21407RAW                                      = 0x00000003,
21408} CovToShaderSel;
21409
21410/*******************************************************
21411 * RMI Enums
21412 *******************************************************/
21413
21414/*
21415 * RMIPerfSel enum
21416 */
21417
21418typedef enum RMIPerfSel {
21419RMI_PERF_SEL_NONE                        = 0x00000000,
21420RMI_PERF_SEL_BUSY                        = 0x00000001,
21421RMI_PERF_SEL_REG_CLK_VLD                 = 0x00000002,
21422RMI_PERF_SEL_DYN_CLK_CMN_VLD             = 0x00000003,
21423RMI_PERF_SEL_DYN_CLK_RB_VLD              = 0x00000004,
21424RMI_PERF_SEL_DYN_CLK_PERF_VLD            = 0x00000005,
21425RMI_PERF_SEL_PERF_WINDOW                 = 0x00000006,
21426RMI_PERF_SEL_EVENT_SEND                  = 0x00000007,
21427RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008,
21428RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009,
21429RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a,
21430RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b,
21431RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c,
21432RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d,
21433RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e,
21434RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f,
21435RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010,
21436RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011,
21437RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012,
21438RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013,
21439RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014,
21440RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015,
21441RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016,
21442RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017,
21443RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018,
21444RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019,
21445RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a,
21446RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b,
21447RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c,
21448RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d,
21449RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e,
21450RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f,
21451RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020,
21452RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021,
21453RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022,
21454RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023,
21455RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024,
21456RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025,
21457RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026,
21458RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027,
21459RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028,
21460RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029,
21461RMI_PERF_SEL_UTCL1_TRANSLATION_MISS      = 0x0000002a,
21462RMI_PERF_SEL_UTCL1_PERMISSION_MISS       = 0x0000002b,
21463RMI_PERF_SEL_UTCL1_REQUEST               = 0x0000002c,
21464RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX    = 0x0000002d,
21465RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT    = 0x0000002e,
21466RMI_PERF_SEL_UTCL1_LFIFO_FULL            = 0x0000002f,
21467RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES   = 0x00000030,
21468RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS  = 0x00000031,
21469RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL   = 0x00000032,
21470RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL         = 0x00000033,
21471RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS      = 0x00000034,
21472RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID        = 0x00000035,
21473RMI_PERF_SEL_RB_RMI_WRREQ_BUSY           = 0x00000036,
21474RMI_PERF_SEL_RB_RMI_WRREQ_CID0           = 0x00000037,
21475RMI_PERF_SEL_RB_RMI_WRREQ_CID1           = 0x00000038,
21476RMI_PERF_SEL_RB_RMI_WRREQ_CID2           = 0x00000039,
21477RMI_PERF_SEL_RB_RMI_WRREQ_CID3           = 0x0000003a,
21478RMI_PERF_SEL_RB_RMI_WRREQ_CID4           = 0x0000003b,
21479RMI_PERF_SEL_RB_RMI_WRREQ_CID5           = 0x0000003c,
21480RMI_PERF_SEL_RB_RMI_WRREQ_CID6           = 0x0000003d,
21481RMI_PERF_SEL_RB_RMI_WRREQ_CID7           = 0x0000003e,
21482RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID = 0x0000003f,
21483RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000040,
21484RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000041,
21485RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY      = 0x00000042,
21486RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID  = 0x00000043,
21487RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0     = 0x00000044,
21488RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1     = 0x00000045,
21489RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2     = 0x00000046,
21490RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3     = 0x00000047,
21491RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4     = 0x00000048,
21492RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5     = 0x00000049,
21493RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6     = 0x0000004a,
21494RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7     = 0x0000004b,
21495RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0    = 0x0000004c,
21496RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1    = 0x0000004d,
21497RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2    = 0x0000004e,
21498RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3    = 0x0000004f,
21499RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID     = 0x00000050,
21500RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID        = 0x00000051,
21501RMI_PERF_SEL_RB_RMI_RDREQ_BUSY           = 0x00000052,
21502RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0        = 0x00000053,
21503RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1        = 0x00000054,
21504RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2        = 0x00000055,
21505RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3        = 0x00000056,
21506RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4        = 0x00000057,
21507RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5        = 0x00000058,
21508RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6        = 0x00000059,
21509RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7        = 0x0000005a,
21510RMI_PERF_SEL_RB_RMI_RDREQ_CID0           = 0x0000005b,
21511RMI_PERF_SEL_RB_RMI_RDREQ_CID1           = 0x0000005c,
21512RMI_PERF_SEL_RB_RMI_RDREQ_CID2           = 0x0000005d,
21513RMI_PERF_SEL_RB_RMI_RDREQ_CID3           = 0x0000005e,
21514RMI_PERF_SEL_RB_RMI_RDREQ_CID4           = 0x0000005f,
21515RMI_PERF_SEL_RB_RMI_RDREQ_CID5           = 0x00000060,
21516RMI_PERF_SEL_RB_RMI_RDREQ_CID6           = 0x00000061,
21517RMI_PERF_SEL_RB_RMI_RDREQ_CID7           = 0x00000062,
21518RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000063,
21519RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000064,
21520RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000065,
21521RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY      = 0x00000066,
21522RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000067,
21523RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0  = 0x00000068,
21524RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1  = 0x00000069,
21525RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2  = 0x0000006a,
21526RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3  = 0x0000006b,
21527RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4  = 0x0000006c,
21528RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5  = 0x0000006d,
21529RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6  = 0x0000006e,
21530RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7  = 0x0000006f,
21531RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000070,
21532RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000071,
21533RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000072,
21534RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000073,
21535RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID        = 0x00000074,
21536RMI_PERF_SEL_RMI_TC_REQ_BUSY             = 0x00000075,
21537RMI_PERF_SEL_RMI_TC_WRREQ_CID0           = 0x00000076,
21538RMI_PERF_SEL_RMI_TC_WRREQ_CID1           = 0x00000077,
21539RMI_PERF_SEL_RMI_TC_WRREQ_CID2           = 0x00000078,
21540RMI_PERF_SEL_RMI_TC_WRREQ_CID3           = 0x00000079,
21541RMI_PERF_SEL_RMI_TC_WRREQ_CID4           = 0x0000007a,
21542RMI_PERF_SEL_RMI_TC_WRREQ_CID5           = 0x0000007b,
21543RMI_PERF_SEL_RMI_TC_WRREQ_CID6           = 0x0000007c,
21544RMI_PERF_SEL_RMI_TC_WRREQ_CID7           = 0x0000007d,
21545RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000007e,
21546RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID  = 0x0000007f,
21547RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID        = 0x00000080,
21548RMI_PERF_SEL_RMI_TC_RDREQ_CID0           = 0x00000081,
21549RMI_PERF_SEL_RMI_TC_RDREQ_CID1           = 0x00000082,
21550RMI_PERF_SEL_RMI_TC_RDREQ_CID2           = 0x00000083,
21551RMI_PERF_SEL_RMI_TC_RDREQ_CID3           = 0x00000084,
21552RMI_PERF_SEL_RMI_TC_RDREQ_CID4           = 0x00000085,
21553RMI_PERF_SEL_RMI_TC_RDREQ_CID5           = 0x00000086,
21554RMI_PERF_SEL_RMI_TC_RDREQ_CID6           = 0x00000087,
21555RMI_PERF_SEL_RMI_TC_RDREQ_CID7           = 0x00000088,
21556RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000089,
21557RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID  = 0x0000008a,
21558RMI_PERF_SEL_UTCL1_BUSY                  = 0x0000008b,
21559RMI_PERF_SEL_RMI_UTC_REQ                 = 0x0000008c,
21560RMI_PERF_SEL_RMI_UTC_BUSY                = 0x0000008d,
21561RMI_PERF_SEL_UTCL1_UTCL2_REQ             = 0x0000008e,
21562RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY     = 0x0000008f,
21563RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT       = 0x00000090,
21564RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT       = 0x00000091,
21565RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x00000092,
21566RMI_PERF_SEL_XNACK_FIFO_NUM_USED         = 0x00000093,
21567RMI_PERF_SEL_LAT_FIFO_NUM_USED           = 0x00000094,
21568RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ       = 0x00000095,
21569RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ    = 0x00000096,
21570RMI_PERF_SEL_XNACK_FIFO_FULL             = 0x00000097,
21571RMI_PERF_SEL_XNACK_FIFO_BUSY             = 0x00000098,
21572RMI_PERF_SEL_LAT_FIFO_FULL               = 0x00000099,
21573RMI_PERF_SEL_SKID_FIFO_DEPTH             = 0x0000009a,
21574RMI_PERF_SEL_TCIW_INFLIGHT_COUNT         = 0x0000009b,
21575RMI_PERF_SEL_PRT_FIFO_NUM_USED           = 0x0000009c,
21576RMI_PERF_SEL_PRT_FIFO_REQ                = 0x0000009d,
21577RMI_PERF_SEL_PRT_FIFO_BUSY               = 0x0000009e,
21578RMI_PERF_SEL_TCIW_REQ                    = 0x0000009f,
21579RMI_PERF_SEL_TCIW_BUSY                   = 0x000000a0,
21580RMI_PERF_SEL_SKID_FIFO_REQ               = 0x000000a1,
21581RMI_PERF_SEL_SKID_FIFO_BUSY              = 0x000000a2,
21582RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0  = 0x000000a3,
21583RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1  = 0x000000a4,
21584RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2  = 0x000000a5,
21585RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3  = 0x000000a6,
21586RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR       = 0x000000a7,
21587RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR      = 0x000000a8,
21588RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB      = 0x000000a9,
21589RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB     = 0x000000aa,
21590RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000ab,
21591RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000ac,
21592RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000ad,
21593RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000ae,
21594RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000af,
21595RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000b0,
21596RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000b1,
21597RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000b2,
21598RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000b3,
21599RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000b4,
21600RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000b5,
21601RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000b6,
21602RMI_PERF_SEL_POP_DEMUX_RTS_RTR           = 0x000000b7,
21603RMI_PERF_SEL_POP_DEMUX_RTSB_RTR          = 0x000000b8,
21604RMI_PERF_SEL_POP_DEMUX_RTS_RTRB          = 0x000000b9,
21605RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB         = 0x000000ba,
21606RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR        = 0x000000bb,
21607RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR       = 0x000000bc,
21608RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB       = 0x000000bd,
21609RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB      = 0x000000be,
21610RMI_PERF_SEL_UTC_POP_RTS_RTR             = 0x000000bf,
21611RMI_PERF_SEL_UTC_POP_RTSB_RTR            = 0x000000c0,
21612RMI_PERF_SEL_UTC_POP_RTS_RTRB            = 0x000000c1,
21613RMI_PERF_SEL_UTC_POP_RTSB_RTRB           = 0x000000c2,
21614RMI_PERF_SEL_POP_XNACK_RTS_RTR           = 0x000000c3,
21615RMI_PERF_SEL_POP_XNACK_RTSB_RTR          = 0x000000c4,
21616RMI_PERF_SEL_POP_XNACK_RTS_RTRB          = 0x000000c5,
21617RMI_PERF_SEL_POP_XNACK_RTSB_RTRB         = 0x000000c6,
21618RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR      = 0x000000c7,
21619RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR     = 0x000000c8,
21620RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB     = 0x000000c9,
21621RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB    = 0x000000ca,
21622RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000cb,
21623RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000cc,
21624RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000cd,
21625RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000ce,
21626RMI_PERF_SEL_SKID_FIFO_IN_RTS            = 0x000000cf,
21627RMI_PERF_SEL_SKID_FIFO_IN_RTSB           = 0x000000d0,
21628RMI_PERF_SEL_SKID_FIFO_OUT_RTS           = 0x000000d1,
21629RMI_PERF_SEL_SKID_FIFO_OUT_RTSB          = 0x000000d2,
21630RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR  = 0x000000d3,
21631RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000d4,
21632RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR   = 0x000000d5,
21633RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR   = 0x000000d6,
21634RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR    = 0x000000d7,
21635RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR    = 0x000000d8,
21636RMI_PERF_SEL_REORDER_FIFO_REQ            = 0x000000d9,
21637RMI_PERF_SEL_REORDER_FIFO_BUSY           = 0x000000da,
21638RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID  = 0x000000db,
21639RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0     = 0x000000dc,
21640RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1     = 0x000000dd,
21641RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2     = 0x000000de,
21642RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3     = 0x000000df,
21643RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4     = 0x000000e0,
21644RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5     = 0x000000e1,
21645RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6     = 0x000000e2,
21646RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7     = 0x000000e3,
21647RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0    = 0x000000e4,
21648RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1    = 0x000000e5,
21649RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2    = 0x000000e6,
21650RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3    = 0x000000e7,
21651} RMIPerfSel;
21652
21653/*******************************************************
21654 * IH Enums
21655 *******************************************************/
21656
21657/*
21658 * IH_PERF_SEL enum
21659 */
21660
21661typedef enum IH_PERF_SEL {
21662IH_PERF_SEL_CYCLE                        = 0x00000000,
21663IH_PERF_SEL_IDLE                         = 0x00000001,
21664IH_PERF_SEL_INPUT_IDLE                   = 0x00000002,
21665IH_PERF_SEL_BUFFER_IDLE                  = 0x00000003,
21666IH_PERF_SEL_RB0_FULL                     = 0x00000004,
21667IH_PERF_SEL_RB0_OVERFLOW                 = 0x00000005,
21668IH_PERF_SEL_RB0_WPTR_WRITEBACK           = 0x00000006,
21669IH_PERF_SEL_RB0_WPTR_WRAP                = 0x00000007,
21670IH_PERF_SEL_RB0_RPTR_WRAP                = 0x00000008,
21671IH_PERF_SEL_MC_WR_IDLE                   = 0x00000009,
21672IH_PERF_SEL_MC_WR_COUNT                  = 0x0000000a,
21673IH_PERF_SEL_MC_WR_STALL                  = 0x0000000b,
21674IH_PERF_SEL_MC_WR_CLEAN_PENDING          = 0x0000000c,
21675IH_PERF_SEL_MC_WR_CLEAN_STALL            = 0x0000000d,
21676IH_PERF_SEL_BIF_LINE0_RISING             = 0x0000000e,
21677IH_PERF_SEL_BIF_LINE0_FALLING            = 0x0000000f,
21678IH_PERF_SEL_RB1_FULL                     = 0x00000010,
21679IH_PERF_SEL_RB1_OVERFLOW                 = 0x00000011,
21680Reserved18                               = 0x00000012,
21681IH_PERF_SEL_RB1_WPTR_WRAP                = 0x00000013,
21682IH_PERF_SEL_RB1_RPTR_WRAP                = 0x00000014,
21683IH_PERF_SEL_RB2_FULL                     = 0x00000015,
21684IH_PERF_SEL_RB2_OVERFLOW                 = 0x00000016,
21685Reserved23                               = 0x00000017,
21686IH_PERF_SEL_RB2_WPTR_WRAP                = 0x00000018,
21687IH_PERF_SEL_RB2_RPTR_WRAP                = 0x00000019,
21688Reserved26                               = 0x0000001a,
21689Reserved27                               = 0x0000001b,
21690Reserved28                               = 0x0000001c,
21691Reserved29                               = 0x0000001d,
21692IH_PERF_SEL_RB0_FULL_VF0                 = 0x0000001e,
21693IH_PERF_SEL_RB0_FULL_VF1                 = 0x0000001f,
21694IH_PERF_SEL_RB0_FULL_VF2                 = 0x00000020,
21695IH_PERF_SEL_RB0_FULL_VF3                 = 0x00000021,
21696IH_PERF_SEL_RB0_FULL_VF4                 = 0x00000022,
21697IH_PERF_SEL_RB0_FULL_VF5                 = 0x00000023,
21698IH_PERF_SEL_RB0_FULL_VF6                 = 0x00000024,
21699IH_PERF_SEL_RB0_FULL_VF7                 = 0x00000025,
21700IH_PERF_SEL_RB0_FULL_VF8                 = 0x00000026,
21701IH_PERF_SEL_RB0_FULL_VF9                 = 0x00000027,
21702IH_PERF_SEL_RB0_FULL_VF10                = 0x00000028,
21703IH_PERF_SEL_RB0_FULL_VF11                = 0x00000029,
21704IH_PERF_SEL_RB0_FULL_VF12                = 0x0000002a,
21705IH_PERF_SEL_RB0_FULL_VF13                = 0x0000002b,
21706IH_PERF_SEL_RB0_FULL_VF14                = 0x0000002c,
21707IH_PERF_SEL_RB0_FULL_VF15                = 0x0000002d,
21708IH_PERF_SEL_RB0_OVERFLOW_VF0             = 0x0000002e,
21709IH_PERF_SEL_RB0_OVERFLOW_VF1             = 0x0000002f,
21710IH_PERF_SEL_RB0_OVERFLOW_VF2             = 0x00000030,
21711IH_PERF_SEL_RB0_OVERFLOW_VF3             = 0x00000031,
21712IH_PERF_SEL_RB0_OVERFLOW_VF4             = 0x00000032,
21713IH_PERF_SEL_RB0_OVERFLOW_VF5             = 0x00000033,
21714IH_PERF_SEL_RB0_OVERFLOW_VF6             = 0x00000034,
21715IH_PERF_SEL_RB0_OVERFLOW_VF7             = 0x00000035,
21716IH_PERF_SEL_RB0_OVERFLOW_VF8             = 0x00000036,
21717IH_PERF_SEL_RB0_OVERFLOW_VF9             = 0x00000037,
21718IH_PERF_SEL_RB0_OVERFLOW_VF10            = 0x00000038,
21719IH_PERF_SEL_RB0_OVERFLOW_VF11            = 0x00000039,
21720IH_PERF_SEL_RB0_OVERFLOW_VF12            = 0x0000003a,
21721IH_PERF_SEL_RB0_OVERFLOW_VF13            = 0x0000003b,
21722IH_PERF_SEL_RB0_OVERFLOW_VF14            = 0x0000003c,
21723IH_PERF_SEL_RB0_OVERFLOW_VF15            = 0x0000003d,
21724IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0       = 0x0000003e,
21725IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1       = 0x0000003f,
21726IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2       = 0x00000040,
21727IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3       = 0x00000041,
21728IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4       = 0x00000042,
21729IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5       = 0x00000043,
21730IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6       = 0x00000044,
21731IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7       = 0x00000045,
21732IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8       = 0x00000046,
21733IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9       = 0x00000047,
21734IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10      = 0x00000048,
21735IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11      = 0x00000049,
21736IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12      = 0x0000004a,
21737IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13      = 0x0000004b,
21738IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14      = 0x0000004c,
21739IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15      = 0x0000004d,
21740IH_PERF_SEL_RB0_WPTR_WRAP_VF0            = 0x0000004e,
21741IH_PERF_SEL_RB0_WPTR_WRAP_VF1            = 0x0000004f,
21742IH_PERF_SEL_RB0_WPTR_WRAP_VF2            = 0x00000050,
21743IH_PERF_SEL_RB0_WPTR_WRAP_VF3            = 0x00000051,
21744IH_PERF_SEL_RB0_WPTR_WRAP_VF4            = 0x00000052,
21745IH_PERF_SEL_RB0_WPTR_WRAP_VF5            = 0x00000053,
21746IH_PERF_SEL_RB0_WPTR_WRAP_VF6            = 0x00000054,
21747IH_PERF_SEL_RB0_WPTR_WRAP_VF7            = 0x00000055,
21748IH_PERF_SEL_RB0_WPTR_WRAP_VF8            = 0x00000056,
21749IH_PERF_SEL_RB0_WPTR_WRAP_VF9            = 0x00000057,
21750IH_PERF_SEL_RB0_WPTR_WRAP_VF10           = 0x00000058,
21751IH_PERF_SEL_RB0_WPTR_WRAP_VF11           = 0x00000059,
21752IH_PERF_SEL_RB0_WPTR_WRAP_VF12           = 0x0000005a,
21753IH_PERF_SEL_RB0_WPTR_WRAP_VF13           = 0x0000005b,
21754IH_PERF_SEL_RB0_WPTR_WRAP_VF14           = 0x0000005c,
21755IH_PERF_SEL_RB0_WPTR_WRAP_VF15           = 0x0000005d,
21756IH_PERF_SEL_RB0_RPTR_WRAP_VF0            = 0x0000005e,
21757IH_PERF_SEL_RB0_RPTR_WRAP_VF1            = 0x0000005f,
21758IH_PERF_SEL_RB0_RPTR_WRAP_VF2            = 0x00000060,
21759IH_PERF_SEL_RB0_RPTR_WRAP_VF3            = 0x00000061,
21760IH_PERF_SEL_RB0_RPTR_WRAP_VF4            = 0x00000062,
21761IH_PERF_SEL_RB0_RPTR_WRAP_VF5            = 0x00000063,
21762IH_PERF_SEL_RB0_RPTR_WRAP_VF6            = 0x00000064,
21763IH_PERF_SEL_RB0_RPTR_WRAP_VF7            = 0x00000065,
21764IH_PERF_SEL_RB0_RPTR_WRAP_VF8            = 0x00000066,
21765IH_PERF_SEL_RB0_RPTR_WRAP_VF9            = 0x00000067,
21766IH_PERF_SEL_RB0_RPTR_WRAP_VF10           = 0x00000068,
21767IH_PERF_SEL_RB0_RPTR_WRAP_VF11           = 0x00000069,
21768IH_PERF_SEL_RB0_RPTR_WRAP_VF12           = 0x0000006a,
21769IH_PERF_SEL_RB0_RPTR_WRAP_VF13           = 0x0000006b,
21770IH_PERF_SEL_RB0_RPTR_WRAP_VF14           = 0x0000006c,
21771IH_PERF_SEL_RB0_RPTR_WRAP_VF15           = 0x0000006d,
21772IH_PERF_SEL_BIF_LINE0_RISING_VF0         = 0x0000006e,
21773IH_PERF_SEL_BIF_LINE0_RISING_VF1         = 0x0000006f,
21774IH_PERF_SEL_BIF_LINE0_RISING_VF2         = 0x00000070,
21775IH_PERF_SEL_BIF_LINE0_RISING_VF3         = 0x00000071,
21776IH_PERF_SEL_BIF_LINE0_RISING_VF4         = 0x00000072,
21777IH_PERF_SEL_BIF_LINE0_RISING_VF5         = 0x00000073,
21778IH_PERF_SEL_BIF_LINE0_RISING_VF6         = 0x00000074,
21779IH_PERF_SEL_BIF_LINE0_RISING_VF7         = 0x00000075,
21780IH_PERF_SEL_BIF_LINE0_RISING_VF8         = 0x00000076,
21781IH_PERF_SEL_BIF_LINE0_RISING_VF9         = 0x00000077,
21782IH_PERF_SEL_BIF_LINE0_RISING_VF10        = 0x00000078,
21783IH_PERF_SEL_BIF_LINE0_RISING_VF11        = 0x00000079,
21784IH_PERF_SEL_BIF_LINE0_RISING_VF12        = 0x0000007a,
21785IH_PERF_SEL_BIF_LINE0_RISING_VF13        = 0x0000007b,
21786IH_PERF_SEL_BIF_LINE0_RISING_VF14        = 0x0000007c,
21787IH_PERF_SEL_BIF_LINE0_RISING_VF15        = 0x0000007d,
21788IH_PERF_SEL_BIF_LINE0_FALLING_VF0        = 0x0000007e,
21789IH_PERF_SEL_BIF_LINE0_FALLING_VF1        = 0x0000007f,
21790IH_PERF_SEL_BIF_LINE0_FALLING_VF2        = 0x00000080,
21791IH_PERF_SEL_BIF_LINE0_FALLING_VF3        = 0x00000081,
21792IH_PERF_SEL_BIF_LINE0_FALLING_VF4        = 0x00000082,
21793IH_PERF_SEL_BIF_LINE0_FALLING_VF5        = 0x00000083,
21794IH_PERF_SEL_BIF_LINE0_FALLING_VF6        = 0x00000084,
21795IH_PERF_SEL_BIF_LINE0_FALLING_VF7        = 0x00000085,
21796IH_PERF_SEL_BIF_LINE0_FALLING_VF8        = 0x00000086,
21797IH_PERF_SEL_BIF_LINE0_FALLING_VF9        = 0x00000087,
21798IH_PERF_SEL_BIF_LINE0_FALLING_VF10       = 0x00000088,
21799IH_PERF_SEL_BIF_LINE0_FALLING_VF11       = 0x00000089,
21800IH_PERF_SEL_BIF_LINE0_FALLING_VF12       = 0x0000008a,
21801IH_PERF_SEL_BIF_LINE0_FALLING_VF13       = 0x0000008b,
21802IH_PERF_SEL_BIF_LINE0_FALLING_VF14       = 0x0000008c,
21803IH_PERF_SEL_BIF_LINE0_FALLING_VF15       = 0x0000008d,
21804Reserved142                              = 0x0000008e,
21805Reserved143                              = 0x0000008f,
21806Reserved144                              = 0x00000090,
21807Reserved145                              = 0x00000091,
21808Reserved146                              = 0x00000092,
21809Reserved147                              = 0x00000093,
21810Reserved148                              = 0x00000094,
21811Reserved149                              = 0x00000095,
21812IH_PERF_SEL_CLIENT0_INT                  = 0x00000096,
21813IH_PERF_SEL_CLIENT1_INT                  = 0x00000097,
21814IH_PERF_SEL_CLIENT2_INT                  = 0x00000098,
21815IH_PERF_SEL_CLIENT3_INT                  = 0x00000099,
21816IH_PERF_SEL_CLIENT4_INT                  = 0x0000009a,
21817IH_PERF_SEL_CLIENT5_INT                  = 0x0000009b,
21818IH_PERF_SEL_CLIENT6_INT                  = 0x0000009c,
21819IH_PERF_SEL_CLIENT7_INT                  = 0x0000009d,
21820IH_PERF_SEL_CLIENT8_INT                  = 0x0000009e,
21821IH_PERF_SEL_CLIENT9_INT                  = 0x0000009f,
21822IH_PERF_SEL_CLIENT10_INT                 = 0x000000a0,
21823IH_PERF_SEL_CLIENT11_INT                 = 0x000000a1,
21824IH_PERF_SEL_CLIENT12_INT                 = 0x000000a2,
21825IH_PERF_SEL_CLIENT13_INT                 = 0x000000a3,
21826IH_PERF_SEL_CLIENT14_INT                 = 0x000000a4,
21827IH_PERF_SEL_CLIENT15_INT                 = 0x000000a5,
21828IH_PERF_SEL_CLIENT16_INT                 = 0x000000a6,
21829IH_PERF_SEL_CLIENT17_INT                 = 0x000000a7,
21830IH_PERF_SEL_CLIENT18_INT                 = 0x000000a8,
21831IH_PERF_SEL_CLIENT19_INT                 = 0x000000a9,
21832IH_PERF_SEL_CLIENT20_INT                 = 0x000000aa,
21833IH_PERF_SEL_CLIENT21_INT                 = 0x000000ab,
21834IH_PERF_SEL_CLIENT22_INT                 = 0x000000ac,
21835IH_PERF_SEL_CLIENT23_INT                 = 0x000000ad,
21836IH_PERF_SEL_CLIENT24_INT                 = 0x000000ae,
21837IH_PERF_SEL_CLIENT25_INT                 = 0x000000af,
21838IH_PERF_SEL_CLIENT26_INT                 = 0x000000b0,
21839IH_PERF_SEL_CLIENT27_INT                 = 0x000000b1,
21840IH_PERF_SEL_CLIENT28_INT                 = 0x000000b2,
21841IH_PERF_SEL_CLIENT29_INT                 = 0x000000b3,
21842IH_PERF_SEL_CLIENT30_INT                 = 0x000000b4,
21843IH_PERF_SEL_CLIENT31_INT                 = 0x000000b5,
21844Reserved182                              = 0x000000b6,
21845Reserved183                              = 0x000000b7,
21846Reserved184                              = 0x000000b8,
21847Reserved185                              = 0x000000b9,
21848Reserved186                              = 0x000000ba,
21849Reserved187                              = 0x000000bb,
21850Reserved188                              = 0x000000bc,
21851Reserved189                              = 0x000000bd,
21852Reserved190                              = 0x000000be,
21853Reserved191                              = 0x000000bf,
21854Reserved192                              = 0x000000c0,
21855Reserved193                              = 0x000000c1,
21856Reserved194                              = 0x000000c2,
21857Reserved195                              = 0x000000c3,
21858Reserved196                              = 0x000000c4,
21859Reserved197                              = 0x000000c5,
21860Reserved198                              = 0x000000c6,
21861Reserved199                              = 0x000000c7,
21862Reserved200                              = 0x000000c8,
21863Reserved201                              = 0x000000c9,
21864Reserved202                              = 0x000000ca,
21865Reserved203                              = 0x000000cb,
21866Reserved204                              = 0x000000cc,
21867Reserved205                              = 0x000000cd,
21868Reserved206                              = 0x000000ce,
21869Reserved207                              = 0x000000cf,
21870Reserved208                              = 0x000000d0,
21871Reserved209                              = 0x000000d1,
21872Reserved210                              = 0x000000d2,
21873Reserved211                              = 0x000000d3,
21874Reserved212                              = 0x000000d4,
21875Reserved213                              = 0x000000d5,
21876Reserved214                              = 0x000000d6,
21877Reserved215                              = 0x000000d7,
21878Reserved216                              = 0x000000d8,
21879Reserved217                              = 0x000000d9,
21880Reserved218                              = 0x000000da,
21881Reserved219                              = 0x000000db,
21882IH_PERF_SEL_RB1_FULL_VF0                 = 0x000000dc,
21883IH_PERF_SEL_RB1_FULL_VF1                 = 0x000000dd,
21884IH_PERF_SEL_RB1_FULL_VF2                 = 0x000000de,
21885IH_PERF_SEL_RB1_FULL_VF3                 = 0x000000df,
21886IH_PERF_SEL_RB1_FULL_VF4                 = 0x000000e0,
21887IH_PERF_SEL_RB1_FULL_VF5                 = 0x000000e1,
21888IH_PERF_SEL_RB1_FULL_VF6                 = 0x000000e2,
21889IH_PERF_SEL_RB1_FULL_VF7                 = 0x000000e3,
21890IH_PERF_SEL_RB1_FULL_VF8                 = 0x000000e4,
21891IH_PERF_SEL_RB1_FULL_VF9                 = 0x000000e5,
21892IH_PERF_SEL_RB1_FULL_VF10                = 0x000000e6,
21893IH_PERF_SEL_RB1_FULL_VF11                = 0x000000e7,
21894IH_PERF_SEL_RB1_FULL_VF12                = 0x000000e8,
21895IH_PERF_SEL_RB1_FULL_VF13                = 0x000000e9,
21896IH_PERF_SEL_RB1_FULL_VF14                = 0x000000ea,
21897IH_PERF_SEL_RB1_FULL_VF15                = 0x000000eb,
21898IH_PERF_SEL_RB1_OVERFLOW_VF0             = 0x000000ec,
21899IH_PERF_SEL_RB1_OVERFLOW_VF1             = 0x000000ed,
21900IH_PERF_SEL_RB1_OVERFLOW_VF2             = 0x000000ee,
21901IH_PERF_SEL_RB1_OVERFLOW_VF3             = 0x000000ef,
21902IH_PERF_SEL_RB1_OVERFLOW_VF4             = 0x000000f0,
21903IH_PERF_SEL_RB1_OVERFLOW_VF5             = 0x000000f1,
21904IH_PERF_SEL_RB1_OVERFLOW_VF6             = 0x000000f2,
21905IH_PERF_SEL_RB1_OVERFLOW_VF7             = 0x000000f3,
21906IH_PERF_SEL_RB1_OVERFLOW_VF8             = 0x000000f4,
21907IH_PERF_SEL_RB1_OVERFLOW_VF9             = 0x000000f5,
21908IH_PERF_SEL_RB1_OVERFLOW_VF10            = 0x000000f6,
21909IH_PERF_SEL_RB1_OVERFLOW_VF11            = 0x000000f7,
21910IH_PERF_SEL_RB1_OVERFLOW_VF12            = 0x000000f8,
21911IH_PERF_SEL_RB1_OVERFLOW_VF13            = 0x000000f9,
21912IH_PERF_SEL_RB1_OVERFLOW_VF14            = 0x000000fa,
21913IH_PERF_SEL_RB1_OVERFLOW_VF15            = 0x000000fb,
21914Reserved252                              = 0x000000fc,
21915Reserved253                              = 0x000000fd,
21916Reserved254                              = 0x000000fe,
21917Reserved255                              = 0x000000ff,
21918Reserved256                              = 0x00000100,
21919Reserved257                              = 0x00000101,
21920Reserved258                              = 0x00000102,
21921Reserved259                              = 0x00000103,
21922Reserved260                              = 0x00000104,
21923Reserved261                              = 0x00000105,
21924Reserved262                              = 0x00000106,
21925Reserved263                              = 0x00000107,
21926Reserved264                              = 0x00000108,
21927Reserved265                              = 0x00000109,
21928Reserved266                              = 0x0000010a,
21929Reserved267                              = 0x0000010b,
21930IH_PERF_SEL_RB1_WPTR_WRAP_VF0            = 0x0000010c,
21931IH_PERF_SEL_RB1_WPTR_WRAP_VF1            = 0x0000010d,
21932IH_PERF_SEL_RB1_WPTR_WRAP_VF2            = 0x0000010e,
21933IH_PERF_SEL_RB1_WPTR_WRAP_VF3            = 0x0000010f,
21934IH_PERF_SEL_RB1_WPTR_WRAP_VF4            = 0x00000110,
21935IH_PERF_SEL_RB1_WPTR_WRAP_VF5            = 0x00000111,
21936IH_PERF_SEL_RB1_WPTR_WRAP_VF6            = 0x00000112,
21937IH_PERF_SEL_RB1_WPTR_WRAP_VF7            = 0x00000113,
21938IH_PERF_SEL_RB1_WPTR_WRAP_VF8            = 0x00000114,
21939IH_PERF_SEL_RB1_WPTR_WRAP_VF9            = 0x00000115,
21940IH_PERF_SEL_RB1_WPTR_WRAP_VF10           = 0x00000116,
21941IH_PERF_SEL_RB1_WPTR_WRAP_VF11           = 0x00000117,
21942IH_PERF_SEL_RB1_WPTR_WRAP_VF12           = 0x00000118,
21943IH_PERF_SEL_RB1_WPTR_WRAP_VF13           = 0x00000119,
21944IH_PERF_SEL_RB1_WPTR_WRAP_VF14           = 0x0000011a,
21945IH_PERF_SEL_RB1_WPTR_WRAP_VF15           = 0x0000011b,
21946IH_PERF_SEL_RB1_RPTR_WRAP_VF0            = 0x0000011c,
21947IH_PERF_SEL_RB1_RPTR_WRAP_VF1            = 0x0000011d,
21948IH_PERF_SEL_RB1_RPTR_WRAP_VF2            = 0x0000011e,
21949IH_PERF_SEL_RB1_RPTR_WRAP_VF3            = 0x0000011f,
21950IH_PERF_SEL_RB1_RPTR_WRAP_VF4            = 0x00000120,
21951IH_PERF_SEL_RB1_RPTR_WRAP_VF5            = 0x00000121,
21952IH_PERF_SEL_RB1_RPTR_WRAP_VF6            = 0x00000122,
21953IH_PERF_SEL_RB1_RPTR_WRAP_VF7            = 0x00000123,
21954IH_PERF_SEL_RB1_RPTR_WRAP_VF8            = 0x00000124,
21955IH_PERF_SEL_RB1_RPTR_WRAP_VF9            = 0x00000125,
21956IH_PERF_SEL_RB1_RPTR_WRAP_VF10           = 0x00000126,
21957IH_PERF_SEL_RB1_RPTR_WRAP_VF11           = 0x00000127,
21958IH_PERF_SEL_RB1_RPTR_WRAP_VF12           = 0x00000128,
21959IH_PERF_SEL_RB1_RPTR_WRAP_VF13           = 0x00000129,
21960IH_PERF_SEL_RB1_RPTR_WRAP_VF14           = 0x0000012a,
21961IH_PERF_SEL_RB1_RPTR_WRAP_VF15           = 0x0000012b,
21962Reserved300                              = 0x0000012c,
21963Reserved301                              = 0x0000012d,
21964Reserved302                              = 0x0000012e,
21965Reserved303                              = 0x0000012f,
21966Reserved304                              = 0x00000130,
21967Reserved305                              = 0x00000131,
21968Reserved306                              = 0x00000132,
21969Reserved307                              = 0x00000133,
21970Reserved308                              = 0x00000134,
21971Reserved309                              = 0x00000135,
21972Reserved310                              = 0x00000136,
21973Reserved311                              = 0x00000137,
21974Reserved312                              = 0x00000138,
21975Reserved313                              = 0x00000139,
21976Reserved314                              = 0x0000013a,
21977Reserved315                              = 0x0000013b,
21978Reserved316                              = 0x0000013c,
21979Reserved317                              = 0x0000013d,
21980Reserved318                              = 0x0000013e,
21981Reserved319                              = 0x0000013f,
21982Reserved320                              = 0x00000140,
21983Reserved321                              = 0x00000141,
21984Reserved322                              = 0x00000142,
21985Reserved323                              = 0x00000143,
21986Reserved324                              = 0x00000144,
21987Reserved325                              = 0x00000145,
21988Reserved326                              = 0x00000146,
21989Reserved327                              = 0x00000147,
21990Reserved328                              = 0x00000148,
21991Reserved329                              = 0x00000149,
21992Reserved330                              = 0x0000014a,
21993Reserved331                              = 0x0000014b,
21994IH_PERF_SEL_RB2_FULL_VF0                 = 0x0000014c,
21995IH_PERF_SEL_RB2_FULL_VF1                 = 0x0000014d,
21996IH_PERF_SEL_RB2_FULL_VF2                 = 0x0000014e,
21997IH_PERF_SEL_RB2_FULL_VF3                 = 0x0000014f,
21998IH_PERF_SEL_RB2_FULL_VF4                 = 0x00000150,
21999IH_PERF_SEL_RB2_FULL_VF5                 = 0x00000151,
22000IH_PERF_SEL_RB2_FULL_VF6                 = 0x00000152,

22001IH_PERF_SEL_RB2_FULL_VF7                 = 0x00000153,
22002IH_PERF_SEL_RB2_FULL_VF8                 = 0x00000154,
22003IH_PERF_SEL_RB2_FULL_VF9                 = 0x00000155,
22004IH_PERF_SEL_RB2_FULL_VF10                = 0x00000156,
22005IH_PERF_SEL_RB2_FULL_VF11                = 0x00000157,
22006IH_PERF_SEL_RB2_FULL_VF12                = 0x00000158,
22007IH_PERF_SEL_RB2_FULL_VF13                = 0x00000159,
22008IH_PERF_SEL_RB2_FULL_VF14                = 0x0000015a,
22009IH_PERF_SEL_RB2_FULL_VF15                = 0x0000015b,
22010IH_PERF_SEL_RB2_OVERFLOW_VF0             = 0x0000015c,
22011IH_PERF_SEL_RB2_OVERFLOW_VF1             = 0x0000015d,
22012IH_PERF_SEL_RB2_OVERFLOW_VF2             = 0x0000015e,
22013IH_PERF_SEL_RB2_OVERFLOW_VF3             = 0x0000015f,
22014IH_PERF_SEL_RB2_OVERFLOW_VF4             = 0x00000160,
22015IH_PERF_SEL_RB2_OVERFLOW_VF5             = 0x00000161,
22016IH_PERF_SEL_RB2_OVERFLOW_VF6             = 0x00000162,
22017IH_PERF_SEL_RB2_OVERFLOW_VF7             = 0x00000163,
22018IH_PERF_SEL_RB2_OVERFLOW_VF8             = 0x00000164,
22019IH_PERF_SEL_RB2_OVERFLOW_VF9             = 0x00000165,
22020IH_PERF_SEL_RB2_OVERFLOW_VF10            = 0x00000166,
22021IH_PERF_SEL_RB2_OVERFLOW_VF11            = 0x00000167,
22022IH_PERF_SEL_RB2_OVERFLOW_VF12            = 0x00000168,
22023IH_PERF_SEL_RB2_OVERFLOW_VF13            = 0x00000169,
22024IH_PERF_SEL_RB2_OVERFLOW_VF14            = 0x0000016a,
22025IH_PERF_SEL_RB2_OVERFLOW_VF15            = 0x0000016b,
22026Reserved364                              = 0x0000016c,
22027Reserved365                              = 0x0000016d,
22028Reserved366                              = 0x0000016e,
22029Reserved367                              = 0x0000016f,
22030Reserved368                              = 0x00000170,
22031Reserved369                              = 0x00000171,
22032Reserved370                              = 0x00000172,
22033Reserved371                              = 0x00000173,
22034Reserved372                              = 0x00000174,
22035Reserved373                              = 0x00000175,
22036Reserved374                              = 0x00000176,
22037Reserved375                              = 0x00000177,
22038Reserved376                              = 0x00000178,
22039Reserved377                              = 0x00000179,
22040Reserved378                              = 0x0000017a,
22041Reserved379                              = 0x0000017b,
22042IH_PERF_SEL_RB2_WPTR_WRAP_VF0            = 0x0000017c,
22043IH_PERF_SEL_RB2_WPTR_WRAP_VF1            = 0x0000017d,
22044IH_PERF_SEL_RB2_WPTR_WRAP_VF2            = 0x0000017e,
22045IH_PERF_SEL_RB2_WPTR_WRAP_VF3            = 0x0000017f,
22046IH_PERF_SEL_RB2_WPTR_WRAP_VF4            = 0x00000180,
22047IH_PERF_SEL_RB2_WPTR_WRAP_VF5            = 0x00000181,
22048IH_PERF_SEL_RB2_WPTR_WRAP_VF6            = 0x00000182,
22049IH_PERF_SEL_RB2_WPTR_WRAP_VF7            = 0x00000183,
22050IH_PERF_SEL_RB2_WPTR_WRAP_VF8            = 0x00000184,
22051IH_PERF_SEL_RB2_WPTR_WRAP_VF9            = 0x00000185,
22052IH_PERF_SEL_RB2_WPTR_WRAP_VF10           = 0x00000186,
22053IH_PERF_SEL_RB2_WPTR_WRAP_VF11           = 0x00000187,
22054IH_PERF_SEL_RB2_WPTR_WRAP_VF12           = 0x00000188,
22055IH_PERF_SEL_RB2_WPTR_WRAP_VF13           = 0x00000189,
22056IH_PERF_SEL_RB2_WPTR_WRAP_VF14           = 0x0000018a,
22057IH_PERF_SEL_RB2_WPTR_WRAP_VF15           = 0x0000018b,
22058IH_PERF_SEL_RB2_RPTR_WRAP_VF0            = 0x0000018c,
22059IH_PERF_SEL_RB2_RPTR_WRAP_VF1            = 0x0000018d,
22060IH_PERF_SEL_RB2_RPTR_WRAP_VF2            = 0x0000018e,
22061IH_PERF_SEL_RB2_RPTR_WRAP_VF3            = 0x0000018f,
22062IH_PERF_SEL_RB2_RPTR_WRAP_VF4            = 0x00000190,
22063IH_PERF_SEL_RB2_RPTR_WRAP_VF5            = 0x00000191,
22064IH_PERF_SEL_RB2_RPTR_WRAP_VF6            = 0x00000192,
22065IH_PERF_SEL_RB2_RPTR_WRAP_VF7            = 0x00000193,
22066IH_PERF_SEL_RB2_RPTR_WRAP_VF8            = 0x00000194,
22067IH_PERF_SEL_RB2_RPTR_WRAP_VF9            = 0x00000195,
22068IH_PERF_SEL_RB2_RPTR_WRAP_VF10           = 0x00000196,
22069IH_PERF_SEL_RB2_RPTR_WRAP_VF11           = 0x00000197,
22070IH_PERF_SEL_RB2_RPTR_WRAP_VF12           = 0x00000198,
22071IH_PERF_SEL_RB2_RPTR_WRAP_VF13           = 0x00000199,
22072IH_PERF_SEL_RB2_RPTR_WRAP_VF14           = 0x0000019a,
22073IH_PERF_SEL_RB2_RPTR_WRAP_VF15           = 0x0000019b,
22074Reserved412                              = 0x0000019c,
22075Reserved413                              = 0x0000019d,
22076Reserved414                              = 0x0000019e,
22077Reserved415                              = 0x0000019f,
22078Reserved416                              = 0x000001a0,
22079Reserved417                              = 0x000001a1,
22080Reserved418                              = 0x000001a2,
22081Reserved419                              = 0x000001a3,
22082Reserved420                              = 0x000001a4,
22083Reserved421                              = 0x000001a5,
22084Reserved422                              = 0x000001a6,
22085Reserved423                              = 0x000001a7,
22086Reserved424                              = 0x000001a8,
22087Reserved425                              = 0x000001a9,
22088Reserved426                              = 0x000001aa,
22089Reserved427                              = 0x000001ab,
22090Reserved428                              = 0x000001ac,
22091Reserved429                              = 0x000001ad,
22092Reserved430                              = 0x000001ae,
22093Reserved431                              = 0x000001af,
22094Reserved432                              = 0x000001b0,
22095Reserved433                              = 0x000001b1,
22096Reserved434                              = 0x000001b2,
22097Reserved435                              = 0x000001b3,
22098Reserved436                              = 0x000001b4,
22099Reserved437                              = 0x000001b5,
22100Reserved438                              = 0x000001b6,
22101Reserved439                              = 0x000001b7,
22102Reserved440                              = 0x000001b8,
22103Reserved441                              = 0x000001b9,
22104Reserved442                              = 0x000001ba,
22105Reserved443                              = 0x000001bb,
22106Reserved444                              = 0x000001bc,
22107Reserved445                              = 0x000001bd,
22108Reserved446                              = 0x000001be,
22109Reserved447                              = 0x000001bf,
22110Reserved448                              = 0x000001c0,
22111Reserved449                              = 0x000001c1,
22112Reserved450                              = 0x000001c2,
22113Reserved451                              = 0x000001c3,
22114Reserved452                              = 0x000001c4,
22115Reserved453                              = 0x000001c5,
22116Reserved454                              = 0x000001c6,
22117Reserved455                              = 0x000001c7,
22118Reserved456                              = 0x000001c8,
22119Reserved457                              = 0x000001c9,
22120Reserved458                              = 0x000001ca,
22121Reserved459                              = 0x000001cb,
22122Reserved460                              = 0x000001cc,
22123Reserved461                              = 0x000001cd,
22124Reserved462                              = 0x000001ce,
22125Reserved463                              = 0x000001cf,
22126Reserved464                              = 0x000001d0,
22127Reserved465                              = 0x000001d1,
22128Reserved466                              = 0x000001d2,
22129Reserved467                              = 0x000001d3,
22130Reserved468                              = 0x000001d4,
22131Reserved469                              = 0x000001d5,
22132Reserved470                              = 0x000001d6,
22133Reserved471                              = 0x000001d7,
22134Reserved472                              = 0x000001d8,
22135Reserved473                              = 0x000001d9,
22136Reserved474                              = 0x000001da,
22137Reserved475                              = 0x000001db,
22138Reserved476                              = 0x000001dc,
22139Reserved477                              = 0x000001dd,
22140Reserved478                              = 0x000001de,
22141Reserved479                              = 0x000001df,
22142Reserved480                              = 0x000001e0,
22143Reserved481                              = 0x000001e1,
22144Reserved482                              = 0x000001e2,
22145Reserved483                              = 0x000001e3,
22146Reserved484                              = 0x000001e4,
22147Reserved485                              = 0x000001e5,
22148Reserved486                              = 0x000001e6,
22149Reserved487                              = 0x000001e7,
22150Reserved488                              = 0x000001e8,
22151Reserved489                              = 0x000001e9,
22152Reserved490                              = 0x000001ea,
22153Reserved491                              = 0x000001eb,
22154Reserved492                              = 0x000001ec,
22155Reserved493                              = 0x000001ed,
22156Reserved494                              = 0x000001ee,
22157Reserved495                              = 0x000001ef,
22158Reserved496                              = 0x000001f0,
22159Reserved497                              = 0x000001f1,
22160Reserved498                              = 0x000001f2,
22161Reserved499                              = 0x000001f3,
22162Reserved500                              = 0x000001f4,
22163Reserved501                              = 0x000001f5,
22164Reserved502                              = 0x000001f6,
22165Reserved503                              = 0x000001f7,
22166Reserved504                              = 0x000001f8,
22167Reserved505                              = 0x000001f9,
22168Reserved506                              = 0x000001fa,
22169Reserved507                              = 0x000001fb,
22170Reserved508                              = 0x000001fc,
22171Reserved509                              = 0x000001fd,
22172Reserved510                              = 0x000001fe,
22173Reserved511                              = 0x000001ff,
22174} IH_PERF_SEL;
22175
22176/*******************************************************
22177 * SEM Enums
22178 *******************************************************/
22179
22180/*
22181 * SEM_PERF_SEL enum
22182 */
22183
22184typedef enum SEM_PERF_SEL {
22185SEM_PERF_SEL_CYCLE                       = 0x00000000,
22186SEM_PERF_SEL_IDLE                        = 0x00000001,
22187SEM_PERF_SEL_SDMA0_REQ_SIGNAL            = 0x00000002,
22188SEM_PERF_SEL_SDMA1_REQ_SIGNAL            = 0x00000003,
22189SEM_PERF_SEL_UVD_REQ_SIGNAL              = 0x00000004,
22190SEM_PERF_SEL_VCE0_REQ_SIGNAL             = 0x00000005,
22191SEM_PERF_SEL_ACP_REQ_SIGNAL              = 0x00000006,
22192SEM_PERF_SEL_ISP_REQ_SIGNAL              = 0x00000007,
22193SEM_PERF_SEL_VCE1_REQ_SIGNAL             = 0x00000008,
22194SEM_PERF_SEL_VP8_REQ_SIGNAL              = 0x00000009,
22195SEM_PERF_SEL_CPG_E0_REQ_SIGNAL           = 0x0000000a,
22196SEM_PERF_SEL_CPG_E1_REQ_SIGNAL           = 0x0000000b,
22197SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL     = 0x0000000c,
22198SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL     = 0x0000000d,
22199SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL     = 0x0000000e,
22200SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL     = 0x0000000f,
22201SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL     = 0x00000010,
22202SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL     = 0x00000011,
22203SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL     = 0x00000012,
22204SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL     = 0x00000013,
22205SEM_PERF_SEL_SDMA0_REQ_WAIT              = 0x00000014,
22206SEM_PERF_SEL_SDMA1_REQ_WAIT              = 0x00000015,
22207SEM_PERF_SEL_UVD_REQ_WAIT                = 0x00000016,
22208SEM_PERF_SEL_VCE0_REQ_WAIT               = 0x00000017,
22209SEM_PERF_SEL_ACP_REQ_WAIT                = 0x00000018,
22210SEM_PERF_SEL_ISP_REQ_WAIT                = 0x00000019,
22211SEM_PERF_SEL_VCE1_REQ_WAIT               = 0x0000001a,
22212SEM_PERF_SEL_VP8_REQ_WAIT                = 0x0000001b,
22213SEM_PERF_SEL_CPG_E0_REQ_WAIT             = 0x0000001c,
22214SEM_PERF_SEL_CPG_E1_REQ_WAIT             = 0x0000001d,
22215SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT       = 0x0000001e,
22216SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT       = 0x0000001f,
22217SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT       = 0x00000020,
22218SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT       = 0x00000021,
22219SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT       = 0x00000022,
22220SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT       = 0x00000023,
22221SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT       = 0x00000024,
22222SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT       = 0x00000025,
22223SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT       = 0x00000026,
22224SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT       = 0x00000027,
22225SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT       = 0x00000028,
22226SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT       = 0x00000029,
22227SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT       = 0x0000002a,
22228SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT       = 0x0000002b,
22229SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT       = 0x0000002c,
22230SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT       = 0x0000002d,
22231SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT       = 0x0000002e,
22232SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT       = 0x0000002f,
22233SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT      = 0x00000030,
22234SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT      = 0x00000031,
22235SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT      = 0x00000032,
22236SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT      = 0x00000033,
22237SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT      = 0x00000034,
22238SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT      = 0x00000035,
22239SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT      = 0x00000036,
22240SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT      = 0x00000037,
22241SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT      = 0x00000038,
22242SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT      = 0x00000039,
22243SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT      = 0x0000003a,
22244SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT      = 0x0000003b,
22245SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT      = 0x0000003c,
22246SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT      = 0x0000003d,
22247SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT      = 0x0000003e,
22248SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT      = 0x0000003f,
22249SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT      = 0x00000040,
22250SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT      = 0x00000041,
22251SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT      = 0x00000042,
22252SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT      = 0x00000043,
22253SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT      = 0x00000044,
22254SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT      = 0x00000045,
22255SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT       = 0x00000046,
22256SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT       = 0x00000047,
22257SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT       = 0x00000048,
22258SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT       = 0x00000049,
22259SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT       = 0x0000004a,
22260SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT       = 0x0000004b,
22261SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT       = 0x0000004c,
22262SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT       = 0x0000004d,
22263SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT       = 0x0000004e,
22264SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT       = 0x0000004f,
22265SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT      = 0x00000050,
22266SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT      = 0x00000051,
22267SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT      = 0x00000052,
22268SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT      = 0x00000053,
22269SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT      = 0x00000054,
22270SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT      = 0x00000055,
22271SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT      = 0x00000056,
22272SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT      = 0x00000057,
22273SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT      = 0x00000058,
22274SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT      = 0x00000059,
22275SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT      = 0x0000005a,
22276SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT      = 0x0000005b,
22277SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT      = 0x0000005c,
22278SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT      = 0x0000005d,
22279SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT      = 0x0000005e,
22280SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT      = 0x0000005f,
22281SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT      = 0x00000060,
22282SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT      = 0x00000061,
22283SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT      = 0x00000062,
22284SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT      = 0x00000063,
22285SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT      = 0x00000064,
22286SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT      = 0x00000065,
22287SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT      = 0x00000066,
22288SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT      = 0x00000067,
22289SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT      = 0x00000068,
22290SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT      = 0x00000069,
22291SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT      = 0x0000006a,
22292SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT      = 0x0000006b,
22293SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT      = 0x0000006c,
22294SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT      = 0x0000006d,
22295SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT      = 0x0000006e,
22296SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT      = 0x0000006f,
22297SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT     = 0x00000070,
22298SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT     = 0x00000071,
22299SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT     = 0x00000072,
22300SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT     = 0x00000073,
22301SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT     = 0x00000074,
22302SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT     = 0x00000075,
22303SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT     = 0x00000076,
22304SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT     = 0x00000077,
22305SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT     = 0x00000078,
22306SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT     = 0x00000079,
22307SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT     = 0x0000007a,
22308SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT     = 0x0000007b,
22309SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT     = 0x0000007c,
22310SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT     = 0x0000007d,
22311SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT     = 0x0000007e,
22312SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT     = 0x0000007f,
22313SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT     = 0x00000080,
22314SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT     = 0x00000081,
22315SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT     = 0x00000082,
22316SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT     = 0x00000083,
22317SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT     = 0x00000084,
22318SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT     = 0x00000085,
22319SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT      = 0x00000086,
22320SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT      = 0x00000087,
22321SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT      = 0x00000088,
22322SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT      = 0x00000089,
22323SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT      = 0x0000008a,
22324SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT      = 0x0000008b,
22325SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT      = 0x0000008c,
22326SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT      = 0x0000008d,
22327SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT      = 0x0000008e,
22328SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT      = 0x0000008f,
22329SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT     = 0x00000090,
22330SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT     = 0x00000091,
22331SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT     = 0x00000092,
22332SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT     = 0x00000093,
22333SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT     = 0x00000094,
22334SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT     = 0x00000095,
22335SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT     = 0x00000096,
22336SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT     = 0x00000097,
22337SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT     = 0x00000098,
22338SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT     = 0x00000099,
22339SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT     = 0x0000009a,
22340SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT     = 0x0000009b,
22341SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT     = 0x0000009c,
22342SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT     = 0x0000009d,
22343SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT     = 0x0000009e,
22344SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT     = 0x0000009f,
22345SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT     = 0x000000a0,
22346SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT     = 0x000000a1,
22347SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT     = 0x000000a2,
22348SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT     = 0x000000a3,
22349SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT     = 0x000000a4,
22350SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT     = 0x000000a5,
22351SEM_PERF_SEL_MC_RD_REQ                   = 0x000000a6,
22352SEM_PERF_SEL_MC_RD_RET                   = 0x000000a7,
22353SEM_PERF_SEL_MC_WR_REQ                   = 0x000000a8,
22354SEM_PERF_SEL_MC_WR_RET                   = 0x000000a9,
22355SEM_PERF_SEL_ATC_REQ                     = 0x000000aa,
22356SEM_PERF_SEL_ATC_RET                     = 0x000000ab,
22357SEM_PERF_SEL_ATC_XNACK                   = 0x000000ac,
22358SEM_PERF_SEL_ATC_INVALIDATION            = 0x000000ad,
22359} SEM_PERF_SEL;
22360
22361/*******************************************************
22362 * SDMA Enums
22363 *******************************************************/
22364
22365/*
22366 * SDMA_PERF_SEL enum
22367 */
22368
22369typedef enum SDMA_PERF_SEL {
22370SDMA_PERF_SEL_CYCLE                      = 0x00000000,
22371SDMA_PERF_SEL_IDLE                       = 0x00000001,
22372SDMA_PERF_SEL_REG_IDLE                   = 0x00000002,
22373SDMA_PERF_SEL_RB_EMPTY                   = 0x00000003,
22374SDMA_PERF_SEL_RB_FULL                    = 0x00000004,
22375SDMA_PERF_SEL_RB_WPTR_WRAP               = 0x00000005,
22376SDMA_PERF_SEL_RB_RPTR_WRAP               = 0x00000006,
22377SDMA_PERF_SEL_RB_WPTR_POLL_READ          = 0x00000007,
22378SDMA_PERF_SEL_RB_RPTR_WB                 = 0x00000008,
22379SDMA_PERF_SEL_RB_CMD_IDLE                = 0x00000009,
22380SDMA_PERF_SEL_RB_CMD_FULL                = 0x0000000a,
22381SDMA_PERF_SEL_IB_CMD_IDLE                = 0x0000000b,
22382SDMA_PERF_SEL_IB_CMD_FULL                = 0x0000000c,
22383SDMA_PERF_SEL_EX_IDLE                    = 0x0000000d,
22384SDMA_PERF_SEL_SRBM_REG_SEND              = 0x0000000e,
22385SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE  = 0x0000000f,
22386SDMA_PERF_SEL_MC_WR_IDLE                 = 0x00000010,
22387SDMA_PERF_SEL_MC_WR_COUNT                = 0x00000011,
22388SDMA_PERF_SEL_MC_RD_IDLE                 = 0x00000012,
22389SDMA_PERF_SEL_MC_RD_COUNT                = 0x00000013,
22390SDMA_PERF_SEL_MC_RD_RET_STALL            = 0x00000014,
22391SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE         = 0x00000015,
22392SDMA_PERF_SEL_SEM_IDLE                   = 0x00000018,
22393SDMA_PERF_SEL_SEM_REQ_STALL              = 0x00000019,
22394SDMA_PERF_SEL_SEM_REQ_COUNT              = 0x0000001a,
22395SDMA_PERF_SEL_SEM_RESP_INCOMPLETE        = 0x0000001b,
22396SDMA_PERF_SEL_SEM_RESP_FAIL              = 0x0000001c,
22397SDMA_PERF_SEL_SEM_RESP_PASS              = 0x0000001d,
22398SDMA_PERF_SEL_INT_IDLE                   = 0x0000001e,
22399SDMA_PERF_SEL_INT_REQ_STALL              = 0x0000001f,
22400SDMA_PERF_SEL_INT_REQ_COUNT              = 0x00000020,
22401SDMA_PERF_SEL_INT_RESP_ACCEPTED          = 0x00000021,
22402SDMA_PERF_SEL_INT_RESP_RETRY             = 0x00000022,
22403SDMA_PERF_SEL_NUM_PACKET                 = 0x00000023,
22404SDMA_PERF_SEL_CE_WREQ_IDLE               = 0x00000025,
22405SDMA_PERF_SEL_CE_WR_IDLE                 = 0x00000026,
22406SDMA_PERF_SEL_CE_SPLIT_IDLE              = 0x00000027,
22407SDMA_PERF_SEL_CE_RREQ_IDLE               = 0x00000028,
22408SDMA_PERF_SEL_CE_OUT_IDLE                = 0x00000029,
22409SDMA_PERF_SEL_CE_IN_IDLE                 = 0x0000002a,
22410SDMA_PERF_SEL_CE_DST_IDLE                = 0x0000002b,
22411SDMA_PERF_SEL_CE_AFIFO_FULL              = 0x0000002e,
22412SDMA_PERF_SEL_CE_INFO_FULL               = 0x00000031,
22413SDMA_PERF_SEL_CE_INFO1_FULL              = 0x00000032,
22414SDMA_PERF_SEL_CE_RD_STALL                = 0x00000033,
22415SDMA_PERF_SEL_CE_WR_STALL                = 0x00000034,
22416SDMA_PERF_SEL_GFX_SELECT                 = 0x00000035,
22417SDMA_PERF_SEL_RLC0_SELECT                = 0x00000036,
22418SDMA_PERF_SEL_RLC1_SELECT                = 0x00000037,
22419SDMA_PERF_SEL_PAGE_SELECT                = 0x00000038,
22420SDMA_PERF_SEL_CTX_CHANGE                 = 0x00000039,
22421SDMA_PERF_SEL_CTX_CHANGE_EXPIRED         = 0x0000003a,
22422SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION       = 0x0000003b,
22423SDMA_PERF_SEL_DOORBELL                   = 0x0000003c,
22424SDMA_PERF_SEL_RD_BA_RTR                  = 0x0000003d,
22425SDMA_PERF_SEL_WR_BA_RTR                  = 0x0000003e,
22426SDMA_PERF_SEL_F32_L1_WR_VLD              = 0x0000003f,
22427SDMA_PERF_SEL_CE_L1_WR_VLD               = 0x00000040,
22428SDMA_PERF_SEL_CE_L1_STALL                = 0x00000041,
22429SDMA_PERF_SEL_SDMA_INVACK_NFLUSH         = 0x00000042,
22430SDMA_PERF_SEL_SDMA_INVACK_FLUSH          = 0x00000043,
22431SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH        = 0x00000044,
22432SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH         = 0x00000045,
22433SDMA_PERF_SEL_ATCL2_RET_XNACK            = 0x00000046,
22434SDMA_PERF_SEL_ATCL2_RET_ACK              = 0x00000047,
22435SDMA_PERF_SEL_ATCL2_FREE                 = 0x00000048,
22436SDMA_PERF_SEL_SDMA_ATCL2_SEND            = 0x00000049,
22437SDMA_PERF_SEL_DMA_L1_WR_SEND             = 0x0000004a,
22438SDMA_PERF_SEL_DMA_L1_RD_SEND             = 0x0000004b,
22439SDMA_PERF_SEL_DMA_MC_WR_SEND             = 0x0000004c,
22440SDMA_PERF_SEL_DMA_MC_RD_SEND             = 0x0000004d,
22441SDMA_PERF_SEL_L1_WR_FIFO_IDLE            = 0x0000004e,
22442SDMA_PERF_SEL_L1_RD_FIFO_IDLE            = 0x0000004f,
22443SDMA_PERF_SEL_L1_WRL2_IDLE               = 0x00000050,
22444SDMA_PERF_SEL_L1_RDL2_IDLE               = 0x00000051,
22445SDMA_PERF_SEL_L1_WRMC_IDLE               = 0x00000052,
22446SDMA_PERF_SEL_L1_RDMC_IDLE               = 0x00000053,
22447SDMA_PERF_SEL_L1_WR_INV_IDLE             = 0x00000054,
22448SDMA_PERF_SEL_L1_RD_INV_IDLE             = 0x00000055,
22449SDMA_PERF_SEL_L1_WR_INV_EN               = 0x00000056,
22450SDMA_PERF_SEL_L1_RD_INV_EN               = 0x00000057,
22451SDMA_PERF_SEL_L1_WR_WAIT_INVADR          = 0x00000058,
22452SDMA_PERF_SEL_L1_RD_WAIT_INVADR          = 0x00000059,
22453SDMA_PERF_SEL_IS_INVREQ_ADDR_WR          = 0x0000005a,
22454SDMA_PERF_SEL_IS_INVREQ_ADDR_RD          = 0x0000005b,
22455SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT        = 0x0000005c,
22456SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT        = 0x0000005d,
22457SDMA_PERF_SEL_L1_INV_MIDDLE              = 0x0000005e,
22458SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER    = 0x000000fe,
22459SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER    = 0x000000ff,
22460} SDMA_PERF_SEL;
22461
22462/*******************************************************
22463 * SMUIO Enums
22464 *******************************************************/
22465
22466/*
22467 * ROM_SIGNATURE value
22468 */
22469
22470#define ROM_SIGNATURE                  0x0000aa55
22471
22472/*******************************************************
22473 * XDMA_CMN Enums
22474 *******************************************************/
22475
22476/*
22477 * ENUM_XDMA_LOCAL_SW_MODE enum
22478 */
22479
22480typedef enum ENUM_XDMA_LOCAL_SW_MODE {
22481XDMA_LOCAL_SW_MODE_SW_256B_D             = 0x00000002,
22482XDMA_LOCAL_SW_MODE_SW_64KB_D             = 0x0000000a,
22483XDMA_LOCAL_SW_MODE_SW_64KB_D_X           = 0x0000001a,
22484} ENUM_XDMA_LOCAL_SW_MODE;
22485
22486/*******************************************************
22487 * XDMA_SLV Enums
22488 *******************************************************/
22489
22490/*
22491 * ENUM_XDMA_SLV_ALPHA_POSITION enum
22492 */
22493
22494typedef enum ENUM_XDMA_SLV_ALPHA_POSITION {
22495XDMA_SLV_ALPHA_POSITION_7_0              = 0x00000000,
22496XDMA_SLV_ALPHA_POSITION_15_8             = 0x00000001,
22497XDMA_SLV_ALPHA_POSITION_23_16            = 0x00000002,
22498XDMA_SLV_ALPHA_POSITION_31_24            = 0x00000003,
22499} ENUM_XDMA_SLV_ALPHA_POSITION;
22500
22501/*******************************************************
22502 * XDMA_MSTR Enums
22503 *******************************************************/
22504
22505/*
22506 * ENUM_XDMA_MSTR_ALPHA_POSITION enum
22507 */
22508
22509typedef enum ENUM_XDMA_MSTR_ALPHA_POSITION {
22510XDMA_MSTR_ALPHA_POSITION_7_0             = 0x00000000,
22511XDMA_MSTR_ALPHA_POSITION_15_8            = 0x00000001,
22512XDMA_MSTR_ALPHA_POSITION_23_16           = 0x00000002,
22513XDMA_MSTR_ALPHA_POSITION_31_24           = 0x00000003,
22514} ENUM_XDMA_MSTR_ALPHA_POSITION;
22515
22516/*
22517 * ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL enum
22518 */
22519
22520typedef enum ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL {
22521XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE0      = 0x00000000,
22522XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE1      = 0x00000001,
22523XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE2      = 0x00000002,
22524XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE3      = 0x00000003,
22525XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE4      = 0x00000004,
22526XDMA_MSTR_VSYNC_GSL_CHECK_SEL_PIPE5      = 0x00000005,
22527} ENUM_XDMA_MSTR_VSYNC_GSL_CHECK_SEL;
22528
22529
22530#endif /*_vega10_ENUM_HEADER*/
22531
22532