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23#ifndef _HWMGR_H_
24#define _HWMGR_H_
25
26#include <linux/seq_file.h>
27#include "amd_powerplay.h"
28#include "pp_instance.h"
29#include "hardwaremanager.h"
30#include "pp_power_source.h"
31#include "hwmgr_ppt.h"
32#include "ppatomctrl.h"
33#include "hwmgr_ppt.h"
34#include "power_state.h"
35
36struct pp_instance;
37struct pp_hwmgr;
38struct phm_fan_speed_info;
39struct pp_atomctrl_voltage_table;
40
41#define VOLTAGE_SCALE 4
42
43uint8_t convert_to_vid(uint16_t vddc);
44
45enum DISPLAY_GAP {
46 DISPLAY_GAP_VBLANK_OR_WM = 0,
47 DISPLAY_GAP_VBLANK = 1,
48 DISPLAY_GAP_WATERMARK = 2,
49 DISPLAY_GAP_IGNORE = 3
50};
51typedef enum DISPLAY_GAP DISPLAY_GAP;
52
53struct vi_dpm_level {
54 bool enabled;
55 uint32_t value;
56 uint32_t param1;
57};
58
59struct vi_dpm_table {
60 uint32_t count;
61 struct vi_dpm_level dpm_level[1];
62};
63
64enum PP_Result {
65 PP_Result_TableImmediateExit = 0x13,
66};
67
68#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
69#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
70#define PCIE_PERF_REQ_GEN1 2
71#define PCIE_PERF_REQ_GEN2 3
72#define PCIE_PERF_REQ_GEN3 4
73
74enum PP_FEATURE_MASK {
75 PP_SCLK_DPM_MASK = 0x1,
76 PP_MCLK_DPM_MASK = 0x2,
77 PP_PCIE_DPM_MASK = 0x4,
78 PP_SCLK_DEEP_SLEEP_MASK = 0x8,
79 PP_POWER_CONTAINMENT_MASK = 0x10,
80 PP_UVD_HANDSHAKE_MASK = 0x20,
81 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
82 PP_VBI_TIME_SUPPORT_MASK = 0x80,
83 PP_ULV_MASK = 0x100,
84 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
85 PP_CLOCK_STRETCH_MASK = 0x400,
86 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
87 PP_SOCCLK_DPM_MASK = 0x1000,
88 PP_DCEFCLK_DPM_MASK = 0x2000,
89};
90
91enum PHM_BackEnd_Magic {
92 PHM_Dummy_Magic = 0xAA5555AA,
93 PHM_RV770_Magic = 0xDCBAABCD,
94 PHM_Kong_Magic = 0x239478DF,
95 PHM_NIslands_Magic = 0x736C494E,
96 PHM_Sumo_Magic = 0x8339FA11,
97 PHM_SIslands_Magic = 0x369431AC,
98 PHM_Trinity_Magic = 0x96751873,
99 PHM_CIslands_Magic = 0x38AC78B0,
100 PHM_Kv_Magic = 0xDCBBABC0,
101 PHM_VIslands_Magic = 0x20130307,
102 PHM_Cz_Magic = 0x67DCBA25,
103 PHM_Rv_Magic = 0x20161121
104};
105
106
107#define PHM_PCIE_POWERGATING_TARGET_GFX 0
108#define PHM_PCIE_POWERGATING_TARGET_DDI 1
109#define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2
110#define PHM_PCIE_POWERGATING_TARGET_PHY 3
111
112typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input,
113 void *output, void *storage, int result);
114
115typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr);
116
117struct phm_set_power_state_input {
118 const struct pp_hw_power_state *pcurrent_state;
119 const struct pp_hw_power_state *pnew_state;
120};
121
122struct phm_acp_arbiter {
123 uint32_t acpclk;
124};
125
126struct phm_uvd_arbiter {
127 uint32_t vclk;
128 uint32_t dclk;
129 uint32_t vclk_ceiling;
130 uint32_t dclk_ceiling;
131 uint32_t vclk_soft_min;
132 uint32_t dclk_soft_min;
133};
134
135struct phm_vce_arbiter {
136 uint32_t evclk;
137 uint32_t ecclk;
138};
139
140struct phm_gfx_arbiter {
141 uint32_t sclk;
142 uint32_t sclk_hard_min;
143 uint32_t mclk;
144 uint32_t sclk_over_drive;
145 uint32_t mclk_over_drive;
146 uint32_t sclk_threshold;
147 uint32_t num_cus;
148 uint32_t gfxclk;
149 uint32_t fclk;
150};
151
152
153struct phm_master_table_item {
154 phm_check_function isFunctionNeededInRuntimeTable;
155 phm_table_function tableFunction;
156};
157
158enum phm_master_table_flag {
159 PHM_MasterTableFlag_None = 0,
160 PHM_MasterTableFlag_ExitOnError = 1,
161};
162
163
164struct phm_master_table_header {
165 uint32_t storage_size;
166 uint32_t flags;
167 const struct phm_master_table_item *master_list;
168};
169
170struct phm_runtime_table_header {
171 uint32_t storage_size;
172 bool exit_error;
173 phm_table_function *function_list;
174};
175
176struct phm_clock_array {
177 uint32_t count;
178 uint32_t values[1];
179};
180
181struct phm_clock_voltage_dependency_record {
182 uint32_t clk;
183 uint32_t v;
184};
185
186struct phm_vceclock_voltage_dependency_record {
187 uint32_t ecclk;
188 uint32_t evclk;
189 uint32_t v;
190};
191
192struct phm_uvdclock_voltage_dependency_record {
193 uint32_t vclk;
194 uint32_t dclk;
195 uint32_t v;
196};
197
198struct phm_samuclock_voltage_dependency_record {
199 uint32_t samclk;
200 uint32_t v;
201};
202
203struct phm_acpclock_voltage_dependency_record {
204 uint32_t acpclk;
205 uint32_t v;
206};
207
208struct phm_clock_voltage_dependency_table {
209 uint32_t count;
210 struct phm_clock_voltage_dependency_record entries[1];
211};
212
213struct phm_phase_shedding_limits_record {
214 uint32_t Voltage;
215 uint32_t Sclk;
216 uint32_t Mclk;
217};
218
219
220extern int phm_dispatch_table(struct pp_hwmgr *hwmgr,
221 struct phm_runtime_table_header *rt_table,
222 void *input, void *output);
223
224extern int phm_construct_table(struct pp_hwmgr *hwmgr,
225 const struct phm_master_table_header *master_table,
226 struct phm_runtime_table_header *rt_table);
227
228extern int phm_destroy_table(struct pp_hwmgr *hwmgr,
229 struct phm_runtime_table_header *rt_table);
230
231
232struct phm_uvd_clock_voltage_dependency_record {
233 uint32_t vclk;
234 uint32_t dclk;
235 uint32_t v;
236};
237
238struct phm_uvd_clock_voltage_dependency_table {
239 uint8_t count;
240 struct phm_uvd_clock_voltage_dependency_record entries[1];
241};
242
243struct phm_acp_clock_voltage_dependency_record {
244 uint32_t acpclk;
245 uint32_t v;
246};
247
248struct phm_acp_clock_voltage_dependency_table {
249 uint32_t count;
250 struct phm_acp_clock_voltage_dependency_record entries[1];
251};
252
253struct phm_vce_clock_voltage_dependency_record {
254 uint32_t ecclk;
255 uint32_t evclk;
256 uint32_t v;
257};
258
259struct phm_phase_shedding_limits_table {
260 uint32_t count;
261 struct phm_phase_shedding_limits_record entries[1];
262};
263
264struct phm_vceclock_voltage_dependency_table {
265 uint8_t count;
266 struct phm_vceclock_voltage_dependency_record entries[1];
267};
268
269struct phm_uvdclock_voltage_dependency_table {
270 uint8_t count;
271 struct phm_uvdclock_voltage_dependency_record entries[1];
272};
273
274struct phm_samuclock_voltage_dependency_table {
275 uint8_t count;
276 struct phm_samuclock_voltage_dependency_record entries[1];
277};
278
279struct phm_acpclock_voltage_dependency_table {
280 uint32_t count;
281 struct phm_acpclock_voltage_dependency_record entries[1];
282};
283
284struct phm_vce_clock_voltage_dependency_table {
285 uint8_t count;
286 struct phm_vce_clock_voltage_dependency_record entries[1];
287};
288
289struct pp_hwmgr_func {
290 int (*backend_init)(struct pp_hwmgr *hw_mgr);
291 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
292 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
293 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
294
295 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
296 struct pp_power_state *prequest_ps,
297 const struct pp_power_state *pcurrent_ps);
298
299 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
300 enum amd_dpm_forced_level level);
301
302 int (*dynamic_state_management_enable)(
303 struct pp_hwmgr *hw_mgr);
304 int (*dynamic_state_management_disable)(
305 struct pp_hwmgr *hw_mgr);
306
307 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
308 struct pp_hw_power_state *hw_ps);
309
310 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
311 unsigned long, struct pp_power_state *);
312 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
313 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
314 int (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
315 int (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
316 int (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
317 int (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
318 int (*power_state_set)(struct pp_hwmgr *hwmgr,
319 const void *state);
320 int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
321 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
322 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
323 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
324 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
325 const uint32_t *msg_id);
326 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
327 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
328 int (*get_temperature)(struct pp_hwmgr *hwmgr);
329 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
330 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
331 int (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
332 int (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
333 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
334 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
335 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
336 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
337 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
338 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
339 int (*register_internal_thermal_interrupt)(struct pp_hwmgr *hwmgr,
340 const void *thermal_interrupt_info);
341 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
342 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
343 const struct pp_hw_power_state *pstate1,
344 const struct pp_hw_power_state *pstate2,
345 bool *equal);
346 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
347 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
348 bool cc6_disable, bool pstate_disable,
349 bool pstate_switch_disable);
350 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
351 struct amd_pp_simple_clock_info *info);
352 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
353 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
354 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
355 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
356 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
357 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
358 enum amd_pp_clock_type type,
359 struct pp_clock_levels_with_latency *clocks);
360 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
361 enum amd_pp_clock_type type,
362 struct pp_clock_levels_with_voltage *clocks);
363 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
364 struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
365 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
366 struct pp_display_clock_request *clock);
367 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
368 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
369 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
370 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
371 int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
372 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
373 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
374 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
375 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
376 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
377 int (*set_power_profile_state)(struct pp_hwmgr *hwmgr,
378 struct amd_pp_profile *request);
379 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
380 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
381};
382
383struct pp_table_func {
384 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
385 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
386 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
387 int (*pptable_get_vce_state_table_entry)(
388 struct pp_hwmgr *hwmgr,
389 unsigned long i,
390 struct amd_vce_state *vce_state,
391 void **clock_info,
392 unsigned long *flag);
393};
394
395union phm_cac_leakage_record {
396 struct {
397 uint16_t Vddc;
398 uint32_t Leakage;
399 };
400 struct {
401 uint16_t Vddc1;
402 uint16_t Vddc2;
403 uint16_t Vddc3;
404 };
405};
406
407struct phm_cac_leakage_table {
408 uint32_t count;
409 union phm_cac_leakage_record entries[1];
410};
411
412struct phm_samu_clock_voltage_dependency_record {
413 uint32_t samclk;
414 uint32_t v;
415};
416
417
418struct phm_samu_clock_voltage_dependency_table {
419 uint8_t count;
420 struct phm_samu_clock_voltage_dependency_record entries[1];
421};
422
423struct phm_cac_tdp_table {
424 uint16_t usTDP;
425 uint16_t usConfigurableTDP;
426 uint16_t usTDC;
427 uint16_t usBatteryPowerLimit;
428 uint16_t usSmallPowerLimit;
429 uint16_t usLowCACLeakage;
430 uint16_t usHighCACLeakage;
431 uint16_t usMaximumPowerDeliveryLimit;
432 uint16_t usEDCLimit;
433 uint16_t usOperatingTempMinLimit;
434 uint16_t usOperatingTempMaxLimit;
435 uint16_t usOperatingTempStep;
436 uint16_t usOperatingTempHyst;
437 uint16_t usDefaultTargetOperatingTemp;
438 uint16_t usTargetOperatingTemp;
439 uint16_t usPowerTuneDataSetID;
440 uint16_t usSoftwareShutdownTemp;
441 uint16_t usClockStretchAmount;
442 uint16_t usTemperatureLimitHotspot;
443 uint16_t usTemperatureLimitLiquid1;
444 uint16_t usTemperatureLimitLiquid2;
445 uint16_t usTemperatureLimitVrVddc;
446 uint16_t usTemperatureLimitVrMvdd;
447 uint16_t usTemperatureLimitPlx;
448 uint8_t ucLiquid1_I2C_address;
449 uint8_t ucLiquid2_I2C_address;
450 uint8_t ucLiquid_I2C_Line;
451 uint8_t ucVr_I2C_address;
452 uint8_t ucVr_I2C_Line;
453 uint8_t ucPlx_I2C_address;
454 uint8_t ucPlx_I2C_Line;
455 uint32_t usBoostPowerLimit;
456 uint8_t ucCKS_LDO_REFSEL;
457};
458
459struct phm_tdp_table {
460 uint16_t usTDP;
461 uint16_t usConfigurableTDP;
462 uint16_t usTDC;
463 uint16_t usBatteryPowerLimit;
464 uint16_t usSmallPowerLimit;
465 uint16_t usLowCACLeakage;
466 uint16_t usHighCACLeakage;
467 uint16_t usMaximumPowerDeliveryLimit;
468 uint16_t usEDCLimit;
469 uint16_t usOperatingTempMinLimit;
470 uint16_t usOperatingTempMaxLimit;
471 uint16_t usOperatingTempStep;
472 uint16_t usOperatingTempHyst;
473 uint16_t usDefaultTargetOperatingTemp;
474 uint16_t usTargetOperatingTemp;
475 uint16_t usPowerTuneDataSetID;
476 uint16_t usSoftwareShutdownTemp;
477 uint16_t usClockStretchAmount;
478 uint16_t usTemperatureLimitTedge;
479 uint16_t usTemperatureLimitHotspot;
480 uint16_t usTemperatureLimitLiquid1;
481 uint16_t usTemperatureLimitLiquid2;
482 uint16_t usTemperatureLimitHBM;
483 uint16_t usTemperatureLimitVrVddc;
484 uint16_t usTemperatureLimitVrMvdd;
485 uint16_t usTemperatureLimitPlx;
486 uint8_t ucLiquid1_I2C_address;
487 uint8_t ucLiquid2_I2C_address;
488 uint8_t ucLiquid_I2C_Line;
489 uint8_t ucVr_I2C_address;
490 uint8_t ucVr_I2C_Line;
491 uint8_t ucPlx_I2C_address;
492 uint8_t ucPlx_I2C_Line;
493 uint8_t ucLiquid_I2C_LineSDA;
494 uint8_t ucVr_I2C_LineSDA;
495 uint8_t ucPlx_I2C_LineSDA;
496 uint32_t usBoostPowerLimit;
497 uint16_t usBoostStartTemperature;
498 uint16_t usBoostStopTemperature;
499 uint32_t ulBoostClock;
500};
501
502struct phm_ppm_table {
503 uint8_t ppm_design;
504 uint16_t cpu_core_number;
505 uint32_t platform_tdp;
506 uint32_t small_ac_platform_tdp;
507 uint32_t platform_tdc;
508 uint32_t small_ac_platform_tdc;
509 uint32_t apu_tdp;
510 uint32_t dgpu_tdp;
511 uint32_t dgpu_ulv_power;
512 uint32_t tj_max;
513};
514
515struct phm_vq_budgeting_record {
516 uint32_t ulCUs;
517 uint32_t ulSustainableSOCPowerLimitLow;
518 uint32_t ulSustainableSOCPowerLimitHigh;
519 uint32_t ulMinSclkLow;
520 uint32_t ulMinSclkHigh;
521 uint8_t ucDispConfig;
522 uint32_t ulDClk;
523 uint32_t ulEClk;
524 uint32_t ulSustainableSclk;
525 uint32_t ulSustainableCUs;
526};
527
528struct phm_vq_budgeting_table {
529 uint8_t numEntries;
530 struct phm_vq_budgeting_record entries[1];
531};
532
533struct phm_clock_and_voltage_limits {
534 uint32_t sclk;
535 uint32_t mclk;
536 uint32_t gfxclk;
537 uint16_t vddc;
538 uint16_t vddci;
539 uint16_t vddgfx;
540 uint16_t vddmem;
541};
542
543
544
545struct phm_ppt_v1_information {
546 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
547 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
548 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
549 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
550 struct phm_clock_array *valid_sclk_values;
551 struct phm_clock_array *valid_mclk_values;
552 struct phm_clock_array *valid_socclk_values;
553 struct phm_clock_array *valid_dcefclk_values;
554 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
555 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
556 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
557 struct phm_ppm_table *ppm_parameter_table;
558 struct phm_cac_tdp_table *cac_dtp_table;
559 struct phm_tdp_table *tdp_table;
560 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
561 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
562 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
563 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
564 struct phm_ppt_v1_pcie_table *pcie_table;
565 struct phm_ppt_v1_gpio_table *gpio_table;
566 uint16_t us_ulv_voltage_offset;
567 uint16_t us_ulv_smnclk_did;
568 uint16_t us_ulv_mp1clk_did;
569 uint16_t us_ulv_gfxclk_bypass;
570 uint16_t us_gfxclk_slew_rate;
571 uint16_t us_min_gfxclk_freq_limit;
572};
573
574struct phm_ppt_v2_information {
575 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
576 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
577 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
578 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
579 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
580 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
581 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
582 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
583
584 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
585
586 struct phm_clock_array *valid_sclk_values;
587 struct phm_clock_array *valid_mclk_values;
588 struct phm_clock_array *valid_socclk_values;
589 struct phm_clock_array *valid_dcefclk_values;
590
591 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
592 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
593
594 struct phm_ppm_table *ppm_parameter_table;
595 struct phm_cac_tdp_table *cac_dtp_table;
596 struct phm_tdp_table *tdp_table;
597
598 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
599 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
600 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
601 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
602
603 struct phm_ppt_v1_pcie_table *pcie_table;
604
605 uint16_t us_ulv_voltage_offset;
606 uint16_t us_ulv_smnclk_did;
607 uint16_t us_ulv_mp1clk_did;
608 uint16_t us_ulv_gfxclk_bypass;
609 uint16_t us_gfxclk_slew_rate;
610 uint16_t us_min_gfxclk_freq_limit;
611
612 uint8_t uc_gfx_dpm_voltage_mode;
613 uint8_t uc_soc_dpm_voltage_mode;
614 uint8_t uc_uclk_dpm_voltage_mode;
615 uint8_t uc_uvd_dpm_voltage_mode;
616 uint8_t uc_vce_dpm_voltage_mode;
617 uint8_t uc_mp0_dpm_voltage_mode;
618 uint8_t uc_dcef_dpm_voltage_mode;
619};
620
621struct phm_dynamic_state_info {
622 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
623 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
624 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
625 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
626 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
627 struct phm_clock_array *valid_sclk_values;
628 struct phm_clock_array *valid_mclk_values;
629 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
630 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
631 uint32_t mclk_sclk_ratio;
632 uint32_t sclk_mclk_delta;
633 uint32_t vddc_vddci_delta;
634 uint32_t min_vddc_for_pcie_gen2;
635 struct phm_cac_leakage_table *cac_leakage_table;
636 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
637
638 struct phm_vce_clock_voltage_dependency_table
639 *vce_clock_voltage_dependency_table;
640 struct phm_uvd_clock_voltage_dependency_table
641 *uvd_clock_voltage_dependency_table;
642 struct phm_acp_clock_voltage_dependency_table
643 *acp_clock_voltage_dependency_table;
644 struct phm_samu_clock_voltage_dependency_table
645 *samu_clock_voltage_dependency_table;
646
647 struct phm_ppm_table *ppm_parameter_table;
648 struct phm_cac_tdp_table *cac_dtp_table;
649 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
650 struct phm_vq_budgeting_table *vq_budgeting_table;
651};
652
653struct pp_fan_info {
654 bool bNoFan;
655 uint8_t ucTachometerPulsesPerRevolution;
656 uint32_t ulMinRPM;
657 uint32_t ulMaxRPM;
658};
659
660struct pp_advance_fan_control_parameters {
661 uint16_t usTMin;
662 uint16_t usTMed;
663 uint16_t usTHigh;
664 uint16_t usPWMMin;
665 uint16_t usPWMMed;
666 uint16_t usPWMHigh;
667 uint8_t ucTHyst;
668 uint32_t ulCycleDelay;
669 uint16_t usTMax;
670 uint8_t ucFanControlMode;
671 uint16_t usFanPWMMinLimit;
672 uint16_t usFanPWMMaxLimit;
673 uint16_t usFanPWMStep;
674 uint16_t usDefaultMaxFanPWM;
675 uint16_t usFanOutputSensitivity;
676 uint16_t usDefaultFanOutputSensitivity;
677 uint16_t usMaxFanPWM;
678 uint16_t usFanRPMMinLimit;
679 uint16_t usFanRPMMaxLimit;
680 uint16_t usFanRPMStep;
681 uint16_t usDefaultMaxFanRPM;
682 uint16_t usMaxFanRPM;
683 uint16_t usFanCurrentLow;
684 uint16_t usFanCurrentHigh;
685 uint16_t usFanRPMLow;
686 uint16_t usFanRPMHigh;
687 uint32_t ulMinFanSCLKAcousticLimit;
688 uint8_t ucTargetTemperature;
689 uint8_t ucMinimumPWMLimit;
690 uint16_t usFanGainEdge;
691 uint16_t usFanGainHotspot;
692 uint16_t usFanGainLiquid;
693 uint16_t usFanGainVrVddc;
694 uint16_t usFanGainVrMvdd;
695 uint16_t usFanGainPlx;
696 uint16_t usFanGainHbm;
697 uint8_t ucEnableZeroRPM;
698 uint8_t ucFanStopTemperature;
699 uint8_t ucFanStartTemperature;
700 uint32_t ulMaxFanSCLKAcousticLimit;
701 uint32_t ulTargetGfxClk;
702 uint16_t usZeroRPMStartTemperature;
703 uint16_t usZeroRPMStopTemperature;
704};
705
706struct pp_thermal_controller_info {
707 uint8_t ucType;
708 uint8_t ucI2cLine;
709 uint8_t ucI2cAddress;
710 struct pp_fan_info fanInfo;
711 struct pp_advance_fan_control_parameters advanceFanControlParameters;
712};
713
714struct phm_microcode_version_info {
715 uint32_t SMC;
716 uint32_t DMCU;
717 uint32_t MC;
718 uint32_t NB;
719};
720
721enum PP_TABLE_VERSION {
722 PP_TABLE_V0 = 0,
723 PP_TABLE_V1,
724 PP_TABLE_V2,
725 PP_TABLE_MAX
726};
727
728
729
730
731struct pp_hwmgr {
732 uint32_t chip_family;
733 uint32_t chip_id;
734
735 uint32_t pp_table_version;
736 void *device;
737 struct pp_smumgr *smumgr;
738 const void *soft_pp_table;
739 uint32_t soft_pp_table_size;
740 void *hardcode_pp_table;
741 bool need_pp_table_upload;
742
743 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
744 uint32_t num_vce_state_tables;
745
746 enum amd_dpm_forced_level dpm_level;
747 enum amd_dpm_forced_level saved_dpm_level;
748 bool block_hw_access;
749 struct phm_gfx_arbiter gfx_arbiter;
750 struct phm_acp_arbiter acp_arbiter;
751 struct phm_uvd_arbiter uvd_arbiter;
752 struct phm_vce_arbiter vce_arbiter;
753 uint32_t usec_timeout;
754 void *pptable;
755 struct phm_platform_descriptor platform_descriptor;
756 void *backend;
757 enum PP_DAL_POWERLEVEL dal_power_level;
758 struct phm_dynamic_state_info dyn_state;
759 struct phm_runtime_table_header setup_asic;
760 struct phm_runtime_table_header power_down_asic;
761 struct phm_runtime_table_header disable_dynamic_state_management;
762 struct phm_runtime_table_header enable_dynamic_state_management;
763 struct phm_runtime_table_header set_power_state;
764 struct phm_runtime_table_header enable_clock_power_gatings;
765 struct phm_runtime_table_header display_configuration_changed;
766 struct phm_runtime_table_header start_thermal_controller;
767 struct phm_runtime_table_header set_temperature_range;
768 const struct pp_hwmgr_func *hwmgr_func;
769 const struct pp_table_func *pptable_func;
770 struct pp_power_state *ps;
771 enum pp_power_source power_source;
772 uint32_t num_ps;
773 struct pp_thermal_controller_info thermal_controller;
774 bool fan_ctrl_is_in_default_mode;
775 uint32_t fan_ctrl_default_mode;
776 bool fan_ctrl_enabled;
777 uint32_t tmin;
778 struct phm_microcode_version_info microcode_version_info;
779 uint32_t ps_size;
780 struct pp_power_state *current_ps;
781 struct pp_power_state *request_ps;
782 struct pp_power_state *boot_ps;
783 struct pp_power_state *uvd_ps;
784 struct amd_pp_display_configuration display_config;
785 uint32_t feature_mask;
786
787
788 struct amd_pp_profile gfx_power_profile;
789 struct amd_pp_profile compute_power_profile;
790 struct amd_pp_profile default_gfx_power_profile;
791 struct amd_pp_profile default_compute_power_profile;
792 enum amd_pp_profile_type current_power_profile;
793};
794
795extern int hwmgr_early_init(struct pp_instance *handle);
796extern int hwmgr_hw_init(struct pp_instance *handle);
797extern int hwmgr_hw_fini(struct pp_instance *handle);
798extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
799 uint32_t value, uint32_t mask);
800
801extern void phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
802 uint32_t indirect_port,
803 uint32_t index,
804 uint32_t value,
805 uint32_t mask);
806
807
808
809extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
810extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
811extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
812
813extern int phm_trim_voltage_table(struct pp_atomctrl_voltage_table *vol_table);
814extern int phm_get_svi2_mvdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
815extern int phm_get_svi2_vddci_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_clock_voltage_dependency_table *dep_table);
816extern int phm_get_svi2_vdd_voltage_table(struct pp_atomctrl_voltage_table *vol_table, phm_ppt_v1_voltage_lookup_table *lookup_table);
817extern void phm_trim_voltage_table_to_fit_state_table(uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table);
818extern int phm_reset_single_dpm_table(void *table, uint32_t count, int max);
819extern void phm_setup_pcie_table_entry(void *table, uint32_t index, uint32_t pcie_gen, uint32_t pcie_lanes);
820extern int32_t phm_get_dpm_level_enable_mask_value(void *table);
821extern uint8_t phm_get_voltage_id(struct pp_atomctrl_voltage_table *voltage_table,
822 uint32_t voltage);
823extern uint8_t phm_get_voltage_index(struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage);
824extern uint16_t phm_find_closest_vddci(struct pp_atomctrl_voltage_table *vddci_table, uint16_t vddci);
825extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level);
826extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
827 uint16_t virtual_voltage_id, int32_t *sclk);
828extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
829extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
830extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
831
832extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
833extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
834extern int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
835
836extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
837 uint32_t sclk, uint16_t id, uint16_t *voltage);
838
839#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
840
841#define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
842#define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK
843
844#define PHM_SET_FIELD(origval, reg, field, fieldval) \
845 (((origval) & ~PHM_FIELD_MASK(reg, field)) | \
846 (PHM_FIELD_MASK(reg, field) & ((fieldval) << PHM_FIELD_SHIFT(reg, field))))
847
848#define PHM_GET_FIELD(value, reg, field) \
849 (((value) & PHM_FIELD_MASK(reg, field)) >> \
850 PHM_FIELD_SHIFT(reg, field))
851
852
853
854
855#define PHM_READ_FIELD(device, reg, field) \
856 PHM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
857
858#define PHM_READ_INDIRECT_FIELD(device, port, reg, field) \
859 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
860 reg, field)
861
862#define PHM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
863 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
864 reg, field)
865
866#define PHM_WRITE_FIELD(device, reg, field, fieldval) \
867 cgs_write_register(device, mm##reg, PHM_SET_FIELD( \
868 cgs_read_register(device, mm##reg), reg, field, fieldval))
869
870#define PHM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
871 cgs_write_ind_register(device, port, ix##reg, \
872 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
873 reg, field, fieldval))
874
875#define PHM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
876 cgs_write_ind_register(device, port, ix##reg, \
877 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
878 reg, field, fieldval))
879
880#define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask) \
881 phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
882
883
884#define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
885 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
886
887#define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
888 PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval) \
889 << PHM_FIELD_SHIFT(reg, field), PHM_FIELD_MASK(reg, field))
890
891
892#endif
893
