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25#include <drm/drmP.h>
26#include "radeon.h"
27#include "radeon_asic.h"
28#include "rs780d.h"
29#include "r600_dpm.h"
30#include "rs780_dpm.h"
31#include "atom.h"
32#include <linux/seq_file.h>
33
34static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
35{
36 struct igp_ps *ps = rps->ps_priv;
37
38 return ps;
39}
40
41static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev)
42{
43 struct igp_power_info *pi = rdev->pm.dpm.priv;
44
45 return pi;
46}
47
48static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
49{
50 struct igp_power_info *pi = rs780_get_pi(rdev);
51 struct radeon_mode_info *minfo = &rdev->mode_info;
52 struct drm_crtc *crtc;
53 struct radeon_crtc *radeon_crtc;
54 int i;
55
56
57 pi->crtc_id = 0;
58 pi->refresh_rate = 60;
59
60 for (i = 0; i < rdev->num_crtc; i++) {
61 crtc = (struct drm_crtc *)minfo->crtcs[i];
62 if (crtc && crtc->enabled) {
63 radeon_crtc = to_radeon_crtc(crtc);
64 pi->crtc_id = radeon_crtc->crtc_id;
65 if (crtc->mode.htotal && crtc->mode.vtotal)
66 pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);
67 break;
68 }
69 }
70}
71
72static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
73
74static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
75 struct radeon_ps *boot_ps)
76{
77 struct atom_clock_dividers dividers;
78 struct igp_ps *default_state = rs780_get_ps(boot_ps);
79 int i, ret;
80
81 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
82 default_state->sclk_low, false, ÷rs);
83 if (ret)
84 return ret;
85
86 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
87 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
88 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
89
90 if (dividers.enable_post_div)
91 r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
92 else
93 r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
94
95 r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
96 r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
97
98 r600_engine_clock_entry_enable(rdev, 0, true);
99 for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
100 r600_engine_clock_entry_enable(rdev, i, false);
101
102 r600_enable_mclk_control(rdev, false);
103 r600_voltage_control_enable_pins(rdev, 0);
104
105 return 0;
106}
107
108static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
109 struct radeon_ps *boot_ps)
110{
111 int ret = 0;
112 int i;
113
114 r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
115
116 r600_set_at(rdev, 0, 0, 0, 0);
117
118 r600_set_git(rdev, R600_GICST_DFLT);
119
120 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
121 r600_set_tc(rdev, i, 0, 0);
122
123 r600_select_td(rdev, R600_TD_DFLT);
124 r600_set_vrc(rdev, 0);
125
126 r600_set_tpu(rdev, R600_TPU_DFLT);
127 r600_set_tpc(rdev, R600_TPC_DFLT);
128
129 r600_set_sstu(rdev, R600_SSTU_DFLT);
130 r600_set_sst(rdev, R600_SST_DFLT);
131
132 r600_set_fctu(rdev, R600_FCTU_DFLT);
133 r600_set_fct(rdev, R600_FCT_DFLT);
134
135 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
136 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
137 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
138 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
139 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
140
141 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
142 r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
143 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
144
145 ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
146
147 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
148 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
149 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0);
150
151 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
152 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
153 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
154
155 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
156 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
157 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
158
159 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH);
160 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
161 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH);
162
163 r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
164 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
165 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
166 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
167
168 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
169
170 r600_set_vrc(rdev, RS780_CGFTV_DFLT);
171
172 return ret;
173}
174
175static void rs780_start_dpm(struct radeon_device *rdev)
176{
177 r600_enable_sclk_control(rdev, false);
178 r600_enable_mclk_control(rdev, false);
179
180 r600_dynamicpm_enable(rdev, true);
181
182 radeon_wait_for_vblank(rdev, 0);
183 radeon_wait_for_vblank(rdev, 1);
184
185 r600_enable_spll_bypass(rdev, true);
186 r600_wait_for_spll_change(rdev);
187 r600_enable_spll_bypass(rdev, false);
188 r600_wait_for_spll_change(rdev);
189
190 r600_enable_spll_bypass(rdev, true);
191 r600_wait_for_spll_change(rdev);
192 r600_enable_spll_bypass(rdev, false);
193 r600_wait_for_spll_change(rdev);
194
195 r600_enable_sclk_control(rdev, true);
196}
197
198
199static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
200{
201 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
202 ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
203
204 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
205 RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
206 ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
207}
208
209static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
210{
211 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
212
213 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
214 ~STARTING_FEEDBACK_DIV_MASK);
215
216 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
217 ~FORCED_FEEDBACK_DIV_MASK);
218
219 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
220}
221
222static void rs780_voltage_scaling_init(struct radeon_device *rdev)
223{
224 struct igp_power_info *pi = rs780_get_pi(rdev);
225 struct drm_device *dev = rdev->ddev;
226 u32 fv_throt_pwm_fb_div_range[3];
227 u32 fv_throt_pwm_range[4];
228
229 if (dev->pdev->device == 0x9614) {
230 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
231 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
232 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
233 } else if ((dev->pdev->device == 0x9714) ||
234 (dev->pdev->device == 0x9715)) {
235 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
236 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
237 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
238 } else {
239 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
240 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
241 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
242 }
243
244 if (pi->pwm_voltage_control) {
245 fv_throt_pwm_range[0] = pi->min_voltage;
246 fv_throt_pwm_range[1] = pi->min_voltage;
247 fv_throt_pwm_range[2] = pi->max_voltage;
248 fv_throt_pwm_range[3] = pi->max_voltage;
249 } else {
250 fv_throt_pwm_range[0] = pi->invert_pwm_required ?
251 RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
252 fv_throt_pwm_range[1] = pi->invert_pwm_required ?
253 RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
254 fv_throt_pwm_range[2] = pi->invert_pwm_required ?
255 RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
256 fv_throt_pwm_range[3] = pi->invert_pwm_required ?
257 RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
258 }
259
260 WREG32_P(FVTHROT_PWM_CTRL_REG0,
261 STARTING_PWM_HIGHTIME(pi->max_voltage),
262 ~STARTING_PWM_HIGHTIME_MASK);
263
264 WREG32_P(FVTHROT_PWM_CTRL_REG0,
265 NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
266 ~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
267
268 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
269 ~FORCE_STARTING_PWM_HIGHTIME);
270
271 if (pi->invert_pwm_required)
272 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
273 else
274 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
275
276 rs780_voltage_scaling_enable(rdev, true);
277
278 WREG32(FVTHROT_PWM_CTRL_REG1,
279 (MIN_PWM_HIGHTIME(pi->min_voltage) |
280 MAX_PWM_HIGHTIME(pi->max_voltage)));
281
282 WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
283 WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
284 WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
285 WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
286
287 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
288 RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
289 ~RANGE0_PWM_FEEDBACK_DIV_MASK);
290
291 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
292 (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) |
293 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
294
295 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
296 (RANGE0_PWM(fv_throt_pwm_range[1]) |
297 RANGE1_PWM(fv_throt_pwm_range[2])));
298 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
299 (RANGE2_PWM(fv_throt_pwm_range[1]) |
300 RANGE3_PWM(fv_throt_pwm_range[2])));
301}
302
303static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
304{
305 if (enable)
306 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
307 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
308 else
309 WREG32_P(FVTHROT_CNTRL_REG, 0,
310 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
311}
312
313static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
314{
315 if (enable)
316 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
317 else
318 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
319}
320
321static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
322{
323 WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
324 WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
325 WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
326 WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
327 WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
328
329 WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
330 WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
331 WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
332 WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
333 WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
334}
335
336static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
337{
338 WREG32_P(FVTHROT_FBDIV_REG2,
339 FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
340 ~FB_DIV_TIMER_VAL_MASK);
341
342 WREG32_P(FVTHROT_CNTRL_REG,
343 REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf),
344 ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK));
345}
346
347static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
348{
349 WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
350}
351
352static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
353{
354 WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
355 WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
356 WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
357 WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
358
359 WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
360}
361
362static void rs780_program_at(struct radeon_device *rdev)
363{
364 struct igp_power_info *pi = rs780_get_pi(rdev);
365
366 WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
367 WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
368 WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
369 WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
370 WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
371}
372
373static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
374{
375 WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
376}
377
378static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage)
379{
380 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
381
382 if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
383 (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
384 return;
385
386 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
387
388 udelay(1);
389
390 WREG32_P(FVTHROT_PWM_CTRL_REG0,
391 STARTING_PWM_HIGHTIME(voltage),
392 ~STARTING_PWM_HIGHTIME_MASK);
393
394 WREG32_P(FVTHROT_PWM_CTRL_REG0,
395 FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
396
397 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
398 ~RANGE_PWM_FEEDBACK_DIV_EN);
399
400 udelay(1);
401
402 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
403}
404
405static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)
406{
407 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
408
409 if (current_state->sclk_low == current_state->sclk_high)
410 return;
411
412 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
413
414 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
415 ~FORCED_FEEDBACK_DIV_MASK);
416 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
417 ~STARTING_FEEDBACK_DIV_MASK);
418 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
419
420 udelay(100);
421
422 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
423}
424
425static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
426 struct radeon_ps *new_ps,
427 struct radeon_ps *old_ps)
428{
429 struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
430 struct igp_ps *new_state = rs780_get_ps(new_ps);
431 struct igp_ps *old_state = rs780_get_ps(old_ps);
432 int ret;
433
434 if ((new_state->sclk_high == old_state->sclk_high) &&
435 (new_state->sclk_low == old_state->sclk_low))
436 return 0;
437
438 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
439 new_state->sclk_low, false, &min_dividers);
440 if (ret)
441 return ret;
442
443 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
444 new_state->sclk_high, false, &max_dividers);
445 if (ret)
446 return ret;
447
448 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
449 old_state->sclk_high, false, ¤t_max_dividers);
450 if (ret)
451 return ret;
452
453 if ((min_dividers.ref_div != max_dividers.ref_div) ||
454 (min_dividers.post_div != max_dividers.post_div) ||
455 (max_dividers.ref_div != current_max_dividers.ref_div) ||
456 (max_dividers.post_div != current_max_dividers.post_div))
457 return -EINVAL;
458
459 rs780_force_fbdiv(rdev, max_dividers.fb_div);
460
461 if (max_dividers.fb_div > min_dividers.fb_div) {
462 WREG32_P(FVTHROT_FBDIV_REG0,
463 MIN_FEEDBACK_DIV(min_dividers.fb_div) |
464 MAX_FEEDBACK_DIV(max_dividers.fb_div),
465 ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK));
466
467 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
468 }
469
470 return 0;
471}
472
473static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
474 struct radeon_ps *new_ps,
475 struct radeon_ps *old_ps)
476{
477 struct igp_ps *new_state = rs780_get_ps(new_ps);
478 struct igp_ps *old_state = rs780_get_ps(old_ps);
479 struct igp_power_info *pi = rs780_get_pi(rdev);
480
481 if ((new_state->sclk_high == old_state->sclk_high) &&
482 (new_state->sclk_low == old_state->sclk_low))
483 return;
484
485 if (pi->crtc_id == 0)
486 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
487 else
488 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
489
490}
491
492static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
493 struct radeon_ps *new_ps,
494 struct radeon_ps *old_ps)
495{
496 struct igp_ps *new_state = rs780_get_ps(new_ps);
497 struct igp_ps *old_state = rs780_get_ps(old_ps);
498
499 if ((new_state->sclk_high == old_state->sclk_high) &&
500 (new_state->sclk_low == old_state->sclk_low))
501 return;
502
503 if (new_state->sclk_high == new_state->sclk_low)
504 return;
505
506 rs780_clk_scaling_enable(rdev, true);
507}
508
509static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
510 enum rs780_vddc_level vddc)
511{
512 struct igp_power_info *pi = rs780_get_pi(rdev);
513
514 if (vddc == RS780_VDDC_LEVEL_HIGH)
515 return pi->max_voltage;
516 else if (vddc == RS780_VDDC_LEVEL_LOW)
517 return pi->min_voltage;
518 else
519 return pi->max_voltage;
520}
521
522static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
523 struct radeon_ps *new_ps)
524{
525 struct igp_ps *new_state = rs780_get_ps(new_ps);
526 struct igp_power_info *pi = rs780_get_pi(rdev);
527 enum rs780_vddc_level vddc_high, vddc_low;
528
529 udelay(100);
530
531 if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
532 (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
533 return;
534
535 vddc_high = rs780_get_voltage_for_vddc_level(rdev,
536 new_state->max_voltage);
537 vddc_low = rs780_get_voltage_for_vddc_level(rdev,
538 new_state->min_voltage);
539
540 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
541
542 udelay(1);
543 if (vddc_high > vddc_low) {
544 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
545 RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
546
547 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
548 } else if (vddc_high == vddc_low) {
549 if (pi->max_voltage != vddc_high) {
550 WREG32_P(FVTHROT_PWM_CTRL_REG0,
551 STARTING_PWM_HIGHTIME(vddc_high),
552 ~STARTING_PWM_HIGHTIME_MASK);
553
554 WREG32_P(FVTHROT_PWM_CTRL_REG0,
555 FORCE_STARTING_PWM_HIGHTIME,
556 ~FORCE_STARTING_PWM_HIGHTIME);
557 }
558 }
559
560 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
561}
562
563static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
564 struct radeon_ps *new_ps,
565 struct radeon_ps *old_ps)
566{
567 struct igp_ps *new_state = rs780_get_ps(new_ps);
568 struct igp_ps *current_state = rs780_get_ps(old_ps);
569
570 if ((new_ps->vclk == old_ps->vclk) &&
571 (new_ps->dclk == old_ps->dclk))
572 return;
573
574 if (new_state->sclk_high >= current_state->sclk_high)
575 return;
576
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
578}
579
580static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
581 struct radeon_ps *new_ps,
582 struct radeon_ps *old_ps)
583{
584 struct igp_ps *new_state = rs780_get_ps(new_ps);
585 struct igp_ps *current_state = rs780_get_ps(old_ps);
586
587 if ((new_ps->vclk == old_ps->vclk) &&
588 (new_ps->dclk == old_ps->dclk))
589 return;
590
591 if (new_state->sclk_high < current_state->sclk_high)
592 return;
593
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
595}
596
597int rs780_dpm_enable(struct radeon_device *rdev)
598{
599 struct igp_power_info *pi = rs780_get_pi(rdev);
600 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
601 int ret;
602
603 rs780_get_pm_mode_parameters(rdev);
604 rs780_disable_vbios_powersaving(rdev);
605
606 if (r600_dynamicpm_enabled(rdev))
607 return -EINVAL;
608 ret = rs780_initialize_dpm_parameters(rdev, boot_ps);
609 if (ret)
610 return ret;
611 rs780_start_dpm(rdev);
612
613 rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
614 rs780_preset_starting_fbdiv(rdev);
615 if (pi->voltage_control)
616 rs780_voltage_scaling_init(rdev);
617 rs780_clk_scaling_enable(rdev, true);
618 rs780_set_engine_clock_sc(rdev);
619 rs780_set_engine_clock_wfc(rdev);
620 rs780_program_at(rdev);
621 rs780_set_engine_clock_tdc(rdev);
622 rs780_set_engine_clock_ssc(rdev);
623
624 if (pi->gfx_clock_gating)
625 r600_gfx_clockgating_enable(rdev, true);
626
627 return 0;
628}
629
630void rs780_dpm_disable(struct radeon_device *rdev)
631{
632 struct igp_power_info *pi = rs780_get_pi(rdev);
633
634 r600_dynamicpm_enable(rdev, false);
635
636 rs780_clk_scaling_enable(rdev, false);
637 rs780_voltage_scaling_enable(rdev, false);
638
639 if (pi->gfx_clock_gating)
640 r600_gfx_clockgating_enable(rdev, false);
641
642 if (rdev->irq.installed &&
643 (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
644 rdev->irq.dpm_thermal = false;
645 radeon_irq_set(rdev);
646 }
647}
648
649int rs780_dpm_set_power_state(struct radeon_device *rdev)
650{
651 struct igp_power_info *pi = rs780_get_pi(rdev);
652 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
653 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
654 int ret;
655
656 rs780_get_pm_mode_parameters(rdev);
657
658 rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
659
660 if (pi->voltage_control) {
661 rs780_force_voltage(rdev, pi->max_voltage);
662 mdelay(5);
663 }
664
665 ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps);
666 if (ret)
667 return ret;
668 rs780_set_engine_clock_spc(rdev, new_ps, old_ps);
669
670 rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps);
671
672 if (pi->voltage_control)
673 rs780_enable_voltage_scaling(rdev, new_ps);
674
675 rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
676
677 return 0;
678}
679
680void rs780_dpm_setup_asic(struct radeon_device *rdev)
681{
682
683}
684
685void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
686{
687 rs780_get_pm_mode_parameters(rdev);
688 rs780_program_at(rdev);
689}
690
691union igp_info {
692 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
693 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
694};
695
696union power_info {
697 struct _ATOM_POWERPLAY_INFO info;
698 struct _ATOM_POWERPLAY_INFO_V2 info_2;
699 struct _ATOM_POWERPLAY_INFO_V3 info_3;
700 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
701 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
702 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
703};
704
705union pplib_clock_info {
706 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
707 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
708 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
709 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
710};
711
712union pplib_power_state {
713 struct _ATOM_PPLIB_STATE v1;
714 struct _ATOM_PPLIB_STATE_V2 v2;
715};
716
717static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
718 struct radeon_ps *rps,
719 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
720 u8 table_rev)
721{
722 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
723 rps->class = le16_to_cpu(non_clock_info->usClassification);
724 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
725
726 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
729 } else {
730 rps->vclk = 0;
731 rps->dclk = 0;
732 }
733
734 if (r600_is_uvd_state(rps->class, rps->class2)) {
735 if ((rps->vclk == 0) || (rps->dclk == 0)) {
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ;
737 rps->dclk = RS780_DEFAULT_DCLK_FREQ;
738 }
739 }
740
741 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
742 rdev->pm.dpm.boot_ps = rps;
743 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
744 rdev->pm.dpm.uvd_ps = rps;
745}
746
747static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
748 struct radeon_ps *rps,
749 union pplib_clock_info *clock_info)
750{
751 struct igp_ps *ps = rs780_get_ps(rps);
752 u32 sclk;
753
754 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
755 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
756 ps->sclk_low = sclk;
757 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
758 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
759 ps->sclk_high = sclk;
760 switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
761 case ATOM_PPLIB_RS780_VOLTAGE_NONE:
762 default:
763 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
764 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
765 break;
766 case ATOM_PPLIB_RS780_VOLTAGE_LOW:
767 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
768 ps->max_voltage = RS780_VDDC_LEVEL_LOW;
769 break;
770 case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
771 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
772 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
773 break;
774 case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
775 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
776 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
777 break;
778 }
779 ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
780
781 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
782 ps->sclk_low = rdev->clock.default_sclk;
783 ps->sclk_high = rdev->clock.default_sclk;
784 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
785 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
786 }
787}
788
789static int rs780_parse_power_table(struct radeon_device *rdev)
790{
791 struct radeon_mode_info *mode_info = &rdev->mode_info;
792 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
793 union pplib_power_state *power_state;
794 int i;
795 union pplib_clock_info *clock_info;
796 union power_info *power_info;
797 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
798 u16 data_offset;
799 u8 frev, crev;
800 struct igp_ps *ps;
801
802 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
803 &frev, &crev, &data_offset))
804 return -EINVAL;
805 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
806
807 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
808 power_info->pplib.ucNumStates, GFP_KERNEL);
809 if (!rdev->pm.dpm.ps)
810 return -ENOMEM;
811
812 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
813 power_state = (union pplib_power_state *)
814 (mode_info->atom_context->bios + data_offset +
815 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
816 i * power_info->pplib.ucStateEntrySize);
817 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
818 (mode_info->atom_context->bios + data_offset +
819 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
820 (power_state->v1.ucNonClockStateIndex *
821 power_info->pplib.ucNonClockSize));
822 if (power_info->pplib.ucStateEntrySize - 1) {
823 clock_info = (union pplib_clock_info *)
824 (mode_info->atom_context->bios + data_offset +
825 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
826 (power_state->v1.ucClockStateIndices[0] *
827 power_info->pplib.ucClockInfoSize));
828 ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
829 if (ps == NULL) {
830 kfree(rdev->pm.dpm.ps);
831 return -ENOMEM;
832 }
833 rdev->pm.dpm.ps[i].ps_priv = ps;
834 rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
835 non_clock_info,
836 power_info->pplib.ucNonClockSize);
837 rs780_parse_pplib_clock_info(rdev,
838 &rdev->pm.dpm.ps[i],
839 clock_info);
840 }
841 }
842 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
843 return 0;
844}
845
846int rs780_dpm_init(struct radeon_device *rdev)
847{
848 struct igp_power_info *pi;
849 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
850 union igp_info *info;
851 u16 data_offset;
852 u8 frev, crev;
853 int ret;
854
855 pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
856 if (pi == NULL)
857 return -ENOMEM;
858 rdev->pm.dpm.priv = pi;
859
860 ret = r600_get_platform_caps(rdev);
861 if (ret)
862 return ret;
863
864 ret = rs780_parse_power_table(rdev);
865 if (ret)
866 return ret;
867
868 pi->voltage_control = false;
869 pi->gfx_clock_gating = true;
870
871 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
872 &frev, &crev, &data_offset)) {
873 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
874
875
876 switch (crev) {
877 case 1:
878 pi->num_of_cycles_in_period =
879 info->info.ucNumberOfCyclesInPeriod;
880 pi->num_of_cycles_in_period |=
881 info->info.ucNumberOfCyclesInPeriodHi << 8;
882 pi->invert_pwm_required =
883 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
884 pi->boot_voltage = info->info.ucStartingPWM_HighTime;
885 pi->max_voltage = info->info.ucMaxNBVoltage;
886 pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;
887 pi->min_voltage = info->info.ucMinNBVoltage;
888 pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;
889 pi->inter_voltage_low =
890 le16_to_cpu(info->info.usInterNBVoltageLow);
891 pi->inter_voltage_high =
892 le16_to_cpu(info->info.usInterNBVoltageHigh);
893 pi->voltage_control = true;
894 pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
895 break;
896 case 2:
897 pi->num_of_cycles_in_period =
898 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
899 pi->invert_pwm_required =
900 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
901 pi->boot_voltage =
902 le16_to_cpu(info->info_2.usBootUpNBVoltage);
903 pi->max_voltage =
904 le16_to_cpu(info->info_2.usMaxNBVoltage);
905 pi->min_voltage =
906 le16_to_cpu(info->info_2.usMinNBVoltage);
907 pi->system_config =
908 le32_to_cpu(info->info_2.ulSystemConfig);
909 pi->pwm_voltage_control =
910 (pi->system_config & 0x4) ? true : false;
911 pi->voltage_control = true;
912 pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
913 break;
914 default:
915 DRM_ERROR("No integrated system info for your GPU\n");
916 return -EINVAL;
917 }
918 if (pi->min_voltage > pi->max_voltage)
919 pi->voltage_control = false;
920 if (pi->pwm_voltage_control) {
921 if ((pi->num_of_cycles_in_period == 0) ||
922 (pi->max_voltage == 0) ||
923 (pi->min_voltage == 0))
924 pi->voltage_control = false;
925 } else {
926 if ((pi->num_of_cycles_in_period == 0) ||
927 (pi->max_voltage == 0))
928 pi->voltage_control = false;
929 }
930
931 return 0;
932 }
933 radeon_dpm_fini(rdev);
934 return -EINVAL;
935}
936
937void rs780_dpm_print_power_state(struct radeon_device *rdev,
938 struct radeon_ps *rps)
939{
940 struct igp_ps *ps = rs780_get_ps(rps);
941
942 r600_dpm_print_class_info(rps->class, rps->class2);
943 r600_dpm_print_cap_info(rps->caps);
944 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
945 printk("\t\tpower level 0 sclk: %u vddc_index: %d\n",
946 ps->sclk_low, ps->min_voltage);
947 printk("\t\tpower level 1 sclk: %u vddc_index: %d\n",
948 ps->sclk_high, ps->max_voltage);
949 r600_dpm_print_ps_status(rdev, rps);
950}
951
952void rs780_dpm_fini(struct radeon_device *rdev)
953{
954 int i;
955
956 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
957 kfree(rdev->pm.dpm.ps[i].ps_priv);
958 }
959 kfree(rdev->pm.dpm.ps);
960 kfree(rdev->pm.dpm.priv);
961}
962
963u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
964{
965 struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
966
967 if (low)
968 return requested_state->sclk_low;
969 else
970 return requested_state->sclk_high;
971}
972
973u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
974{
975 struct igp_power_info *pi = rs780_get_pi(rdev);
976
977 return pi->bootup_uma_clk;
978}
979
980void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
981 struct seq_file *m)
982{
983 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
984 struct igp_ps *ps = rs780_get_ps(rps);
985 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
986 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
987 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
988 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
989 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
990 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
991 (post_div * ref_div);
992
993 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
994
995
996 if (sclk < (ps->sclk_low + 500))
997 seq_printf(m, "power level 0 sclk: %u vddc_index: %d\n",
998 ps->sclk_low, ps->min_voltage);
999 else
1000 seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n",
1001 ps->sclk_high, ps->max_voltage);
1002}
1003
1004
1005u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev)
1006{
1007 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
1008 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1009 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
1010 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
1011 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
1012 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
1013 (post_div * ref_div);
1014
1015 return sclk;
1016}
1017
1018
1019u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev)
1020{
1021 struct igp_power_info *pi = rs780_get_pi(rdev);
1022
1023 return pi->bootup_uma_clk;
1024}
1025
1026int rs780_dpm_force_performance_level(struct radeon_device *rdev,
1027 enum radeon_dpm_forced_level level)
1028{
1029 struct igp_power_info *pi = rs780_get_pi(rdev);
1030 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1031 struct igp_ps *ps = rs780_get_ps(rps);
1032 struct atom_clock_dividers dividers;
1033 int ret;
1034
1035 rs780_clk_scaling_enable(rdev, false);
1036 rs780_voltage_scaling_enable(rdev, false);
1037
1038 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1039 if (pi->voltage_control)
1040 rs780_force_voltage(rdev, pi->max_voltage);
1041
1042 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1043 ps->sclk_high, false, ÷rs);
1044 if (ret)
1045 return ret;
1046
1047 rs780_force_fbdiv(rdev, dividers.fb_div);
1048 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1049 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1050 ps->sclk_low, false, ÷rs);
1051 if (ret)
1052 return ret;
1053
1054 rs780_force_fbdiv(rdev, dividers.fb_div);
1055
1056 if (pi->voltage_control)
1057 rs780_force_voltage(rdev, pi->min_voltage);
1058 } else {
1059 if (pi->voltage_control)
1060 rs780_force_voltage(rdev, pi->max_voltage);
1061
1062 if (ps->sclk_high != ps->sclk_low) {
1063 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
1064 rs780_clk_scaling_enable(rdev, true);
1065 }
1066
1067 if (pi->voltage_control) {
1068 rs780_voltage_scaling_enable(rdev, true);
1069 rs780_enable_voltage_scaling(rdev, rps);
1070 }
1071 }
1072
1073 rdev->pm.dpm.forced_level = level;
1074
1075 return 0;
1076}
1077
