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20#ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21#define _ASM_X86_AMD_IOMMU_TYPES_H
22
23#include <linux/types.h>
24#include <linux/mutex.h>
25#include <linux/msi.h>
26#include <linux/list.h>
27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/irqreturn.h>
30
31
32
33
34#define MAX_IOMMUS 32
35
36
37
38
39#define DEV_TABLE_ENTRY_SIZE 32
40#define ALIAS_TABLE_ENTRY_SIZE 2
41#define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
42
43
44#define MMIO_CAP_HDR_OFFSET 0x00
45#define MMIO_RANGE_OFFSET 0x0c
46#define MMIO_MISC_OFFSET 0x10
47
48
49#define MMIO_RANGE_LD_MASK 0xff000000
50#define MMIO_RANGE_FD_MASK 0x00ff0000
51#define MMIO_RANGE_BUS_MASK 0x0000ff00
52#define MMIO_RANGE_LD_SHIFT 24
53#define MMIO_RANGE_FD_SHIFT 16
54#define MMIO_RANGE_BUS_SHIFT 8
55#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
56#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
57#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
58#define MMIO_MSI_NUM(x) ((x) & 0x1f)
59
60
61#define MMIO_EXCL_ENABLE_MASK 0x01ULL
62#define MMIO_EXCL_ALLOW_MASK 0x02ULL
63
64
65#define MMIO_DEV_TABLE_OFFSET 0x0000
66#define MMIO_CMD_BUF_OFFSET 0x0008
67#define MMIO_EVT_BUF_OFFSET 0x0010
68#define MMIO_CONTROL_OFFSET 0x0018
69#define MMIO_EXCL_BASE_OFFSET 0x0020
70#define MMIO_EXCL_LIMIT_OFFSET 0x0028
71#define MMIO_EXT_FEATURES 0x0030
72#define MMIO_PPR_LOG_OFFSET 0x0038
73#define MMIO_GA_LOG_BASE_OFFSET 0x00e0
74#define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
75#define MMIO_CMD_HEAD_OFFSET 0x2000
76#define MMIO_CMD_TAIL_OFFSET 0x2008
77#define MMIO_EVT_HEAD_OFFSET 0x2010
78#define MMIO_EVT_TAIL_OFFSET 0x2018
79#define MMIO_STATUS_OFFSET 0x2020
80#define MMIO_PPR_HEAD_OFFSET 0x2030
81#define MMIO_PPR_TAIL_OFFSET 0x2038
82#define MMIO_GA_HEAD_OFFSET 0x2040
83#define MMIO_GA_TAIL_OFFSET 0x2048
84#define MMIO_CNTR_CONF_OFFSET 0x4000
85#define MMIO_CNTR_REG_OFFSET 0x40000
86#define MMIO_REG_END_OFFSET 0x80000
87
88
89
90
91#define FEATURE_PREFETCH (1ULL<<0)
92#define FEATURE_PPR (1ULL<<1)
93#define FEATURE_X2APIC (1ULL<<2)
94#define FEATURE_NX (1ULL<<3)
95#define FEATURE_GT (1ULL<<4)
96#define FEATURE_IA (1ULL<<6)
97#define FEATURE_GA (1ULL<<7)
98#define FEATURE_HE (1ULL<<8)
99#define FEATURE_PC (1ULL<<9)
100#define FEATURE_GAM_VAPIC (1ULL<<21)
101
102#define FEATURE_PASID_SHIFT 32
103#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
104
105#define FEATURE_GLXVAL_SHIFT 14
106#define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
107
108
109
110
111
112
113#define PASID_MASK 0x0000ffff
114
115
116#define MMIO_STATUS_EVT_INT_MASK (1 << 1)
117#define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
118#define MMIO_STATUS_PPR_INT_MASK (1 << 6)
119#define MMIO_STATUS_GALOG_RUN_MASK (1 << 8)
120#define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
121#define MMIO_STATUS_GALOG_INT_MASK (1 << 10)
122
123
124#define EVENT_ENTRY_SIZE 0x10
125#define EVENT_TYPE_SHIFT 28
126#define EVENT_TYPE_MASK 0xf
127#define EVENT_TYPE_ILL_DEV 0x1
128#define EVENT_TYPE_IO_FAULT 0x2
129#define EVENT_TYPE_DEV_TAB_ERR 0x3
130#define EVENT_TYPE_PAGE_TAB_ERR 0x4
131#define EVENT_TYPE_ILL_CMD 0x5
132#define EVENT_TYPE_CMD_HARD_ERR 0x6
133#define EVENT_TYPE_IOTLB_INV_TO 0x7
134#define EVENT_TYPE_INV_DEV_REQ 0x8
135#define EVENT_DEVID_MASK 0xffff
136#define EVENT_DEVID_SHIFT 0
137#define EVENT_DOMID_MASK 0xffff
138#define EVENT_DOMID_SHIFT 0
139#define EVENT_FLAGS_MASK 0xfff
140#define EVENT_FLAGS_SHIFT 0x10
141
142
143#define CONTROL_IOMMU_EN 0x00ULL
144#define CONTROL_HT_TUN_EN 0x01ULL
145#define CONTROL_EVT_LOG_EN 0x02ULL
146#define CONTROL_EVT_INT_EN 0x03ULL
147#define CONTROL_COMWAIT_EN 0x04ULL
148#define CONTROL_INV_TIMEOUT 0x05ULL
149#define CONTROL_PASSPW_EN 0x08ULL
150#define CONTROL_RESPASSPW_EN 0x09ULL
151#define CONTROL_COHERENT_EN 0x0aULL
152#define CONTROL_ISOC_EN 0x0bULL
153#define CONTROL_CMDBUF_EN 0x0cULL
154#define CONTROL_PPFLOG_EN 0x0dULL
155#define CONTROL_PPFINT_EN 0x0eULL
156#define CONTROL_PPR_EN 0x0fULL
157#define CONTROL_GT_EN 0x10ULL
158#define CONTROL_GA_EN 0x11ULL
159#define CONTROL_GAM_EN 0x19ULL
160#define CONTROL_GALOG_EN 0x1CULL
161#define CONTROL_GAINT_EN 0x1DULL
162
163#define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
164#define CTRL_INV_TO_NONE 0
165#define CTRL_INV_TO_1MS 1
166#define CTRL_INV_TO_10MS 2
167#define CTRL_INV_TO_100MS 3
168#define CTRL_INV_TO_1S 4
169#define CTRL_INV_TO_10S 5
170#define CTRL_INV_TO_100S 6
171
172
173#define CMD_COMPL_WAIT 0x01
174#define CMD_INV_DEV_ENTRY 0x02
175#define CMD_INV_IOMMU_PAGES 0x03
176#define CMD_INV_IOTLB_PAGES 0x04
177#define CMD_INV_IRT 0x05
178#define CMD_COMPLETE_PPR 0x07
179#define CMD_INV_ALL 0x08
180
181#define CMD_COMPL_WAIT_STORE_MASK 0x01
182#define CMD_COMPL_WAIT_INT_MASK 0x02
183#define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
184#define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
185#define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
186
187#define PPR_STATUS_MASK 0xf
188#define PPR_STATUS_SHIFT 12
189
190#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
191
192
193#define DEV_ENTRY_VALID 0x00
194#define DEV_ENTRY_TRANSLATION 0x01
195#define DEV_ENTRY_IR 0x3d
196#define DEV_ENTRY_IW 0x3e
197#define DEV_ENTRY_NO_PAGE_FAULT 0x62
198#define DEV_ENTRY_EX 0x67
199#define DEV_ENTRY_SYSMGT1 0x68
200#define DEV_ENTRY_SYSMGT2 0x69
201#define DEV_ENTRY_IRQ_TBL_EN 0x80
202#define DEV_ENTRY_INIT_PASS 0xb8
203#define DEV_ENTRY_EINT_PASS 0xb9
204#define DEV_ENTRY_NMI_PASS 0xba
205#define DEV_ENTRY_LINT0_PASS 0xbe
206#define DEV_ENTRY_LINT1_PASS 0xbf
207#define DEV_ENTRY_MODE_MASK 0x07
208#define DEV_ENTRY_MODE_SHIFT 0x09
209
210#define MAX_DEV_TABLE_ENTRIES 0xffff
211
212
213#define CMD_BUFFER_SIZE 8192
214#define CMD_BUFFER_UNINITIALIZED 1
215#define CMD_BUFFER_ENTRIES 512
216#define MMIO_CMD_SIZE_SHIFT 56
217#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
218
219
220#define EVT_BUFFER_SIZE 8192
221#define EVT_LEN_MASK (0x9ULL << 56)
222
223
224#define PPR_LOG_ENTRIES 512
225#define PPR_LOG_SIZE_SHIFT 56
226#define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
227#define PPR_ENTRY_SIZE 16
228#define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
229
230#define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
231#define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
232#define PPR_DEVID(x) ((x) & 0xffffULL)
233#define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
234#define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
235#define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
236#define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
237
238#define PPR_REQ_FAULT 0x01
239
240
241#define GA_LOG_ENTRIES 512
242#define GA_LOG_SIZE_SHIFT 56
243#define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT)
244#define GA_ENTRY_SIZE 8
245#define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
246
247#define GA_TAG(x) (u32)(x & 0xffffffffULL)
248#define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL)
249#define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
250
251#define GA_GUEST_NR 0x1
252
253
254#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
255#define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
256#define DTE_IRQ_TABLE_LEN_MASK (0xfULL << 1)
257#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
258#define DTE_IRQ_TABLE_LEN (8ULL << 1)
259#define DTE_IRQ_REMAP_ENABLE 1ULL
260
261#define PAGE_MODE_NONE 0x00
262#define PAGE_MODE_1_LEVEL 0x01
263#define PAGE_MODE_2_LEVEL 0x02
264#define PAGE_MODE_3_LEVEL 0x03
265#define PAGE_MODE_4_LEVEL 0x04
266#define PAGE_MODE_5_LEVEL 0x05
267#define PAGE_MODE_6_LEVEL 0x06
268
269#define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
270#define PM_LEVEL_SIZE(x) (((x) < 6) ? \
271 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
272 (0xffffffffffffffffULL))
273#define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
274#define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
275#define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
276 IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW)
277#define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
278
279#define PM_MAP_4k 0
280#define PM_ADDR_MASK 0x000ffffffffff000ULL
281#define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
282 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
283#define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
284
285
286
287
288
289#define PAGE_SIZE_LEVEL(pagesize) \
290 ((__ffs(pagesize) - 12) / 9)
291
292
293
294
295#define PAGE_SIZE_PTE_COUNT(pagesize) \
296 (1ULL << ((__ffs(pagesize) - 12) % 9))
297
298
299
300
301
302#define PAGE_SIZE_ALIGN(address, pagesize) \
303 ((address) & ~((pagesize) - 1))
304
305
306
307
308
309#define PAGE_SIZE_PTE(address, pagesize) \
310 (((address) | ((pagesize) - 1)) & \
311 (~(pagesize >> 1)) & PM_ADDR_MASK)
312
313
314
315
316#define PTE_PAGE_SIZE(pte) \
317 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
318
319
320
321
322#define PTE_LEVEL_PAGE_SIZE(level) \
323 (1ULL << (12 + (9 * (level))))
324
325
326
327
328#define IOMMU_PTE_PR (1ULL << 0)
329#define IOMMU_PTE_U (1ULL << 59)
330#define IOMMU_PTE_FC (1ULL << 60)
331#define IOMMU_PTE_IR (1ULL << 61)
332#define IOMMU_PTE_IW (1ULL << 62)
333
334
335
336
337#define DTE_FLAG_V (1ULL << 0)
338#define DTE_FLAG_TV (1ULL << 1)
339#define DTE_FLAG_IR (1ULL << 61)
340#define DTE_FLAG_IW (1ULL << 62)
341
342#define DTE_FLAG_MASK (0x3ffULL << 32)
343#define DTE_FLAG_IOTLB (1ULL << 32)
344#define DTE_FLAG_SA (1ULL << 34)
345#define DTE_FLAG_GV (1ULL << 55)
346#define DTE_GLX_SHIFT (56)
347#define DTE_GLX_MASK (3)
348#define DEV_DOMID_MASK 0xffffULL
349
350#define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
351#define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
352#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL)
353
354#define DTE_GCR3_INDEX_A 0
355#define DTE_GCR3_INDEX_B 1
356#define DTE_GCR3_INDEX_C 1
357
358#define DTE_GCR3_SHIFT_A 58
359#define DTE_GCR3_SHIFT_B 16
360#define DTE_GCR3_SHIFT_C 43
361
362#define GCR3_VALID 0x01ULL
363
364#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
365#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR)
366#define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK))
367#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
368
369#define IOMMU_PROT_MASK 0x03
370#define IOMMU_PROT_IR 0x01
371#define IOMMU_PROT_IW 0x02
372
373
374#define IOMMU_CAP_IOTLB 24
375#define IOMMU_CAP_NPCACHE 26
376#define IOMMU_CAP_EFR 27
377
378
379#define IOMMU_FEAT_GASUP_SHIFT 6
380
381
382#define IOMMU_EFR_GASUP_SHIFT 7
383
384#define MAX_DOMAIN_ID 65536
385
386
387#define PD_DMA_OPS_MASK (1UL << 0)
388#define PD_DEFAULT_MASK (1UL << 1)
389
390#define PD_PASSTHROUGH_MASK (1UL << 2)
391
392#define PD_IOMMUV2_MASK (1UL << 3)
393
394extern bool amd_iommu_dump;
395#define DUMP_printk(format, arg...) \
396 do { \
397 if (amd_iommu_dump) \
398 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
399 } while(0);
400
401
402extern bool amd_iommu_np_cache;
403
404extern bool amd_iommu_iotlb_sup;
405
406#define MAX_IRQS_PER_TABLE 256
407#define IRQ_TABLE_ALIGNMENT 128
408
409struct irq_remap_table {
410 spinlock_t lock;
411 unsigned min_index;
412 u32 *table;
413};
414
415extern struct irq_remap_table **irq_lookup_table;
416
417
418extern bool amd_iommu_irq_remap;
419
420
421extern struct kmem_cache *amd_iommu_irq_cache;
422
423
424
425
426#define for_each_iommu(iommu) \
427 list_for_each_entry((iommu), &amd_iommu_list, list)
428#define for_each_iommu_safe(iommu, next) \
429 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
430
431#define APERTURE_RANGE_SHIFT 27
432#define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
433#define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
434#define APERTURE_MAX_RANGES 32
435#define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
436#define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
437
438
439
440
441
442
443struct amd_iommu_fault {
444 u64 address;
445 u32 pasid;
446 u16 device_id;
447 u16 tag;
448 u16 flags;
449
450};
451
452
453struct iommu_domain;
454struct amd_irte_ops;
455
456#define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0)
457
458
459
460
461
462struct protection_domain {
463 struct list_head list;
464 struct list_head dev_list;
465 struct iommu_domain domain;
466
467 spinlock_t lock;
468 struct mutex api_lock;
469 u16 id;
470 int mode;
471 u64 *pt_root;
472 int glx;
473 u64 *gcr3_tbl;
474 unsigned long flags;
475 bool updated;
476 unsigned dev_cnt;
477 unsigned dev_iommu[MAX_IOMMUS];
478};
479
480
481
482
483
484struct amd_iommu {
485 struct list_head list;
486
487
488 int index;
489
490
491 spinlock_t lock;
492
493
494 struct pci_dev *dev;
495
496
497 struct pci_dev *root_pdev;
498
499
500 u64 mmio_phys;
501
502
503 u64 mmio_phys_end;
504
505
506 u8 __iomem *mmio_base;
507
508
509 u32 cap;
510
511
512 u8 acpi_flags;
513
514
515 u64 features;
516
517
518 bool is_iommu_v2;
519
520
521 u16 devid;
522
523
524
525
526
527
528 u16 cap_ptr;
529
530
531 u16 pci_seg;
532
533
534 u64 exclusion_start;
535
536 u64 exclusion_length;
537
538
539 u8 *cmd_buf;
540 u32 cmd_buf_head;
541 u32 cmd_buf_tail;
542
543
544 u8 *evt_buf;
545
546
547 u8 *ppr_log;
548
549
550 u8 *ga_log;
551
552
553 u8 *ga_log_tail;
554
555
556 bool int_enabled;
557
558
559 bool need_sync;
560
561
562 struct device *iommu_dev;
563
564
565
566
567
568
569
570 u32 stored_addr_lo;
571 u32 stored_addr_hi;
572
573
574
575
576
577 u32 stored_l1[6][0x12];
578
579
580 u32 stored_l2[0x83];
581
582
583 u8 max_banks;
584 u8 max_counters;
585
586 u32 flags;
587 volatile u64 __aligned(8) cmd_sem;
588
589 struct amd_irte_ops *irte_ops;
590};
591
592#define ACPIHID_UID_LEN 256
593#define ACPIHID_HID_LEN 9
594
595struct acpihid_map_entry {
596 struct list_head list;
597 u8 uid[ACPIHID_UID_LEN];
598 u8 hid[ACPIHID_HID_LEN];
599 u16 devid;
600 u16 root_devid;
601 bool cmd_line;
602 struct iommu_group *group;
603};
604
605struct devid_map {
606 struct list_head list;
607 u8 id;
608 u16 devid;
609 bool cmd_line;
610};
611
612
613
614
615struct iommu_dev_data {
616 struct list_head list;
617 struct list_head dev_data_list;
618 struct protection_domain *domain;
619 u16 devid;
620 u16 alias;
621 bool iommu_v2;
622 bool passthrough;
623 struct {
624 bool enabled;
625 int qdep;
626 } ats;
627 bool pri_tlp;
628
629 u32 errata;
630 bool use_vapic;
631 bool defer_attach;
632};
633
634
635extern struct list_head ioapic_map;
636extern struct list_head hpet_map;
637extern struct list_head acpihid_map;
638
639
640
641
642
643extern struct list_head amd_iommu_list;
644
645
646
647
648
649extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
650
651
652extern int amd_iommus_present;
653
654
655
656
657extern spinlock_t amd_iommu_pd_lock;
658extern struct list_head amd_iommu_pd_list;
659
660
661
662
663struct dev_table_entry {
664 u64 data[4];
665};
666
667
668
669
670struct unity_map_entry {
671 struct list_head list;
672
673
674 u16 devid_start;
675
676 u16 devid_end;
677
678
679 u64 address_start;
680
681 u64 address_end;
682
683
684 int prot;
685};
686
687
688
689
690
691extern struct list_head amd_iommu_unity_map;
692
693
694
695
696
697
698
699
700
701extern struct dev_table_entry *amd_iommu_dev_table;
702
703
704
705
706
707extern u16 *amd_iommu_alias_table;
708
709
710
711
712extern struct amd_iommu **amd_iommu_rlookup_table;
713
714
715extern unsigned amd_iommu_aperture_order;
716
717
718extern u16 amd_iommu_last_bdf;
719
720
721extern unsigned long *amd_iommu_pd_alloc_bitmap;
722
723
724
725
726
727extern u32 amd_iommu_unmap_flush;
728
729
730extern u32 amd_iommu_max_pasid;
731
732extern bool amd_iommu_v2_present;
733
734extern bool amd_iommu_force_isolation;
735
736
737extern int amd_iommu_max_glx_val;
738
739
740
741
742
743extern void iommu_flush_all_caches(struct amd_iommu *iommu);
744
745static inline int get_ioapic_devid(int id)
746{
747 struct devid_map *entry;
748
749 list_for_each_entry(entry, &ioapic_map, list) {
750 if (entry->id == id)
751 return entry->devid;
752 }
753
754 return -EINVAL;
755}
756
757static inline int get_hpet_devid(int id)
758{
759 struct devid_map *entry;
760
761 list_for_each_entry(entry, &hpet_map, list) {
762 if (entry->id == id)
763 return entry->devid;
764 }
765
766 return -EINVAL;
767}
768
769enum amd_iommu_intr_mode_type {
770 AMD_IOMMU_GUEST_IR_LEGACY,
771
772
773
774
775
776 AMD_IOMMU_GUEST_IR_LEGACY_GA,
777 AMD_IOMMU_GUEST_IR_VAPIC,
778};
779
780#define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
781 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
782
783#define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
784
785union irte {
786 u32 val;
787 struct {
788 u32 valid : 1,
789 no_fault : 1,
790 int_type : 3,
791 rq_eoi : 1,
792 dm : 1,
793 rsvd_1 : 1,
794 destination : 8,
795 vector : 8,
796 rsvd_2 : 8;
797 } fields;
798};
799
800union irte_ga_lo {
801 u64 val;
802
803
804 struct {
805 u64 valid : 1,
806 no_fault : 1,
807
808 int_type : 3,
809 rq_eoi : 1,
810 dm : 1,
811
812 guest_mode : 1,
813 destination : 8,
814 rsvd : 48;
815 } fields_remap;
816
817
818 struct {
819 u64 valid : 1,
820 no_fault : 1,
821
822 ga_log_intr : 1,
823 rsvd1 : 3,
824 is_run : 1,
825
826 guest_mode : 1,
827 destination : 8,
828 rsvd2 : 16,
829 ga_tag : 32;
830 } fields_vapic;
831};
832
833union irte_ga_hi {
834 u64 val;
835 struct {
836 u64 vector : 8,
837 rsvd_1 : 4,
838 ga_root_ptr : 40,
839 rsvd_2 : 12;
840 } fields;
841};
842
843struct irte_ga {
844 union irte_ga_lo lo;
845 union irte_ga_hi hi;
846};
847
848struct amd_ir_data {
849 u32 cached_ga_tag;
850 void *entry;
851 void *ref;
852 u16 pi_devid;
853};
854
855struct amd_irte_ops {
856 void (*prepare)(void *, int, u32, u32, u8, u32, int);
857 void (*activate)(void *, u16, u16);
858 void (*deactivate)(void *, u16, u16);
859 void (*set_affinity)(void *, u16, u16, u8, u32);
860 void *(*get)(struct irq_remap_table *, int);
861 void (*set_allocated)(struct irq_remap_table *, int);
862 bool (*is_allocated)(struct irq_remap_table *, int);
863 void (*clear_allocated)(struct irq_remap_table *, int);
864};
865
866#ifdef CONFIG_IRQ_REMAP
867extern struct amd_irte_ops irte_32_ops;
868extern struct amd_irte_ops irte_128_ops;
869#endif
870
871#endif
872