LXR linux/drivers/net/ethernet/chelsio/cxgb3/cxgb3

   1/*
   2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32#ifndef __CHIOCTL_H__
  33#define __CHIOCTL_H__
  34
  35/*
  36 * Ioctl commands specific to this driver.
  37 */
  38enum {
  39        CHELSIO_GETMTUTAB               = 1029,
  40        CHELSIO_SETMTUTAB               = 1030,
  41        CHELSIO_SET_PM                  = 1032,
  42        CHELSIO_GET_PM                  = 1033,
  43        CHELSIO_GET_MEM                 = 1038,
  44        CHELSIO_LOAD_FW                 = 1041,
  45        CHELSIO_SET_TRACE_FILTER        = 1044,
  46        CHELSIO_SET_QSET_PARAMS         = 1045,
  47        CHELSIO_GET_QSET_PARAMS         = 1046,
  48        CHELSIO_SET_QSET_NUM            = 1047,
  49        CHELSIO_GET_QSET_NUM            = 1048,
  50};
  51
  52struct ch_reg {
  53        uint32_t cmd;
  54        uint32_t addr;
  55        uint32_t val;
  56};
  57
  58struct ch_cntxt {
  59        uint32_t cmd;
  60        uint32_t cntxt_type;
  61        uint32_t cntxt_id;
  62        uint32_t data[4];
  63};
  64
  65/* context types */
  66enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ };
  67
  68struct ch_desc {
  69        uint32_t cmd;
  70        uint32_t queue_num;
  71        uint32_t idx;
  72        uint32_t size;
  73        uint8_t data[128];
  74};
  75
  76struct ch_mem_range {
  77        uint32_t cmd;
  78        uint32_t mem_id;
  79        uint32_t addr;
  80        uint32_t len;
  81        uint32_t version;
  82        uint8_t buf[0];
  83};
  84
  85struct ch_qset_params {
  86        uint32_t cmd;
  87        uint32_t qset_idx;
  88        int32_t txq_size[3];
  89        int32_t rspq_size;
  90        int32_t fl_size[2];
  91        int32_t intr_lat;
  92        int32_t polling;
  93        int32_t lro;
  94        int32_t cong_thres;
  95        int32_t  vector;
  96        int32_t  qnum;
  97};
  98
  99struct ch_pktsched_params {
 100        uint32_t cmd;
 101        uint8_t sched;
 102        uint8_t idx;
 103        uint8_t min;
 104        uint8_t max;
 105        uint8_t binding;
 106};
 107
 108#ifndef TCB_SIZE
 109# define TCB_SIZE   128
 110#endif
 111
 112/* TCB size in 32-bit words */
 113#define TCB_WORDS (TCB_SIZE / 4)
 114
 115enum { MEM_CM, MEM_PMRX, MEM_PMTX };    /* ch_mem_range.mem_id values */
 116
 117struct ch_mtus {
 118        uint32_t cmd;
 119        uint32_t nmtus;
 120        uint16_t mtus[NMTUS];
 121};
 122
 123struct ch_pm {
 124        uint32_t cmd;
 125        uint32_t tx_pg_sz;
 126        uint32_t tx_num_pg;
 127        uint32_t rx_pg_sz;
 128        uint32_t rx_num_pg;
 129        uint32_t pm_total;
 130};
 131
 132struct ch_tcam {
 133        uint32_t cmd;
 134        uint32_t tcam_size;
 135        uint32_t nservers;
 136        uint32_t nroutes;
 137        uint32_t nfilters;
 138};
 139
 140struct ch_tcb {
 141        uint32_t cmd;
 142        uint32_t tcb_index;
 143        uint32_t tcb_data[TCB_WORDS];
 144};
 145
 146struct ch_tcam_word {
 147        uint32_t cmd;
 148        uint32_t addr;
 149        uint32_t buf[3];
 150};
 151
 152struct ch_trace {
 153        uint32_t cmd;
 154        uint32_t sip;
 155        uint32_t sip_mask;
 156        uint32_t dip;
 157        uint32_t dip_mask;
 158        uint16_t sport;
 159        uint16_t sport_mask;
 160        uint16_t dport;
 161        uint16_t dport_mask;
 162        uint32_t vlan:12;
 163        uint32_t vlan_mask:12;
 164        uint32_t intf:4;
 165        uint32_t intf_mask:4;
 166        uint8_t proto;
 167        uint8_t proto_mask;
 168        uint8_t invert_match:1;
 169        uint8_t config_tx:1;
 170        uint8_t config_rx:1;
 171        uint8_t trace_tx:1;
 172        uint8_t trace_rx:1;
 173};
 174
 175#define SIOCCHIOCTL SIOCDEVPRIVATE
 176
 177#endif
 178