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34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
38#include <linux/slab.h>
39#include <linux/hash.h>
40#include <net/ip.h>
41#include <net/busy_poll.h>
42#include <net/vxlan.h>
43#include <net/devlink.h>
44
45#include <linux/mlx4/driver.h>
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/cmd.h>
48#include <linux/mlx4/cq.h>
49
50#include "mlx4_en.h"
51#include "en_port.h"
52
53int mlx4_en_setup_tc(struct net_device *dev, u8 up)
54{
55 struct mlx4_en_priv *priv = netdev_priv(dev);
56 int i;
57 unsigned int offset = 0;
58
59 if (up && up != MLX4_EN_NUM_UP_HIGH)
60 return -EINVAL;
61
62 netdev_set_num_tc(dev, up);
63 netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
64
65 for (i = 0; i < up; i++) {
66 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
67 offset += priv->num_tx_rings_p_up;
68 }
69
70#ifdef CONFIG_MLX4_EN_DCB
71 if (!mlx4_is_slave(priv->mdev->dev)) {
72 if (up) {
73 if (priv->dcbx_cap)
74 priv->flags |= MLX4_EN_FLAG_DCB_ENABLED;
75 } else {
76 priv->flags &= ~MLX4_EN_FLAG_DCB_ENABLED;
77 priv->cee_config.pfc_state = false;
78 }
79 }
80#endif
81
82 return 0;
83}
84
85int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc)
86{
87 struct mlx4_en_priv *priv = netdev_priv(dev);
88 struct mlx4_en_dev *mdev = priv->mdev;
89 struct mlx4_en_port_profile new_prof;
90 struct mlx4_en_priv *tmp;
91 int port_up = 0;
92 int err = 0;
93
94 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
95 if (!tmp)
96 return -ENOMEM;
97
98 mutex_lock(&mdev->state_lock);
99 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
100 new_prof.num_up = (tc == 0) ? MLX4_EN_NUM_UP_LOW :
101 MLX4_EN_NUM_UP_HIGH;
102 new_prof.tx_ring_num[TX] = new_prof.num_tx_rings_p_up *
103 new_prof.num_up;
104 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof);
105 if (err)
106 goto out;
107
108 if (priv->port_up) {
109 port_up = 1;
110 mlx4_en_stop_port(dev, 1);
111 }
112
113 mlx4_en_safe_replace_resources(priv, tmp);
114 if (port_up) {
115 err = mlx4_en_start_port(dev);
116 if (err) {
117 en_err(priv, "Failed starting port for setup TC\n");
118 goto out;
119 }
120 }
121
122 err = mlx4_en_setup_tc(dev, tc);
123out:
124 mutex_unlock(&mdev->state_lock);
125 kfree(tmp);
126 return err;
127}
128
129static int __mlx4_en_setup_tc(struct net_device *dev, enum tc_setup_type type,
130 void *type_data)
131{
132 struct tc_mqprio_qopt *mqprio = type_data;
133
134 if (type != TC_SETUP_MQPRIO)
135 return -EOPNOTSUPP;
136
137 if (mqprio->num_tc && mqprio->num_tc != MLX4_EN_NUM_UP_HIGH)
138 return -EINVAL;
139
140 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
141
142 return mlx4_en_alloc_tx_queue_per_tc(dev, mqprio->num_tc);
143}
144
145#ifdef CONFIG_RFS_ACCEL
146
147struct mlx4_en_filter {
148 struct list_head next;
149 struct work_struct work;
150
151 u8 ip_proto;
152 __be32 src_ip;
153 __be32 dst_ip;
154 __be16 src_port;
155 __be16 dst_port;
156
157 int rxq_index;
158 struct mlx4_en_priv *priv;
159 u32 flow_id;
160 int id;
161 u64 reg_id;
162 u8 activated;
163
164
165 struct hlist_node filter_chain;
166};
167
168static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
169
170static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
171{
172 switch (ip_proto) {
173 case IPPROTO_UDP:
174 return MLX4_NET_TRANS_RULE_ID_UDP;
175 case IPPROTO_TCP:
176 return MLX4_NET_TRANS_RULE_ID_TCP;
177 default:
178 return MLX4_NET_TRANS_RULE_NUM;
179 }
180};
181
182
183
184
185static void mlx4_en_filter_work(struct work_struct *work)
186{
187 struct mlx4_en_filter *filter = container_of(work,
188 struct mlx4_en_filter,
189 work);
190 struct mlx4_en_priv *priv = filter->priv;
191 struct mlx4_spec_list spec_tcp_udp = {
192 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
193 {
194 .tcp_udp = {
195 .dst_port = filter->dst_port,
196 .dst_port_msk = (__force __be16)-1,
197 .src_port = filter->src_port,
198 .src_port_msk = (__force __be16)-1,
199 },
200 },
201 };
202 struct mlx4_spec_list spec_ip = {
203 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
204 {
205 .ipv4 = {
206 .dst_ip = filter->dst_ip,
207 .dst_ip_msk = (__force __be32)-1,
208 .src_ip = filter->src_ip,
209 .src_ip_msk = (__force __be32)-1,
210 },
211 },
212 };
213 struct mlx4_spec_list spec_eth = {
214 .id = MLX4_NET_TRANS_RULE_ID_ETH,
215 };
216 struct mlx4_net_trans_rule rule = {
217 .list = LIST_HEAD_INIT(rule.list),
218 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
219 .exclusive = 1,
220 .allow_loopback = 1,
221 .promisc_mode = MLX4_FS_REGULAR,
222 .port = priv->port,
223 .priority = MLX4_DOMAIN_RFS,
224 };
225 int rc;
226 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
227
228 if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
229 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
230 filter->ip_proto);
231 goto ignore;
232 }
233 list_add_tail(&spec_eth.list, &rule.list);
234 list_add_tail(&spec_ip.list, &rule.list);
235 list_add_tail(&spec_tcp_udp.list, &rule.list);
236
237 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
238 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
239 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
240
241 filter->activated = 0;
242
243 if (filter->reg_id) {
244 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
245 if (rc && rc != -ENOENT)
246 en_err(priv, "Error detaching flow. rc = %d\n", rc);
247 }
248
249 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
250 if (rc)
251 en_err(priv, "Error attaching flow. err = %d\n", rc);
252
253ignore:
254 mlx4_en_filter_rfs_expire(priv);
255
256 filter->activated = 1;
257}
258
259static inline struct hlist_head *
260filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
261 __be16 src_port, __be16 dst_port)
262{
263 unsigned long l;
264 int bucket_idx;
265
266 l = (__force unsigned long)src_port |
267 ((__force unsigned long)dst_port << 2);
268 l ^= (__force unsigned long)(src_ip ^ dst_ip);
269
270 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
271
272 return &priv->filter_hash[bucket_idx];
273}
274
275static struct mlx4_en_filter *
276mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
277 __be32 dst_ip, u8 ip_proto, __be16 src_port,
278 __be16 dst_port, u32 flow_id)
279{
280 struct mlx4_en_filter *filter = NULL;
281
282 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
283 if (!filter)
284 return NULL;
285
286 filter->priv = priv;
287 filter->rxq_index = rxq_index;
288 INIT_WORK(&filter->work, mlx4_en_filter_work);
289
290 filter->src_ip = src_ip;
291 filter->dst_ip = dst_ip;
292 filter->ip_proto = ip_proto;
293 filter->src_port = src_port;
294 filter->dst_port = dst_port;
295
296 filter->flow_id = flow_id;
297
298 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
299
300 list_add_tail(&filter->next, &priv->filters);
301 hlist_add_head(&filter->filter_chain,
302 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
303 dst_port));
304
305 return filter;
306}
307
308static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
309{
310 struct mlx4_en_priv *priv = filter->priv;
311 int rc;
312
313 list_del(&filter->next);
314
315 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
316 if (rc && rc != -ENOENT)
317 en_err(priv, "Error detaching flow. rc = %d\n", rc);
318
319 kfree(filter);
320}
321
322static inline struct mlx4_en_filter *
323mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
324 u8 ip_proto, __be16 src_port, __be16 dst_port)
325{
326 struct mlx4_en_filter *filter;
327 struct mlx4_en_filter *ret = NULL;
328
329 hlist_for_each_entry(filter,
330 filter_hash_bucket(priv, src_ip, dst_ip,
331 src_port, dst_port),
332 filter_chain) {
333 if (filter->src_ip == src_ip &&
334 filter->dst_ip == dst_ip &&
335 filter->ip_proto == ip_proto &&
336 filter->src_port == src_port &&
337 filter->dst_port == dst_port) {
338 ret = filter;
339 break;
340 }
341 }
342
343 return ret;
344}
345
346static int
347mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
348 u16 rxq_index, u32 flow_id)
349{
350 struct mlx4_en_priv *priv = netdev_priv(net_dev);
351 struct mlx4_en_filter *filter;
352 const struct iphdr *ip;
353 const __be16 *ports;
354 u8 ip_proto;
355 __be32 src_ip;
356 __be32 dst_ip;
357 __be16 src_port;
358 __be16 dst_port;
359 int nhoff = skb_network_offset(skb);
360 int ret = 0;
361
362 if (skb->protocol != htons(ETH_P_IP))
363 return -EPROTONOSUPPORT;
364
365 ip = (const struct iphdr *)(skb->data + nhoff);
366 if (ip_is_fragment(ip))
367 return -EPROTONOSUPPORT;
368
369 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
370 return -EPROTONOSUPPORT;
371 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
372
373 ip_proto = ip->protocol;
374 src_ip = ip->saddr;
375 dst_ip = ip->daddr;
376 src_port = ports[0];
377 dst_port = ports[1];
378
379 spin_lock_bh(&priv->filters_lock);
380 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
381 src_port, dst_port);
382 if (filter) {
383 if (filter->rxq_index == rxq_index)
384 goto out;
385
386 filter->rxq_index = rxq_index;
387 } else {
388 filter = mlx4_en_filter_alloc(priv, rxq_index,
389 src_ip, dst_ip, ip_proto,
390 src_port, dst_port, flow_id);
391 if (!filter) {
392 ret = -ENOMEM;
393 goto err;
394 }
395 }
396
397 queue_work(priv->mdev->workqueue, &filter->work);
398
399out:
400 ret = filter->id;
401err:
402 spin_unlock_bh(&priv->filters_lock);
403
404 return ret;
405}
406
407void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
408{
409 struct mlx4_en_filter *filter, *tmp;
410 LIST_HEAD(del_list);
411
412 spin_lock_bh(&priv->filters_lock);
413 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
414 list_move(&filter->next, &del_list);
415 hlist_del(&filter->filter_chain);
416 }
417 spin_unlock_bh(&priv->filters_lock);
418
419 list_for_each_entry_safe(filter, tmp, &del_list, next) {
420 cancel_work_sync(&filter->work);
421 mlx4_en_filter_free(filter);
422 }
423}
424
425static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
426{
427 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
428 LIST_HEAD(del_list);
429 int i = 0;
430
431 spin_lock_bh(&priv->filters_lock);
432 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
433 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
434 break;
435
436 if (filter->activated &&
437 !work_pending(&filter->work) &&
438 rps_may_expire_flow(priv->dev,
439 filter->rxq_index, filter->flow_id,
440 filter->id)) {
441 list_move(&filter->next, &del_list);
442 hlist_del(&filter->filter_chain);
443 } else
444 last_filter = filter;
445
446 i++;
447 }
448
449 if (last_filter && (&last_filter->next != priv->filters.next))
450 list_move(&priv->filters, &last_filter->next);
451
452 spin_unlock_bh(&priv->filters_lock);
453
454 list_for_each_entry_safe(filter, tmp, &del_list, next)
455 mlx4_en_filter_free(filter);
456}
457#endif
458
459static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
460 __be16 proto, u16 vid)
461{
462 struct mlx4_en_priv *priv = netdev_priv(dev);
463 struct mlx4_en_dev *mdev = priv->mdev;
464 int err;
465 int idx;
466
467 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
468
469 set_bit(vid, priv->active_vlans);
470
471
472 mutex_lock(&mdev->state_lock);
473 if (mdev->device_up && priv->port_up) {
474 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
475 if (err) {
476 en_err(priv, "Failed configuring VLAN filter\n");
477 goto out;
478 }
479 }
480 err = mlx4_register_vlan(mdev->dev, priv->port, vid, &idx);
481 if (err)
482 en_dbg(HW, priv, "Failed adding vlan %d\n", vid);
483
484out:
485 mutex_unlock(&mdev->state_lock);
486 return err;
487}
488
489static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
490 __be16 proto, u16 vid)
491{
492 struct mlx4_en_priv *priv = netdev_priv(dev);
493 struct mlx4_en_dev *mdev = priv->mdev;
494 int err = 0;
495
496 en_dbg(HW, priv, "Killing VID:%d\n", vid);
497
498 clear_bit(vid, priv->active_vlans);
499
500
501 mutex_lock(&mdev->state_lock);
502 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
503
504 if (mdev->device_up && priv->port_up) {
505 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
506 if (err)
507 en_err(priv, "Failed configuring VLAN filter\n");
508 }
509 mutex_unlock(&mdev->state_lock);
510
511 return err;
512}
513
514static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
515{
516 int i;
517 for (i = ETH_ALEN - 1; i >= 0; --i) {
518 dst_mac[i] = src_mac & 0xff;
519 src_mac >>= 8;
520 }
521 memset(&dst_mac[ETH_ALEN], 0, 2);
522}
523
524
525static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
526 int qpn, u64 *reg_id)
527{
528 int err;
529
530 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
531 priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
532 return 0;
533
534 err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
535 MLX4_DOMAIN_NIC, reg_id);
536 if (err) {
537 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
538 return err;
539 }
540 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
541 return 0;
542}
543
544
545static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
546 unsigned char *mac, int *qpn, u64 *reg_id)
547{
548 struct mlx4_en_dev *mdev = priv->mdev;
549 struct mlx4_dev *dev = mdev->dev;
550 int err;
551
552 switch (dev->caps.steering_mode) {
553 case MLX4_STEERING_MODE_B0: {
554 struct mlx4_qp qp;
555 u8 gid[16] = {0};
556
557 qp.qpn = *qpn;
558 memcpy(&gid[10], mac, ETH_ALEN);
559 gid[5] = priv->port;
560
561 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
562 break;
563 }
564 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
565 struct mlx4_spec_list spec_eth = { {NULL} };
566 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
567
568 struct mlx4_net_trans_rule rule = {
569 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
570 .exclusive = 0,
571 .allow_loopback = 1,
572 .promisc_mode = MLX4_FS_REGULAR,
573 .priority = MLX4_DOMAIN_NIC,
574 };
575
576 rule.port = priv->port;
577 rule.qpn = *qpn;
578 INIT_LIST_HEAD(&rule.list);
579
580 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
581 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
582 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
583 list_add_tail(&spec_eth.list, &rule.list);
584
585 err = mlx4_flow_attach(dev, &rule, reg_id);
586 break;
587 }
588 default:
589 return -EINVAL;
590 }
591 if (err)
592 en_warn(priv, "Failed Attaching Unicast\n");
593
594 return err;
595}
596
597static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
598 unsigned char *mac, int qpn, u64 reg_id)
599{
600 struct mlx4_en_dev *mdev = priv->mdev;
601 struct mlx4_dev *dev = mdev->dev;
602
603 switch (dev->caps.steering_mode) {
604 case MLX4_STEERING_MODE_B0: {
605 struct mlx4_qp qp;
606 u8 gid[16] = {0};
607
608 qp.qpn = qpn;
609 memcpy(&gid[10], mac, ETH_ALEN);
610 gid[5] = priv->port;
611
612 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
613 break;
614 }
615 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
616 mlx4_flow_detach(dev, reg_id);
617 break;
618 }
619 default:
620 en_err(priv, "Invalid steering mode.\n");
621 }
622}
623
624static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
625{
626 struct mlx4_en_dev *mdev = priv->mdev;
627 struct mlx4_dev *dev = mdev->dev;
628 int index = 0;
629 int err = 0;
630 int *qpn = &priv->base_qpn;
631 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
632
633 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
634 priv->dev->dev_addr);
635 index = mlx4_register_mac(dev, priv->port, mac);
636 if (index < 0) {
637 err = index;
638 en_err(priv, "Failed adding MAC: %pM\n",
639 priv->dev->dev_addr);
640 return err;
641 }
642
643 en_info(priv, "Steering Mode %d\n", dev->caps.steering_mode);
644
645 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
646 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
647 *qpn = base_qpn + index;
648 return 0;
649 }
650
651 err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP,
652 MLX4_RES_USAGE_DRIVER);
653 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
654 if (err) {
655 en_err(priv, "Failed to reserve qp for mac registration\n");
656 mlx4_unregister_mac(dev, priv->port, mac);
657 return err;
658 }
659
660 return 0;
661}
662
663static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
664{
665 struct mlx4_en_dev *mdev = priv->mdev;
666 struct mlx4_dev *dev = mdev->dev;
667 int qpn = priv->base_qpn;
668
669 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
670 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
671 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
672 priv->dev->dev_addr);
673 mlx4_unregister_mac(dev, priv->port, mac);
674 } else {
675 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
676 priv->port, qpn);
677 mlx4_qp_release_range(dev, qpn, 1);
678 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
679 }
680}
681
682static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
683 unsigned char *new_mac, unsigned char *prev_mac)
684{
685 struct mlx4_en_dev *mdev = priv->mdev;
686 struct mlx4_dev *dev = mdev->dev;
687 int err = 0;
688 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
689
690 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
691 struct hlist_head *bucket;
692 unsigned int mac_hash;
693 struct mlx4_mac_entry *entry;
694 struct hlist_node *tmp;
695 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
696
697 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
698 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
699 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
700 mlx4_en_uc_steer_release(priv, entry->mac,
701 qpn, entry->reg_id);
702 mlx4_unregister_mac(dev, priv->port,
703 prev_mac_u64);
704 hlist_del_rcu(&entry->hlist);
705 synchronize_rcu();
706 memcpy(entry->mac, new_mac, ETH_ALEN);
707 entry->reg_id = 0;
708 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
709 hlist_add_head_rcu(&entry->hlist,
710 &priv->mac_hash[mac_hash]);
711 mlx4_register_mac(dev, priv->port, new_mac_u64);
712 err = mlx4_en_uc_steer_add(priv, new_mac,
713 &qpn,
714 &entry->reg_id);
715 if (err)
716 return err;
717 if (priv->tunnel_reg_id) {
718 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
719 priv->tunnel_reg_id = 0;
720 }
721 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
722 &priv->tunnel_reg_id);
723 return err;
724 }
725 }
726 return -EINVAL;
727 }
728
729 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
730}
731
732static void mlx4_en_update_user_mac(struct mlx4_en_priv *priv,
733 unsigned char new_mac[ETH_ALEN + 2])
734{
735 struct mlx4_en_dev *mdev = priv->mdev;
736 int err;
737
738 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_USER_MAC_EN))
739 return;
740
741 err = mlx4_SET_PORT_user_mac(mdev->dev, priv->port, new_mac);
742 if (err)
743 en_err(priv, "Failed to pass user MAC(%pM) to Firmware for port %d, with error %d\n",
744 new_mac, priv->port, err);
745}
746
747static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
748 unsigned char new_mac[ETH_ALEN + 2])
749{
750 int err = 0;
751
752 if (priv->port_up) {
753
754 err = mlx4_en_replace_mac(priv, priv->base_qpn,
755 new_mac, priv->current_mac);
756 if (err)
757 en_err(priv, "Failed changing HW MAC address\n");
758 } else
759 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
760
761 if (!err)
762 memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
763
764 return err;
765}
766
767static int mlx4_en_set_mac(struct net_device *dev, void *addr)
768{
769 struct mlx4_en_priv *priv = netdev_priv(dev);
770 struct mlx4_en_dev *mdev = priv->mdev;
771 struct sockaddr *saddr = addr;
772 unsigned char new_mac[ETH_ALEN + 2];
773 int err;
774
775 if (!is_valid_ether_addr(saddr->sa_data))
776 return -EADDRNOTAVAIL;
777
778 mutex_lock(&mdev->state_lock);
779 memcpy(new_mac, saddr->sa_data, ETH_ALEN);
780 err = mlx4_en_do_set_mac(priv, new_mac);
781 if (err)
782 goto out;
783
784 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
785 mlx4_en_update_user_mac(priv, new_mac);
786out:
787 mutex_unlock(&mdev->state_lock);
788
789 return err;
790}
791
792static void mlx4_en_clear_list(struct net_device *dev)
793{
794 struct mlx4_en_priv *priv = netdev_priv(dev);
795 struct mlx4_en_mc_list *tmp, *mc_to_del;
796
797 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
798 list_del(&mc_to_del->list);
799 kfree(mc_to_del);
800 }
801}
802
803static void mlx4_en_cache_mclist(struct net_device *dev)
804{
805 struct mlx4_en_priv *priv = netdev_priv(dev);
806 struct netdev_hw_addr *ha;
807 struct mlx4_en_mc_list *tmp;
808
809 mlx4_en_clear_list(dev);
810 netdev_for_each_mc_addr(ha, dev) {
811 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
812 if (!tmp) {
813 mlx4_en_clear_list(dev);
814 return;
815 }
816 memcpy(tmp->addr, ha->addr, ETH_ALEN);
817 list_add_tail(&tmp->list, &priv->mc_list);
818 }
819}
820
821static void update_mclist_flags(struct mlx4_en_priv *priv,
822 struct list_head *dst,
823 struct list_head *src)
824{
825 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
826 bool found;
827
828
829
830
831 list_for_each_entry(dst_tmp, dst, list) {
832 found = false;
833 list_for_each_entry(src_tmp, src, list) {
834 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
835 found = true;
836 break;
837 }
838 }
839 if (!found)
840 dst_tmp->action = MCLIST_REM;
841 }
842
843
844
845
846 list_for_each_entry(src_tmp, src, list) {
847 found = false;
848 list_for_each_entry(dst_tmp, dst, list) {
849 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
850 dst_tmp->action = MCLIST_NONE;
851 found = true;
852 break;
853 }
854 }
855 if (!found) {
856 new_mc = kmemdup(src_tmp,
857 sizeof(struct mlx4_en_mc_list),
858 GFP_KERNEL);
859 if (!new_mc)
860 return;
861
862 new_mc->action = MCLIST_ADD;
863 list_add_tail(&new_mc->list, dst);
864 }
865 }
866}
867
868static void mlx4_en_set_rx_mode(struct net_device *dev)
869{
870 struct mlx4_en_priv *priv = netdev_priv(dev);
871
872 if (!priv->port_up)
873 return;
874
875 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
876}
877
878static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
879 struct mlx4_en_dev *mdev)
880{
881 int err = 0;
882
883 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
884 if (netif_msg_rx_status(priv))
885 en_warn(priv, "Entering promiscuous mode\n");
886 priv->flags |= MLX4_EN_FLAG_PROMISC;
887
888
889 switch (mdev->dev->caps.steering_mode) {
890 case MLX4_STEERING_MODE_DEVICE_MANAGED:
891 err = mlx4_flow_steer_promisc_add(mdev->dev,
892 priv->port,
893 priv->base_qpn,
894 MLX4_FS_ALL_DEFAULT);
895 if (err)
896 en_err(priv, "Failed enabling promiscuous mode\n");
897 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
898 break;
899
900 case MLX4_STEERING_MODE_B0:
901 err = mlx4_unicast_promisc_add(mdev->dev,
902 priv->base_qpn,
903 priv->port);
904 if (err)
905 en_err(priv, "Failed enabling unicast promiscuous mode\n");
906
907
908
909
910 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
911 err = mlx4_multicast_promisc_add(mdev->dev,
912 priv->base_qpn,
913 priv->port);
914 if (err)
915 en_err(priv, "Failed enabling multicast promiscuous mode\n");
916 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
917 }
918 break;
919
920 case MLX4_STEERING_MODE_A0:
921 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
922 priv->port,
923 priv->base_qpn,
924 1);
925 if (err)
926 en_err(priv, "Failed enabling promiscuous mode\n");
927 break;
928 }
929
930
931 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
932 0, MLX4_MCAST_DISABLE);
933 if (err)
934 en_err(priv, "Failed disabling multicast filter\n");
935 }
936}
937
938static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
939 struct mlx4_en_dev *mdev)
940{
941 int err = 0;
942
943 if (netif_msg_rx_status(priv))
944 en_warn(priv, "Leaving promiscuous mode\n");
945 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
946
947
948 switch (mdev->dev->caps.steering_mode) {
949 case MLX4_STEERING_MODE_DEVICE_MANAGED:
950 err = mlx4_flow_steer_promisc_remove(mdev->dev,
951 priv->port,
952 MLX4_FS_ALL_DEFAULT);
953 if (err)
954 en_err(priv, "Failed disabling promiscuous mode\n");
955 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
956 break;
957
958 case MLX4_STEERING_MODE_B0:
959 err = mlx4_unicast_promisc_remove(mdev->dev,
960 priv->base_qpn,
961 priv->port);
962 if (err)
963 en_err(priv, "Failed disabling unicast promiscuous mode\n");
964
965 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
966 err = mlx4_multicast_promisc_remove(mdev->dev,
967 priv->base_qpn,
968 priv->port);
969 if (err)
970 en_err(priv, "Failed disabling multicast promiscuous mode\n");
971 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
972 }
973 break;
974
975 case MLX4_STEERING_MODE_A0:
976 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
977 priv->port,
978 priv->base_qpn, 0);
979 if (err)
980 en_err(priv, "Failed disabling promiscuous mode\n");
981 break;
982 }
983}
984
985static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
986 struct net_device *dev,
987 struct mlx4_en_dev *mdev)
988{
989 struct mlx4_en_mc_list *mclist, *tmp;
990 u64 mcast_addr = 0;
991 u8 mc_list[16] = {0};
992 int err = 0;
993
994
995 if (dev->flags & IFF_ALLMULTI) {
996 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
997 0, MLX4_MCAST_DISABLE);
998 if (err)
999 en_err(priv, "Failed disabling multicast filter\n");
1000
1001
1002 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
1003 switch (mdev->dev->caps.steering_mode) {
1004 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1005 err = mlx4_flow_steer_promisc_add(mdev->dev,
1006 priv->port,
1007 priv->base_qpn,
1008 MLX4_FS_MC_DEFAULT);
1009 break;
1010
1011 case MLX4_STEERING_MODE_B0:
1012 err = mlx4_multicast_promisc_add(mdev->dev,
1013 priv->base_qpn,
1014 priv->port);
1015 break;
1016
1017 case MLX4_STEERING_MODE_A0:
1018 break;
1019 }
1020 if (err)
1021 en_err(priv, "Failed entering multicast promisc mode\n");
1022 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1023 }
1024 } else {
1025
1026 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1027 switch (mdev->dev->caps.steering_mode) {
1028 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1029 err = mlx4_flow_steer_promisc_remove(mdev->dev,
1030 priv->port,
1031 MLX4_FS_MC_DEFAULT);
1032 break;
1033
1034 case MLX4_STEERING_MODE_B0:
1035 err = mlx4_multicast_promisc_remove(mdev->dev,
1036 priv->base_qpn,
1037 priv->port);
1038 break;
1039
1040 case MLX4_STEERING_MODE_A0:
1041 break;
1042 }
1043 if (err)
1044 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1045 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1046 }
1047
1048 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1049 0, MLX4_MCAST_DISABLE);
1050 if (err)
1051 en_err(priv, "Failed disabling multicast filter\n");
1052
1053
1054 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1055 1, MLX4_MCAST_CONFIG);
1056
1057
1058
1059 netif_addr_lock_bh(dev);
1060 mlx4_en_cache_mclist(dev);
1061 netif_addr_unlock_bh(dev);
1062 list_for_each_entry(mclist, &priv->mc_list, list) {
1063 mcast_addr = mlx4_mac_to_u64(mclist->addr);
1064 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1065 mcast_addr, 0, MLX4_MCAST_CONFIG);
1066 }
1067 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1068 0, MLX4_MCAST_ENABLE);
1069 if (err)
1070 en_err(priv, "Failed enabling multicast filter\n");
1071
1072 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1073 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1074 if (mclist->action == MCLIST_REM) {
1075
1076 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1077 mc_list[5] = priv->port;
1078 err = mlx4_multicast_detach(mdev->dev,
1079 priv->rss_map.indir_qp,
1080 mc_list,
1081 MLX4_PROT_ETH,
1082 mclist->reg_id);
1083 if (err)
1084 en_err(priv, "Fail to detach multicast address\n");
1085
1086 if (mclist->tunnel_reg_id) {
1087 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1088 if (err)
1089 en_err(priv, "Failed to detach multicast address\n");
1090 }
1091
1092
1093 list_del(&mclist->list);
1094 kfree(mclist);
1095 } else if (mclist->action == MCLIST_ADD) {
1096
1097 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1098
1099 mc_list[5] = priv->port;
1100 err = mlx4_multicast_attach(mdev->dev,
1101 priv->rss_map.indir_qp,
1102 mc_list,
1103 priv->port, 0,
1104 MLX4_PROT_ETH,
1105 &mclist->reg_id);
1106 if (err)
1107 en_err(priv, "Fail to attach multicast address\n");
1108
1109 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1110 &mclist->tunnel_reg_id);
1111 if (err)
1112 en_err(priv, "Failed to attach multicast address\n");
1113 }
1114 }
1115 }
1116}
1117
1118static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1119 struct net_device *dev,
1120 struct mlx4_en_dev *mdev)
1121{
1122 struct netdev_hw_addr *ha;
1123 struct mlx4_mac_entry *entry;
1124 struct hlist_node *tmp;
1125 bool found;
1126 u64 mac;
1127 int err = 0;
1128 struct hlist_head *bucket;
1129 unsigned int i;
1130 int removed = 0;
1131 u32 prev_flags;
1132
1133
1134
1135
1136
1137
1138 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1139 bucket = &priv->mac_hash[i];
1140 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
1141 found = false;
1142 netdev_for_each_uc_addr(ha, dev) {
1143 if (ether_addr_equal_64bits(entry->mac,
1144 ha->addr)) {
1145 found = true;
1146 break;
1147 }
1148 }
1149
1150
1151 if (ether_addr_equal_64bits(entry->mac,
1152 priv->current_mac))
1153 found = true;
1154
1155 if (!found) {
1156 mac = mlx4_mac_to_u64(entry->mac);
1157 mlx4_en_uc_steer_release(priv, entry->mac,
1158 priv->base_qpn,
1159 entry->reg_id);
1160 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1161
1162 hlist_del_rcu(&entry->hlist);
1163 kfree_rcu(entry, rcu);
1164 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1165 entry->mac, priv->port);
1166 ++removed;
1167 }
1168 }
1169 }
1170
1171
1172
1173
1174 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1175 return;
1176
1177 prev_flags = priv->flags;
1178 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1179
1180
1181 netdev_for_each_uc_addr(ha, dev) {
1182 found = false;
1183 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
1184 hlist_for_each_entry(entry, bucket, hlist) {
1185 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1186 found = true;
1187 break;
1188 }
1189 }
1190
1191 if (!found) {
1192 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1193 if (!entry) {
1194 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1195 ha->addr, priv->port);
1196 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1197 break;
1198 }
1199 mac = mlx4_mac_to_u64(ha->addr);
1200 memcpy(entry->mac, ha->addr, ETH_ALEN);
1201 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1202 if (err < 0) {
1203 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1204 ha->addr, priv->port, err);
1205 kfree(entry);
1206 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1207 break;
1208 }
1209 err = mlx4_en_uc_steer_add(priv, ha->addr,
1210 &priv->base_qpn,
1211 &entry->reg_id);
1212 if (err) {
1213 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1214 ha->addr, priv->port, err);
1215 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1216 kfree(entry);
1217 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1218 break;
1219 } else {
1220 unsigned int mac_hash;
1221 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1222 ha->addr, priv->port);
1223 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1224 bucket = &priv->mac_hash[mac_hash];
1225 hlist_add_head_rcu(&entry->hlist, bucket);
1226 }
1227 }
1228 }
1229
1230 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1231 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1232 priv->port);
1233 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1234 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1235 priv->port);
1236 }
1237}
1238
1239static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1240{
1241 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1242 rx_mode_task);
1243 struct mlx4_en_dev *mdev = priv->mdev;
1244 struct net_device *dev = priv->dev;
1245
1246 mutex_lock(&mdev->state_lock);
1247 if (!mdev->device_up) {
1248 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1249 goto out;
1250 }
1251 if (!priv->port_up) {
1252 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1253 goto out;
1254 }
1255
1256 if (!netif_carrier_ok(dev)) {
1257 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1258 if (priv->port_state.link_state) {
1259 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1260 netif_carrier_on(dev);
1261 en_dbg(LINK, priv, "Link Up\n");
1262 }
1263 }
1264 }
1265
1266 if (dev->priv_flags & IFF_UNICAST_FLT)
1267 mlx4_en_do_uc_filter(priv, dev, mdev);
1268
1269
1270 if ((dev->flags & IFF_PROMISC) ||
1271 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
1272 mlx4_en_set_promisc_mode(priv, mdev);
1273 goto out;
1274 }
1275
1276
1277 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1278 mlx4_en_clear_promisc_mode(priv, mdev);
1279
1280 mlx4_en_do_multicast(priv, dev, mdev);
1281out:
1282 mutex_unlock(&mdev->state_lock);
1283}
1284
1285#ifdef CONFIG_NET_POLL_CONTROLLER
1286static void mlx4_en_netpoll(struct net_device *dev)
1287{
1288 struct mlx4_en_priv *priv = netdev_priv(dev);
1289 struct mlx4_en_cq *cq;
1290 int i;
1291
1292 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
1293 cq = priv->tx_cq[TX][i];
1294 napi_schedule(&cq->napi);
1295 }
1296}
1297#endif
1298
1299static int mlx4_en_set_rss_steer_rules(struct mlx4_en_priv *priv)
1300{
1301 u64 reg_id;
1302 int err = 0;
1303 int *qpn = &priv->base_qpn;
1304 struct mlx4_mac_entry *entry;
1305
1306 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, ®_id);
1307 if (err)
1308 return err;
1309
1310 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
1311 &priv->tunnel_reg_id);
1312 if (err)
1313 goto tunnel_err;
1314
1315 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1316 if (!entry) {
1317 err = -ENOMEM;
1318 goto alloc_err;
1319 }
1320
1321 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
1322 memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
1323 entry->reg_id = reg_id;
1324 hlist_add_head_rcu(&entry->hlist,
1325 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
1326
1327 return 0;
1328
1329alloc_err:
1330 if (priv->tunnel_reg_id)
1331 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1332
1333tunnel_err:
1334 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
1335 return err;
1336}
1337
1338static void mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv *priv)
1339{
1340 u64 mac;
1341 unsigned int i;
1342 int qpn = priv->base_qpn;
1343 struct hlist_head *bucket;
1344 struct hlist_node *tmp;
1345 struct mlx4_mac_entry *entry;
1346
1347 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1348 bucket = &priv->mac_hash[i];
1349 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
1350 mac = mlx4_mac_to_u64(entry->mac);
1351 en_dbg(DRV, priv, "Registering MAC:%pM for deleting\n",
1352 entry->mac);
1353 mlx4_en_uc_steer_release(priv, entry->mac,
1354 qpn, entry->reg_id);
1355
1356 mlx4_unregister_mac(priv->mdev->dev, priv->port, mac);
1357 hlist_del_rcu(&entry->hlist);
1358 kfree_rcu(entry, rcu);
1359 }
1360 }
1361
1362 if (priv->tunnel_reg_id) {
1363 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1364 priv->tunnel_reg_id = 0;
1365 }
1366}
1367
1368static void mlx4_en_tx_timeout(struct net_device *dev)
1369{
1370 struct mlx4_en_priv *priv = netdev_priv(dev);
1371 struct mlx4_en_dev *mdev = priv->mdev;
1372 int i;
1373
1374 if (netif_msg_timer(priv))
1375 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
1376
1377 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
1378 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX][i];
1379
1380 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1381 continue;
1382 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
1383 i, tx_ring->qpn, tx_ring->sp_cqn,
1384 tx_ring->cons, tx_ring->prod);
1385 }
1386
1387 priv->port_stats.tx_timeout++;
1388 en_dbg(DRV, priv, "Scheduling watchdog\n");
1389 queue_work(mdev->workqueue, &priv->watchdog_task);
1390}
1391
1392
1393static void
1394mlx4_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1395{
1396 struct mlx4_en_priv *priv = netdev_priv(dev);
1397
1398 spin_lock_bh(&priv->stats_lock);
1399 mlx4_en_fold_software_stats(dev);
1400 netdev_stats_to_stats64(stats, &dev->stats);
1401 spin_unlock_bh(&priv->stats_lock);
1402}
1403
1404static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1405{
1406 struct mlx4_en_cq *cq;
1407 int i, t;
1408
1409
1410
1411
1412
1413
1414
1415 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
1416 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
1417 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1418 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
1419 en_dbg(INTR, priv, "Default coalescing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1420 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
1421
1422
1423 for (i = 0; i < priv->rx_ring_num; i++) {
1424 cq = priv->rx_cq[i];
1425 cq->moder_cnt = priv->rx_frames;
1426 cq->moder_time = priv->rx_usecs;
1427 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1428 priv->last_moder_packets[i] = 0;
1429 priv->last_moder_bytes[i] = 0;
1430 }
1431
1432 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
1433 for (i = 0; i < priv->tx_ring_num[t]; i++) {
1434 cq = priv->tx_cq[t][i];
1435 cq->moder_cnt = priv->tx_frames;
1436 cq->moder_time = priv->tx_usecs;
1437 }
1438 }
1439
1440
1441 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1442 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1443 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1444 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1445 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
1446 priv->adaptive_rx_coal = 1;
1447 priv->last_moder_jiffies = 0;
1448 priv->last_moder_tx_packets = 0;
1449}
1450
1451static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1452{
1453 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
1454 u32 pkt_rate_high, pkt_rate_low;
1455 struct mlx4_en_cq *cq;
1456 unsigned long packets;
1457 unsigned long rate;
1458 unsigned long avg_pkt_size;
1459 unsigned long rx_packets;
1460 unsigned long rx_bytes;
1461 unsigned long rx_pkt_diff;
1462 int moder_time;
1463 int ring, err;
1464
1465 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1466 return;
1467
1468 pkt_rate_low = READ_ONCE(priv->pkt_rate_low);
1469 pkt_rate_high = READ_ONCE(priv->pkt_rate_high);
1470
1471 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1472 rx_packets = READ_ONCE(priv->rx_ring[ring]->packets);
1473 rx_bytes = READ_ONCE(priv->rx_ring[ring]->bytes);
1474
1475 rx_pkt_diff = rx_packets - priv->last_moder_packets[ring];
1476 packets = rx_pkt_diff;
1477 rate = packets * HZ / period;
1478 avg_pkt_size = packets ? (rx_bytes -
1479 priv->last_moder_bytes[ring]) / packets : 0;
1480
1481
1482
1483 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1484 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
1485 if (rate <= pkt_rate_low)
1486 moder_time = priv->rx_usecs_low;
1487 else if (rate >= pkt_rate_high)
1488 moder_time = priv->rx_usecs_high;
1489 else
1490 moder_time = (rate - pkt_rate_low) *
1491 (priv->rx_usecs_high - priv->rx_usecs_low) /
1492 (pkt_rate_high - pkt_rate_low) +
1493 priv->rx_usecs_low;
1494 } else {
1495 moder_time = priv->rx_usecs_low;
1496 }
1497
1498 cq = priv->rx_cq[ring];
1499 if (moder_time != priv->last_moder_time[ring] ||
1500 cq->moder_cnt != priv->rx_frames) {
1501 priv->last_moder_time[ring] = moder_time;
1502 cq->moder_time = moder_time;
1503 cq->moder_cnt = priv->rx_frames;
1504 err = mlx4_en_set_cq_moder(priv, cq);
1505 if (err)
1506 en_err(priv, "Failed modifying moderation for cq:%d\n",
1507 ring);
1508 }
1509 priv->last_moder_packets[ring] = rx_packets;
1510 priv->last_moder_bytes[ring] = rx_bytes;
1511 }
1512
1513 priv->last_moder_jiffies = jiffies;
1514}
1515
1516static void mlx4_en_do_get_stats(struct work_struct *work)
1517{
1518 struct delayed_work *delay = to_delayed_work(work);
1519 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1520 stats_task);
1521 struct mlx4_en_dev *mdev = priv->mdev;
1522 int err;
1523
1524 mutex_lock(&mdev->state_lock);
1525 if (mdev->device_up) {
1526 if (priv->port_up) {
1527 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1528 if (err)
1529 en_dbg(HW, priv, "Could not update stats\n");
1530
1531 mlx4_en_auto_moderation(priv);
1532 }
1533
1534 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1535 }
1536 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
1537 mlx4_en_do_set_mac(priv, priv->current_mac);
1538 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1539 }
1540 mutex_unlock(&mdev->state_lock);
1541}
1542
1543
1544
1545
1546static void mlx4_en_service_task(struct work_struct *work)
1547{
1548 struct delayed_work *delay = to_delayed_work(work);
1549 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1550 service_task);
1551 struct mlx4_en_dev *mdev = priv->mdev;
1552
1553 mutex_lock(&mdev->state_lock);
1554 if (mdev->device_up) {
1555 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1556 mlx4_en_ptp_overflow_check(mdev);
1557
1558 mlx4_en_recover_from_oom(priv);
1559 queue_delayed_work(mdev->workqueue, &priv->service_task,
1560 SERVICE_TASK_DELAY);
1561 }
1562 mutex_unlock(&mdev->state_lock);
1563}
1564
1565static void mlx4_en_linkstate(struct work_struct *work)
1566{
1567 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1568 linkstate_task);
1569 struct mlx4_en_dev *mdev = priv->mdev;
1570 int linkstate = priv->link_state;
1571
1572 mutex_lock(&mdev->state_lock);
1573
1574
1575 if (priv->last_link_state != linkstate) {
1576 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
1577 en_info(priv, "Link Down\n");
1578 netif_carrier_off(priv->dev);
1579 } else {
1580 en_info(priv, "Link Up\n");
1581 netif_carrier_on(priv->dev);
1582 }
1583 }
1584 priv->last_link_state = linkstate;
1585 mutex_unlock(&mdev->state_lock);
1586}
1587
1588static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1589{
1590 struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1591 int numa_node = priv->mdev->dev->numa_node;
1592
1593 if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1594 return -ENOMEM;
1595
1596 cpumask_set_cpu(cpumask_local_spread(ring_idx, numa_node),
1597 ring->affinity_mask);
1598 return 0;
1599}
1600
1601static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1602{
1603 free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1604}
1605
1606int mlx4_en_start_port(struct net_device *dev)
1607{
1608 struct mlx4_en_priv *priv = netdev_priv(dev);
1609 struct mlx4_en_dev *mdev = priv->mdev;
1610 struct mlx4_en_cq *cq;
1611 struct mlx4_en_tx_ring *tx_ring;
1612 int rx_index = 0;
1613 int err = 0;
1614 int i, t;
1615 int j;
1616 u8 mc_list[16] = {0};
1617
1618 if (priv->port_up) {
1619 en_dbg(DRV, priv, "start port called while port already up\n");
1620 return 0;
1621 }
1622
1623 INIT_LIST_HEAD(&priv->mc_list);
1624 INIT_LIST_HEAD(&priv->curr_list);
1625 INIT_LIST_HEAD(&priv->ethtool_list);
1626 memset(&priv->ethtool_rules[0], 0,
1627 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
1628
1629
1630 dev->mtu = min(dev->mtu, priv->max_mtu);
1631 mlx4_en_calc_rx_buf(dev);
1632 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
1633
1634
1635 err = mlx4_en_activate_rx_rings(priv);
1636 if (err) {
1637 en_err(priv, "Failed to activate RX rings\n");
1638 return err;
1639 }
1640 for (i = 0; i < priv->rx_ring_num; i++) {
1641 cq = priv->rx_cq[i];
1642
1643 err = mlx4_en_init_affinity_hint(priv, i);
1644 if (err) {
1645 en_err(priv, "Failed preparing IRQ affinity hint\n");
1646 goto cq_err;
1647 }
1648
1649 err = mlx4_en_activate_cq(priv, cq, i);
1650 if (err) {
1651 en_err(priv, "Failed activating Rx CQ\n");
1652 mlx4_en_free_affinity_hint(priv, i);
1653 goto cq_err;
1654 }
1655
1656 for (j = 0; j < cq->size; j++) {
1657 struct mlx4_cqe *cqe = NULL;
1658
1659 cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1660 priv->cqe_factor;
1661 cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1662 }
1663
1664 err = mlx4_en_set_cq_moder(priv, cq);
1665 if (err) {
1666 en_err(priv, "Failed setting cq moderation parameters\n");
1667 mlx4_en_deactivate_cq(priv, cq);
1668 mlx4_en_free_affinity_hint(priv, i);
1669 goto cq_err;
1670 }
1671 mlx4_en_arm_cq(priv, cq);
1672 priv->rx_ring[i]->cqn = cq->mcq.cqn;
1673 ++rx_index;
1674 }
1675
1676
1677 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
1678 err = mlx4_en_get_qp(priv);
1679 if (err) {
1680 en_err(priv, "Failed getting eth qp\n");
1681 goto cq_err;
1682 }
1683 mdev->mac_removed[priv->port] = 0;
1684
1685 priv->counter_index =
1686 mlx4_get_default_counter_index(mdev->dev, priv->port);
1687
1688 err = mlx4_en_config_rss_steer(priv);
1689 if (err) {
1690 en_err(priv, "Failed configuring rss steering\n");
1691 goto mac_err;
1692 }
1693
1694 err = mlx4_en_create_drop_qp(priv);
1695 if (err)
1696 goto rss_err;
1697
1698
1699 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
1700 u8 num_tx_rings_p_up = t == TX ?
1701 priv->num_tx_rings_p_up : priv->tx_ring_num[t];
1702
1703 for (i = 0; i < priv->tx_ring_num[t]; i++) {
1704
1705 cq = priv->tx_cq[t][i];
1706 err = mlx4_en_activate_cq(priv, cq, i);
1707 if (err) {
1708 en_err(priv, "Failed allocating Tx CQ\n");
1709 goto tx_err;
1710 }
1711 err = mlx4_en_set_cq_moder(priv, cq);
1712 if (err) {
1713 en_err(priv, "Failed setting cq moderation parameters\n");
1714 mlx4_en_deactivate_cq(priv, cq);
1715 goto tx_err;
1716 }
1717 en_dbg(DRV, priv,
1718 "Resetting index of collapsed CQ:%d to -1\n", i);
1719 cq->buf->wqe_index = cpu_to_be16(0xffff);
1720
1721
1722 tx_ring = priv->tx_ring[t][i];
1723 err = mlx4_en_activate_tx_ring(priv, tx_ring,
1724 cq->mcq.cqn,
1725 i / num_tx_rings_p_up);
1726 if (err) {
1727 en_err(priv, "Failed allocating Tx ring\n");
1728 mlx4_en_deactivate_cq(priv, cq);
1729 goto tx_err;
1730 }
1731 if (t != TX_XDP) {
1732 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
1733 tx_ring->recycle_ring = NULL;
1734 } else {
1735
1736 tx_ring->recycle_ring = NULL;
1737 }
1738
1739
1740 mlx4_en_arm_cq(priv, cq);
1741
1742
1743 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1744 *((u32 *)(tx_ring->buf + j)) = 0xffffffff;
1745 }
1746 }
1747
1748
1749 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1750 priv->rx_skb_size + ETH_FCS_LEN,
1751 priv->prof->tx_pause,
1752 priv->prof->tx_ppp,
1753 priv->prof->rx_pause,
1754 priv->prof->rx_ppp);
1755 if (err) {
1756 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1757 priv->port, err);
1758 goto tx_err;
1759 }
1760
1761 err = mlx4_SET_PORT_user_mtu(mdev->dev, priv->port, dev->mtu);
1762 if (err) {
1763 en_err(priv, "Failed to pass user MTU(%d) to Firmware for port %d, with error %d\n",
1764 dev->mtu, priv->port, err);
1765 goto tx_err;
1766 }
1767
1768
1769 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1770 if (err) {
1771 en_err(priv, "Failed setting default qp numbers\n");
1772 goto tx_err;
1773 }
1774
1775 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1776 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
1777 if (err) {
1778 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1779 err);
1780 goto tx_err;
1781 }
1782 }
1783
1784
1785 en_dbg(HW, priv, "Initializing port\n");
1786 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1787 if (err) {
1788 en_err(priv, "Failed Initializing port\n");
1789 goto tx_err;
1790 }
1791
1792
1793 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0 &&
1794 mlx4_en_set_rss_steer_rules(priv))
1795 mlx4_warn(mdev, "Failed setting steering rules\n");
1796
1797
1798 eth_broadcast_addr(&mc_list[10]);
1799 mc_list[5] = priv->port;
1800 if (mlx4_multicast_attach(mdev->dev, priv->rss_map.indir_qp, mc_list,
1801 priv->port, 0, MLX4_PROT_ETH,
1802 &priv->broadcast_id))
1803 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1804
1805
1806 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1807
1808
1809 queue_work(mdev->workqueue, &priv->rx_mode_task);
1810
1811 if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1812 udp_tunnel_get_rx_info(dev);
1813
1814 priv->port_up = true;
1815
1816
1817
1818
1819 for (i = 0; i < priv->rx_ring_num; i++) {
1820 local_bh_disable();
1821 napi_schedule(&priv->rx_cq[i]->napi);
1822 local_bh_enable();
1823 }
1824
1825 netif_tx_start_all_queues(dev);
1826 netif_device_attach(dev);
1827
1828 return 0;
1829
1830tx_err:
1831 if (t == MLX4_EN_NUM_TX_TYPES) {
1832 t--;
1833 i = priv->tx_ring_num[t];
1834 }
1835 while (t >= 0) {
1836 while (i--) {
1837 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[t][i]);
1838 mlx4_en_deactivate_cq(priv, priv->tx_cq[t][i]);
1839 }
1840 if (!t--)
1841 break;
1842 i = priv->tx_ring_num[t];
1843 }
1844 mlx4_en_destroy_drop_qp(priv);
1845rss_err:
1846 mlx4_en_release_rss_steer(priv);
1847mac_err:
1848 mlx4_en_put_qp(priv);
1849cq_err:
1850 while (rx_index--) {
1851 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
1852 mlx4_en_free_affinity_hint(priv, rx_index);
1853 }
1854 for (i = 0; i < priv->rx_ring_num; i++)
1855 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
1856
1857 return err;
1858}
1859
1860
1861void mlx4_en_stop_port(struct net_device *dev, int detach)
1862{
1863 struct mlx4_en_priv *priv = netdev_priv(dev);
1864 struct mlx4_en_dev *mdev = priv->mdev;
1865 struct mlx4_en_mc_list *mclist, *tmp;
1866 struct ethtool_flow_id *flow, *tmp_flow;
1867 int i, t;
1868 u8 mc_list[16] = {0};
1869
1870 if (!priv->port_up) {
1871 en_dbg(DRV, priv, "stop port called while port already down\n");
1872 return;
1873 }
1874
1875
1876 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1877
1878
1879 netif_tx_lock_bh(dev);
1880 if (detach)
1881 netif_device_detach(dev);
1882 netif_tx_stop_all_queues(dev);
1883 netif_tx_unlock_bh(dev);
1884
1885 netif_tx_disable(dev);
1886
1887 spin_lock_bh(&priv->stats_lock);
1888 mlx4_en_fold_software_stats(dev);
1889
1890 priv->port_up = false;
1891 spin_unlock_bh(&priv->stats_lock);
1892
1893 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
1894
1895
1896 if (mdev->dev->caps.steering_mode ==
1897 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1898 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1899 MLX4_EN_FLAG_MC_PROMISC);
1900 mlx4_flow_steer_promisc_remove(mdev->dev,
1901 priv->port,
1902 MLX4_FS_ALL_DEFAULT);
1903 mlx4_flow_steer_promisc_remove(mdev->dev,
1904 priv->port,
1905 MLX4_FS_MC_DEFAULT);
1906 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1907 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1908
1909
1910 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1911 priv->port);
1912
1913
1914 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1915 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1916 priv->port);
1917 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1918 }
1919 }
1920
1921
1922 eth_broadcast_addr(&mc_list[10]);
1923 mc_list[5] = priv->port;
1924 mlx4_multicast_detach(mdev->dev, priv->rss_map.indir_qp, mc_list,
1925 MLX4_PROT_ETH, priv->broadcast_id);
1926 list_for_each_entry(mclist, &priv->curr_list, list) {
1927 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1928 mc_list[5] = priv->port;
1929 mlx4_multicast_detach(mdev->dev, priv->rss_map.indir_qp,
1930 mc_list, MLX4_PROT_ETH, mclist->reg_id);
1931 if (mclist->tunnel_reg_id)
1932 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1933 }
1934 mlx4_en_clear_list(dev);
1935 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1936 list_del(&mclist->list);
1937 kfree(mclist);
1938 }
1939
1940
1941 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1942
1943
1944 if (mdev->dev->caps.steering_mode ==
1945 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1946 ASSERT_RTNL();
1947 list_for_each_entry_safe(flow, tmp_flow,
1948 &priv->ethtool_list, list) {
1949 mlx4_flow_detach(mdev->dev, flow->id);
1950 list_del(&flow->list);
1951 }
1952 }
1953
1954 mlx4_en_destroy_drop_qp(priv);
1955
1956
1957 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
1958 for (i = 0; i < priv->tx_ring_num[t]; i++) {
1959 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[t][i]);
1960 mlx4_en_deactivate_cq(priv, priv->tx_cq[t][i]);
1961 }
1962 }
1963 msleep(10);
1964
1965 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1966 for (i = 0; i < priv->tx_ring_num[t]; i++)
1967 mlx4_en_free_tx_buf(dev, priv->tx_ring[t][i]);
1968
1969 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
1970 mlx4_en_delete_rss_steer_rules(priv);
1971
1972
1973 mlx4_en_release_rss_steer(priv);
1974
1975
1976 mlx4_en_put_qp(priv);
1977 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
1978 mdev->mac_removed[priv->port] = 1;
1979
1980
1981 for (i = 0; i < priv->rx_ring_num; i++) {
1982 struct mlx4_en_cq *cq = priv->rx_cq[i];
1983
1984 napi_synchronize(&cq->napi);
1985 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
1986 mlx4_en_deactivate_cq(priv, cq);
1987
1988 mlx4_en_free_affinity_hint(priv, i);
1989 }
1990}
1991
1992static void mlx4_en_restart(struct work_struct *work)
1993{
1994 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1995 watchdog_task);
1996 struct mlx4_en_dev *mdev = priv->mdev;
1997 struct net_device *dev = priv->dev;
1998
1999 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
2000
2001 rtnl_lock();
2002 mutex_lock(&mdev->state_lock);
2003 if (priv->port_up) {
2004 mlx4_en_stop_port(dev, 1);
2005 if (mlx4_en_start_port(dev))
2006 en_err(priv, "Failed restarting port %d\n", priv->port);
2007 }
2008 mutex_unlock(&mdev->state_lock);
2009 rtnl_unlock();
2010}
2011
2012static void mlx4_en_clear_stats(struct net_device *dev)
2013{
2014 struct mlx4_en_priv *priv = netdev_priv(dev);
2015 struct mlx4_en_dev *mdev = priv->mdev;
2016 struct mlx4_en_tx_ring **tx_ring;
2017 int i;
2018
2019 if (!mlx4_is_slave(mdev->dev))
2020 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
2021 en_dbg(HW, priv, "Failed dumping statistics\n");
2022
2023 memset(&priv->pstats, 0, sizeof(priv->pstats));
2024 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
2025 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
2026 memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats));
2027 memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats));
2028 memset(&priv->rx_priority_flowstats, 0,
2029 sizeof(priv->rx_priority_flowstats));
2030 memset(&priv->tx_priority_flowstats, 0,
2031 sizeof(priv->tx_priority_flowstats));
2032 memset(&priv->pf_stats, 0, sizeof(priv->pf_stats));
2033
2034 tx_ring = priv->tx_ring[TX];
2035 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
2036 tx_ring[i]->bytes = 0;
2037 tx_ring[i]->packets = 0;
2038 tx_ring[i]->tx_csum = 0;
2039 tx_ring[i]->tx_dropped = 0;
2040 tx_ring[i]->queue_stopped = 0;
2041 tx_ring[i]->wake_queue = 0;
2042 tx_ring[i]->tso_packets = 0;
2043 tx_ring[i]->xmit_more = 0;
2044 }
2045 for (i = 0; i < priv->rx_ring_num; i++) {
2046 priv->rx_ring[i]->bytes = 0;
2047 priv->rx_ring[i]->packets = 0;
2048 priv->rx_ring[i]->csum_ok = 0;
2049 priv->rx_ring[i]->csum_none = 0;
2050 priv->rx_ring[i]->csum_complete = 0;
2051 }
2052}
2053
2054static int mlx4_en_open(struct net_device *dev)
2055{
2056 struct mlx4_en_priv *priv = netdev_priv(dev);
2057 struct mlx4_en_dev *mdev = priv->mdev;
2058 int err = 0;
2059
2060 mutex_lock(&mdev->state_lock);
2061
2062 if (!mdev->device_up) {
2063 en_err(priv, "Cannot open - device down/disabled\n");
2064 err = -EBUSY;
2065 goto out;
2066 }
2067
2068
2069 mlx4_en_clear_stats(dev);
2070
2071 err = mlx4_en_start_port(dev);
2072 if (err)
2073 en_err(priv, "Failed starting port:%d\n", priv->port);
2074
2075out:
2076 mutex_unlock(&mdev->state_lock);
2077 return err;
2078}
2079
2080
2081static int mlx4_en_close(struct net_device *dev)
2082{
2083 struct mlx4_en_priv *priv = netdev_priv(dev);
2084 struct mlx4_en_dev *mdev = priv->mdev;
2085
2086 en_dbg(IFDOWN, priv, "Close port called\n");
2087
2088 mutex_lock(&mdev->state_lock);
2089
2090 mlx4_en_stop_port(dev, 0);
2091 netif_carrier_off(dev);
2092
2093 mutex_unlock(&mdev->state_lock);
2094 return 0;
2095}
2096
2097static void mlx4_en_free_resources(struct mlx4_en_priv *priv)
2098{
2099 int i, t;
2100
2101#ifdef CONFIG_RFS_ACCEL
2102 priv->dev->rx_cpu_rmap = NULL;
2103#endif
2104
2105 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2106 for (i = 0; i < priv->tx_ring_num[t]; i++) {
2107 if (priv->tx_ring[t] && priv->tx_ring[t][i])
2108 mlx4_en_destroy_tx_ring(priv,
2109 &priv->tx_ring[t][i]);
2110 if (priv->tx_cq[t] && priv->tx_cq[t][i])
2111 mlx4_en_destroy_cq(priv, &priv->tx_cq[t][i]);
2112 }
2113 kfree(priv->tx_ring[t]);
2114 kfree(priv->tx_cq[t]);
2115 }
2116
2117 for (i = 0; i < priv->rx_ring_num; i++) {
2118 if (priv->rx_ring[i])
2119 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2120 priv->prof->rx_ring_size, priv->stride);
2121 if (priv->rx_cq[i])
2122 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2123 }
2124
2125}
2126
2127static int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
2128{
2129 struct mlx4_en_port_profile *prof = priv->prof;
2130 int i, t;
2131 int node;
2132
2133
2134 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2135 for (i = 0; i < priv->tx_ring_num[t]; i++) {
2136 node = cpu_to_node(i % num_online_cpus());
2137 if (mlx4_en_create_cq(priv, &priv->tx_cq[t][i],
2138 prof->tx_ring_size, i, t, node))
2139 goto err;
2140
2141 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[t][i],
2142 prof->tx_ring_size,
2143 TXBB_SIZE, node, i))
2144 goto err;
2145 }
2146 }
2147
2148
2149 for (i = 0; i < priv->rx_ring_num; i++) {
2150 node = cpu_to_node(i % num_online_cpus());
2151 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
2152 prof->rx_ring_size, i, RX, node))
2153 goto err;
2154
2155 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
2156 prof->rx_ring_size, priv->stride,
2157 node))
2158 goto err;
2159 }
2160
2161#ifdef CONFIG_RFS_ACCEL
2162 priv->dev->rx_cpu_rmap = mlx4_get_cpu_rmap(priv->mdev->dev, priv->port);
2163#endif
2164
2165 return 0;
2166
2167err:
2168 en_err(priv, "Failed to allocate NIC resources\n");
2169 for (i = 0; i < priv->rx_ring_num; i++) {
2170 if (priv->rx_ring[i])
2171 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2172 prof->rx_ring_size,
2173 priv->stride);
2174 if (priv->rx_cq[i])
2175 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2176 }
2177 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2178 for (i = 0; i < priv->tx_ring_num[t]; i++) {
2179 if (priv->tx_ring[t][i])
2180 mlx4_en_destroy_tx_ring(priv,
2181 &priv->tx_ring[t][i]);
2182 if (priv->tx_cq[t][i])
2183 mlx4_en_destroy_cq(priv, &priv->tx_cq[t][i]);
2184 }
2185 }
2186 return -ENOMEM;
2187}
2188
2189
2190static int mlx4_en_copy_priv(struct mlx4_en_priv *dst,
2191 struct mlx4_en_priv *src,
2192 struct mlx4_en_port_profile *prof)
2193{
2194 int t;
2195
2196 memcpy(&dst->hwtstamp_config, &prof->hwtstamp_config,
2197 sizeof(dst->hwtstamp_config));
2198 dst->num_tx_rings_p_up = prof->num_tx_rings_p_up;
2199 dst->rx_ring_num = prof->rx_ring_num;
2200 dst->flags = prof->flags;
2201 dst->mdev = src->mdev;
2202 dst->port = src->port;
2203 dst->dev = src->dev;
2204 dst->prof = prof;
2205 dst->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2206 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2207
2208 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2209 dst->tx_ring_num[t] = prof->tx_ring_num[t];
2210 if (!dst->tx_ring_num[t])
2211 continue;
2212
2213 dst->tx_ring[t] = kzalloc(sizeof(struct mlx4_en_tx_ring *) *
2214 MAX_TX_RINGS, GFP_KERNEL);
2215 if (!dst->tx_ring[t])
2216 goto err_free_tx;
2217
2218 dst->tx_cq[t] = kzalloc(sizeof(struct mlx4_en_cq *) *
2219 MAX_TX_RINGS, GFP_KERNEL);
2220 if (!dst->tx_cq[t]) {
2221 kfree(dst->tx_ring[t]);
2222 goto err_free_tx;
2223 }
2224 }
2225
2226 return 0;
2227
2228err_free_tx:
2229 while (t--) {
2230 kfree(dst->tx_ring[t]);
2231 kfree(dst->tx_cq[t]);
2232 }
2233 return -ENOMEM;
2234}
2235
2236static void mlx4_en_update_priv(struct mlx4_en_priv *dst,
2237 struct mlx4_en_priv *src)
2238{
2239 int t;
2240 memcpy(dst->rx_ring, src->rx_ring,
2241 sizeof(struct mlx4_en_rx_ring *) * src->rx_ring_num);
2242 memcpy(dst->rx_cq, src->rx_cq,
2243 sizeof(struct mlx4_en_cq *) * src->rx_ring_num);
2244 memcpy(&dst->hwtstamp_config, &src->hwtstamp_config,
2245 sizeof(dst->hwtstamp_config));
2246 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2247 dst->tx_ring_num[t] = src->tx_ring_num[t];
2248 dst->tx_ring[t] = src->tx_ring[t];
2249 dst->tx_cq[t] = src->tx_cq[t];
2250 }
2251 dst->num_tx_rings_p_up = src->num_tx_rings_p_up;
2252 dst->rx_ring_num = src->rx_ring_num;
2253 memcpy(dst->prof, src->prof, sizeof(struct mlx4_en_port_profile));
2254}
2255
2256int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
2257 struct mlx4_en_priv *tmp,
2258 struct mlx4_en_port_profile *prof)
2259{
2260 int t;
2261
2262 mlx4_en_copy_priv(tmp, priv, prof);
2263
2264 if (mlx4_en_alloc_resources(tmp)) {
2265 en_warn(priv,
2266 "%s: Resource allocation failed, using previous configuration\n",
2267 __func__);
2268 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2269 kfree(tmp->tx_ring[t]);
2270 kfree(tmp->tx_cq[t]);
2271 }
2272 return -ENOMEM;
2273 }
2274 return 0;
2275}
2276
2277void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
2278 struct mlx4_en_priv *tmp)
2279{
2280 mlx4_en_free_resources(priv);
2281 mlx4_en_update_priv(priv, tmp);
2282}
2283
2284void mlx4_en_destroy_netdev(struct net_device *dev)
2285{
2286 struct mlx4_en_priv *priv = netdev_priv(dev);
2287 struct mlx4_en_dev *mdev = priv->mdev;
2288
2289 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
2290
2291
2292 if (priv->registered) {
2293 devlink_port_type_clear(mlx4_get_devlink_port(mdev->dev,
2294 priv->port));
2295 unregister_netdev(dev);
2296 }
2297
2298 if (priv->allocated)
2299 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2300
2301 cancel_delayed_work(&priv->stats_task);
2302 cancel_delayed_work(&priv->service_task);
2303
2304 flush_workqueue(mdev->workqueue);
2305
2306 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2307 mlx4_en_remove_timestamp(mdev);
2308
2309
2310 mutex_lock(&mdev->state_lock);
2311 mdev->pndev[priv->port] = NULL;
2312 mdev->upper[priv->port] = NULL;
2313
2314#ifdef CONFIG_RFS_ACCEL
2315 mlx4_en_cleanup_filters(priv);
2316#endif
2317
2318 mlx4_en_free_resources(priv);
2319 mutex_unlock(&mdev->state_lock);
2320
2321 free_netdev(dev);
2322}
2323
2324static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2325{
2326 struct mlx4_en_priv *priv = netdev_priv(dev);
2327 struct mlx4_en_dev *mdev = priv->mdev;
2328 int err = 0;
2329
2330 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
2331 dev->mtu, new_mtu);
2332
2333 dev->mtu = new_mtu;
2334
2335 if (netif_running(dev)) {
2336 mutex_lock(&mdev->state_lock);
2337 if (!mdev->device_up) {
2338
2339
2340 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
2341 } else {
2342 mlx4_en_stop_port(dev, 1);
2343 err = mlx4_en_start_port(dev);
2344 if (err) {
2345 en_err(priv, "Failed restarting port:%d\n",
2346 priv->port);
2347 queue_work(mdev->workqueue, &priv->watchdog_task);
2348 }
2349 }
2350 mutex_unlock(&mdev->state_lock);
2351 }
2352 return 0;
2353}
2354
2355static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
2356{
2357 struct mlx4_en_priv *priv = netdev_priv(dev);
2358 struct mlx4_en_dev *mdev = priv->mdev;
2359 struct hwtstamp_config config;
2360
2361 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2362 return -EFAULT;
2363
2364
2365 if (config.flags)
2366 return -EINVAL;
2367
2368
2369 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2370 return -EINVAL;
2371
2372
2373 switch (config.tx_type) {
2374 case HWTSTAMP_TX_OFF:
2375 case HWTSTAMP_TX_ON:
2376 break;
2377 default:
2378 return -ERANGE;
2379 }
2380
2381
2382 switch (config.rx_filter) {
2383 case HWTSTAMP_FILTER_NONE:
2384 break;
2385 case HWTSTAMP_FILTER_ALL:
2386 case HWTSTAMP_FILTER_SOME:
2387 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2388 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2389 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2390 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2391 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2392 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2393 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2394 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2395 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2396 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2397 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2398 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2399 case HWTSTAMP_FILTER_NTP_ALL:
2400 config.rx_filter = HWTSTAMP_FILTER_ALL;
2401 break;
2402 default:
2403 return -ERANGE;
2404 }
2405
2406 if (mlx4_en_reset_config(dev, config, dev->features)) {
2407 config.tx_type = HWTSTAMP_TX_OFF;
2408 config.rx_filter = HWTSTAMP_FILTER_NONE;
2409 }
2410
2411 return copy_to_user(ifr->ifr_data, &config,
2412 sizeof(config)) ? -EFAULT : 0;
2413}
2414
2415static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2416{
2417 struct mlx4_en_priv *priv = netdev_priv(dev);
2418
2419 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2420 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2421}
2422
2423static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2424{
2425 switch (cmd) {
2426 case SIOCSHWTSTAMP:
2427 return mlx4_en_hwtstamp_set(dev, ifr);
2428 case SIOCGHWTSTAMP:
2429 return mlx4_en_hwtstamp_get(dev, ifr);
2430 default:
2431 return -EOPNOTSUPP;
2432 }
2433}
2434
2435static netdev_features_t mlx4_en_fix_features(struct net_device *netdev,
2436 netdev_features_t features)
2437{
2438 struct mlx4_en_priv *en_priv = netdev_priv(netdev);
2439 struct mlx4_en_dev *mdev = en_priv->mdev;
2440
2441
2442
2443
2444
2445 if (features & NETIF_F_HW_VLAN_CTAG_RX &&
2446 !(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2447 features |= NETIF_F_HW_VLAN_STAG_RX;
2448 else
2449 features &= ~NETIF_F_HW_VLAN_STAG_RX;
2450
2451 return features;
2452}
2453
2454static int mlx4_en_set_features(struct net_device *netdev,
2455 netdev_features_t features)
2456{
2457 struct mlx4_en_priv *priv = netdev_priv(netdev);
2458 bool reset = false;
2459 int ret = 0;
2460
2461 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) {
2462 en_info(priv, "Turn %s RX-FCS\n",
2463 (features & NETIF_F_RXFCS) ? "ON" : "OFF");
2464 reset = true;
2465 }
2466
2467 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) {
2468 u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0;
2469
2470 en_info(priv, "Turn %s RX-ALL\n",
2471 ignore_fcs_value ? "ON" : "OFF");
2472 ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev,
2473 priv->port, ignore_fcs_value);
2474 if (ret)
2475 return ret;
2476 }
2477
2478 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2479 en_info(priv, "Turn %s RX vlan strip offload\n",
2480 (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
2481 reset = true;
2482 }
2483
2484 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX))
2485 en_info(priv, "Turn %s TX vlan strip offload\n",
2486 (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF");
2487
2488 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_STAG_TX))
2489 en_info(priv, "Turn %s TX S-VLAN strip offload\n",
2490 (features & NETIF_F_HW_VLAN_STAG_TX) ? "ON" : "OFF");
2491
2492 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) {
2493 en_info(priv, "Turn %s loopback\n",
2494 (features & NETIF_F_LOOPBACK) ? "ON" : "OFF");
2495 mlx4_en_update_loopback_state(netdev, features);
2496 }
2497
2498 if (reset) {
2499 ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2500 features);
2501 if (ret)
2502 return ret;
2503 }
2504
2505 return 0;
2506}
2507
2508static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2509{
2510 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2511 struct mlx4_en_dev *mdev = en_priv->mdev;
2512
2513 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac);
2514}
2515
2516static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2517 __be16 vlan_proto)
2518{
2519 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2520 struct mlx4_en_dev *mdev = en_priv->mdev;
2521
2522 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos,
2523 vlan_proto);
2524}
2525
2526static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2527 int max_tx_rate)
2528{
2529 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2530 struct mlx4_en_dev *mdev = en_priv->mdev;
2531
2532 return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate,
2533 max_tx_rate);
2534}
2535
2536static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2537{
2538 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2539 struct mlx4_en_dev *mdev = en_priv->mdev;
2540
2541 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2542}
2543
2544static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2545{
2546 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2547 struct mlx4_en_dev *mdev = en_priv->mdev;
2548
2549 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2550}
2551
2552static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2553{
2554 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2555 struct mlx4_en_dev *mdev = en_priv->mdev;
2556
2557 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2558}
2559
2560static int mlx4_en_get_vf_stats(struct net_device *dev, int vf,
2561 struct ifla_vf_stats *vf_stats)
2562{
2563 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2564 struct mlx4_en_dev *mdev = en_priv->mdev;
2565
2566 return mlx4_get_vf_stats(mdev->dev, en_priv->port, vf, vf_stats);
2567}
2568
2569#define PORT_ID_BYTE_LEN 8
2570static int mlx4_en_get_phys_port_id(struct net_device *dev,
2571 struct netdev_phys_item_id *ppid)
2572{
2573 struct mlx4_en_priv *priv = netdev_priv(dev);
2574 struct mlx4_dev *mdev = priv->mdev->dev;
2575 int i;
2576 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2577
2578 if (!phys_port_id)
2579 return -EOPNOTSUPP;
2580
2581 ppid->id_len = sizeof(phys_port_id);
2582 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2583 ppid->id[i] = phys_port_id & 0xff;
2584 phys_port_id >>= 8;
2585 }
2586 return 0;
2587}
2588
2589static void mlx4_en_add_vxlan_offloads(struct work_struct *work)
2590{
2591 int ret;
2592 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2593 vxlan_add_task);
2594
2595 ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2596 if (ret)
2597 goto out;
2598
2599 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2600 VXLAN_STEER_BY_OUTER_MAC, 1);
2601out:
2602 if (ret) {
2603 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2604 return;
2605 }
2606
2607
2608 priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2609 NETIF_F_RXCSUM |
2610 NETIF_F_TSO | NETIF_F_TSO6 |
2611 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
2612 NETIF_F_GSO_PARTIAL;
2613}
2614
2615static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
2616{
2617 int ret;
2618 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2619 vxlan_del_task);
2620
2621 priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2622 NETIF_F_RXCSUM |
2623 NETIF_F_TSO | NETIF_F_TSO6 |
2624 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
2625 NETIF_F_GSO_PARTIAL);
2626
2627 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2628 VXLAN_STEER_BY_OUTER_MAC, 0);
2629 if (ret)
2630 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2631
2632 priv->vxlan_port = 0;
2633}
2634
2635static void mlx4_en_add_vxlan_port(struct net_device *dev,
2636 struct udp_tunnel_info *ti)
2637{
2638 struct mlx4_en_priv *priv = netdev_priv(dev);
2639 __be16 port = ti->port;
2640 __be16 current_port;
2641
2642 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2643 return;
2644
2645 if (ti->sa_family != AF_INET)
2646 return;
2647
2648 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
2649 return;
2650
2651 current_port = priv->vxlan_port;
2652 if (current_port && current_port != port) {
2653 en_warn(priv, "vxlan port %d configured, can't add port %d\n",
2654 ntohs(current_port), ntohs(port));
2655 return;
2656 }
2657
2658 priv->vxlan_port = port;
2659 queue_work(priv->mdev->workqueue, &priv->vxlan_add_task);
2660}
2661
2662static void mlx4_en_del_vxlan_port(struct net_device *dev,
2663 struct udp_tunnel_info *ti)
2664{
2665 struct mlx4_en_priv *priv = netdev_priv(dev);
2666 __be16 port = ti->port;
2667 __be16 current_port;
2668
2669 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2670 return;
2671
2672 if (ti->sa_family != AF_INET)
2673 return;
2674
2675 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
2676 return;
2677
2678 current_port = priv->vxlan_port;
2679 if (current_port != port) {
2680 en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port));
2681 return;
2682 }
2683
2684 queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
2685}
2686
2687static netdev_features_t mlx4_en_features_check(struct sk_buff *skb,
2688 struct net_device *dev,
2689 netdev_features_t features)
2690{
2691 features = vlan_features_check(skb, features);
2692 features = vxlan_features_check(skb, features);
2693
2694
2695
2696
2697
2698 if (skb->encapsulation &&
2699 (skb->ip_summed == CHECKSUM_PARTIAL)) {
2700 struct mlx4_en_priv *priv = netdev_priv(dev);
2701
2702 if (!priv->vxlan_port ||
2703 (ip_hdr(skb)->version != 4) ||
2704 (udp_hdr(skb)->dest != priv->vxlan_port))
2705 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2706 }
2707
2708 return features;
2709}
2710
2711static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate)
2712{
2713 struct mlx4_en_priv *priv = netdev_priv(dev);
2714 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX][queue_index];
2715 struct mlx4_update_qp_params params;
2716 int err;
2717
2718 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT))
2719 return -EOPNOTSUPP;
2720
2721
2722 if (maxrate >> 12) {
2723 params.rate_unit = MLX4_QP_RATE_LIMIT_GBS;
2724 params.rate_val = maxrate / 1000;
2725 } else if (maxrate) {
2726 params.rate_unit = MLX4_QP_RATE_LIMIT_MBS;
2727 params.rate_val = maxrate;
2728 } else {
2729 params.rate_unit = 0;
2730 params.rate_val = 0;
2731 }
2732
2733 err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT,
2734 ¶ms);
2735 return err;
2736}
2737
2738static const struct net_device_ops mlx4_netdev_ops = {
2739 .ndo_size = sizeof(struct net_device_ops),
2740 .ndo_open = mlx4_en_open,
2741 .ndo_stop = mlx4_en_close,
2742 .ndo_start_xmit = mlx4_en_xmit,
2743 .ndo_select_queue = mlx4_en_select_queue,
2744 .ndo_get_stats64 = mlx4_en_get_stats64,
2745 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2746 .ndo_set_mac_address = mlx4_en_set_mac,
2747 .ndo_validate_addr = eth_validate_addr,
2748 .extended.ndo_change_mtu = mlx4_en_change_mtu,
2749 .ndo_do_ioctl = mlx4_en_ioctl,
2750 .ndo_tx_timeout = mlx4_en_tx_timeout,
2751 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2752 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2753#ifdef CONFIG_NET_POLL_CONTROLLER
2754 .ndo_poll_controller = mlx4_en_netpoll,
2755#endif
2756 .ndo_set_features = mlx4_en_set_features,
2757 .ndo_fix_features = mlx4_en_fix_features,
2758 .extended.ndo_setup_tc_rh = __mlx4_en_setup_tc,
2759#ifdef CONFIG_RFS_ACCEL
2760 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2761#endif
2762 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
2763 .extended.ndo_udp_tunnel_add = mlx4_en_add_vxlan_port,
2764 .extended.ndo_udp_tunnel_del = mlx4_en_del_vxlan_port,
2765 .ndo_features_check = mlx4_en_features_check,
2766 .extended.ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
2767};
2768
2769static const struct net_device_ops mlx4_netdev_ops_master = {
2770 .ndo_size = sizeof(struct net_device_ops),
2771 .ndo_open = mlx4_en_open,
2772 .ndo_stop = mlx4_en_close,
2773 .ndo_start_xmit = mlx4_en_xmit,
2774 .ndo_select_queue = mlx4_en_select_queue,
2775 .ndo_get_stats64 = mlx4_en_get_stats64,
2776 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2777 .ndo_set_mac_address = mlx4_en_set_mac,
2778 .ndo_validate_addr = eth_validate_addr,
2779 .extended.ndo_change_mtu = mlx4_en_change_mtu,
2780 .ndo_tx_timeout = mlx4_en_tx_timeout,
2781 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2782 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2783 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
2784 .extended.ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
2785 .ndo_set_vf_rate = mlx4_en_set_vf_rate,
2786 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
2787 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2788 .ndo_get_vf_stats = mlx4_en_get_vf_stats,
2789 .ndo_get_vf_config = mlx4_en_get_vf_config,
2790#ifdef CONFIG_NET_POLL_CONTROLLER
2791 .ndo_poll_controller = mlx4_en_netpoll,
2792#endif
2793 .ndo_set_features = mlx4_en_set_features,
2794 .ndo_fix_features = mlx4_en_fix_features,
2795 .extended.ndo_setup_tc_rh = __mlx4_en_setup_tc,
2796#ifdef CONFIG_RFS_ACCEL
2797 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2798#endif
2799 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
2800 .extended.ndo_udp_tunnel_add = mlx4_en_add_vxlan_port,
2801 .extended.ndo_udp_tunnel_del = mlx4_en_del_vxlan_port,
2802 .ndo_features_check = mlx4_en_features_check,
2803 .extended.ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
2804};
2805
2806void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
2807 struct mlx4_en_stats_bitmap *stats_bitmap,
2808 u8 rx_ppp, u8 rx_pause,
2809 u8 tx_ppp, u8 tx_pause)
2810{
2811 int last_i = NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PF_STATS;
2812
2813 if (!mlx4_is_slave(dev) &&
2814 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) {
2815 mutex_lock(&stats_bitmap->mutex);
2816 bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS);
2817
2818 if (rx_ppp)
2819 bitmap_set(stats_bitmap->bitmap, last_i,
2820 NUM_FLOW_PRIORITY_STATS_RX);
2821 last_i += NUM_FLOW_PRIORITY_STATS_RX;
2822
2823 if (rx_pause && !(rx_ppp))
2824 bitmap_set(stats_bitmap->bitmap, last_i,
2825 NUM_FLOW_STATS_RX);
2826 last_i += NUM_FLOW_STATS_RX;
2827
2828 if (tx_ppp)
2829 bitmap_set(stats_bitmap->bitmap, last_i,
2830 NUM_FLOW_PRIORITY_STATS_TX);
2831 last_i += NUM_FLOW_PRIORITY_STATS_TX;
2832
2833 if (tx_pause && !(tx_ppp))
2834 bitmap_set(stats_bitmap->bitmap, last_i,
2835 NUM_FLOW_STATS_TX);
2836 last_i += NUM_FLOW_STATS_TX;
2837
2838 mutex_unlock(&stats_bitmap->mutex);
2839 }
2840}
2841
2842void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
2843 struct mlx4_en_stats_bitmap *stats_bitmap,
2844 u8 rx_ppp, u8 rx_pause,
2845 u8 tx_ppp, u8 tx_pause)
2846{
2847 int last_i = 0;
2848
2849 mutex_init(&stats_bitmap->mutex);
2850 bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS);
2851
2852 if (mlx4_is_slave(dev)) {
2853 bitmap_set(stats_bitmap->bitmap, last_i +
2854 MLX4_FIND_NETDEV_STAT(rx_packets), 1);
2855 bitmap_set(stats_bitmap->bitmap, last_i +
2856 MLX4_FIND_NETDEV_STAT(tx_packets), 1);
2857 bitmap_set(stats_bitmap->bitmap, last_i +
2858 MLX4_FIND_NETDEV_STAT(rx_bytes), 1);
2859 bitmap_set(stats_bitmap->bitmap, last_i +
2860 MLX4_FIND_NETDEV_STAT(tx_bytes), 1);
2861 bitmap_set(stats_bitmap->bitmap, last_i +
2862 MLX4_FIND_NETDEV_STAT(rx_dropped), 1);
2863 bitmap_set(stats_bitmap->bitmap, last_i +
2864 MLX4_FIND_NETDEV_STAT(tx_dropped), 1);
2865 } else {
2866 bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS);
2867 }
2868 last_i += NUM_MAIN_STATS;
2869
2870 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS);
2871 last_i += NUM_PORT_STATS;
2872
2873 if (mlx4_is_master(dev))
2874 bitmap_set(stats_bitmap->bitmap, last_i,
2875 NUM_PF_STATS);
2876 last_i += NUM_PF_STATS;
2877
2878 mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap,
2879 rx_ppp, rx_pause,
2880 tx_ppp, tx_pause);
2881 last_i += NUM_FLOW_STATS;
2882
2883 if (!mlx4_is_slave(dev))
2884 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS);
2885}
2886
2887struct mlx4_en_bond {
2888 struct work_struct work;
2889 struct mlx4_en_priv *priv;
2890 int is_bonded;
2891 struct mlx4_port_map port_map;
2892};
2893
2894static void mlx4_en_bond_work(struct work_struct *work)
2895{
2896 struct mlx4_en_bond *bond = container_of(work,
2897 struct mlx4_en_bond,
2898 work);
2899 int err = 0;
2900 struct mlx4_dev *dev = bond->priv->mdev->dev;
2901
2902 if (bond->is_bonded) {
2903 if (!mlx4_is_bonded(dev)) {
2904 err = mlx4_bond(dev);
2905 if (err)
2906 en_err(bond->priv, "Fail to bond device\n");
2907 }
2908 if (!err) {
2909 err = mlx4_port_map_set(dev, &bond->port_map);
2910 if (err)
2911 en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n",
2912 bond->port_map.port1,
2913 bond->port_map.port2,
2914 err);
2915 }
2916 } else if (mlx4_is_bonded(dev)) {
2917 err = mlx4_unbond(dev);
2918 if (err)
2919 en_err(bond->priv, "Fail to unbond device\n");
2920 }
2921 dev_put(bond->priv->dev);
2922 kfree(bond);
2923}
2924
2925static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded,
2926 u8 v2p_p1, u8 v2p_p2)
2927{
2928 struct mlx4_en_bond *bond = NULL;
2929
2930 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
2931 if (!bond)
2932 return -ENOMEM;
2933
2934 INIT_WORK(&bond->work, mlx4_en_bond_work);
2935 bond->priv = priv;
2936 bond->is_bonded = is_bonded;
2937 bond->port_map.port1 = v2p_p1;
2938 bond->port_map.port2 = v2p_p2;
2939 dev_hold(priv->dev);
2940 queue_work(priv->mdev->workqueue, &bond->work);
2941 return 0;
2942}
2943
2944int mlx4_en_netdev_event(struct notifier_block *this,
2945 unsigned long event, void *ptr)
2946{
2947 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2948 u8 port = 0;
2949 struct mlx4_en_dev *mdev;
2950 struct mlx4_dev *dev;
2951 int i, num_eth_ports = 0;
2952 bool do_bond = true;
2953 struct mlx4_en_priv *priv;
2954 u8 v2p_port1 = 0;
2955 u8 v2p_port2 = 0;
2956
2957 if (!net_eq(dev_net(ndev), &init_net))
2958 return NOTIFY_DONE;
2959
2960 mdev = container_of(this, struct mlx4_en_dev, nb);
2961 dev = mdev->dev;
2962
2963
2964
2965
2966 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
2967 ++num_eth_ports;
2968 if (!port && (mdev->pndev[i] == ndev))
2969 port = i;
2970 mdev->upper[i] = mdev->pndev[i] ?
2971 netdev_master_upper_dev_get(mdev->pndev[i]) : NULL;
2972
2973 if (!mdev->upper[i])
2974 do_bond = false;
2975 if (num_eth_ports < 2)
2976 continue;
2977
2978 if (mdev->upper[i] != mdev->upper[i-1])
2979 do_bond = false;
2980 }
2981
2982 do_bond = (num_eth_ports == 2) ? do_bond : false;
2983
2984
2985 if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port)
2986 return NOTIFY_DONE;
2987
2988 priv = netdev_priv(ndev);
2989 if (do_bond) {
2990 struct netdev_notifier_bonding_info *notifier_info = ptr;
2991 struct netdev_bonding_info *bonding_info =
2992 ¬ifier_info->bonding_info;
2993
2994
2995 if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) &&
2996 (bonding_info->master.bond_mode != BOND_MODE_XOR) &&
2997 (bonding_info->master.bond_mode != BOND_MODE_8023AD))
2998 do_bond = false;
2999
3000
3001 if (bonding_info->master.num_slaves != 2)
3002 do_bond = false;
3003
3004
3005 if (do_bond) {
3006 if (bonding_info->master.bond_mode ==
3007 BOND_MODE_ACTIVEBACKUP) {
3008
3009
3010
3011 if (bonding_info->slave.state ==
3012 BOND_STATE_BACKUP) {
3013 if (port == 1) {
3014 v2p_port1 = 2;
3015 v2p_port2 = 2;
3016 } else {
3017 v2p_port1 = 1;
3018 v2p_port2 = 1;
3019 }
3020 } else {
3021 if (port == 1) {
3022 v2p_port1 = 1;
3023 v2p_port2 = 1;
3024 } else {
3025 v2p_port1 = 2;
3026 v2p_port2 = 2;
3027 }
3028 }
3029 } else {
3030
3031
3032
3033 __s8 link = bonding_info->slave.link;
3034
3035 if (port == 1)
3036 v2p_port2 = 2;
3037 else
3038 v2p_port1 = 1;
3039 if ((link == BOND_LINK_UP) ||
3040 (link == BOND_LINK_FAIL)) {
3041 if (port == 1)
3042 v2p_port1 = 1;
3043 else
3044 v2p_port2 = 2;
3045 } else {
3046 if (port == 1)
3047 v2p_port1 = 2;
3048 else
3049 v2p_port2 = 1;
3050 }
3051 }
3052 }
3053 }
3054
3055 mlx4_en_queue_bond_work(priv, do_bond,
3056 v2p_port1, v2p_port2);
3057
3058 return NOTIFY_DONE;
3059}
3060
3061int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
3062 struct mlx4_en_port_profile *prof)
3063{
3064 struct net_device *dev;
3065 struct mlx4_en_priv *priv;
3066 int i, t;
3067 int err;
3068
3069 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
3070 MAX_TX_RINGS, MAX_RX_RINGS);
3071 if (dev == NULL)
3072 return -ENOMEM;
3073
3074 netif_set_real_num_tx_queues(dev, prof->tx_ring_num[TX]);
3075 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
3076
3077 SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev);
3078 dev->dev_port = port - 1;
3079
3080
3081
3082
3083
3084 priv = netdev_priv(dev);
3085 memset(priv, 0, sizeof(struct mlx4_en_priv));
3086 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
3087 spin_lock_init(&priv->stats_lock);
3088 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
3089 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
3090 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
3091 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
3092 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
3093 INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads);
3094 INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads);
3095#ifdef CONFIG_RFS_ACCEL
3096 INIT_LIST_HEAD(&priv->filters);
3097 spin_lock_init(&priv->filters_lock);
3098#endif
3099
3100 priv->dev = dev;
3101 priv->mdev = mdev;
3102 priv->ddev = &mdev->pdev->dev;
3103 priv->prof = prof;
3104 priv->port = port;
3105 priv->port_up = false;
3106 priv->flags = prof->flags;
3107 priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
3108 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
3109 MLX4_WQE_CTRL_SOLICITED);
3110 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
3111 priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
3112 netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
3113
3114 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
3115 priv->tx_ring_num[t] = prof->tx_ring_num[t];
3116 if (!priv->tx_ring_num[t])
3117 continue;
3118
3119 priv->tx_ring[t] = kzalloc(sizeof(struct mlx4_en_tx_ring *) *
3120 MAX_TX_RINGS, GFP_KERNEL);
3121 if (!priv->tx_ring[t]) {
3122 err = -ENOMEM;
3123 goto err_free_tx;
3124 }
3125 priv->tx_cq[t] = kzalloc(sizeof(struct mlx4_en_cq *) *
3126 MAX_TX_RINGS, GFP_KERNEL);
3127 if (!priv->tx_cq[t]) {
3128 kfree(priv->tx_ring[t]);
3129 err = -ENOMEM;
3130 goto out;
3131 }
3132 }
3133 priv->rx_ring_num = prof->rx_ring_num;
3134 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
3135 priv->cqe_size = mdev->dev->caps.cqe_size;
3136 priv->mac_index = -1;
3137 priv->msg_enable = MLX4_EN_MSG_LEVEL;
3138#ifdef CONFIG_MLX4_EN_DCB
3139 if (!mlx4_is_slave(priv->mdev->dev)) {
3140 priv->dcbx_cap = DCB_CAP_DCBX_VER_CEE | DCB_CAP_DCBX_HOST |
3141 DCB_CAP_DCBX_VER_IEEE;
3142 priv->flags |= MLX4_EN_DCB_ENABLED;
3143 priv->cee_config.pfc_state = false;
3144
3145 for (i = 0; i < MLX4_EN_NUM_UP_HIGH; i++)
3146 priv->cee_config.dcb_pfc[i] = pfc_disabled;
3147
3148 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
3149 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
3150 dev->dcbnl_ops_ext = &mlx4_en_dcbnl_ops_ext;
3151 } else {
3152 en_info(priv, "enabling only PFC DCB ops\n");
3153 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
3154 }
3155 }
3156#endif
3157
3158 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
3159 INIT_HLIST_HEAD(&priv->mac_hash[i]);
3160
3161
3162 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
3163
3164 if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
3165 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
3166 priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
3167
3168
3169 dev->addr_len = ETH_ALEN;
3170 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
3171 if (!is_valid_ether_addr(dev->dev_addr)) {
3172 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
3173 priv->port, dev->dev_addr);
3174 err = -EINVAL;
3175 goto out;
3176 } else if (mlx4_is_slave(priv->mdev->dev) &&
3177 (priv->mdev->dev->port_random_macs & 1 << priv->port)) {
3178
3179
3180
3181 dev->addr_assign_type |= NET_ADDR_RANDOM;
3182 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
3183 }
3184
3185 memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
3186
3187 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
3188 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
3189 err = mlx4_en_alloc_resources(priv);
3190 if (err)
3191 goto out;
3192
3193
3194 priv->hwtstamp_config.flags = 0;
3195 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
3196 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
3197
3198
3199 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
3200 MLX4_EN_PAGE_SIZE);
3201 if (err) {
3202 en_err(priv, "Failed to allocate page for rx qps\n");
3203 goto out;
3204 }
3205 priv->allocated = 1;
3206
3207
3208
3209
3210 if (mlx4_is_master(priv->mdev->dev))
3211 dev->netdev_ops = &mlx4_netdev_ops_master;
3212 else
3213 dev->netdev_ops = &mlx4_netdev_ops;
3214 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
3215 netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
3216 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3217
3218 SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops);
3219
3220
3221
3222
3223 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3224 if (mdev->LSO_support)
3225 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
3226
3227 dev->vlan_features = dev->hw_features;
3228
3229 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
3230 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
3231 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3232 NETIF_F_HW_VLAN_CTAG_FILTER;
3233 dev->hw_features |= NETIF_F_LOOPBACK |
3234 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3235
3236 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
3237 dev->features |= NETIF_F_HW_VLAN_STAG_RX |
3238 NETIF_F_HW_VLAN_STAG_FILTER;
3239 dev->hw_features |= NETIF_F_HW_VLAN_STAG_RX;
3240 }
3241
3242 if (mlx4_is_slave(mdev->dev)) {
3243 bool vlan_offload_disabled;
3244 int phv;
3245
3246 err = get_phv_bit(mdev->dev, port, &phv);
3247 if (!err && phv) {
3248 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
3249 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
3250 }
3251 err = mlx4_get_is_vlan_offload_disabled(mdev->dev, port,
3252 &vlan_offload_disabled);
3253 if (!err && vlan_offload_disabled) {
3254 dev->hw_features &= ~(NETIF_F_HW_VLAN_CTAG_TX |
3255 NETIF_F_HW_VLAN_CTAG_RX |
3256 NETIF_F_HW_VLAN_STAG_TX |
3257 NETIF_F_HW_VLAN_STAG_RX);
3258 dev->features &= ~(NETIF_F_HW_VLAN_CTAG_TX |
3259 NETIF_F_HW_VLAN_CTAG_RX |
3260 NETIF_F_HW_VLAN_STAG_TX |
3261 NETIF_F_HW_VLAN_STAG_RX);
3262 }
3263 } else {
3264 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
3265 !(mdev->dev->caps.flags2 &
3266 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
3267 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
3268 }
3269
3270 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
3271 dev->hw_features |= NETIF_F_RXFCS;
3272
3273 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)
3274 dev->hw_features |= NETIF_F_RXALL;
3275
3276 if (mdev->dev->caps.steering_mode ==
3277 MLX4_STEERING_MODE_DEVICE_MANAGED &&
3278 mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
3279 dev->hw_features |= NETIF_F_NTUPLE;
3280
3281 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
3282 dev->priv_flags |= IFF_UNICAST_FLT;
3283
3284
3285 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
3286 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3287 } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
3288 priv->rss_hash_fn = ETH_RSS_HASH_XOR;
3289 } else {
3290 en_warn(priv,
3291 "No RSS hash capabilities exposed, using Toeplitz\n");
3292 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3293 }
3294
3295 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
3296 dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3297 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3298 NETIF_F_GSO_PARTIAL;
3299 dev->features |= NETIF_F_GSO_UDP_TUNNEL |
3300 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3301 NETIF_F_GSO_PARTIAL;
3302 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3303 }
3304
3305
3306 dev->extended->min_mtu = MLX4_EN_MIN_MTU;
3307 dev->extended->max_mtu = priv->max_mtu;
3308
3309 mdev->pndev[port] = dev;
3310 mdev->upper[port] = NULL;
3311
3312 netif_carrier_off(dev);
3313 mlx4_en_set_default_moderation(priv);
3314
3315 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num[TX]);
3316 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
3317
3318 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
3319
3320
3321 mlx4_en_calc_rx_buf(dev);
3322 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
3323 priv->rx_skb_size + ETH_FCS_LEN,
3324 prof->tx_pause, prof->tx_ppp,
3325 prof->rx_pause, prof->rx_ppp);
3326 if (err) {
3327 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
3328 priv->port, err);
3329 goto out;
3330 }
3331
3332 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
3333 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
3334 if (err) {
3335 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
3336 err);
3337 goto out;
3338 }
3339 }
3340
3341
3342 en_warn(priv, "Initializing port\n");
3343 err = mlx4_INIT_PORT(mdev->dev, priv->port);
3344 if (err) {
3345 en_err(priv, "Failed Initializing port\n");
3346 goto out;
3347 }
3348 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
3349
3350
3351 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
3352 mlx4_en_init_timestamp(mdev);
3353
3354 queue_delayed_work(mdev->workqueue, &priv->service_task,
3355 SERVICE_TASK_DELAY);
3356
3357 mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap,
3358 mdev->profile.prof[priv->port].rx_ppp,
3359 mdev->profile.prof[priv->port].rx_pause,
3360 mdev->profile.prof[priv->port].tx_ppp,
3361 mdev->profile.prof[priv->port].tx_pause);
3362
3363 err = register_netdev(dev);
3364 if (err) {
3365 en_err(priv, "Netdev registration failed for port %d\n", port);
3366 goto out;
3367 }
3368
3369 priv->registered = 1;
3370 devlink_port_type_eth_set(mlx4_get_devlink_port(mdev->dev, priv->port),
3371 dev);
3372
3373 return 0;
3374
3375err_free_tx:
3376 while (t--) {
3377 kfree(priv->tx_ring[t]);
3378 kfree(priv->tx_cq[t]);
3379 }
3380out:
3381 mlx4_en_destroy_netdev(dev);
3382 return err;
3383}
3384
3385int mlx4_en_reset_config(struct net_device *dev,
3386 struct hwtstamp_config ts_config,
3387 netdev_features_t features)
3388{
3389 struct mlx4_en_priv *priv = netdev_priv(dev);
3390 struct mlx4_en_dev *mdev = priv->mdev;
3391 struct mlx4_en_port_profile new_prof;
3392 struct mlx4_en_priv *tmp;
3393 int port_up = 0;
3394 int err = 0;
3395
3396 if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
3397 priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
3398 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3399 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS))
3400 return 0;
3401
3402 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3403 (features & NETIF_F_HW_VLAN_CTAG_RX) &&
3404 (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
3405 en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
3406 return -EINVAL;
3407 }
3408
3409 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
3410 if (!tmp)
3411 return -ENOMEM;
3412
3413 mutex_lock(&mdev->state_lock);
3414
3415 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
3416 memcpy(&new_prof.hwtstamp_config, &ts_config, sizeof(ts_config));
3417
3418 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof);
3419 if (err)
3420 goto out;
3421
3422 if (priv->port_up) {
3423 port_up = 1;
3424 mlx4_en_stop_port(dev, 1);
3425 }
3426
3427 en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n",
3428 ts_config.rx_filter,
3429 !!(features & NETIF_F_HW_VLAN_CTAG_RX));
3430
3431 mlx4_en_safe_replace_resources(priv, tmp);
3432
3433 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
3434 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3435 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3436 else
3437 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3438 } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
3439
3440
3441
3442 if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
3443 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3444 else
3445 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3446 }
3447
3448 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) {
3449 if (features & NETIF_F_RXFCS)
3450 dev->features |= NETIF_F_RXFCS;
3451 else
3452 dev->features &= ~NETIF_F_RXFCS;
3453 }
3454
3455
3456
3457
3458
3459 if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
3460 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
3461 en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
3462 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3463 }
3464
3465 if (port_up) {
3466 err = mlx4_en_start_port(dev);
3467 if (err)
3468 en_err(priv, "Failed starting port\n");
3469 }
3470
3471out:
3472 mutex_unlock(&mdev->state_lock);
3473 kfree(tmp);
3474 if (!err)
3475 netdev_features_change(dev);
3476 return err;
3477}
3478