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19#ifndef HPSA_H
20#define HPSA_H
21
22#include <scsi/scsicam.h>
23
24#define IO_OK 0
25#define IO_ERROR 1
26
27struct ctlr_info;
28
29struct access_method {
30 void (*submit_command)(struct ctlr_info *h,
31 struct CommandList *c);
32 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
33 bool (*intr_pending)(struct ctlr_info *h);
34 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
35};
36
37
38struct hpsa_sas_node {
39 struct device *parent_dev;
40 struct list_head port_list_head;
41};
42
43struct hpsa_sas_port {
44 struct list_head port_list_entry;
45 u64 sas_address;
46 struct sas_port *port;
47 int next_phy_index;
48 struct list_head phy_list_head;
49 struct hpsa_sas_node *parent_node;
50 struct sas_rphy *rphy;
51};
52
53struct hpsa_sas_phy {
54 struct list_head phy_list_entry;
55 struct sas_phy *phy;
56 struct hpsa_sas_port *parent_port;
57 bool added_to_port;
58};
59
60#define EXTERNAL_QD 7
61struct hpsa_scsi_dev_t {
62 unsigned int devtype;
63 int bus, target, lun;
64 unsigned char scsi3addr[8];
65 u8 physical_device : 1;
66 u8 expose_device;
67 u8 removed : 1;
68#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
69 unsigned char device_id[16];
70 u64 sas_address;
71 unsigned char vendor[8];
72 unsigned char model[16];
73 unsigned char rev;
74 unsigned char raid_level;
75 unsigned char volume_offline;
76 u16 queue_depth;
77 atomic_t reset_cmds_out;
78 atomic_t ioaccel_cmds_out;
79
80
81
82 u32 ioaccel_handle;
83 u8 active_path_index;
84 u8 path_map;
85 u8 bay;
86 u8 box[8];
87 u16 phys_connector[8];
88 int offload_config;
89 int offload_enabled;
90 int offload_to_be_enabled;
91 int hba_ioaccel_enabled;
92 int offload_to_mirror;
93
94
95 struct raid_map_data raid_map;
96
97
98
99
100
101
102
103
104
105 struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
106 int nphysical_disks;
107 int supports_aborts;
108 struct hpsa_sas_port *sas_port;
109 int external;
110};
111
112struct reply_queue_buffer {
113 u64 *head;
114 size_t size;
115 u8 wraparound;
116 u32 current_entry;
117 dma_addr_t busaddr;
118};
119
120#pragma pack(1)
121struct bmic_controller_parameters {
122 u8 led_flags;
123 u8 enable_command_list_verification;
124 u8 backed_out_write_drives;
125 u16 stripes_for_parity;
126 u8 parity_distribution_mode_flags;
127 u16 max_driver_requests;
128 u16 elevator_trend_count;
129 u8 disable_elevator;
130 u8 force_scan_complete;
131 u8 scsi_transfer_mode;
132 u8 force_narrow;
133 u8 rebuild_priority;
134 u8 expand_priority;
135 u8 host_sdb_asic_fix;
136 u8 pdpi_burst_from_host_disabled;
137 char software_name[64];
138 char hardware_name[32];
139 u8 bridge_revision;
140 u8 snapshot_priority;
141 u32 os_specific;
142 u8 post_prompt_timeout;
143 u8 automatic_drive_slamming;
144 u8 reserved1;
145 u8 nvram_flags;
146 u8 cache_nvram_flags;
147 u8 drive_config_flags;
148 u16 reserved2;
149 u8 temp_warning_level;
150 u8 temp_shutdown_level;
151 u8 temp_condition_reset;
152 u8 max_coalesce_commands;
153 u32 max_coalesce_delay;
154 u8 orca_password[4];
155 u8 access_id[16];
156 u8 reserved[356];
157};
158#pragma pack()
159
160struct ctlr_info {
161 int ctlr;
162 char devname[8];
163 char *product_name;
164 struct pci_dev *pdev;
165 u32 board_id;
166 u64 sas_address;
167 void __iomem *vaddr;
168 unsigned long paddr;
169 int nr_cmds;
170#define HPSA_CMDS_RESERVED_FOR_ABORTS 2
171#define HPSA_CMDS_RESERVED_FOR_DRIVER 1
172 struct CfgTable __iomem *cfgtable;
173 int interrupts_enabled;
174 int max_commands;
175 atomic_t commands_outstanding;
176# define PERF_MODE_INT 0
177# define DOORBELL_INT 1
178# define SIMPLE_MODE_INT 2
179# define MEMQ_MODE_INT 3
180 unsigned int intr[MAX_REPLY_QUEUES];
181 unsigned int msix_vector;
182 unsigned int msi_vector;
183 int intr_mode;
184 struct access_method access;
185
186
187 unsigned int Qdepth;
188 unsigned int maxSG;
189 spinlock_t lock;
190 int maxsgentries;
191 u8 max_cmd_sg_entries;
192 int chainsize;
193 struct SGDescriptor **cmd_sg_list;
194 struct ioaccel2_sg_element **ioaccel2_cmd_sg_list;
195
196
197 struct CommandList *cmd_pool;
198 dma_addr_t cmd_pool_dhandle;
199 struct io_accel1_cmd *ioaccel_cmd_pool;
200 dma_addr_t ioaccel_cmd_pool_dhandle;
201 struct io_accel2_cmd *ioaccel2_cmd_pool;
202 dma_addr_t ioaccel2_cmd_pool_dhandle;
203 struct ErrorInfo *errinfo_pool;
204 dma_addr_t errinfo_pool_dhandle;
205 unsigned long *cmd_pool_bits;
206 int scan_finished;
207 u8 scan_waiting : 1;
208 spinlock_t scan_lock;
209 wait_queue_head_t scan_wait_queue;
210
211 struct Scsi_Host *scsi_host;
212 spinlock_t devlock;
213 int ndevices;
214 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
215
216
217
218 u32 trans_support;
219 u32 trans_offset;
220 struct TransTable_struct __iomem *transtable;
221 unsigned long transMethod;
222
223
224#define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
225 atomic_t passthru_cmds_avail;
226
227
228
229
230 size_t reply_queue_size;
231 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
232 u8 nreply_queues;
233 u32 *blockFetchTable;
234 u32 *ioaccel1_blockFetchTable;
235 u32 *ioaccel2_blockFetchTable;
236 u32 __iomem *ioaccel2_bft2_regs;
237 unsigned char *hba_inquiry_data;
238 u32 driver_support;
239 u32 fw_support;
240 int ioaccel_support;
241 int ioaccel_maxsg;
242 u64 last_intr_timestamp;
243 u32 last_heartbeat;
244 u64 last_heartbeat_timestamp;
245 u32 heartbeat_sample_interval;
246 atomic_t firmware_flash_in_progress;
247 u32 __percpu *lockup_detected;
248 struct delayed_work monitor_ctlr_work;
249 struct delayed_work rescan_ctlr_work;
250 struct delayed_work event_monitor_work;
251 int remove_in_progress;
252
253 u8 q[MAX_REPLY_QUEUES];
254 char intrname[MAX_REPLY_QUEUES][16];
255 u32 TMFSupportFlags;
256#define HPSATMF_BITS_SUPPORTED (1 << 0)
257#define HPSATMF_PHYS_LUN_RESET (1 << 1)
258#define HPSATMF_PHYS_NEX_RESET (1 << 2)
259#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
260#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
261#define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
262#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
263#define HPSATMF_PHYS_QRY_TASK (1 << 7)
264#define HPSATMF_PHYS_QRY_TSET (1 << 8)
265#define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
266#define HPSATMF_IOACCEL_ENABLED (1 << 15)
267#define HPSATMF_MASK_SUPPORTED (1 << 16)
268#define HPSATMF_LOG_LUN_RESET (1 << 17)
269#define HPSATMF_LOG_NEX_RESET (1 << 18)
270#define HPSATMF_LOG_TASK_ABORT (1 << 19)
271#define HPSATMF_LOG_TSET_ABORT (1 << 20)
272#define HPSATMF_LOG_CLEAR_ACA (1 << 21)
273#define HPSATMF_LOG_CLEAR_TSET (1 << 22)
274#define HPSATMF_LOG_QRY_TASK (1 << 23)
275#define HPSATMF_LOG_QRY_TSET (1 << 24)
276#define HPSATMF_LOG_QRY_ASYNC (1 << 25)
277 u32 events;
278#define CTLR_STATE_CHANGE_EVENT (1 << 0)
279#define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
280#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
281#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
282#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
283#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
284#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
285
286#define RESCAN_REQUIRED_EVENT_BITS \
287 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
288 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
289 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
290 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
291 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
292 spinlock_t offline_device_lock;
293 struct list_head offline_device_list;
294 int acciopath_status;
295 int drv_req_rescan;
296 int raid_offload_debug;
297 int discovery_polling;
298 struct ReportLUNdata *lastlogicals;
299 int needs_abort_tags_swizzled;
300 struct workqueue_struct *resubmit_wq;
301 struct workqueue_struct *rescan_ctlr_wq;
302 atomic_t abort_cmds_available;
303 wait_queue_head_t event_sync_wait_queue;
304 struct mutex reset_mutex;
305 u8 reset_in_progress;
306 struct hpsa_sas_node *sas_host;
307 spinlock_t reset_lock;
308};
309
310struct offline_device_entry {
311 unsigned char scsi3addr[8];
312 struct list_head offline_list;
313};
314
315#define HPSA_ABORT_MSG 0
316#define HPSA_DEVICE_RESET_MSG 1
317#define HPSA_RESET_TYPE_CONTROLLER 0x00
318#define HPSA_RESET_TYPE_BUS 0x01
319#define HPSA_RESET_TYPE_LUN 0x04
320#define HPSA_PHYS_TARGET_RESET 0x99
321#define HPSA_MSG_SEND_RETRY_LIMIT 10
322#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
323
324
325
326
327#define HPSA_MAX_POLL_TIME_SECS (20)
328
329
330
331
332
333
334
335
336#define HPSA_TUR_RETRY_LIMIT (20)
337#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
338
339
340
341
342
343
344
345
346#define HPSA_BOARD_READY_WAIT_SECS (120)
347#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
348#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
349#define HPSA_BOARD_READY_POLL_INTERVAL \
350 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
351#define HPSA_BOARD_READY_ITERATIONS \
352 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
353 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
354#define HPSA_BOARD_NOT_READY_ITERATIONS \
355 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
356 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
357#define HPSA_POST_RESET_PAUSE_MSECS (3000)
358#define HPSA_POST_RESET_NOOP_RETRIES (12)
359
360
361
362
363
364#define SA5_DOORBELL 0x20
365#define SA5_REQUEST_PORT_OFFSET 0x40
366#define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
367#define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
368#define SA5_REPLY_INTR_MASK_OFFSET 0x34
369#define SA5_REPLY_PORT_OFFSET 0x44
370#define SA5_INTR_STATUS 0x30
371#define SA5_SCRATCHPAD_OFFSET 0xB0
372
373#define SA5_CTCFG_OFFSET 0xB4
374#define SA5_CTMEM_OFFSET 0xB8
375
376#define SA5_INTR_OFF 0x08
377#define SA5B_INTR_OFF 0x04
378#define SA5_INTR_PENDING 0x08
379#define SA5B_INTR_PENDING 0x04
380#define FIFO_EMPTY 0xffffffff
381#define HPSA_FIRMWARE_READY 0xffff0000
382
383#define HPSA_ERROR_BIT 0x02
384
385
386#define SA5_PERF_INTR_PENDING 0x04
387#define SA5_PERF_INTR_OFF 0x05
388#define SA5_OUTDB_STATUS_PERF_BIT 0x01
389#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
390#define SA5_OUTDB_CLEAR 0xA0
391#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
392#define SA5_OUTDB_STATUS 0x9C
393
394
395#define HPSA_INTR_ON 1
396#define HPSA_INTR_OFF 0
397
398
399
400
401#define IOACCEL2_INBOUND_POSTQ_32 0x48
402#define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
403#define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
404
405#define HPSA_PHYSICAL_DEVICE_BUS 0
406#define HPSA_RAID_VOLUME_BUS 1
407#define HPSA_EXTERNAL_RAID_VOLUME_BUS 2
408#define HPSA_HBA_BUS 0
409#define HPSA_LEGACY_HBA_BUS 3
410
411
412
413
414static void SA5_submit_command(struct ctlr_info *h,
415 struct CommandList *c)
416{
417 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
418 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
419}
420
421static void SA5_submit_command_no_read(struct ctlr_info *h,
422 struct CommandList *c)
423{
424 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
425}
426
427static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
428 struct CommandList *c)
429{
430 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
431}
432
433
434
435
436
437
438static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
439{
440 if (val) {
441 h->interrupts_enabled = 1;
442 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
443 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
444 } else {
445 h->interrupts_enabled = 0;
446 writel(SA5_INTR_OFF,
447 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
448 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
449 }
450}
451
452static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
453{
454 if (val) {
455 h->interrupts_enabled = 1;
456 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
457 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
458 } else {
459 h->interrupts_enabled = 0;
460 writel(SA5_PERF_INTR_OFF,
461 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
462 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
463 }
464}
465
466static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
467{
468 struct reply_queue_buffer *rq = &h->reply_queue[q];
469 unsigned long register_value = FIFO_EMPTY;
470
471
472 if (unlikely(!(h->msi_vector || h->msix_vector))) {
473
474
475
476 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
477 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
478
479
480
481 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
482 }
483
484 if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
485 register_value = rq->head[rq->current_entry];
486 rq->current_entry++;
487 atomic_dec(&h->commands_outstanding);
488 } else {
489 register_value = FIFO_EMPTY;
490 }
491
492 if (rq->current_entry == h->max_commands) {
493 rq->current_entry = 0;
494 rq->wraparound ^= 1;
495 }
496 return register_value;
497}
498
499
500
501
502
503static unsigned long SA5_completed(struct ctlr_info *h,
504 __attribute__((unused)) u8 q)
505{
506 unsigned long register_value
507 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
508
509 if (register_value != FIFO_EMPTY)
510 atomic_dec(&h->commands_outstanding);
511
512#ifdef HPSA_DEBUG
513 if (register_value != FIFO_EMPTY)
514 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
515 register_value);
516 else
517 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
518#endif
519
520 return register_value;
521}
522
523
524
525static bool SA5_intr_pending(struct ctlr_info *h)
526{
527 unsigned long register_value =
528 readl(h->vaddr + SA5_INTR_STATUS);
529 return register_value & SA5_INTR_PENDING;
530}
531
532static bool SA5_performant_intr_pending(struct ctlr_info *h)
533{
534 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
535
536 if (!register_value)
537 return false;
538
539
540 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
541 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
542}
543
544#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
545
546static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
547{
548 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
549
550 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
551 true : false;
552}
553
554#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
555#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
556#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
557#define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
558
559static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
560{
561 u64 register_value;
562 struct reply_queue_buffer *rq = &h->reply_queue[q];
563
564 BUG_ON(q >= h->nreply_queues);
565
566 register_value = rq->head[rq->current_entry];
567 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
568 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
569 if (++rq->current_entry == rq->size)
570 rq->current_entry = 0;
571
572
573
574
575
576
577 wmb();
578 writel((q << 24) | rq->current_entry, h->vaddr +
579 IOACCEL_MODE1_CONSUMER_INDEX);
580 atomic_dec(&h->commands_outstanding);
581 }
582 return (unsigned long) register_value;
583}
584
585static struct access_method SA5_access = {
586 SA5_submit_command,
587 SA5_intr_mask,
588 SA5_intr_pending,
589 SA5_completed,
590};
591
592static struct access_method SA5_ioaccel_mode1_access = {
593 SA5_submit_command,
594 SA5_performant_intr_mask,
595 SA5_ioaccel_mode1_intr_pending,
596 SA5_ioaccel_mode1_completed,
597};
598
599static struct access_method SA5_ioaccel_mode2_access = {
600 SA5_submit_command_ioaccel2,
601 SA5_performant_intr_mask,
602 SA5_performant_intr_pending,
603 SA5_performant_completed,
604};
605
606static struct access_method SA5_performant_access = {
607 SA5_submit_command,
608 SA5_performant_intr_mask,
609 SA5_performant_intr_pending,
610 SA5_performant_completed,
611};
612
613static struct access_method SA5_performant_access_no_read = {
614 SA5_submit_command_no_read,
615 SA5_performant_intr_mask,
616 SA5_performant_intr_pending,
617 SA5_performant_completed,
618};
619
620struct board_type {
621 u32 board_id;
622 char *product_name;
623 struct access_method *access;
624};
625
626#endif
627
628