1/* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9#ifndef __FCOE_COMMON__ 10#define __FCOE_COMMON__ 11/*********************/ 12/* FCOE FW CONSTANTS */ 13/*********************/ 14 15#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12 16 17struct fcoe_abts_pkt { 18 __le32 abts_rsp_fc_payload_lo; 19 __le16 abts_rsp_rx_id; 20 u8 abts_rsp_rctl; 21 u8 reserved2; 22}; 23 24/* FCoE additional WQE (Sq/XferQ) information */ 25union fcoe_additional_info_union { 26 __le32 previous_tid; 27 __le32 parent_tid; 28 __le32 burst_length; 29 __le32 seq_rec_updated_offset; 30}; 31 32struct fcoe_exp_ro { 33 __le32 data_offset; 34 __le32 reserved; 35}; 36 37union fcoe_cleanup_addr_exp_ro_union { 38 struct regpair abts_rsp_fc_payload_hi; 39 struct fcoe_exp_ro exp_ro; 40}; 41 42/* FCoE Ramrod Command IDs */ 43enum fcoe_completion_status { 44 FCOE_COMPLETION_STATUS_SUCCESS, 45 FCOE_COMPLETION_STATUS_FCOE_VER_ERR, 46 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR, 47 MAX_FCOE_COMPLETION_STATUS 48}; 49 50struct fc_addr_nw { 51 u8 addr_lo; 52 u8 addr_mid; 53 u8 addr_hi; 54}; 55 56/* FCoE connection offload */ 57struct fcoe_conn_offload_ramrod_data { 58 struct regpair sq_pbl_addr; 59 struct regpair sq_curr_page_addr; 60 struct regpair sq_next_page_addr; 61 struct regpair xferq_pbl_addr; 62 struct regpair xferq_curr_page_addr; 63 struct regpair xferq_next_page_addr; 64 struct regpair respq_pbl_addr; 65 struct regpair respq_curr_page_addr; 66 struct regpair respq_next_page_addr; 67 __le16 dst_mac_addr_lo; 68 __le16 dst_mac_addr_mid; 69 __le16 dst_mac_addr_hi; 70 __le16 src_mac_addr_lo; 71 __le16 src_mac_addr_mid; 72 __le16 src_mac_addr_hi; 73 __le16 tx_max_fc_pay_len; 74 __le16 e_d_tov_timer_val; 75 __le16 rx_max_fc_pay_len; 76 __le16 vlan_tag; 77#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF 78#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0 79#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1 80#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12 81#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7 82#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13 83 __le16 physical_q0; 84 __le16 rec_rr_tov_timer_val; 85 struct fc_addr_nw s_id; 86 u8 max_conc_seqs_c3; 87 struct fc_addr_nw d_id; 88 u8 flags; 89#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1 90#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0 91#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1 92#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1 93#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1 94#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2 95#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1 96#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3 97#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3 98#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4 99#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3 100#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6 101 __le16 conn_id; 102 u8 def_q_idx; 103 u8 reserved[5]; 104}; 105 106/* FCoE terminate connection request */ 107struct fcoe_conn_terminate_ramrod_data { 108 struct regpair terminate_params_addr; 109}; 110 111struct fcoe_slow_sgl_ctx { 112 struct regpair base_sgl_addr; 113 __le16 curr_sge_off; 114 __le16 remainder_num_sges; 115 __le16 curr_sgl_index; 116 __le16 reserved; 117}; 118 119union fcoe_dix_desc_ctx { 120 struct fcoe_slow_sgl_ctx dix_sgl; 121 struct scsi_sge cached_dix_sge; 122}; 123 124struct fcoe_fast_sgl_ctx { 125 struct regpair sgl_start_addr; 126 __le32 sgl_byte_offset; 127 __le16 task_reuse_cnt; 128 __le16 init_offset_in_first_sge; 129}; 130 131struct fcoe_fcp_cmd_payload { 132 __le32 opaque[8]; 133}; 134 135struct fcoe_fcp_rsp_payload { 136 __le32 opaque[6]; 137}; 138 139struct fcoe_fcp_xfer_payload { 140 __le32 opaque[3]; 141}; 142 143/* FCoE firmware function init */ 144struct fcoe_init_func_ramrod_data { 145 struct scsi_init_func_params func_params; 146 struct scsi_init_func_queues q_params; 147 __le16 mtu; 148 __le16 sq_num_pages_in_pbl; 149 __le32 reserved; 150}; 151 152/* FCoE: Mode of the connection: Target or Initiator or both */ 153enum fcoe_mode_type { 154 FCOE_INITIATOR_MODE = 0x0, 155 FCOE_TARGET_MODE = 0x1, 156 FCOE_BOTH_OR_NOT_CHOSEN = 0x3, 157 MAX_FCOE_MODE_TYPE 158}; 159 160struct fcoe_rx_stat { 161 struct regpair fcoe_rx_byte_cnt; 162 struct regpair fcoe_rx_data_pkt_cnt; 163 struct regpair fcoe_rx_xfer_pkt_cnt; 164 struct regpair fcoe_rx_other_pkt_cnt; 165 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt; 166 __le32 fcoe_silent_drop_pkt_rq_full_cnt; 167 __le32 fcoe_silent_drop_pkt_crc_error_cnt; 168 __le32 fcoe_silent_drop_pkt_task_invalid_cnt; 169 __le32 fcoe_silent_drop_total_pkt_cnt; 170 __le32 rsrv; 171}; 172 173struct fcoe_stat_ramrod_data { 174 struct regpair stat_params_addr; 175}; 176 177struct protection_info_ctx { 178 __le16 flags; 179#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3 180#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0 181#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1 182#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2 183#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1 184#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3 185#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF 186#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4 187#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 188#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8 189#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F 190#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9 191 u8 dix_block_size; 192 u8 dst_size; 193}; 194 195union protection_info_union_ctx { 196 struct protection_info_ctx info; 197 __le32 value; 198}; 199 200struct fcp_rsp_payload_padded { 201 struct fcoe_fcp_rsp_payload rsp_payload; 202 __le32 reserved[2]; 203}; 204 205struct fcp_xfer_payload_padded { 206 struct fcoe_fcp_xfer_payload xfer_payload; 207 __le32 reserved[5]; 208}; 209 210struct fcoe_tx_data_params { 211 __le32 data_offset; 212 __le32 offset_in_io; 213 u8 flags; 214#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1 215#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0 216#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1 217#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1 218#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1 219#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2 220#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F 221#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3 222 u8 dif_residual; 223 __le16 seq_cnt; 224 __le16 single_sge_saved_offset; 225 __le16 next_dif_offset; 226 __le16 seq_id; 227 __le16 reserved3; 228}; 229 230struct fcoe_tx_mid_path_params { 231 __le32 parameter; 232 u8 r_ctl; 233 u8 type; 234 u8 cs_ctl; 235 u8 df_ctl; 236 __le16 rx_id; 237 __le16 ox_id; 238}; 239 240struct fcoe_tx_params { 241 struct fcoe_tx_data_params data; 242 struct fcoe_tx_mid_path_params mid_path; 243}; 244 245union fcoe_tx_info_union_ctx { 246 struct fcoe_fcp_cmd_payload fcp_cmd_payload; 247 struct fcp_rsp_payload_padded fcp_rsp_payload; 248 struct fcp_xfer_payload_padded fcp_xfer_payload; 249 struct fcoe_tx_params tx_params; 250}; 251 252struct ystorm_fcoe_task_st_ctx { 253 u8 task_type; 254 u8 sgl_mode; 255#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 256#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0 257#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F 258#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1 259 u8 cached_dix_sge; 260 u8 expect_first_xfer; 261 __le32 num_pbf_zero_write; 262 union protection_info_union_ctx protection_info_union; 263 __le32 data_2_trns_rem; 264 struct scsi_sgl_params sgl_params; 265 u8 reserved1[12]; 266 union fcoe_tx_info_union_ctx tx_info_union; 267 union fcoe_dix_desc_ctx dix_desc; 268 struct scsi_cached_sges data_desc; 269 __le16 ox_id; 270 __le16 rx_id; 271 __le32 task_rety_identifier; 272 u8 reserved2[8]; 273}; 274 275struct ystorm_fcoe_task_ag_ctx { 276 u8 byte0; 277 u8 byte1; 278 __le16 word0; 279 u8 flags0; 280#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF 281#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 282#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 283#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 284#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 285#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 286#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 287#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 288#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 289#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 290 u8 flags1; 291#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 292#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 293#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 294#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 295#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 296#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 297#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 298#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 299#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 300#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 301 u8 flags2; 302#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 303#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 304#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 305#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 306#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 307#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 308#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 309#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 310#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 311#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 312#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 313#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 314#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 315#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 316#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 317#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 318 u8 byte2; 319 __le32 reg0; 320 u8 byte3; 321 u8 byte4; 322 __le16 rx_id; 323 __le16 word2; 324 __le16 word3; 325 __le16 word4; 326 __le16 word5; 327 __le32 reg1; 328 __le32 reg2; 329}; 330 331struct tstorm_fcoe_task_ag_ctx { 332 u8 reserved; 333 u8 byte1; 334 __le16 icid; 335 u8 flags0; 336#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 337#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 338#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 339#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 340#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 341#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 342#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 343#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 344#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 345#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 346 u8 flags1; 347#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 348#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 349#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 350#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 351#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 352#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 353#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 354#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 355#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 356#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 357 u8 flags2; 358#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 359#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 360#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 361#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 362#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 363#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 364#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 365#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 366 u8 flags3; 367#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 368#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 369#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 370#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 371#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 372#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 373#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 374#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 375#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 376#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 377#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 378#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 379#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 380#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 381 u8 flags4; 382#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 383#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 384#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 385#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 386#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 387#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 388#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 389#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 390#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 391#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 392#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 393#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 394#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 395#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 396#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 397#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 398 u8 cleanup_state; 399 __le16 last_sent_tid; 400 __le32 rec_rr_tov_exp_timeout; 401 u8 byte3; 402 u8 byte4; 403 __le16 word2; 404 __le16 word3; 405 __le16 word4; 406 __le32 data_offset_end_of_seq; 407 __le32 data_offset_next; 408}; 409 410struct fcoe_tstorm_fcoe_task_st_ctx_read_write { 411 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union; 412 __le16 flags; 413#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1 414#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0 415#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1 416#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1 417#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1 418#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2 419#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1 420#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3 421#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1 422#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4 423#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1 424#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5 425#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3 426#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6 427#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF 428#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8 429 __le16 seq_cnt; 430 u8 seq_id; 431 u8 ooo_rx_seq_id; 432 __le16 rx_id; 433 struct fcoe_abts_pkt abts_data; 434 __le32 e_d_tov_exp_timeout_val; 435 __le16 ooo_rx_seq_cnt; 436 __le16 reserved1; 437}; 438 439struct fcoe_tstorm_fcoe_task_st_ctx_read_only { 440 u8 task_type; 441 u8 dev_type; 442 u8 conf_supported; 443 u8 glbl_q_num; 444 __le32 cid; 445 __le32 fcp_cmd_trns_size; 446 __le32 rsrv; 447}; 448 449struct tstorm_fcoe_task_st_ctx { 450 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write; 451 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only; 452}; 453 454struct mstorm_fcoe_task_ag_ctx { 455 u8 byte0; 456 u8 byte1; 457 __le16 icid; 458 u8 flags0; 459#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 460#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 461#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 462#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 463#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 464#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 465#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 466#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 467#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 468#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 469 u8 flags1; 470#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 471#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 472#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 473#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 474#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 475#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 476#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 477#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 478#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 479#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 480 u8 flags2; 481#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 482#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 483#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 484#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 485#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 486#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 487#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 488#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 489#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 490#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 491#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 492#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 493#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 494#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 495#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 496#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 497 u8 cleanup_state; 498 __le32 received_bytes; 499 u8 byte3; 500 u8 glbl_q_num; 501 __le16 word1; 502 __le16 tid_to_xfer; 503 __le16 word3; 504 __le16 word4; 505 __le16 word5; 506 __le32 expected_bytes; 507 __le32 reg2; 508}; 509 510struct mstorm_fcoe_task_st_ctx { 511 struct regpair rsp_buf_addr; 512 __le32 rsrv[2]; 513 struct scsi_sgl_params sgl_params; 514 __le32 data_2_trns_rem; 515 __le32 data_buffer_offset; 516 __le16 parent_id; 517 __le16 flags; 518#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF 519#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0 520#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3 521#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4 522#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1 523#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6 524#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1 525#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7 526#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3 527#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8 528#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 529#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10 530#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1 531#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11 532#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1 533#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12 534#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 535#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13 536#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3 537#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14 538 struct scsi_cached_sges data_desc; 539}; 540 541struct ustorm_fcoe_task_ag_ctx { 542 u8 reserved; 543 u8 byte1; 544 __le16 icid; 545 u8 flags0; 546#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 547#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 548#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 549#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 550#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 551#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 552#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 553#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 554 u8 flags1; 555#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 556#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 557#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 558#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 559#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 560#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 561#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 562#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 563 u8 flags2; 564#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 565#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 566#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 567#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 568#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 569#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 570#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 571#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 572#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 573#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 574#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 575#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 576#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 577#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 578#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 579#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 580 u8 flags3; 581#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 582#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 583#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 584#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 585#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 586#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 587#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 588#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 589#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF 590#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 591 __le32 dif_err_intervals; 592 __le32 dif_error_1st_interval; 593 __le32 global_cq_num; 594 __le32 reg3; 595 __le32 reg4; 596 __le32 reg5; 597}; 598 599struct fcoe_task_context { 600 struct ystorm_fcoe_task_st_ctx ystorm_st_context; 601 struct regpair ystorm_st_padding[2]; 602 struct tdif_task_context tdif_context; 603 struct ystorm_fcoe_task_ag_ctx ystorm_ag_context; 604 struct tstorm_fcoe_task_ag_ctx tstorm_ag_context; 605 struct timers_context timer_context; 606 struct tstorm_fcoe_task_st_ctx tstorm_st_context; 607 struct regpair tstorm_st_padding[2]; 608 struct mstorm_fcoe_task_ag_ctx mstorm_ag_context; 609 struct mstorm_fcoe_task_st_ctx mstorm_st_context; 610 struct ustorm_fcoe_task_ag_ctx ustorm_ag_context; 611 struct rdif_task_context rdif_context; 612}; 613 614struct fcoe_tx_stat { 615 struct regpair fcoe_tx_byte_cnt; 616 struct regpair fcoe_tx_data_pkt_cnt; 617 struct regpair fcoe_tx_xfer_pkt_cnt; 618 struct regpair fcoe_tx_other_pkt_cnt; 619}; 620 621struct fcoe_wqe { 622 __le16 task_id; 623 __le16 flags; 624#define FCOE_WQE_REQ_TYPE_MASK 0xF 625#define FCOE_WQE_REQ_TYPE_SHIFT 0 626#define FCOE_WQE_SGL_MODE_MASK 0x1 627#define FCOE_WQE_SGL_MODE_SHIFT 4 628#define FCOE_WQE_CONTINUATION_MASK 0x1 629#define FCOE_WQE_CONTINUATION_SHIFT 5 630#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1 631#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6 632#define FCOE_WQE_RESERVED_MASK 0x1 633#define FCOE_WQE_RESERVED_SHIFT 7 634#define FCOE_WQE_NUM_SGES_MASK 0xF 635#define FCOE_WQE_NUM_SGES_SHIFT 8 636#define FCOE_WQE_RESERVED1_MASK 0xF 637#define FCOE_WQE_RESERVED1_SHIFT 12 638 union fcoe_additional_info_union additional_info_union; 639}; 640 641struct xfrqe_prot_flags { 642 u8 flags; 643#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF 644#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0 645#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1 646#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4 647#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3 648#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5 649#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1 650#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7 651}; 652 653struct fcoe_db_data { 654 u8 params; 655#define FCOE_DB_DATA_DEST_MASK 0x3 656#define FCOE_DB_DATA_DEST_SHIFT 0 657#define FCOE_DB_DATA_AGG_CMD_MASK 0x3 658#define FCOE_DB_DATA_AGG_CMD_SHIFT 2 659#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1 660#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4 661#define FCOE_DB_DATA_RESERVED_MASK 0x1 662#define FCOE_DB_DATA_RESERVED_SHIFT 5 663#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3 664#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6 665 u8 agg_flags; 666 __le16 sq_prod; 667}; 668#endif /* __FCOE_COMMON__ */ 669