1#ifndef _ASM_S390_PCI_CLP_H 2#define _ASM_S390_PCI_CLP_H 3 4#include <asm/clp.h> 5 6/* 7 * Call Logical Processor - Command Codes 8 */ 9#define CLP_LIST_PCI 0x0002 10#define CLP_QUERY_PCI_FN 0x0003 11#define CLP_QUERY_PCI_FNGRP 0x0004 12#define CLP_SET_PCI_FN 0x0005 13 14/* PCI function handle list entry */ 15struct clp_fh_list_entry { 16 u16 device_id; 17 u16 vendor_id; 18 u32 config_state : 1; 19 u32 : 31; 20 u32 fid; /* PCI function id */ 21 u32 fh; /* PCI function handle */ 22} __packed; 23 24#define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */ 25#define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */ 26#define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */ 27#define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */ 28#define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */ 29#define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */ 30#define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */ 31#define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */ 32#define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */ 33#define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */ 34 35/* request or response block header length */ 36#define LIST_PCI_HDR_LEN 32 37 38/* Number of function handles fitting in response block */ 39#define CLP_FH_LIST_NR_ENTRIES \ 40 ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \ 41 / sizeof(struct clp_fh_list_entry)) 42 43#define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */ 44#define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */ 45 46#define CLP_UTIL_STR_LEN 64 47#define CLP_PFIP_NR_SEGMENTS 4 48 49extern bool zpci_unique_uid; 50 51/* List PCI functions request */ 52struct clp_req_list_pci { 53 struct clp_req_hdr hdr; 54 u32 fmt : 4; /* cmd request block format */ 55 u32 : 28; 56 u64 reserved1; 57 u64 resume_token; 58 u64 reserved2; 59} __packed; 60 61/* List PCI functions response */ 62struct clp_rsp_list_pci { 63 struct clp_rsp_hdr hdr; 64 u32 fmt : 4; /* cmd request block format */ 65 u32 : 28; 66 u64 reserved1; 67 u64 resume_token; 68 u32 reserved2; 69 u16 max_fn; 70 u8 : 7; 71 u8 uid_checking : 1; 72 u8 entry_size; 73 struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES]; 74} __packed; 75 76/* Query PCI function request */ 77struct clp_req_query_pci { 78 struct clp_req_hdr hdr; 79 u32 fmt : 4; /* cmd request block format */ 80 u32 : 28; 81 u64 reserved1; 82 u32 fh; /* function handle */ 83 u32 reserved2; 84 u64 reserved3; 85} __packed; 86 87/* Query PCI function response */ 88struct clp_rsp_query_pci { 89 struct clp_rsp_hdr hdr; 90 u32 fmt : 4; /* cmd request block format */ 91 u32 : 28; 92 u64 : 64; 93 u16 vfn; /* virtual fn number */ 94 u16 : 7; 95 u16 util_str_avail : 1; /* utility string available? */ 96 u16 pfgid : 8; /* pci function group id */ 97 u32 fid; /* pci function id */ 98 u8 bar_size[PCI_BAR_COUNT]; 99 u16 pchid; 100 u32 bar[PCI_BAR_COUNT]; 101 u8 pfip[CLP_PFIP_NR_SEGMENTS]; /* pci function internal path */ 102 u32 : 16; 103 u8 fmb_len; 104 u8 pft; /* pci function type */ 105 u64 sdma; /* start dma as */ 106 u64 edma; /* end dma as */ 107 u32 reserved[11]; 108 u32 uid; /* user defined id */ 109 u8 util_str[CLP_UTIL_STR_LEN]; /* utility string */ 110} __packed; 111 112/* Query PCI function group request */ 113struct clp_req_query_pci_grp { 114 struct clp_req_hdr hdr; 115 u32 fmt : 4; /* cmd request block format */ 116 u32 : 28; 117 u64 reserved1; 118 u32 : 24; 119 u32 pfgid : 8; /* function group id */ 120 u32 reserved2; 121 u64 reserved3; 122} __packed; 123 124/* Query PCI function group response */ 125struct clp_rsp_query_pci_grp { 126 struct clp_rsp_hdr hdr; 127 u32 fmt : 4; /* cmd request block format */ 128 u32 : 28; 129 u64 reserved1; 130 u16 : 4; 131 u16 noi : 12; /* number of interrupts */ 132 u8 version; 133 u8 : 6; 134 u8 frame : 1; 135 u8 refresh : 1; /* TLB refresh mode */ 136 u16 reserved2; 137 u16 mui; 138 u64 reserved3; 139 u64 dasm; /* dma address space mask */ 140 u64 msia; /* MSI address */ 141 u64 reserved4; 142 u64 reserved5; 143} __packed; 144 145/* Set PCI function request */ 146struct clp_req_set_pci { 147 struct clp_req_hdr hdr; 148 u32 fmt : 4; /* cmd request block format */ 149 u32 : 28; 150 u64 reserved1; 151 u32 fh; /* function handle */ 152 u16 reserved2; 153 u8 oc; /* operation controls */ 154 u8 ndas; /* number of dma spaces */ 155 u64 reserved3; 156} __packed; 157 158/* Set PCI function response */ 159struct clp_rsp_set_pci { 160 struct clp_rsp_hdr hdr; 161 u32 fmt : 4; /* cmd request block format */ 162 u32 : 28; 163 u64 reserved1; 164 u32 fh; /* function handle */ 165 u32 reserved3; 166 u64 reserved4; 167} __packed; 168 169/* Combined request/response block structures used by clp insn */ 170struct clp_req_rsp_list_pci { 171 struct clp_req_list_pci request; 172 struct clp_rsp_list_pci response; 173} __packed; 174 175struct clp_req_rsp_set_pci { 176 struct clp_req_set_pci request; 177 struct clp_rsp_set_pci response; 178} __packed; 179 180struct clp_req_rsp_query_pci { 181 struct clp_req_query_pci request; 182 struct clp_rsp_query_pci response; 183} __packed; 184 185struct clp_req_rsp_query_pci_grp { 186 struct clp_req_query_pci_grp request; 187 struct clp_rsp_query_pci_grp response; 188} __packed; 189 190#endif 191