1/* 2 * Copyright 2011 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15/* 16 * @file 17 * Global header file. 18 * This header file specifies defines for TILE-Gx. 19 */ 20 21#ifndef __ARCH_CHIP_H__ 22#define __ARCH_CHIP_H__ 23 24/** Specify chip version. 25 * When possible, prefer the CHIP_xxx symbols below for future-proofing. 26 * This is intended for cross-compiling; native compilation should 27 * use the predefined __tile_chip__ symbol. 28 */ 29#define TILE_CHIP 10 30 31/** Specify chip revision. 32 * This provides for the case of a respin of a particular chip type; 33 * the normal value for this symbol is "0". 34 * This is intended for cross-compiling; native compilation should 35 * use the predefined __tile_chip_rev__ symbol. 36 */ 37#define TILE_CHIP_REV 0 38 39/** The name of this architecture. */ 40#define CHIP_ARCH_NAME "tilegx" 41 42/** The ELF e_machine type for binaries for this chip. */ 43#define CHIP_ELF_TYPE() EM_TILEGX 44 45/** The alternate ELF e_machine type for binaries for this chip. */ 46#define CHIP_COMPAT_ELF_TYPE() 0x2597 47 48/** What is the native word size of the machine? */ 49#define CHIP_WORD_SIZE() 64 50 51/** How many bits of a virtual address are used. Extra bits must be 52 * the sign extension of the low bits. 53 */ 54#define CHIP_VA_WIDTH() 42 55 56/** How many bits are in a physical address? */ 57#define CHIP_PA_WIDTH() 40 58 59/** Size of the L2 cache, in bytes. */ 60#define CHIP_L2_CACHE_SIZE() 262144 61 62/** Log size of an L2 cache line in bytes. */ 63#define CHIP_L2_LOG_LINE_SIZE() 6 64 65/** Size of an L2 cache line, in bytes. */ 66#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE()) 67 68/** Associativity of the L2 cache. */ 69#define CHIP_L2_ASSOC() 8 70 71/** Size of the L1 data cache, in bytes. */ 72#define CHIP_L1D_CACHE_SIZE() 32768 73 74/** Log size of an L1 data cache line in bytes. */ 75#define CHIP_L1D_LOG_LINE_SIZE() 6 76 77/** Size of an L1 data cache line, in bytes. */ 78#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE()) 79 80/** Associativity of the L1 data cache. */ 81#define CHIP_L1D_ASSOC() 2 82 83/** Size of the L1 instruction cache, in bytes. */ 84#define CHIP_L1I_CACHE_SIZE() 32768 85 86/** Log size of an L1 instruction cache line in bytes. */ 87#define CHIP_L1I_LOG_LINE_SIZE() 6 88 89/** Size of an L1 instruction cache line, in bytes. */ 90#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE()) 91 92/** Associativity of the L1 instruction cache. */ 93#define CHIP_L1I_ASSOC() 2 94 95/** Stride with which flush instructions must be issued. */ 96#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE() 97 98/** Stride with which inv instructions must be issued. */ 99#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE() 100 101/** Stride with which finv instructions must be issued. */ 102#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE() 103 104/** Can the local cache coherently cache data that is homed elsewhere? */ 105#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1 106 107/** How many simultaneous outstanding victims can the L2 cache have? */ 108#define CHIP_MAX_OUTSTANDING_VICTIMS() 128 109 110/** Does the TLB support the NC and NOALLOC bits? */ 111#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1 112 113/** Does the chip support hash-for-home caching? */ 114#define CHIP_HAS_CBOX_HOME_MAP() 1 115 116/** Number of entries in the chip's home map tables. */ 117#define CHIP_CBOX_HOME_MAP_SIZE() 128 118 119/** Do uncacheable requests miss in the cache regardless of whether 120 * there is matching data? */ 121#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1 122 123/** Does the mf instruction wait for victims? */ 124#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0 125 126/** Does the chip have an "inv" instruction that doesn't also flush? */ 127#define CHIP_HAS_INV() 1 128 129/** Does the chip have a "wh64" instruction? */ 130#define CHIP_HAS_WH64() 1 131 132/** Does this chip have a 'dword_align' instruction? */ 133#define CHIP_HAS_DWORD_ALIGN() 0 134 135/** Number of performance counters. */ 136#define CHIP_PERFORMANCE_COUNTERS() 4 137 138/** Does this chip have auxiliary performance counters? */ 139#define CHIP_HAS_AUX_PERF_COUNTERS() 1 140 141/** Is the CBOX_MSR1 SPR supported? */ 142#define CHIP_HAS_CBOX_MSR1() 0 143 144/** Is the TILE_RTF_HWM SPR supported? */ 145#define CHIP_HAS_TILE_RTF_HWM() 1 146 147/** Is the TILE_WRITE_PENDING SPR supported? */ 148#define CHIP_HAS_TILE_WRITE_PENDING() 0 149 150/** Is the PROC_STATUS SPR supported? */ 151#define CHIP_HAS_PROC_STATUS_SPR() 1 152 153/** Is the DSTREAM_PF SPR supported? */ 154#define CHIP_HAS_DSTREAM_PF() 1 155 156/** Log of the number of mshims we have. */ 157#define CHIP_LOG_NUM_MSHIMS() 2 158 159/** Are the bases of the interrupt vector areas fixed? */ 160#define CHIP_HAS_FIXED_INTVEC_BASE() 0 161 162/** Are the interrupt masks split up into 2 SPRs? */ 163#define CHIP_HAS_SPLIT_INTR_MASK() 0 164 165/** Is the cycle count split up into 2 SPRs? */ 166#define CHIP_HAS_SPLIT_CYCLE() 0 167 168/** Does the chip have a static network? */ 169#define CHIP_HAS_SN() 0 170 171/** Does the chip have a static network processor? */ 172#define CHIP_HAS_SN_PROC() 0 173 174/** Size of the L1 static network processor instruction cache, in bytes. */ 175/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */ 176 177/** Does the chip have DMA support in each tile? */ 178#define CHIP_HAS_TILE_DMA() 0 179 180/** Does the chip have the second revision of the directly accessible 181 * dynamic networks? This encapsulates a number of characteristics, 182 * including the absence of the catch-all, the absence of inline message 183 * tags, the absence of support for network context-switching, and so on. 184 */ 185#define CHIP_HAS_REV1_XDN() 1 186 187/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */ 188#define CHIP_HAS_CMPEXCH() 1 189 190/** Does the chip have memory-mapped I/O support? */ 191#define CHIP_HAS_MMIO() 1 192 193/** Does the chip have post-completion interrupts? */ 194#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1 195 196/** Does the chip have native single step support? */ 197#define CHIP_HAS_SINGLE_STEP() 1 198 199#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */ 200 201/** How many entries are present in the instruction TLB? */ 202#define CHIP_ITLB_ENTRIES() 16 203 204/** How many entries are present in the data TLB? */ 205#define CHIP_DTLB_ENTRIES() 32 206 207/** How many MAF entries does the XAUI shim have? */ 208#define CHIP_XAUI_MAF_ENTRIES() 32 209 210/** Does the memory shim have a source-id table? */ 211#define CHIP_HAS_MSHIM_SRCID_TABLE() 0 212 213/** Does the L1 instruction cache clear on reset? */ 214#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1 215 216/** Does the chip come out of reset with valid coordinates on all tiles? 217 * Note that if defined, this also implies that the upper left is 1,1. 218 */ 219#define CHIP_HAS_VALID_TILE_COORD_RESET() 1 220 221/** Does the chip have unified packet formats? */ 222#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1 223 224/** Does the chip support write reordering? */ 225#define CHIP_HAS_WRITE_REORDERING() 1 226 227/** Does the chip support Y-X routing as well as X-Y? */ 228#define CHIP_HAS_Y_X_ROUTING() 1 229 230/** Is INTCTRL_3 managed with the correct MPL? */ 231#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1 232 233/** Is it possible to configure the chip to be big-endian? */ 234#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1 235 236/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */ 237#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0 238 239/** Is the DIAG_TRACE_WAY SPR supported? */ 240#define CHIP_HAS_DIAG_TRACE_WAY() 0 241 242/** Is the MEM_STRIPE_CONFIG SPR supported? */ 243#define CHIP_HAS_MEM_STRIPE_CONFIG() 1 244 245/** Are the TLB_PERF SPRs supported? */ 246#define CHIP_HAS_TLB_PERF() 1 247 248/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */ 249#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0 250 251/** Does the chip support rev1 DMA packets? */ 252#define CHIP_HAS_REV1_DMA_PACKETS() 1 253 254/** Does the chip have an IPI shim? */ 255#define CHIP_HAS_IPI() 1 256 257#endif /* !__OPEN_SOURCE__ */ 258#endif /* __ARCH_CHIP_H__ */ 259