1#ifndef _ASM_X86_APIC_H
2#define _ASM_X86_APIC_H
3
4#include <linux/cpumask.h>
5#include <linux/pm.h>
6
7#include <asm/alternative.h>
8#include <asm/cpufeature.h>
9#include <asm/apicdef.h>
10#include <linux/atomic.h>
11#include <asm/fixmap.h>
12#include <asm/mpspec.h>
13#include <asm/msr.h>
14#include <asm/idle.h>
15
16#define ARCH_APICTIMER_STOPS_ON_C3 1
17
18
19
20
21#define APIC_QUIET 0
22#define APIC_VERBOSE 1
23#define APIC_DEBUG 2
24
25
26#define APIC_EXTNMI_BSP 0
27#define APIC_EXTNMI_ALL 1
28#define APIC_EXTNMI_NONE 2
29
30
31
32
33
34
35
36#define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
38 printk(s, ##a); \
39 } while (0)
40
41
42#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43extern void generic_apic_probe(void);
44#else
45static inline void generic_apic_probe(void)
46{
47}
48#endif
49
50#ifdef CONFIG_X86_LOCAL_APIC
51
52extern unsigned int apic_verbosity;
53extern int local_apic_timer_c2_ok;
54
55extern int disable_apic;
56extern unsigned int lapic_timer_frequency;
57
58#ifdef CONFIG_SMP
59extern void __inquire_remote_apic(int apicid);
60#else
61static inline void __inquire_remote_apic(int apicid)
62{
63}
64#endif
65
66static inline void default_inquire_remote_apic(int apicid)
67{
68 if (apic_verbosity >= APIC_DEBUG)
69 __inquire_remote_apic(apicid);
70}
71
72
73
74
75
76
77
78
79
80static inline bool apic_from_smp_config(void)
81{
82 return smp_found_config && !disable_apic;
83}
84
85
86
87
88#ifdef CONFIG_PARAVIRT
89#include <asm/paravirt.h>
90#endif
91
92#ifdef CONFIG_X86_64
93extern int is_vsmp_box(void);
94#else
95static inline int is_vsmp_box(void)
96{
97 return 0;
98}
99#endif
100extern void xapic_wait_icr_idle(void);
101extern u32 safe_xapic_wait_icr_idle(void);
102extern void xapic_icr_write(u32, u32);
103extern int setup_profiling_timer(unsigned int);
104
105static inline void native_apic_mem_write(u32 reg, u32 v)
106{
107 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
108
109 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
110 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
111 ASM_OUTPUT2("0" (v), "m" (*addr)));
112}
113
114static inline u32 native_apic_mem_read(u32 reg)
115{
116 return *((volatile u32 *)(APIC_BASE + reg));
117}
118
119extern void native_apic_wait_icr_idle(void);
120extern u32 native_safe_apic_wait_icr_idle(void);
121extern void native_apic_icr_write(u32 low, u32 id);
122extern u64 native_apic_icr_read(void);
123
124extern int x2apic_mode;
125
126#ifdef CONFIG_X86_X2APIC
127
128
129
130
131
132static inline void x2apic_wrmsr_fence(void)
133{
134 asm volatile("mfence" : : : "memory");
135}
136
137static inline void native_apic_msr_write(u32 reg, u32 v)
138{
139 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
140 reg == APIC_LVR)
141 return;
142
143 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
144}
145
146static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
147{
148 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
149}
150
151static inline u32 native_apic_msr_read(u32 reg)
152{
153 u64 msr;
154
155 if (reg == APIC_DFR)
156 return -1;
157
158 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
159 return (u32)msr;
160}
161
162static inline void native_x2apic_wait_icr_idle(void)
163{
164
165 return;
166}
167
168static inline u32 native_safe_x2apic_wait_icr_idle(void)
169{
170
171 return 0;
172}
173
174static inline void native_x2apic_icr_write(u32 low, u32 id)
175{
176 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
177}
178
179static inline u64 native_x2apic_icr_read(void)
180{
181 unsigned long val;
182
183 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
184 return val;
185}
186
187extern int x2apic_phys;
188extern int x2apic_preenabled;
189extern void check_x2apic(void);
190extern void enable_x2apic(void);
191extern void x2apic_icr_write(u32 low, u32 id);
192static inline int x2apic_enabled(void)
193{
194 u64 msr;
195
196 if (!cpu_has_x2apic)
197 return 0;
198
199 rdmsrl(MSR_IA32_APICBASE, msr);
200 if (msr & X2APIC_ENABLE)
201 return 1;
202 return 0;
203}
204
205#define x2apic_supported() (cpu_has_x2apic)
206static inline void x2apic_force_phys(void)
207{
208 x2apic_phys = 1;
209}
210#else
211static inline void disable_x2apic(void)
212{
213}
214static inline void check_x2apic(void)
215{
216}
217static inline void enable_x2apic(void)
218{
219}
220static inline int x2apic_enabled(void)
221{
222 return 0;
223}
224static inline void x2apic_force_phys(void)
225{
226}
227
228#define nox2apic 0
229#define x2apic_preenabled 0
230#define x2apic_supported() 0
231#endif
232
233extern void enable_IR_x2apic(void);
234
235extern int get_physical_broadcast(void);
236
237extern int lapic_get_maxlvt(void);
238extern void clear_local_APIC(void);
239extern void connect_bsp_APIC(void);
240extern void disconnect_bsp_APIC(int virt_wire_setup);
241extern void disable_local_APIC(void);
242extern void lapic_shutdown(void);
243extern int verify_local_APIC(void);
244extern void sync_Arb_IDs(void);
245extern void init_bsp_APIC(void);
246extern void setup_local_APIC(void);
247extern void end_local_APIC_setup(void);
248extern void bsp_end_local_APIC_setup(void);
249extern void init_apic_mappings(void);
250void register_lapic_address(unsigned long address);
251extern void setup_boot_APIC_clock(void);
252extern void setup_secondary_APIC_clock(void);
253extern int APIC_init_uniprocessor(void);
254extern int apic_force_enable(unsigned long addr);
255
256
257
258
259#ifdef CONFIG_X86_64
260extern int apic_is_clustered_box(void);
261#else
262static inline int apic_is_clustered_box(void)
263{
264 return 0;
265}
266#endif
267
268extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
269
270#else
271static inline void lapic_shutdown(void) { }
272#define local_apic_timer_c2_ok 1
273static inline void init_apic_mappings(void) { }
274static inline void disable_local_APIC(void) { }
275# define setup_boot_APIC_clock x86_init_noop
276# define setup_secondary_APIC_clock x86_init_noop
277#endif
278
279#ifdef CONFIG_X86_64
280#define SET_APIC_ID(x) (apic->set_apic_id(x))
281#else
282
283#endif
284
285
286
287
288
289
290
291
292
293
294
295struct apic {
296 char *name;
297
298 int (*probe)(void);
299 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
300 int (*apic_id_valid)(int apicid);
301 int (*apic_id_registered)(void);
302
303 u32 irq_delivery_mode;
304 u32 irq_dest_mode;
305
306 const struct cpumask *(*target_cpus)(void);
307
308 int disable_esr;
309
310 int dest_logical;
311 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
312 unsigned long (*check_apicid_present)(int apicid);
313
314 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
315 const struct cpumask *mask);
316 void (*init_apic_ldr)(void);
317
318 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
319
320 void (*setup_apic_routing)(void);
321 int (*multi_timer_check)(int apic, int irq);
322 int (*cpu_present_to_apicid)(int mps_cpu);
323 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
324 void (*setup_portio_remap)(void);
325 int (*check_phys_apicid_present)(int phys_apicid);
326 void (*enable_apic_mode)(void);
327 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
328
329
330
331
332
333
334 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
335
336 unsigned int (*get_apic_id)(unsigned long x);
337 unsigned long (*set_apic_id)(unsigned int id);
338 unsigned long apic_id_mask;
339
340 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
341 const struct cpumask *andmask,
342 unsigned int *apicid);
343
344
345 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
346 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
347 int vector);
348 void (*send_IPI_allbutself)(int vector);
349 void (*send_IPI_all)(int vector);
350 void (*send_IPI_self)(int vector);
351
352
353 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
354
355 int trampoline_phys_low;
356 int trampoline_phys_high;
357
358 void (*wait_for_init_deassert)(atomic_t *deassert);
359 void (*smp_callin_clear_local_apic)(void);
360 void (*inquire_remote_apic)(int apicid);
361
362
363 u32 (*read)(u32 reg);
364 void (*write)(u32 reg, u32 v);
365
366
367
368
369
370
371
372 void (*eoi_write)(u32 reg, u32 v);
373 u64 (*icr_read)(void);
374 void (*icr_write)(u32 low, u32 high);
375 void (*wait_icr_idle)(void);
376 u32 (*safe_wait_icr_idle)(void);
377
378#ifdef CONFIG_X86_32
379
380
381
382
383
384
385
386
387
388
389 int (*x86_32_early_logical_apicid)(int cpu);
390
391
392
393
394
395
396
397 int (*x86_32_numa_cpu_node)(int cpu);
398#endif
399};
400
401
402
403
404
405
406extern struct apic *apic;
407
408
409
410
411
412
413
414
415
416#define apic_driver(sym) \
417 static const struct apic *__apicdrivers_##sym __used \
418 __aligned(sizeof(struct apic *)) \
419 __section(.apicdrivers) = { &sym }
420
421#define apic_drivers(sym1, sym2) \
422 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
423 __aligned(sizeof(struct apic *)) \
424 __section(.apicdrivers) = { &sym1, &sym2 }
425
426extern struct apic *__apicdrivers[], *__apicdrivers_end[];
427
428
429
430
431#ifdef CONFIG_SMP
432extern atomic_t init_deasserted;
433extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
434#endif
435
436#ifdef CONFIG_X86_LOCAL_APIC
437
438static inline u32 apic_read(u32 reg)
439{
440 return apic->read(reg);
441}
442
443static inline void apic_write(u32 reg, u32 val)
444{
445 apic->write(reg, val);
446}
447
448static inline void apic_eoi(void)
449{
450 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
451}
452
453static inline u64 apic_icr_read(void)
454{
455 return apic->icr_read();
456}
457
458static inline void apic_icr_write(u32 low, u32 high)
459{
460 apic->icr_write(low, high);
461}
462
463static inline void apic_wait_icr_idle(void)
464{
465 apic->wait_icr_idle();
466}
467
468static inline u32 safe_apic_wait_icr_idle(void)
469{
470 return apic->safe_wait_icr_idle();
471}
472
473extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
474
475#else
476
477static inline u32 apic_read(u32 reg) { return 0; }
478static inline void apic_write(u32 reg, u32 val) { }
479static inline void apic_eoi(void) { }
480static inline u64 apic_icr_read(void) { return 0; }
481static inline void apic_icr_write(u32 low, u32 high) { }
482static inline void apic_wait_icr_idle(void) { }
483static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
484static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
485
486#endif
487
488static inline void ack_APIC_irq(void)
489{
490
491
492
493
494 apic_eoi();
495}
496
497static inline unsigned default_get_apic_id(unsigned long x)
498{
499 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
500
501 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
502 return (x >> 24) & 0xFF;
503 else
504 return (x >> 24) & 0x0F;
505}
506
507
508
509
510#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
511#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
512
513#ifdef CONFIG_X86_64
514extern void apic_send_IPI_self(int vector);
515
516DECLARE_PER_CPU(int, x2apic_extra_bits);
517
518extern int default_cpu_present_to_apicid(int mps_cpu);
519extern int default_check_phys_apicid_present(int phys_apicid);
520#endif
521
522static inline void default_wait_for_init_deassert(atomic_t *deassert)
523{
524 while (!atomic_read(deassert))
525 cpu_relax();
526 return;
527}
528
529extern void generic_bigsmp_probe(void);
530
531
532#ifdef CONFIG_X86_LOCAL_APIC
533
534#include <asm/smp.h>
535
536#define APIC_DFR_VALUE (APIC_DFR_FLAT)
537
538static inline const struct cpumask *default_target_cpus(void)
539{
540#ifdef CONFIG_SMP
541 return cpu_online_mask;
542#else
543 return cpumask_of(0);
544#endif
545}
546
547static inline const struct cpumask *online_target_cpus(void)
548{
549 return cpu_online_mask;
550}
551
552DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
553
554
555static inline unsigned int read_apic_id(void)
556{
557 unsigned int reg;
558
559 reg = apic_read(APIC_ID);
560
561 return apic->get_apic_id(reg);
562}
563
564static inline int default_apic_id_valid(int apicid)
565{
566 return (apicid < 255);
567}
568
569extern int default_acpi_madt_oem_check(char *, char *);
570
571extern void default_setup_apic_routing(void);
572
573extern struct apic apic_noop;
574
575#ifdef CONFIG_X86_32
576
577static inline int noop_x86_32_early_logical_apicid(int cpu)
578{
579 return BAD_APICID;
580}
581
582
583
584
585
586
587
588
589extern void default_init_apic_ldr(void);
590
591static inline int default_apic_id_registered(void)
592{
593 return physid_isset(read_apic_id(), phys_cpu_present_map);
594}
595
596static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
597{
598 return cpuid_apic >> index_msb;
599}
600
601#endif
602
603static inline int
604flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
605 const struct cpumask *andmask,
606 unsigned int *apicid)
607{
608 unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
609 cpumask_bits(andmask)[0] &
610 cpumask_bits(cpu_online_mask)[0] &
611 APIC_ALL_CPUS;
612
613 if (likely(cpu_mask)) {
614 *apicid = (unsigned int)cpu_mask;
615 return 0;
616 } else {
617 return -EINVAL;
618 }
619}
620
621extern int
622default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
623 const struct cpumask *andmask,
624 unsigned int *apicid);
625
626static inline void
627flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
628 const struct cpumask *mask)
629{
630
631
632
633
634
635
636
637
638 cpumask_clear(retmask);
639 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
640}
641
642static inline void
643default_vector_allocation_domain(int cpu, struct cpumask *retmask,
644 const struct cpumask *mask)
645{
646 cpumask_copy(retmask, cpumask_of(cpu));
647}
648
649static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
650{
651 return physid_isset(apicid, *map);
652}
653
654static inline unsigned long default_check_apicid_present(int bit)
655{
656 return physid_isset(bit, phys_cpu_present_map);
657}
658
659static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
660{
661 *retmap = *phys_map;
662}
663
664static inline int __default_cpu_present_to_apicid(int mps_cpu)
665{
666 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
667 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
668 else
669 return BAD_APICID;
670}
671
672static inline int
673__default_check_phys_apicid_present(int phys_apicid)
674{
675 return physid_isset(phys_apicid, phys_cpu_present_map);
676}
677
678#ifdef CONFIG_X86_32
679static inline int default_cpu_present_to_apicid(int mps_cpu)
680{
681 return __default_cpu_present_to_apicid(mps_cpu);
682}
683
684static inline int
685default_check_phys_apicid_present(int phys_apicid)
686{
687 return __default_check_phys_apicid_present(phys_apicid);
688}
689#else
690extern int default_cpu_present_to_apicid(int mps_cpu);
691extern int default_check_phys_apicid_present(int phys_apicid);
692#endif
693
694#ifdef CONFIG_SMP
695bool apic_id_is_primary_thread(unsigned int id);
696#else
697static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
698#endif
699
700#endif
701
702extern void irq_enter(void);
703extern void irq_exit(void);
704
705static inline void entering_irq(void)
706{
707 irq_enter();
708 exit_idle();
709}
710
711static inline void entering_ack_irq(void)
712{
713 entering_irq();
714 ack_APIC_irq();
715}
716
717static inline void ipi_entering_ack_irq(void)
718{
719 irq_enter();
720 ack_APIC_irq();
721}
722
723static inline void exiting_irq(void)
724{
725 irq_exit();
726}
727
728static inline void exiting_ack_irq(void)
729{
730 ack_APIC_irq();
731 irq_exit();
732}
733
734extern void ioapic_zap_locks(void);
735
736#endif
737