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11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
17#include <linux/gpio.h>
18#include <linux/slab.h>
19#include <linux/irq.h>
20
21#define MPC8XXX_GPIO_PINS 32
22
23#define GPIO_DIR 0x00
24#define GPIO_ODR 0x04
25#define GPIO_DAT 0x08
26#define GPIO_IER 0x0c
27#define GPIO_IMR 0x10
28#define GPIO_ICR 0x14
29#define GPIO_ICR2 0x18
30
31struct mpc8xxx_gpio_chip {
32 struct of_mm_gpio_chip mm_gc;
33 spinlock_t lock;
34
35
36
37
38
39 u32 data;
40 struct irq_domain *irq;
41 const void *of_dev_id_data;
42};
43
44static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
45{
46 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
47}
48
49static inline struct mpc8xxx_gpio_chip *
50to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
51{
52 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
53}
54
55static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
56{
57 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
58
59 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
60}
61
62
63
64
65
66
67static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
68{
69 u32 val;
70 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
72 u32 out_mask, out_shadow;
73
74 out_mask = in_be32(mm->regs + GPIO_DIR);
75
76 val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
77 out_shadow = mpc8xxx_gc->data & out_mask;
78
79 return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
80}
81
82static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
83{
84 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
85
86 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
87}
88
89static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
90{
91 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
92 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
93 unsigned long flags;
94
95 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
96
97 if (val)
98 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
99 else
100 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
101
102 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
103
104 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
105}
106
107static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
108{
109 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
110 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
111 unsigned long flags;
112
113 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
114
115 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
116
117 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
118
119 return 0;
120}
121
122static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
123{
124 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
125 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
126 unsigned long flags;
127
128 mpc8xxx_gpio_set(gc, gpio, val);
129
130 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
131
132 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
133
134 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
135
136 return 0;
137}
138
139static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
140{
141
142 if (gpio >= 28)
143 return -EINVAL;
144
145 return mpc8xxx_gpio_dir_out(gc, gpio, val);
146}
147
148static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
149{
150 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
151 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
152
153 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
154 return irq_create_mapping(mpc8xxx_gc->irq, offset);
155 else
156 return -ENXIO;
157}
158
159static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
160{
161 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
162 struct irq_chip *chip = irq_desc_get_chip(desc);
163 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
164 unsigned int mask;
165
166 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
167 if (mask)
168 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
169 32 - ffs(mask)));
170 if (chip->irq_eoi)
171 chip->irq_eoi(&desc->irq_data);
172}
173
174static void mpc8xxx_irq_unmask(struct irq_data *d)
175{
176 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
177 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
178 unsigned long flags;
179
180 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
181
182 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
183
184 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
185}
186
187static void mpc8xxx_irq_mask(struct irq_data *d)
188{
189 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
190 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
191 unsigned long flags;
192
193 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
194
195 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
196
197 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
198}
199
200static void mpc8xxx_irq_ack(struct irq_data *d)
201{
202 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
203 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
204
205 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
206}
207
208static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
209{
210 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
211 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
212 unsigned long flags;
213
214 switch (flow_type) {
215 case IRQ_TYPE_EDGE_FALLING:
216 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
217 setbits32(mm->regs + GPIO_ICR,
218 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
219 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
220 break;
221
222 case IRQ_TYPE_EDGE_BOTH:
223 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
224 clrbits32(mm->regs + GPIO_ICR,
225 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
226 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
227 break;
228
229 default:
230 return -EINVAL;
231 }
232
233 return 0;
234}
235
236static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
237{
238 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
239 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
240 unsigned long gpio = irqd_to_hwirq(d);
241 void __iomem *reg;
242 unsigned int shift;
243 unsigned long flags;
244
245 if (gpio < 16) {
246 reg = mm->regs + GPIO_ICR;
247 shift = (15 - gpio) * 2;
248 } else {
249 reg = mm->regs + GPIO_ICR2;
250 shift = (15 - (gpio % 16)) * 2;
251 }
252
253 switch (flow_type) {
254 case IRQ_TYPE_EDGE_FALLING:
255 case IRQ_TYPE_LEVEL_LOW:
256 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
257 clrsetbits_be32(reg, 3 << shift, 2 << shift);
258 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
259 break;
260
261 case IRQ_TYPE_EDGE_RISING:
262 case IRQ_TYPE_LEVEL_HIGH:
263 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
264 clrsetbits_be32(reg, 3 << shift, 1 << shift);
265 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
266 break;
267
268 case IRQ_TYPE_EDGE_BOTH:
269 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
270 clrbits32(reg, 3 << shift);
271 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
272 break;
273
274 default:
275 return -EINVAL;
276 }
277
278 return 0;
279}
280
281static struct irq_chip mpc8xxx_irq_chip = {
282 .name = "mpc8xxx-gpio",
283 .irq_unmask = mpc8xxx_irq_unmask,
284 .irq_mask = mpc8xxx_irq_mask,
285 .irq_ack = mpc8xxx_irq_ack,
286 .irq_set_type = mpc8xxx_irq_set_type,
287};
288
289static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
290 irq_hw_number_t hw)
291{
292 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
293
294 if (mpc8xxx_gc->of_dev_id_data)
295 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
296
297 irq_set_chip_data(virq, h->host_data);
298 irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
299
300 return 0;
301}
302
303static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
304 .map = mpc8xxx_gpio_irq_map,
305 .xlate = irq_domain_xlate_twocell,
306};
307
308static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
309 { .compatible = "fsl,mpc8349-gpio", },
310 { .compatible = "fsl,mpc8572-gpio", },
311 { .compatible = "fsl,mpc8610-gpio", },
312 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
313 { .compatible = "fsl,pq3-gpio", },
314 { .compatible = "fsl,qoriq-gpio", },
315 {}
316};
317
318static void __init mpc8xxx_add_controller(struct device_node *np)
319{
320 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
321 struct of_mm_gpio_chip *mm_gc;
322 struct gpio_chip *gc;
323 const struct of_device_id *id;
324 unsigned hwirq;
325 int ret;
326
327 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
328 if (!mpc8xxx_gc) {
329 ret = -ENOMEM;
330 goto err;
331 }
332
333 spin_lock_init(&mpc8xxx_gc->lock);
334
335 mm_gc = &mpc8xxx_gc->mm_gc;
336 gc = &mm_gc->gc;
337
338 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
339 gc->ngpio = MPC8XXX_GPIO_PINS;
340 gc->direction_input = mpc8xxx_gpio_dir_in;
341 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
342 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
343 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
344 mpc8572_gpio_get : mpc8xxx_gpio_get;
345 gc->set = mpc8xxx_gpio_set;
346 gc->to_irq = mpc8xxx_gpio_to_irq;
347
348 ret = of_mm_gpiochip_add(np, mm_gc);
349 if (ret)
350 goto err;
351
352 hwirq = irq_of_parse_and_map(np, 0);
353 if (hwirq == NO_IRQ)
354 goto skip_irq;
355
356 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
357 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
358 if (!mpc8xxx_gc->irq)
359 goto skip_irq;
360
361 id = of_match_node(mpc8xxx_gpio_ids, np);
362 if (id)
363 mpc8xxx_gc->of_dev_id_data = id->data;
364
365
366 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
367 out_be32(mm_gc->regs + GPIO_IMR, 0);
368
369 irq_set_handler_data(hwirq, mpc8xxx_gc);
370 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
371
372skip_irq:
373 return;
374
375err:
376 pr_err("%s: registration failed with status %d\n",
377 np->full_name, ret);
378 kfree(mpc8xxx_gc);
379
380 return;
381}
382
383static int __init mpc8xxx_add_gpiochips(void)
384{
385 struct device_node *np;
386
387 for_each_matching_node(np, mpc8xxx_gpio_ids)
388 mpc8xxx_add_controller(np);
389
390 return 0;
391}
392arch_initcall(mpc8xxx_add_gpiochips);
393
