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25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_drv.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_dpm.h"
30#include "atom.h"
31#include <linux/power_supply.h>
32#include <linux/hwmon.h>
33#include <linux/hwmon-sysfs.h>
34
35
36static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
37
38static const struct cg_flag_name clocks[] = {
39 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
40 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
41 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
42 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
43 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
44 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
45 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
46 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
47 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
48 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
49 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
50 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
51 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
52 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
53 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
54 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
55 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
56 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
57 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
58 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
59 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
60 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
61 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
62 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
63 {0, NULL},
64};
65
66void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
67{
68 if (adev->pm.dpm_enabled) {
69 mutex_lock(&adev->pm.mutex);
70 if (power_supply_is_system_supplied() > 0)
71 adev->pm.dpm.ac_power = true;
72 else
73 adev->pm.dpm.ac_power = false;
74 if (adev->powerplay.pp_funcs->enable_bapm)
75 amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
76 mutex_unlock(&adev->pm.mutex);
77 }
78}
79
80static ssize_t amdgpu_get_dpm_state(struct device *dev,
81 struct device_attribute *attr,
82 char *buf)
83{
84 struct drm_device *ddev = dev_get_drvdata(dev);
85 struct amdgpu_device *adev = ddev->dev_private;
86 enum amd_pm_state_type pm;
87
88 if (adev->powerplay.pp_funcs->get_current_power_state)
89 pm = amdgpu_dpm_get_current_power_state(adev);
90 else
91 pm = adev->pm.dpm.user_state;
92
93 return snprintf(buf, PAGE_SIZE, "%s\n",
94 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
95 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
96}
97
98static ssize_t amdgpu_set_dpm_state(struct device *dev,
99 struct device_attribute *attr,
100 const char *buf,
101 size_t count)
102{
103 struct drm_device *ddev = dev_get_drvdata(dev);
104 struct amdgpu_device *adev = ddev->dev_private;
105 enum amd_pm_state_type state;
106
107 if (strncmp("battery", buf, strlen("battery")) == 0)
108 state = POWER_STATE_TYPE_BATTERY;
109 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
110 state = POWER_STATE_TYPE_BALANCED;
111 else if (strncmp("performance", buf, strlen("performance")) == 0)
112 state = POWER_STATE_TYPE_PERFORMANCE;
113 else {
114 count = -EINVAL;
115 goto fail;
116 }
117
118 if (adev->powerplay.pp_funcs->dispatch_tasks) {
119 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
120 } else {
121 mutex_lock(&adev->pm.mutex);
122 adev->pm.dpm.user_state = state;
123 mutex_unlock(&adev->pm.mutex);
124
125
126 if (!(adev->flags & AMD_IS_PX) ||
127 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
128 amdgpu_pm_compute_clocks(adev);
129 }
130fail:
131 return count;
132}
133
134static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
135 struct device_attribute *attr,
136 char *buf)
137{
138 struct drm_device *ddev = dev_get_drvdata(dev);
139 struct amdgpu_device *adev = ddev->dev_private;
140 enum amd_dpm_forced_level level = 0xff;
141
142 if ((adev->flags & AMD_IS_PX) &&
143 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
144 return snprintf(buf, PAGE_SIZE, "off\n");
145
146 if (adev->powerplay.pp_funcs->get_performance_level)
147 level = amdgpu_dpm_get_performance_level(adev);
148 else
149 level = adev->pm.dpm.forced_level;
150
151 return snprintf(buf, PAGE_SIZE, "%s\n",
152 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
153 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
154 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
155 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
156 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
157 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
158 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
159 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
160 "unknown");
161}
162
163static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
164 struct device_attribute *attr,
165 const char *buf,
166 size_t count)
167{
168 struct drm_device *ddev = dev_get_drvdata(dev);
169 struct amdgpu_device *adev = ddev->dev_private;
170 enum amd_dpm_forced_level level;
171 enum amd_dpm_forced_level current_level = 0xff;
172 int ret = 0;
173
174
175 if ((adev->flags & AMD_IS_PX) &&
176 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
177 return -EINVAL;
178
179 if (adev->powerplay.pp_funcs->get_performance_level)
180 current_level = amdgpu_dpm_get_performance_level(adev);
181
182 if (strncmp("low", buf, strlen("low")) == 0) {
183 level = AMD_DPM_FORCED_LEVEL_LOW;
184 } else if (strncmp("high", buf, strlen("high")) == 0) {
185 level = AMD_DPM_FORCED_LEVEL_HIGH;
186 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
187 level = AMD_DPM_FORCED_LEVEL_AUTO;
188 } else if (strncmp("manual", buf, strlen("manual")) == 0) {
189 level = AMD_DPM_FORCED_LEVEL_MANUAL;
190 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
191 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
192 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
193 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
194 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
195 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
196 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
197 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
198 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
199 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
200 } else {
201 count = -EINVAL;
202 goto fail;
203 }
204
205 if (current_level == level)
206 return count;
207
208 if (adev->powerplay.pp_funcs->force_performance_level) {
209 mutex_lock(&adev->pm.mutex);
210 if (adev->pm.dpm.thermal_active) {
211 count = -EINVAL;
212 mutex_unlock(&adev->pm.mutex);
213 goto fail;
214 }
215 ret = amdgpu_dpm_force_performance_level(adev, level);
216 if (ret)
217 count = -EINVAL;
218 else
219 adev->pm.dpm.forced_level = level;
220 mutex_unlock(&adev->pm.mutex);
221 }
222
223fail:
224 return count;
225}
226
227static ssize_t amdgpu_get_pp_num_states(struct device *dev,
228 struct device_attribute *attr,
229 char *buf)
230{
231 struct drm_device *ddev = dev_get_drvdata(dev);
232 struct amdgpu_device *adev = ddev->dev_private;
233 struct pp_states_info data;
234 int i, buf_len;
235
236 if (adev->powerplay.pp_funcs->get_pp_num_states)
237 amdgpu_dpm_get_pp_num_states(adev, &data);
238
239 buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
240 for (i = 0; i < data.nums; i++)
241 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
242 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
243 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
244 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
245 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
246
247 return buf_len;
248}
249
250static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
251 struct device_attribute *attr,
252 char *buf)
253{
254 struct drm_device *ddev = dev_get_drvdata(dev);
255 struct amdgpu_device *adev = ddev->dev_private;
256 struct pp_states_info data;
257 enum amd_pm_state_type pm = 0;
258 int i = 0;
259
260 if (adev->powerplay.pp_funcs->get_current_power_state
261 && adev->powerplay.pp_funcs->get_pp_num_states) {
262 pm = amdgpu_dpm_get_current_power_state(adev);
263 amdgpu_dpm_get_pp_num_states(adev, &data);
264
265 for (i = 0; i < data.nums; i++) {
266 if (pm == data.states[i])
267 break;
268 }
269
270 if (i == data.nums)
271 i = -EINVAL;
272 }
273
274 return snprintf(buf, PAGE_SIZE, "%d\n", i);
275}
276
277static ssize_t amdgpu_get_pp_force_state(struct device *dev,
278 struct device_attribute *attr,
279 char *buf)
280{
281 struct drm_device *ddev = dev_get_drvdata(dev);
282 struct amdgpu_device *adev = ddev->dev_private;
283
284 if (adev->pp_force_state_enabled)
285 return amdgpu_get_pp_cur_state(dev, attr, buf);
286 else
287 return snprintf(buf, PAGE_SIZE, "\n");
288}
289
290static ssize_t amdgpu_set_pp_force_state(struct device *dev,
291 struct device_attribute *attr,
292 const char *buf,
293 size_t count)
294{
295 struct drm_device *ddev = dev_get_drvdata(dev);
296 struct amdgpu_device *adev = ddev->dev_private;
297 enum amd_pm_state_type state = 0;
298 unsigned long idx;
299 int ret;
300
301 if (strlen(buf) == 1)
302 adev->pp_force_state_enabled = false;
303 else if (adev->powerplay.pp_funcs->dispatch_tasks &&
304 adev->powerplay.pp_funcs->get_pp_num_states) {
305 struct pp_states_info data;
306
307 ret = kstrtoul(buf, 0, &idx);
308 if (ret || idx >= ARRAY_SIZE(data.states)) {
309 count = -EINVAL;
310 goto fail;
311 }
312
313 amdgpu_dpm_get_pp_num_states(adev, &data);
314 state = data.states[idx];
315
316 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
317 state != POWER_STATE_TYPE_DEFAULT) {
318 amdgpu_dpm_dispatch_task(adev,
319 AMD_PP_TASK_ENABLE_USER_STATE, &state);
320 adev->pp_force_state_enabled = true;
321 }
322 }
323fail:
324 return count;
325}
326
327static ssize_t amdgpu_get_pp_table(struct device *dev,
328 struct device_attribute *attr,
329 char *buf)
330{
331 struct drm_device *ddev = dev_get_drvdata(dev);
332 struct amdgpu_device *adev = ddev->dev_private;
333 char *table = NULL;
334 int size;
335
336 if (adev->powerplay.pp_funcs->get_pp_table)
337 size = amdgpu_dpm_get_pp_table(adev, &table);
338 else
339 return 0;
340
341 if (size >= PAGE_SIZE)
342 size = PAGE_SIZE - 1;
343
344 memcpy(buf, table, size);
345
346 return size;
347}
348
349static ssize_t amdgpu_set_pp_table(struct device *dev,
350 struct device_attribute *attr,
351 const char *buf,
352 size_t count)
353{
354 struct drm_device *ddev = dev_get_drvdata(dev);
355 struct amdgpu_device *adev = ddev->dev_private;
356
357 if (adev->powerplay.pp_funcs->set_pp_table)
358 amdgpu_dpm_set_pp_table(adev, buf, count);
359
360 return count;
361}
362
363static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
364 struct device_attribute *attr,
365 const char *buf,
366 size_t count)
367{
368 struct drm_device *ddev = dev_get_drvdata(dev);
369 struct amdgpu_device *adev = ddev->dev_private;
370 int ret;
371 uint32_t parameter_size = 0;
372 long parameter[64];
373 char buf_cpy[128];
374 char *tmp_str;
375 char *sub_str;
376 const char delimiter[3] = {' ', '\n', '\0'};
377 uint32_t type;
378
379 if (count > 127)
380 return -EINVAL;
381
382 if (*buf == 's')
383 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
384 else if (*buf == 'm')
385 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
386 else if(*buf == 'r')
387 type = PP_OD_RESTORE_DEFAULT_TABLE;
388 else if (*buf == 'c')
389 type = PP_OD_COMMIT_DPM_TABLE;
390 else
391 return -EINVAL;
392
393 memcpy(buf_cpy, buf, count+1);
394
395 tmp_str = buf_cpy;
396
397 while (isspace(*++tmp_str));
398
399 while (tmp_str[0]) {
400 sub_str = strsep(&tmp_str, delimiter);
401 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
402 if (ret)
403 return -EINVAL;
404 parameter_size++;
405
406 while (isspace(*tmp_str))
407 tmp_str++;
408 }
409
410 if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
411 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
412 parameter, parameter_size);
413
414 if (ret)
415 return -EINVAL;
416
417 if (type == PP_OD_COMMIT_DPM_TABLE) {
418 if (adev->powerplay.pp_funcs->dispatch_tasks) {
419 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
420 return count;
421 } else {
422 return -EINVAL;
423 }
424 }
425
426 return count;
427}
428
429static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
430 struct device_attribute *attr,
431 char *buf)
432{
433 struct drm_device *ddev = dev_get_drvdata(dev);
434 struct amdgpu_device *adev = ddev->dev_private;
435 uint32_t size = 0;
436
437 if (adev->powerplay.pp_funcs->print_clock_levels) {
438 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
439 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
440 return size;
441 } else {
442 return snprintf(buf, PAGE_SIZE, "\n");
443 }
444
445}
446
447static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
448 struct device_attribute *attr,
449 char *buf)
450{
451 struct drm_device *ddev = dev_get_drvdata(dev);
452 struct amdgpu_device *adev = ddev->dev_private;
453
454 if (adev->powerplay.pp_funcs->print_clock_levels)
455 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
456 else
457 return snprintf(buf, PAGE_SIZE, "\n");
458}
459
460static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
461 struct device_attribute *attr,
462 const char *buf,
463 size_t count)
464{
465 struct drm_device *ddev = dev_get_drvdata(dev);
466 struct amdgpu_device *adev = ddev->dev_private;
467 int ret;
468 long level;
469 uint32_t i, mask = 0;
470 char sub_str[2];
471
472 for (i = 0; i < strlen(buf); i++) {
473 if (*(buf + i) == '\n')
474 continue;
475 sub_str[0] = *(buf + i);
476 sub_str[1] = '\0';
477 ret = kstrtol(sub_str, 0, &level);
478
479 if (ret) {
480 count = -EINVAL;
481 goto fail;
482 }
483 mask |= 1 << level;
484 }
485
486 if (adev->powerplay.pp_funcs->force_clock_level)
487 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
488
489fail:
490 return count;
491}
492
493static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
494 struct device_attribute *attr,
495 char *buf)
496{
497 struct drm_device *ddev = dev_get_drvdata(dev);
498 struct amdgpu_device *adev = ddev->dev_private;
499
500 if (adev->powerplay.pp_funcs->print_clock_levels)
501 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
502 else
503 return snprintf(buf, PAGE_SIZE, "\n");
504}
505
506static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
507 struct device_attribute *attr,
508 const char *buf,
509 size_t count)
510{
511 struct drm_device *ddev = dev_get_drvdata(dev);
512 struct amdgpu_device *adev = ddev->dev_private;
513 int ret;
514 long level;
515 uint32_t i, mask = 0;
516 char sub_str[2];
517
518 for (i = 0; i < strlen(buf); i++) {
519 if (*(buf + i) == '\n')
520 continue;
521 sub_str[0] = *(buf + i);
522 sub_str[1] = '\0';
523 ret = kstrtol(sub_str, 0, &level);
524
525 if (ret) {
526 count = -EINVAL;
527 goto fail;
528 }
529 mask |= 1 << level;
530 }
531 if (adev->powerplay.pp_funcs->force_clock_level)
532 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
533
534fail:
535 return count;
536}
537
538static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
539 struct device_attribute *attr,
540 char *buf)
541{
542 struct drm_device *ddev = dev_get_drvdata(dev);
543 struct amdgpu_device *adev = ddev->dev_private;
544
545 if (adev->powerplay.pp_funcs->print_clock_levels)
546 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
547 else
548 return snprintf(buf, PAGE_SIZE, "\n");
549}
550
551static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
552 struct device_attribute *attr,
553 const char *buf,
554 size_t count)
555{
556 struct drm_device *ddev = dev_get_drvdata(dev);
557 struct amdgpu_device *adev = ddev->dev_private;
558 int ret;
559 long level;
560 uint32_t i, mask = 0;
561 char sub_str[2];
562
563 for (i = 0; i < strlen(buf); i++) {
564 if (*(buf + i) == '\n')
565 continue;
566 sub_str[0] = *(buf + i);
567 sub_str[1] = '\0';
568 ret = kstrtol(sub_str, 0, &level);
569
570 if (ret) {
571 count = -EINVAL;
572 goto fail;
573 }
574 mask |= 1 << level;
575 }
576 if (adev->powerplay.pp_funcs->force_clock_level)
577 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
578
579fail:
580 return count;
581}
582
583static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
584 struct device_attribute *attr,
585 char *buf)
586{
587 struct drm_device *ddev = dev_get_drvdata(dev);
588 struct amdgpu_device *adev = ddev->dev_private;
589 uint32_t value = 0;
590
591 if (adev->powerplay.pp_funcs->get_sclk_od)
592 value = amdgpu_dpm_get_sclk_od(adev);
593
594 return snprintf(buf, PAGE_SIZE, "%d\n", value);
595}
596
597static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
598 struct device_attribute *attr,
599 const char *buf,
600 size_t count)
601{
602 struct drm_device *ddev = dev_get_drvdata(dev);
603 struct amdgpu_device *adev = ddev->dev_private;
604 int ret;
605 long int value;
606
607 ret = kstrtol(buf, 0, &value);
608
609 if (ret) {
610 count = -EINVAL;
611 goto fail;
612 }
613 if (adev->powerplay.pp_funcs->set_sclk_od)
614 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
615
616 if (adev->powerplay.pp_funcs->dispatch_tasks) {
617 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
618 } else {
619 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
620 amdgpu_pm_compute_clocks(adev);
621 }
622
623fail:
624 return count;
625}
626
627static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
628 struct device_attribute *attr,
629 char *buf)
630{
631 struct drm_device *ddev = dev_get_drvdata(dev);
632 struct amdgpu_device *adev = ddev->dev_private;
633 uint32_t value = 0;
634
635 if (adev->powerplay.pp_funcs->get_mclk_od)
636 value = amdgpu_dpm_get_mclk_od(adev);
637
638 return snprintf(buf, PAGE_SIZE, "%d\n", value);
639}
640
641static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
642 struct device_attribute *attr,
643 const char *buf,
644 size_t count)
645{
646 struct drm_device *ddev = dev_get_drvdata(dev);
647 struct amdgpu_device *adev = ddev->dev_private;
648 int ret;
649 long int value;
650
651 ret = kstrtol(buf, 0, &value);
652
653 if (ret) {
654 count = -EINVAL;
655 goto fail;
656 }
657 if (adev->powerplay.pp_funcs->set_mclk_od)
658 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
659
660 if (adev->powerplay.pp_funcs->dispatch_tasks) {
661 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
662 } else {
663 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
664 amdgpu_pm_compute_clocks(adev);
665 }
666
667fail:
668 return count;
669}
670
671static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
672 struct device_attribute *attr,
673 char *buf)
674{
675 struct drm_device *ddev = dev_get_drvdata(dev);
676 struct amdgpu_device *adev = ddev->dev_private;
677
678 if (adev->powerplay.pp_funcs->get_power_profile_mode)
679 return amdgpu_dpm_get_power_profile_mode(adev, buf);
680
681 return snprintf(buf, PAGE_SIZE, "\n");
682}
683
684
685static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
686 struct device_attribute *attr,
687 const char *buf,
688 size_t count)
689{
690 int ret = 0xff;
691 struct drm_device *ddev = dev_get_drvdata(dev);
692 struct amdgpu_device *adev = ddev->dev_private;
693 uint32_t parameter_size = 0;
694 long parameter[64];
695 char *sub_str, buf_cpy[128];
696 char *tmp_str;
697 uint32_t i = 0;
698 char tmp[2];
699 long int profile_mode = 0;
700 const char delimiter[3] = {' ', '\n', '\0'};
701
702 tmp[0] = *(buf);
703 tmp[1] = '\0';
704 ret = kstrtol(tmp, 0, &profile_mode);
705 if (ret)
706 goto fail;
707
708 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
709 if (count < 2 || count > 127)
710 return -EINVAL;
711 while (isspace(*++buf))
712 i++;
713 memcpy(buf_cpy, buf, count-i);
714 tmp_str = buf_cpy;
715 while (tmp_str[0]) {
716 sub_str = strsep(&tmp_str, delimiter);
717 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
718 if (ret) {
719 count = -EINVAL;
720 goto fail;
721 }
722 parameter_size++;
723 while (isspace(*tmp_str))
724 tmp_str++;
725 }
726 }
727 parameter[parameter_size] = profile_mode;
728 if (adev->powerplay.pp_funcs->set_power_profile_mode)
729 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
730
731 if (!ret)
732 return count;
733fail:
734 return -EINVAL;
735}
736
737static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
738static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
739 amdgpu_get_dpm_forced_performance_level,
740 amdgpu_set_dpm_forced_performance_level);
741static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
742static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
743static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
744 amdgpu_get_pp_force_state,
745 amdgpu_set_pp_force_state);
746static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
747 amdgpu_get_pp_table,
748 amdgpu_set_pp_table);
749static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
750 amdgpu_get_pp_dpm_sclk,
751 amdgpu_set_pp_dpm_sclk);
752static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
753 amdgpu_get_pp_dpm_mclk,
754 amdgpu_set_pp_dpm_mclk);
755static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
756 amdgpu_get_pp_dpm_pcie,
757 amdgpu_set_pp_dpm_pcie);
758static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
759 amdgpu_get_pp_sclk_od,
760 amdgpu_set_pp_sclk_od);
761static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
762 amdgpu_get_pp_mclk_od,
763 amdgpu_set_pp_mclk_od);
764static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
765 amdgpu_get_pp_power_profile_mode,
766 amdgpu_set_pp_power_profile_mode);
767static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
768 amdgpu_get_pp_od_clk_voltage,
769 amdgpu_set_pp_od_clk_voltage);
770
771static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
772 struct device_attribute *attr,
773 char *buf)
774{
775 struct amdgpu_device *adev = dev_get_drvdata(dev);
776 struct drm_device *ddev = adev->ddev;
777 int r, temp, size = sizeof(temp);
778
779
780 if ((adev->flags & AMD_IS_PX) &&
781 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
782 return -EINVAL;
783
784
785 if (!(adev->powerplay.pp_funcs &&
786 adev->powerplay.pp_funcs->read_sensor))
787 return -EINVAL;
788
789
790 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
791 (void *)&temp, &size);
792 if (r)
793 return r;
794
795 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
796}
797
798static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
799 struct device_attribute *attr,
800 char *buf)
801{
802 struct amdgpu_device *adev = dev_get_drvdata(dev);
803 int hyst = to_sensor_dev_attr(attr)->index;
804 int temp;
805
806 if (hyst)
807 temp = adev->pm.dpm.thermal.min_temp;
808 else
809 temp = adev->pm.dpm.thermal.max_temp;
810
811 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
812}
813
814static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
815 struct device_attribute *attr,
816 char *buf)
817{
818 struct amdgpu_device *adev = dev_get_drvdata(dev);
819 u32 pwm_mode = 0;
820
821 if (!adev->powerplay.pp_funcs->get_fan_control_mode)
822 return -EINVAL;
823
824 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
825
826 return sprintf(buf, "%i\n", pwm_mode);
827}
828
829static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
830 struct device_attribute *attr,
831 const char *buf,
832 size_t count)
833{
834 struct amdgpu_device *adev = dev_get_drvdata(dev);
835 int err;
836 int value;
837
838
839 if ((adev->flags & AMD_IS_PX) &&
840 (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
841 return -EINVAL;
842
843 if (!adev->powerplay.pp_funcs->set_fan_control_mode)
844 return -EINVAL;
845
846 err = kstrtoint(buf, 10, &value);
847 if (err)
848 return err;
849
850 amdgpu_dpm_set_fan_control_mode(adev, value);
851
852 return count;
853}
854
855static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
856 struct device_attribute *attr,
857 char *buf)
858{
859 return sprintf(buf, "%i\n", 0);
860}
861
862static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
863 struct device_attribute *attr,
864 char *buf)
865{
866 return sprintf(buf, "%i\n", 255);
867}
868
869static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
870 struct device_attribute *attr,
871 const char *buf, size_t count)
872{
873 struct amdgpu_device *adev = dev_get_drvdata(dev);
874 int err;
875 u32 value;
876
877
878 if ((adev->flags & AMD_IS_PX) &&
879 (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
880 return -EINVAL;
881
882 err = kstrtou32(buf, 10, &value);
883 if (err)
884 return err;
885
886 value = (value * 100) / 255;
887
888 if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
889 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
890 if (err)
891 return err;
892 }
893
894 return count;
895}
896
897static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
898 struct device_attribute *attr,
899 char *buf)
900{
901 struct amdgpu_device *adev = dev_get_drvdata(dev);
902 int err;
903 u32 speed = 0;
904
905
906 if ((adev->flags & AMD_IS_PX) &&
907 (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
908 return -EINVAL;
909
910 if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
911 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
912 if (err)
913 return err;
914 }
915
916 speed = (speed * 255) / 100;
917
918 return sprintf(buf, "%i\n", speed);
919}
920
921static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
922 struct device_attribute *attr,
923 char *buf)
924{
925 struct amdgpu_device *adev = dev_get_drvdata(dev);
926 int err;
927 u32 speed = 0;
928
929
930 if ((adev->flags & AMD_IS_PX) &&
931 (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
932 return -EINVAL;
933
934 if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
935 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
936 if (err)
937 return err;
938 }
939
940 return sprintf(buf, "%i\n", speed);
941}
942
943static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
944 struct device_attribute *attr,
945 char *buf)
946{
947 struct amdgpu_device *adev = dev_get_drvdata(dev);
948 struct drm_device *ddev = adev->ddev;
949 u32 vddgfx;
950 int r, size = sizeof(vddgfx);
951
952
953 if ((adev->flags & AMD_IS_PX) &&
954 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
955 return -EINVAL;
956
957
958 if (!(adev->powerplay.pp_funcs &&
959 adev->powerplay.pp_funcs->read_sensor))
960 return -EINVAL;
961
962
963 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
964 (void *)&vddgfx, &size);
965 if (r)
966 return r;
967
968 return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
969}
970
971static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
972 struct device_attribute *attr,
973 char *buf)
974{
975 return snprintf(buf, PAGE_SIZE, "vddgfx\n");
976}
977
978static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
979 struct device_attribute *attr,
980 char *buf)
981{
982 struct amdgpu_device *adev = dev_get_drvdata(dev);
983 struct drm_device *ddev = adev->ddev;
984 u32 vddnb;
985 int r, size = sizeof(vddnb);
986
987
988 if (adev->flags & AMD_IS_APU)
989 return -EINVAL;
990
991
992 if ((adev->flags & AMD_IS_PX) &&
993 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
994 return -EINVAL;
995
996
997 if (!(adev->powerplay.pp_funcs &&
998 adev->powerplay.pp_funcs->read_sensor))
999 return -EINVAL;
1000
1001
1002 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1003 (void *)&vddnb, &size);
1004 if (r)
1005 return r;
1006
1007 return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1008}
1009
1010static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1011 struct device_attribute *attr,
1012 char *buf)
1013{
1014 return snprintf(buf, PAGE_SIZE, "vddnb\n");
1015}
1016
1017static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1018 struct device_attribute *attr,
1019 char *buf)
1020{
1021 struct amdgpu_device *adev = dev_get_drvdata(dev);
1022 struct drm_device *ddev = adev->ddev;
1023 struct pp_gpu_power query = {0};
1024 int r, size = sizeof(query);
1025 unsigned uw;
1026
1027
1028 if ((adev->flags & AMD_IS_PX) &&
1029 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1030 return -EINVAL;
1031
1032
1033 if (!(adev->powerplay.pp_funcs &&
1034 adev->powerplay.pp_funcs->read_sensor))
1035 return -EINVAL;
1036
1037
1038 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1039 (void *)&query, &size);
1040 if (r)
1041 return r;
1042
1043
1044 uw = (query.average_gpu_power >> 8) * 1000000;
1045
1046 return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1047}
1048
1049static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1050 struct device_attribute *attr,
1051 char *buf)
1052{
1053 return sprintf(buf, "%i\n", 0);
1054}
1055
1056static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1057 struct device_attribute *attr,
1058 char *buf)
1059{
1060 struct amdgpu_device *adev = dev_get_drvdata(dev);
1061 uint32_t limit = 0;
1062
1063 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1064 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1065 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1066 } else {
1067 return snprintf(buf, PAGE_SIZE, "\n");
1068 }
1069}
1070
1071static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1072 struct device_attribute *attr,
1073 char *buf)
1074{
1075 struct amdgpu_device *adev = dev_get_drvdata(dev);
1076 uint32_t limit = 0;
1077
1078 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1079 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1080 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1081 } else {
1082 return snprintf(buf, PAGE_SIZE, "\n");
1083 }
1084}
1085
1086
1087static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1088 struct device_attribute *attr,
1089 const char *buf,
1090 size_t count)
1091{
1092 struct amdgpu_device *adev = dev_get_drvdata(dev);
1093 int err;
1094 u32 value;
1095
1096 err = kstrtou32(buf, 10, &value);
1097 if (err)
1098 return err;
1099
1100 value = value / 1000000;
1101 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1102 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1103 if (err)
1104 return err;
1105 } else {
1106 return -EINVAL;
1107 }
1108
1109 return count;
1110}
1111
1112static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1113static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1114static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1115static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1116static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1117static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1118static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1119static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1120static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1121static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1122static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1123static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1124static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1125static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1126static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1127static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1128
1129static struct attribute *hwmon_attributes[] = {
1130 &sensor_dev_attr_temp1_input.dev_attr.attr,
1131 &sensor_dev_attr_temp1_crit.dev_attr.attr,
1132 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1133 &sensor_dev_attr_pwm1.dev_attr.attr,
1134 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1135 &sensor_dev_attr_pwm1_min.dev_attr.attr,
1136 &sensor_dev_attr_pwm1_max.dev_attr.attr,
1137 &sensor_dev_attr_fan1_input.dev_attr.attr,
1138 &sensor_dev_attr_in0_input.dev_attr.attr,
1139 &sensor_dev_attr_in0_label.dev_attr.attr,
1140 &sensor_dev_attr_in1_input.dev_attr.attr,
1141 &sensor_dev_attr_in1_label.dev_attr.attr,
1142 &sensor_dev_attr_power1_average.dev_attr.attr,
1143 &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1144 &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1145 &sensor_dev_attr_power1_cap.dev_attr.attr,
1146 NULL
1147};
1148
1149static umode_t hwmon_attributes_visible(struct kobject *kobj,
1150 struct attribute *attr, int index)
1151{
1152 struct device *dev = kobj_to_dev(kobj);
1153 struct amdgpu_device *adev = dev_get_drvdata(dev);
1154 umode_t effective_mode = attr->mode;
1155
1156
1157 if (!adev->powerplay.pp_handle) {
1158
1159 if (adev->pm.no_fan &&
1160 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1161 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1162 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1163 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1164 return 0;
1165
1166 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1167 return 0;
1168 }
1169
1170
1171 if (!adev->pm.dpm_enabled &&
1172 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1173 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1174 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1175 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1176 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1177 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1178 return 0;
1179
1180
1181 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1182 attr == &sensor_dev_attr_pwm1.dev_attr.attr) ||
1183 (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1184 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr))
1185 effective_mode &= ~S_IRUGO;
1186
1187 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1188 attr == &sensor_dev_attr_pwm1.dev_attr.attr) ||
1189 (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1190 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr))
1191 effective_mode &= ~S_IWUSR;
1192
1193 if ((adev->flags & AMD_IS_APU) &&
1194 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1195 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1196 attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1197 return 0;
1198
1199
1200 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1201 !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1202 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1203 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1204 return 0;
1205
1206
1207 if (!(adev->flags & AMD_IS_APU) &&
1208 (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1209 attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1210 return 0;
1211
1212 return effective_mode;
1213}
1214
1215static const struct attribute_group hwmon_attrgroup = {
1216 .attrs = hwmon_attributes,
1217 .is_visible = hwmon_attributes_visible,
1218};
1219
1220static const struct attribute_group *hwmon_groups[] = {
1221 &hwmon_attrgroup,
1222 NULL
1223};
1224
1225void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1226{
1227 struct amdgpu_device *adev =
1228 container_of(work, struct amdgpu_device,
1229 pm.dpm.thermal.work);
1230
1231 enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1232 int temp, size = sizeof(temp);
1233
1234 if (!adev->pm.dpm_enabled)
1235 return;
1236
1237 if (adev->powerplay.pp_funcs &&
1238 adev->powerplay.pp_funcs->read_sensor &&
1239 !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1240 (void *)&temp, &size)) {
1241 if (temp < adev->pm.dpm.thermal.min_temp)
1242
1243 dpm_state = adev->pm.dpm.user_state;
1244 } else {
1245 if (adev->pm.dpm.thermal.high_to_low)
1246
1247 dpm_state = adev->pm.dpm.user_state;
1248 }
1249 mutex_lock(&adev->pm.mutex);
1250 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1251 adev->pm.dpm.thermal_active = true;
1252 else
1253 adev->pm.dpm.thermal_active = false;
1254 adev->pm.dpm.state = dpm_state;
1255 mutex_unlock(&adev->pm.mutex);
1256
1257 amdgpu_pm_compute_clocks(adev);
1258}
1259
1260static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1261 enum amd_pm_state_type dpm_state)
1262{
1263 int i;
1264 struct amdgpu_ps *ps;
1265 u32 ui_class;
1266 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1267 true : false;
1268
1269
1270 if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1271 if (amdgpu_dpm_vblank_too_short(adev))
1272 single_display = false;
1273 }
1274
1275
1276
1277
1278 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1279 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1280
1281 if (dpm_state == POWER_STATE_TYPE_BALANCED)
1282 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1283
1284restart_search:
1285
1286 for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1287 ps = &adev->pm.dpm.ps[i];
1288 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1289 switch (dpm_state) {
1290
1291 case POWER_STATE_TYPE_BATTERY:
1292 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1293 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1294 if (single_display)
1295 return ps;
1296 } else
1297 return ps;
1298 }
1299 break;
1300 case POWER_STATE_TYPE_BALANCED:
1301 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1302 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1303 if (single_display)
1304 return ps;
1305 } else
1306 return ps;
1307 }
1308 break;
1309 case POWER_STATE_TYPE_PERFORMANCE:
1310 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1311 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1312 if (single_display)
1313 return ps;
1314 } else
1315 return ps;
1316 }
1317 break;
1318
1319 case POWER_STATE_TYPE_INTERNAL_UVD:
1320 if (adev->pm.dpm.uvd_ps)
1321 return adev->pm.dpm.uvd_ps;
1322 else
1323 break;
1324 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1325 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1326 return ps;
1327 break;
1328 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1329 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1330 return ps;
1331 break;
1332 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1333 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1334 return ps;
1335 break;
1336 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1337 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1338 return ps;
1339 break;
1340 case POWER_STATE_TYPE_INTERNAL_BOOT:
1341 return adev->pm.dpm.boot_ps;
1342 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1343 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1344 return ps;
1345 break;
1346 case POWER_STATE_TYPE_INTERNAL_ACPI:
1347 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1348 return ps;
1349 break;
1350 case POWER_STATE_TYPE_INTERNAL_ULV:
1351 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1352 return ps;
1353 break;
1354 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1355 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1356 return ps;
1357 break;
1358 default:
1359 break;
1360 }
1361 }
1362
1363 switch (dpm_state) {
1364 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1365 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1366 goto restart_search;
1367 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1368 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1369 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1370 if (adev->pm.dpm.uvd_ps) {
1371 return adev->pm.dpm.uvd_ps;
1372 } else {
1373 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1374 goto restart_search;
1375 }
1376 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1377 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1378 goto restart_search;
1379 case POWER_STATE_TYPE_INTERNAL_ACPI:
1380 dpm_state = POWER_STATE_TYPE_BATTERY;
1381 goto restart_search;
1382 case POWER_STATE_TYPE_BATTERY:
1383 case POWER_STATE_TYPE_BALANCED:
1384 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1385 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1386 goto restart_search;
1387 default:
1388 break;
1389 }
1390
1391 return NULL;
1392}
1393
1394static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1395{
1396 struct amdgpu_ps *ps;
1397 enum amd_pm_state_type dpm_state;
1398 int ret;
1399 bool equal = false;
1400
1401
1402 if (!adev->pm.dpm_enabled)
1403 return;
1404
1405 if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1406
1407 if ((!adev->pm.dpm.thermal_active) &&
1408 (!adev->pm.dpm.uvd_active))
1409 adev->pm.dpm.state = adev->pm.dpm.user_state;
1410 }
1411 dpm_state = adev->pm.dpm.state;
1412
1413 ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1414 if (ps)
1415 adev->pm.dpm.requested_ps = ps;
1416 else
1417 return;
1418
1419 if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1420 printk("switching from power state:\n");
1421 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1422 printk("switching to power state:\n");
1423 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1424 }
1425
1426
1427 ps->vce_active = adev->pm.dpm.vce_active;
1428 if (adev->powerplay.pp_funcs->display_configuration_changed)
1429 amdgpu_dpm_display_configuration_changed(adev);
1430
1431 ret = amdgpu_dpm_pre_set_power_state(adev);
1432 if (ret)
1433 return;
1434
1435 if (adev->powerplay.pp_funcs->check_state_equal) {
1436 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1437 equal = false;
1438 }
1439
1440 if (equal)
1441 return;
1442
1443 amdgpu_dpm_set_power_state(adev);
1444 amdgpu_dpm_post_set_power_state(adev);
1445
1446 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1447 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1448
1449 if (adev->powerplay.pp_funcs->force_performance_level) {
1450 if (adev->pm.dpm.thermal_active) {
1451 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1452
1453 amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1454
1455 adev->pm.dpm.forced_level = level;
1456 } else {
1457
1458 amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1459 }
1460 }
1461}
1462
1463void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1464{
1465 if (adev->powerplay.pp_funcs->powergate_uvd) {
1466
1467 mutex_lock(&adev->pm.mutex);
1468 amdgpu_dpm_powergate_uvd(adev, !enable);
1469 mutex_unlock(&adev->pm.mutex);
1470 } else {
1471 if (enable) {
1472 mutex_lock(&adev->pm.mutex);
1473 adev->pm.dpm.uvd_active = true;
1474 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1475 mutex_unlock(&adev->pm.mutex);
1476 } else {
1477 mutex_lock(&adev->pm.mutex);
1478 adev->pm.dpm.uvd_active = false;
1479 mutex_unlock(&adev->pm.mutex);
1480 }
1481 amdgpu_pm_compute_clocks(adev);
1482 }
1483}
1484
1485void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1486{
1487 if (adev->powerplay.pp_funcs->powergate_vce) {
1488
1489 mutex_lock(&adev->pm.mutex);
1490 amdgpu_dpm_powergate_vce(adev, !enable);
1491 mutex_unlock(&adev->pm.mutex);
1492 } else {
1493 if (enable) {
1494 mutex_lock(&adev->pm.mutex);
1495 adev->pm.dpm.vce_active = true;
1496
1497 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1498 mutex_unlock(&adev->pm.mutex);
1499 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1500 AMD_CG_STATE_UNGATE);
1501 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1502 AMD_PG_STATE_UNGATE);
1503 amdgpu_pm_compute_clocks(adev);
1504 } else {
1505 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1506 AMD_PG_STATE_GATE);
1507 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1508 AMD_CG_STATE_GATE);
1509 mutex_lock(&adev->pm.mutex);
1510 adev->pm.dpm.vce_active = false;
1511 mutex_unlock(&adev->pm.mutex);
1512 amdgpu_pm_compute_clocks(adev);
1513 }
1514
1515 }
1516}
1517
1518void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1519{
1520 int i;
1521
1522 if (adev->powerplay.pp_funcs->print_power_state == NULL)
1523 return;
1524
1525 for (i = 0; i < adev->pm.dpm.num_ps; i++)
1526 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1527
1528}
1529
1530int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1531{
1532 int ret;
1533
1534 if (adev->pm.sysfs_initialized)
1535 return 0;
1536
1537 if (adev->pm.dpm_enabled == 0)
1538 return 0;
1539
1540 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1541 DRIVER_NAME, adev,
1542 hwmon_groups);
1543 if (IS_ERR(adev->pm.int_hwmon_dev)) {
1544 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1545 dev_err(adev->dev,
1546 "Unable to register hwmon device: %d\n", ret);
1547 return ret;
1548 }
1549
1550 ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1551 if (ret) {
1552 DRM_ERROR("failed to create device file for dpm state\n");
1553 return ret;
1554 }
1555 ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1556 if (ret) {
1557 DRM_ERROR("failed to create device file for dpm state\n");
1558 return ret;
1559 }
1560
1561
1562 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1563 if (ret) {
1564 DRM_ERROR("failed to create device file pp_num_states\n");
1565 return ret;
1566 }
1567 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1568 if (ret) {
1569 DRM_ERROR("failed to create device file pp_cur_state\n");
1570 return ret;
1571 }
1572 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1573 if (ret) {
1574 DRM_ERROR("failed to create device file pp_force_state\n");
1575 return ret;
1576 }
1577 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1578 if (ret) {
1579 DRM_ERROR("failed to create device file pp_table\n");
1580 return ret;
1581 }
1582
1583 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1584 if (ret) {
1585 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1586 return ret;
1587 }
1588 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1589 if (ret) {
1590 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1591 return ret;
1592 }
1593 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1594 if (ret) {
1595 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1596 return ret;
1597 }
1598 ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1599 if (ret) {
1600 DRM_ERROR("failed to create device file pp_sclk_od\n");
1601 return ret;
1602 }
1603 ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1604 if (ret) {
1605 DRM_ERROR("failed to create device file pp_mclk_od\n");
1606 return ret;
1607 }
1608 ret = device_create_file(adev->dev,
1609 &dev_attr_pp_power_profile_mode);
1610 if (ret) {
1611 DRM_ERROR("failed to create device file "
1612 "pp_power_profile_mode\n");
1613 return ret;
1614 }
1615 ret = device_create_file(adev->dev,
1616 &dev_attr_pp_od_clk_voltage);
1617 if (ret) {
1618 DRM_ERROR("failed to create device file "
1619 "pp_od_clk_voltage\n");
1620 return ret;
1621 }
1622 ret = amdgpu_debugfs_pm_init(adev);
1623 if (ret) {
1624 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1625 return ret;
1626 }
1627
1628 adev->pm.sysfs_initialized = true;
1629
1630 return 0;
1631}
1632
1633void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1634{
1635 if (adev->pm.dpm_enabled == 0)
1636 return;
1637
1638 if (adev->pm.int_hwmon_dev)
1639 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1640 device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1641 device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1642
1643 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1644 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1645 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1646 device_remove_file(adev->dev, &dev_attr_pp_table);
1647
1648 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1649 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1650 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1651 device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1652 device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1653 device_remove_file(adev->dev,
1654 &dev_attr_pp_power_profile_mode);
1655 device_remove_file(adev->dev,
1656 &dev_attr_pp_od_clk_voltage);
1657}
1658
1659void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1660{
1661 struct drm_device *ddev = adev->ddev;
1662 struct drm_crtc *crtc;
1663 struct amdgpu_crtc *amdgpu_crtc;
1664 int i = 0;
1665
1666 if (!adev->pm.dpm_enabled)
1667 return;
1668
1669 if (adev->mode_info.num_crtc)
1670 amdgpu_display_bandwidth_update(adev);
1671
1672 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1673 struct amdgpu_ring *ring = adev->rings[i];
1674 if (ring && ring->ready)
1675 amdgpu_fence_wait_empty(ring);
1676 }
1677
1678 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1679 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1680 } else {
1681 mutex_lock(&adev->pm.mutex);
1682 adev->pm.dpm.new_active_crtcs = 0;
1683 adev->pm.dpm.new_active_crtc_count = 0;
1684 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1685 list_for_each_entry(crtc,
1686 &ddev->mode_config.crtc_list, head) {
1687 amdgpu_crtc = to_amdgpu_crtc(crtc);
1688 if (amdgpu_crtc->enabled) {
1689 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1690 adev->pm.dpm.new_active_crtc_count++;
1691 }
1692 }
1693 }
1694
1695 if (power_supply_is_system_supplied() > 0)
1696 adev->pm.dpm.ac_power = true;
1697 else
1698 adev->pm.dpm.ac_power = false;
1699
1700 amdgpu_dpm_change_power_state_locked(adev);
1701
1702 mutex_unlock(&adev->pm.mutex);
1703 }
1704}
1705
1706
1707
1708
1709#if defined(CONFIG_DEBUG_FS)
1710
1711static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1712{
1713 uint32_t value;
1714 struct pp_gpu_power query = {0};
1715 int size;
1716
1717
1718 if (!(adev->powerplay.pp_funcs &&
1719 adev->powerplay.pp_funcs->read_sensor))
1720 return -EINVAL;
1721
1722
1723 size = sizeof(value);
1724 seq_printf(m, "GFX Clocks and Power:\n");
1725 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1726 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1727 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1728 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1729 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1730 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1731 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1732 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1733 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1734 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1735 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1736 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1737 size = sizeof(query);
1738 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) {
1739 seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8,
1740 query.vddc_power & 0xff);
1741 seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8,
1742 query.vddci_power & 0xff);
1743 seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8,
1744 query.max_gpu_power & 0xff);
1745 seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8,
1746 query.average_gpu_power & 0xff);
1747 }
1748 size = sizeof(value);
1749 seq_printf(m, "\n");
1750
1751
1752 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1753 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1754
1755
1756 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1757 seq_printf(m, "GPU Load: %u %%\n", value);
1758 seq_printf(m, "\n");
1759
1760
1761 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1762 if (!value) {
1763 seq_printf(m, "UVD: Disabled\n");
1764 } else {
1765 seq_printf(m, "UVD: Enabled\n");
1766 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1767 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1768 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1769 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1770 }
1771 }
1772 seq_printf(m, "\n");
1773
1774
1775 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1776 if (!value) {
1777 seq_printf(m, "VCE: Disabled\n");
1778 } else {
1779 seq_printf(m, "VCE: Enabled\n");
1780 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1781 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1782 }
1783 }
1784
1785 return 0;
1786}
1787
1788static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1789{
1790 int i;
1791
1792 for (i = 0; clocks[i].flag; i++)
1793 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1794 (flags & clocks[i].flag) ? "On" : "Off");
1795}
1796
1797static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1798{
1799 struct drm_info_node *node = (struct drm_info_node *) m->private;
1800 struct drm_device *dev = node->minor->dev;
1801 struct amdgpu_device *adev = dev->dev_private;
1802 struct drm_device *ddev = adev->ddev;
1803 u32 flags = 0;
1804
1805 amdgpu_device_ip_get_clockgating_state(adev, &flags);
1806 seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1807 amdgpu_parse_cg_state(m, flags);
1808 seq_printf(m, "\n");
1809
1810 if (!adev->pm.dpm_enabled) {
1811 seq_printf(m, "dpm not enabled\n");
1812 return 0;
1813 }
1814 if ((adev->flags & AMD_IS_PX) &&
1815 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1816 seq_printf(m, "PX asic powered off\n");
1817 } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
1818 mutex_lock(&adev->pm.mutex);
1819 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
1820 adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
1821 else
1822 seq_printf(m, "Debugfs support not implemented for this asic\n");
1823 mutex_unlock(&adev->pm.mutex);
1824 } else {
1825 return amdgpu_debugfs_pm_info_pp(m, adev);
1826 }
1827
1828 return 0;
1829}
1830
1831static const struct drm_info_list amdgpu_pm_info_list[] = {
1832 {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1833};
1834#endif
1835
1836static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1837{
1838#if defined(CONFIG_DEBUG_FS)
1839 return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1840#else
1841 return 0;
1842#endif
1843}
1844
